Memory and compute 3DIC integration without through silicon via

Abstract

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

Description

MEMORY AND COMPUTE 3DIC INTEGRATION WITHOUT THROUGH SILICON VIABACKGROUND

[0001] This specification relates to configuring semiconductor circuit dies for an integrated circuit.

[0002] Modem computing systems include various processing devices that each offer different computing capabilities and trade-offs. At least one device can be an Intellectual Property block (“IP block") that executes a respective portion of a computational operation for different multimedia workloads. Example use cases can involve processing image or speech data captured respectively by a camera or microphone on a mobile (or edge) device as well as performing computations for generative artificial intelligence (“GenAI”) applications. The system-on-chip (“SoC”) can use a heterogeneous computing operation to execute a workload by processing input samples derived from image data, speech data, a text corpus, or a combination of these.

[0003] The workload can be for a machine-learning (“ML”) model, such as a large language model (“LLM”) used to implement an inference computation for a GenAI application. The SoC performs the heterogeneous operation to execute the workload at least by processing data for the input samples using in-memory processing or computing capabilities of the corresponding memory device that stores the input data. The SoC can encounter memory bound issues corresponding memory' bandwidth limits / constraints between the SoC and the memory device. These memory bound issues represent a known bottleneck that can degrade or delay workload execution when running LLM inference computations on edge (or even cloud) devices.SUMMARY

[0004] Certain in-memory computing techniques such as Processing-in-Memory (PiM), including Compute-in-Memory (CiM), Accel erator-in-Memory (AiM). and / or Memory -near- Computing (MnC) (collectively “PiM”), are emerging technologies that can be used to overcome bottlenecks and memory bandwidth constraints at an interface of a SoC and an integrated memory device. These techniques can also expand implementation options to enable GenAI application workloads on edge devices.

[0005] In general, example edge devices (e.g., smartphones or tablets) can include integrated circuitry7for an SoC and a corresponding memory device(s) that couples to theSoC. The memory device can be a dynamic random-access memory (DRAM) device that includes a PiM architecture configured to perform memory-bounded and compute-bounded computations for executing an inference workload or task in the memory device. For example, the memory device can include example PiM (and / or AiM) architectures that are collocated with memory cells, or banks, that store data at the memory- device for routing to compute devices at the PiM architecture.

[0006] The PiM architecture defines one or more PiM blocks of the memory device and each PiM block includes computing resources / elements, such as a processor unit, mode registers, and one or more computational units, e.g., arithmetic logic units (ALUs) or related addition and multiplication circuitry. The PiM blocks are used to execute computations for an example workload that originates at the SoC. The computations can be segmented into respective portions that are allocated between the SoC and the memory device that includes the PiM blocks. As indicated above, the workload can be an example LLM workload for a GenAI application.

[0007] Existing approaches for integrating PiM architectures in a memory device merely repurpose portions of the memory cells into compute logic for the PiM architecture. But these approaches compromise memory density of the memory device by reducing the available area that can be ascribed to memory7cells of the device.

[0008] To address the aforementioned deficiencies, this specification describes techniques for improved integration of compute logic die for PiM architectures with memory7die for storage banks of an integrated memory' device. The techniques allow for an apparatus, such as an integrated circuit (IC) or IC package design, that improves PiM performance by decoupling compute logic die for the PiM architecture from the memory die and integrating respective PiM and memory circuitry as distinct, independent semiconductor die. For example, the PiM compute logic die and memory die can be arranged in a stacked, three- dimensional integrated circuit (3DIC) configuration and coupled to exchange signal communications.

[0009] The memory cells of the semiconductor memory die are fabricated or formed using multiple logic gates that have a first gate node size, whereas the arithmetic circuits of the semiconductor compute logic die are fabricated or formed using multiple logic gates that have a second gate node size. The second gate node size can be different from (or the same as) the first gate node size. In some examples, the second gate node size of the semiconductor compute logic die is less than 10 nanometers (nm). A periphery7of the memory semiconductor die can include a particular wire bonding configuration thatfacilitates power delivery to each of the memory and compute logic die as well as Input / Output (I / O) signaling to each of the memory and compute logic die.

[0010] One aspect of the subject matter described in this specification can be embodied in an apparatus comprising a first semiconductor die comprising a plurality of memory cells; and a second semiconductor die comprising compute logic representing a Processing-in- Memory (PiM) architecture configured to process data stored at the plurality of memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration, and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data that is routed from a memory' cell of the first semiconductor die.

[0011] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, i) the first semiconductor die is a memory die; and ii) the second semiconductor die is a compute logic die that is distinct and separate from the memory die. In some implementations, the apparatus further includes a package that houses or encloses the first semiconductor die and the second semiconductor die in the stacked configuration.

[0012] In some implementations, i) the first semiconductor die comprises a first interconnect region; ii) the second semiconductor die comprises a second interconnect region; and iii) the first and second semiconductor die are coupled by w ay of connection points that extend between the first and second interconnection regions. The apparatus can be an integrated circuit for a memory device comprising compute-in-memory capability. In some implementations, the apparatus is a packaging platform for an integrated circuit. In some implementations, the multiple memory' cells of the first semiconductor die is formed from multiple logic gates that have a first gate node size.

[0013] In some implementations, the compute logic of the second semiconductor die is formed from multiple logic gates that have a second gate node size that is different than the first gate node size. In some implementations, the second gate node size is less than the first gate node size. In some implementations, i) the first gate node size is greater than 10 nanometers, nm; and ii) the second gate node size is less than 10 nm. The compute logic of the second semiconductor die can be formed from multiple logic gates that have a second gate node size, and the first gate node size and the second gate node size are the same.

[0014] One aspect of the subject matter described in this specification can be embodied in a memory device that includes multiple integrated die bundles, each integrated die bundle including an apparatus according to any preceding example aspect and / or implementationdescribed in the above summary or example-stacked die configurations herein. In some implementations, the multiple integrated die bundles are arranged in a stacked configuration.

[0015] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, a first one of the multiple integrated die bundles is coupled to a second one of the multiple integrated die bundles by a wire bonding configuration. In some implementations, the first one of the multiple integrated die bundles is offset from the second one of the multiple integrated die bundles, such that a peripheral bonding region of the first one of the multiple integrated die bundles is not covered by the second one of the multiple integrated die bundles.

[0016] Another aspect of the subject matter described in this specification can be embodied in an integrated circuit comprising: a first semiconductor die comprising multiple memory cells; and a second semiconductor die comprising compute logic representing a PiM architecture configured to process data stored at the multiple memory cells. The first semiconductor die and the second semiconductor die can be: i) arranged in a stacked configuration, and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data that is routed from a memory cell of the first semiconductor die.

[0017] Another aspect of the subject matter described in this specification can be embodied in a method of making or manufacturing an integrated circuit for a memory & compute device. The method includes: forming a first semiconductor die comprising a plurality of memory cells; forming a second semiconductor die comprising compute logic representing a PiM compute module; forming an interconnect region comprising electrical connection points configured for exchanging signal communications between the first and second semiconductor die; arranging the first semiconductor die and the second semiconductor die in a stacked configuration; and coupling the first and second semiconductor using the electrical connection points of the interconnect region.

[0018] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, the PiM compute module of the second semiconductor die is configured to execute computations on data stored at the multiple memory cells. In some implementations, forming an interconnect region comprising electrical connection points comprises forming a first interconnect region at the first semiconductor die, the first interconnect region comprising first electrical connection points. Similarly, forming an interconnect region comprising electrical connection points can include forming a second interconnect region at the second semiconductor die, the secondinterconnect region comprising second electrical connection points. In some implementations, the method of manufacturing the integrated circuit further includes forming a wire bonding configuration that facilitates power delivery to each of the first semiconductor die and the second semiconductor die.

[0019] Other implementations of this and other aspects include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. A system of one or more computers can be so configured by virtue of software, firmware, hardware, or a combination of them installed on the system that in operation causes the system to perform the actions. One or more computer programs can be so configured by virtue of having instructions that, when executed by a data processing apparatus, cause the apparatus to perform the actions.

[0020] The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other potential features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Fig. 1 illustrates top-down planar and side views of example integrated memory circuits.

[0022] Fig. 2 illustrates a cross-sectional view of an example integrated memory circuit and corresponding package features.

[0023] Fig. 3 illustrates a top-down planar view of an example integrated circuit comprising a memory die and a compute die in a stacked configuration.

[0024] Fig. 4 illustrates a cross-sectional view of example integrated circuits that each comprise a memory die and a compute die in a stacked configuration.

[0025] Fig. 5 is an example process of making or manufacturing an integrated circuit for a memory & compute device.

[0026] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0027] Fig. 1 illustrates top-down planar and side views of example integrated memory circuits 102, 104. The integrated memory circuit 102 includes a die 103 with a memory portion 108 and a compute portion 106. The compute portion!06 can be configured ordesigned to include compute logic circuitry. For example, the compute logic circuitry can include computing resources / elements, such as a processor unit, mode registers, and one or more computational units, e.g., arithmetic logic units (ALUs) or related addition and multiplication circuitry. Certain computational units that represent the compute logic can be fabricated or formed atop a surface of the compute portion 106. Relatedly, the memory portion 108 can be configured or designed to include multiple memory cells atop a surface of the memory portion 108. For example, the circuitry for the memory cells may be etched or formed on a surface of die 103 via any of the know circuit fabrication techniques.

[0028] The compute logic portion 106 may be comprised of multiple smaller compute blocks, die portions, or dies 110, whereas the memory portion 108 can be comprised of multiple sections or groups of memory cells 112 formed on different die portions or dies. A section or group of memory cells 112 can represent a memory bank of the memory die 108. In some implementations, the compute portion 106 is a single compute die that undergoes a deposition and fabrication process, which can yield multiple individual compute blocks 110. Similarly, in some implementations, the memory portion 108 is a single memory die that undergoes a deposition and fabrication process, which can yield multiple individual memory storage banks 112.

[0029] As described in more detail below, the compute portion (or die) 106 can include a PiM architecture formed via an example circuit fabrication process. In the example of Fig. 1, integrated memory circuit 102 represents a first approach for integrating PiM architectures in a memory device by repurposing portions 1 16 of die 103, that would otherwise be used as memory cells, into compute logic for the PiM architecture. An example of this is indicated via a side view 105, which shows a side 105s of integrated memory circuit 102 with the compute die portion 106 and memory die portion 108 being flush, with each of the die portions 106 and 108 having respective top surfaces that are generally coplanar. But these approaches compromise memory density of the memory device by reducing the available area that can be ascribed to memory cells of the device. For example, memory density can be reduced by at least the portion 116 of die 103 that is repurposed as a compute portion 106.

[0030] The integrated memory circuit 104 represents a second, different approach for integrating PiM architectures in a memory device, and in a manner that addresses the aforementioned deficiencies of the first approach. The integrated memory' circuit 104 includes a compute die 120 and memoiy die 130. The compute die 120 includes compute logic circuitry fabricated or formed atop a particular surface of the compute die 120.Relatedly, the memory die 130 includes multiple memory cells fabricated or formed atop a surface of memory die 130.

[0031] The integrated memory circuit 104 can be designed and / or manufactured based on the disclosed techniques for improved integration of compute logic die for PiM architectures with memory die for memory / storage banks 134 of an integrated memory' device 118. The techniques allow for improving PiM performance by decoupling compute logic die 120 for the PiM architecture from the memory die 130 and integrating respective PiM and memory circuitry as distinct, independent semiconductor die. For example, in contrast to circuit 102 where a portion 116 of die 103 is repurposed to include both a memory' portion 108 and compute logic portion 106, the memory circuit 104 integrates respective PiM and memory circuitry as distinct, independent semiconductor die 120 (compute) and die 130 (memory). In particular, the techniques disclosed in this specification can provide an apparatus, IC (e.g., integrated memory' circuit 104), or IC package design, that offers improved PiM performance over prior designs.

[0032] The compute logic die 120 and the memory die 130 may be referred to as being distinct, or separate, from one another. This is intended to mean that each die is fabricated on a separate semiconductor substrate. Nevertheless, the integrated memory circuit, may comprise both of the logic die 120 and the memory' die 130, which are functionally coupled to one another in such a way as to enable signal communications to flow between each other. For example, the signal communications can flow from the logic die 120 to the memory die 130, and vice versa, e g., by traversing a signal path that couples the compute logic die 120 and the memory die 130.

[0033] The compute die 120 includes a first interconnect region 122, whereas the memory die 130 includes a second interconnect region 132. The compute die 120 and memory die 130 can be coupled by way of connection points that extend between the first and second interconnection regions 122, 132. The semiconductor die can be silicon or bulk silicon, however other semiconductor materials or w afers can be used, such as germanium, selenium, gallium, etc. Each of the interconnection regions 122, 132 can include a respective set of connection pads 124 for establishing electrical connections that represent the connection points.

[0034] In some implementations, interconnection regions 122, 132 can be enclosed in an example device package 135 or packaging platform that includes a power delivery network (not shown). The power delivery network can be collocated with respective die-to-die interconnect regions 122, 132 of the compute die 120 and memory die 130, respectively. Insome implementations, aspects include a number and sizing of the connection pads 124 in the die-to-die interconnect regions 122, 132 are defined based on an interconnect specification that includes certain signal integrity requirements for signaling routed via the die-to-die interconnect of regions 122, 132. The power delivery network can include multiple connection pillars and a corresponding micro-bump (pBump) pitch that defines a spacing between two or more of the multiple connection pillars that can be performed at the connection pads 124.

[0035] Fig. 2 illustrates a cross-sectional view of an example memory device 202 represented by the integrated memory circuit 104 and corresponding package features such as wire bonds 204, and mold portions 206.

[0036] In general, the memory device 202 includes semiconductor memory and logic die as well as certain dielectric elements that are embedded or encapsulated using epoxy mold compounds that generally form the mold portions 206 (e.g., an example mold-frame).Packaging features of the memory device 202 can form an example packaging platform 135 that includes a mold portion 206 such as an epoxy-molding compound that surrounds, embeds, or encapsulates at least the semiconductor and dielectric elements of the memory device 202. In some implementations, the wire bond connections 204 are external to, or protrude from, the example mold. The memory' device 202 can correspond to device 118 described above with reference the example of Fig. 1. In some implementations, the device 202 includes an additional section 207 that can be used for additional memory die. compute die, mold portion, or a combination of these.

[0037] As show n in the example of Fig. 2, the memory die 130 and the PiM compute logic die 120 can be arranged in a stacked, three-dimensional integrated circuit (3DIC) configuration. The compute die 120 and memory die 130 are coupled to exchange signal communications via their respective die-to-die interconnect regions 122, 132. In some implementations, an apparatus that includes integrated memory circuit 104 also includes an example package 135 that houses or encloses the compute die 120 and the memory die 130 in the stacked configuration.

[0038] In general, example edge devices (e.g.. smartphones or tablets) can include integrated circuitry for an SoC and a corresponding memory device(s) that couples to the SoC. The memory' device 202 can include example PiM and / or AiM architectures that are collocated with memory cells, or banks 134. that store data at the memory' device 202 for routing to a PiM block or module that forms an example PiM architecture. The integrated memory circuit 104 represents the memory device in this example.

[0039] Fig. 3 illustrates a top-down planar view of an example integrated memory circuit 104 comprising a memory die and a compute die in a stacked configuration, such as a 3DIC configuration. Being in a stacked configuration is intended to mean that one die is placed at least partially on top of the other die such that a substantially planar (e.g., upper) surface of one die (e.g., the memory die 130) is at least partially facing, and substantially parallel to a substantially planar (e.g., lower) surface of the other die (e.g.. the compute die 120). It will be understood, of course, that terms like "‘on top”, "‘upper” and “lower” are not intended to be limiting, and are used to describe relative positions of components in the particular orientation shown in the figures.

[0040] In general, example edge devices (e.g., smartphones or tablets) can include integrated circuitry for an SoC and a corresponding memory device(s) that couples to the SoC. In the example of Fig. 3, the semiconductor dies are stacked and interconnected vertically within an example integrated circuit package via die-to-die interconnect region 300, comprising overlapping interconnection regions 122 and 132 (as shown in Fig. 2) of the compute die 120 and memory die 130, respectively. The memory’ device 202 can include example PiM and / or AiM architectures 302 that are collocated with memory cells, or banks 134, that store data at the memory device 202 for routing to a PiM block or module that forms an example PiM architecture. The integrated memory’ circuit 104 represents the memory device in this example.

[0041] As generally indicated above, for integrated memory circuit 104, the compute logic die 120 can be comprised of multiple smaller compute dies (or blocks) 304, whereas the memory’ die 130 can be comprised of multiple sections or groups of memory cells 134. A section or group of memory cells 134 can represent a memory' bank of the memory die 130. In some implementations, the compute die 120 is a single compute die that undergoes a deposition and fabrication process, which can yield multiple individual compute blocks 302 (or 304). Similarly, in some implementations, the memory die 130 is a single memory’ die that undergoes a deposition and fabrication process, which can yield multiple individual memory banks 134.

[0042] The memory cells of the semiconductor memory die 130 are fabricated or formed using multiple logic gates that have a first gate node size, w hereas the arithmetic circuits (described below) of the semiconductor compute logic die 120 are fabricated or formed using multiple logic gates that have a second gate node size. The second gate node size can be different from (or the same as) the first gate node size. In some implementations, the gate node size of logic gates of the memory' die 130 is greater than 10 nanometers (nm), whereasthe second gate node size of logic gates of the compute die 120 is less than 10 nm. In some examples, the gate node size of logic gates of the compute die 120 and memory’ die 130 can be less than 10 nm.

[0043] The gate node size corresponds to a transistor gate length of individual transistor circuits that form at least the arithmetic circuitry' of the compute logic die 120. In some examples, the second gate node size of the semiconductor compute logic die is less than 10 nanometers (nm). A periphery of the memory semiconductor die can include a particular wire bonding configuration that facilitates power delivery’ to each of the memory’ and compute logic die as well as Input / Output (I / O) signaling to each of the memory and compute logic die.

[0044] Fig. 4 illustrates a cross-sectional view of multiple integrated memory’ circuits 104 of memory device 400, where each integrated memory circuit comprises a compute die 120 and a memory die 130 in a stacked configuration. Relatedly, the multiple integrated memory circuits 104 may be also arranged in a stacked configuration 405 in an example memory device 202. When stacked, the compute die 120 and memory die 130 can be arranged in a face-to-face (F2F) configuration such that a side of the compute die 120 that includes the compute logic and processor arrays, and register devices, faces a side of the memory die 130 that includes the memory’ banks and corresponding memory’ cells.

[0045] The multiple integrated memory circuits 104 may be referred to as integrated die bundles, each die bundle comprising comprises a respective compute die 120 and a respective memory die 130 in a stacked configuration. The multiple integrated memory circuits 104 may themselves also be arranged in a stacked configuration. Adjacent ones of the integrated die bundles may be offset from one another in a horizontal direction, as shown in Fig. 4. In this way, a periphery of the memory semiconductor die having a wire bonding configuration may be exposed (e.g., not covered by the next integrated die bundle), so as to permit wire bonding between adjacent integrated die bundles. The periphery of the memory semiconductor die may be referred to as a peripheral bonding region of the integrated die bundle.

[0046] In some implementations, the memory devices 118, 202, 400 includes multiple memory dies. For example, the memory’ devices 118, 202, 400 can include N memory die. where N is an integer greater than 1. Each of the memory devices 1 18, 202, 400 can be a dynamic random-access memory' (DRAM) or Double Data Rate (DDR) synchronous DRAM (SDRAM). Each of the memory devices 118, 202, 400 is configured to perform or support various types of PiM operations. CiM operations, and MnC operations. Each of the memorydevices 118, 202, 400 performs or supports these operations using its multiple PiM compute elements of a corresponding PiM architecture 302.

[0047] In general, the PiM architecture defines one or more PiM modules / blocks of the memory device 118, 202, 400. Each PiM block includes compute elements, such as a processor unit, mode registers, and one or more computational units, e.g., ALUs or related addition and multiplication circuitry. For example, the PiM block can include discrete processors, processor units, register devices, buffers, multiply accumulate cells (MACs). etc. that cooperate to form one or more PiM compute elements.

[0048] Each of the PiM, CiM, and MnC operations can include standard arithmetic operations, such as computations normally performed by an ALU or MAC. These operations can also include computational functions of a hardware accelerator, such as multiplication and addition operations for matrix math, vector computations, linear algebra, and dot-product accumulations. In some implementations, each of the PiM, CiM, and MnC operations are performed in support of ML computations, neural network computations, or both. The PiM operations can also include standard CPU functions.

[0049] In some implementations, the PiM blocks are used to execute computations for an example workload that originates at the SoC. The computations can be segmented into respective portions that are allocated between the SoC and the memory' device 118, 202, 400 that includes the PiM blocks. In the example of Fig. 4, the SoC 102 leverages the configuration of wire bonds 204 to enable chip select logic for selecting one or more of the integrated die bundles of the memory device 400.

[0050] In the example of Fig. 4, the memory device 400 includes four integrated die bundles, where each integrated die bundle includes at least one compute die 120 that is connected to a corresponding memory die 130. The memory device 400 can include more or fewer integrated die bundles. In some implementations, each integrated die bundle corresponds to an integrated memory circuit 104. Each memory device 118, 202, 400 can include a ball grid array (BGA) feature 410 that facilitates connecting or soldering the memory device 118, 202, 400 to a printed circuit board (or PCB).

[0051] In some implementations, each of the memory devices described herein (e.g.. devices 118, 202, 400) can include one or more redistribution layers (RDLs) that can be positioned adjacent, atop, or integrated with a mold-frame of the device, and solder balls may be positioned at the RDL to facilitate I / O connections via a BGA of pins that extend beyond a periphery of the semiconductor die for at least the memory cells of the device. The memorydevices can be configured for direct mounting to a printed circuit board via multiple connection pillars that include or correspond to the BGA feature 410.

[0052] As described above, the power delivery network of the memory devices described herein (e.g., devices 118, 202, 400) can include multiple connection pillars and a corresponding micro-bump pitch that defines a spacing between two or more of the multiple connection pillars. In some implementations, the multiple connection pillars may be for electrically connecting the power delivery network to an example RDL of the device. The micro-bump pitch of the power delivery network can be based on a pitch of the connection pillars of the die-to-die interconnect regions 122, 132.

[0053] Fig. 5 is an example process 500 of making or manufacturing an integrated circuit for a memory & compute device. The 500 may be described alternatively as an example method of making or manufacturing an integrated memory device.

[0054] Process 500 includes forming a first semiconductor die comprising a plurality of memory7cells (502) and forming a second semiconductor die comprising compute units representing a PiM compute module (504). For example, the first semiconductor die can be a memory die 130, whereas the second semiconductor die can be a compute die 120. The PiM compute module of the second semiconductor die is configured to execute computations on data stored at the multiple memory' cells of the first semiconductor die. Process 500 includes forming an interconnect region comprising electrical connection points configured for exchanging signal communications between the first and second semiconductor die (506).

[0055] In some implementations, forming an interconnect region comprising electrical connection points includes: i) forming a first interconnect region at the first semiconductor die. and ii) forming a second interconnect region at the second semiconductor die. The first interconnect region includes first electrical connection points 132, whereas the second interconnect region includes second electrical connection points 122. Process 500 also includes arranging the first semiconductor die and the second semiconductor die in a stacked configuration (508) and coupling the first and second semiconductor using the electrical connection points of the interconnect region (510). In some implementations, process 500 includes forming a wire bonding configuration that facilitates power delivery to each of the first semiconductor die and the second semiconductor die.

[0056] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non- transitory program earner for execution by, or to control the operation of, data processing apparatus. These embodiments can include processes and methods of making or manufacturing a semiconductor device, a wafer-level package, packaging features, or package structures described in this specification.

[0057] Alternatively, or in addition, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0058] The term “computing system” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0059] A computer program (which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0060] A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0061] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry7, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a GPGPU (General purpose graphics processing unit).

[0062] Computers suitable for the execution of a computer program include, by way of example, can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read only memory or a random-access memory or both. Some elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0063] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0064] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., LCD (liquid cry stal display) monitor, for display ing information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that isused by the user; for example, by sending web pages to a web browser on a user's client device in response to requests received from the web browser.

[0065] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN’’), e.g., the Internet.

[0066] The computing system can include clients and servers. A client and server are generally remote from each other and ty pically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0067] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0068] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components andsystems can generally be integrated together in a single software product or packaged into multiple software products.

[0069] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

What is claimed is:

1. An apparatus comprising: a first semiconductor die comprising a plurality of memory cells; and a second semiconductor die comprising compute logic representing a Processing-in- Memory (PiM) architecture configured to process data stored at the plurality of memory cells; wherein the first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration, and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data that is routed from a memory cell of the first semiconductor die.

2. The apparatus of claim 1, wherein: i) the first semiconductor die is a memory die; and ii) the second semiconductor die is a compute logic die that is distinct and separate from the memory die.

3. The apparatus of claim 1 or 2, further comprising: a package that houses or encloses the first semiconductor die and the second semiconductor die in the stacked configuration.

4. The apparatus of any preceding claim, wherein: i) the first semiconductor die comprises a first interconnect region; ii) the second semiconductor die comprises a second interconnect region; and iii) the first and second semiconductor die are coupled by w ay of connection points that extend betw een the first and second interconnection regions.

5. The apparatus of any preceding claim, wherein the apparatus is an integrated circuit for a memory device comprising compute-in-memory capability.

6. The apparatus of any one of claims 1 to 4, wherein the apparatus is a packaging platform for an integrated circuit.

7. The apparatus of any preceding claim, wherein the plurality of memory cells of the first semiconductor die is formed from a plurality of logic gates that have a first gate node size.

8. The apparatus of claim 7, wherein the compute logic of the second semiconductor die is formed from a plurality of logic gates that have a second gate node size that is different than the first gate node size.

9. The apparatus of claim 8, wherein the second gate node size is less than the first gate node size.

10. The apparatus of claim 8 or 9, wherein: i) the first gate node size is greater than 10 nanometers, nm; and ii) the second gate node size is less than 10 nm.

11. The apparatus of claim 7, wherein the compute logic of the second semiconductor die is formed from a plurality of logic gates that have a second gate node size, and the first gate node size and the second gate node size are the same.

12. A memory device comprising a plurality of integrated die bundles, each integrated die bundle comprising an apparatus according to any preceding claim, wherein: the plurality of integrated die bundles are arranged in a stacked configuration.

13. The memory device of claim 12. wherein a first one of the plurality of integrated die bundles is coupled to a second one of the plurality of integrated die bundles by a wire bonding configuration.

14. The memory device of claim 13, wherein the first one of the plurality of integrated die bundles is offset from the second one of the plurality of integrated die bundles, such that a peripheral bonding region of the first one of the plurality of integrated die bundles is not covered by the second one of the plurality of integrated die bundles.

15. An integrated circuit comprising: a first semiconductor die comprising a plurality of memory cells; anda second semiconductor die comprising compute logic representing a Processing-in- Memory (PiM) architecture configured to process data stored at the plurality of memory cells; wherein the first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration, and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data that is routed from a memory cell of the first semiconductor die.

16. A method of manufacturing an integrated circuit for a memory' & compute device, the method comprising: forming a first semiconductor die comprising a plurality7of memory7cells; forming a second semiconductor die comprising compute units representing a Processing-in-Memory (PiM) compute module; forming an interconnect region comprising electrical connection points configured for exchanging signal communications between the first and second semiconductor die; arranging the first semiconductor die and the second semiconductor die in a stacked configuration; and coupling the first and second semiconductor using the electrical connection points of the interconnect region.

17. The method of manufacturing the integrated circuit of claim 16, wherein the PiM compute module of the second semiconductor die is configured to execute computations on data stored at the plurality of memory cells of the first semiconductor die.

18. The method of manufacturing the integrated circuit of claim 17, wherein forming an interconnect region comprising electrical connection points comprises: forming a first interconnect region at the first semiconductor die, the first interconnect region comprising first electrical connection points.

19. The method of manufacturing the integrated circuit of claim 18, wherein forming an interconnect region comprising electrical connection points comprises: forming a second interconnect region at the second semiconductor die, the second interconnect region comprising second electrical connection points.

20. The method of manufacturing the integrated circuit of claim 19. further comprising: forming a wire bonding configuration that facilitates power delivery to each of the first semiconductor die and the second semiconductor die.

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