Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a first semiconductor structure including a peripheral circuit and an interconnect structure electrically connected to the peripheral circuit; a second semiconductor structure; a bonding layer between the first semiconductor structure and the second semiconductor structure; a bonding pad electrically connected to the interconnect structure, the bonding pad extending into the bonding layer; and a contact plug extending through the second semiconductor structure into the bonding layer, where the contact plug is electrically connected to the bonding pad.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration level of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, as improvements in the integration level of semiconductor devices in which memory cells are formed as a single layer on a substrate have reached their limits, three-dimensional semiconductor devices in which memory cells are stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a first semiconductor structure, which includes a peripheral circuit and an interconnection structure electrically connected to the peripheral circuit; a second semiconductor structure; a bonding layer, which is located between the first semiconductor structure and the second semiconductor structure; a bonding pad, which is electrically connected to the interconnection structure, and the bonding pad extends into the bonding layer; and a contact plug, which extends through the second semiconductor structure into the bonding layer, wherein the contact plug is electrically connected to the bonding pad.

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a first bonding layer; a first bonding pad passing through the first bonding layer; a second bonding layer forming a bonding interface with the first bonding layer; a first gate structure located on the second bonding layer; and a first contact plug extending through the first gate structure and the second bonding layer and electrically connected to the first bonding pad, and the first contact plug may include a metal layer and a barrier layer surrounding the sidewalls of the metal layer and extending between the metal layer and the first bonding pad.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a first wafer including a first bonding layer and a first bonding pad; forming a second wafer including a second bonding layer and a first sacrificial plug; bonding the first bonding layer and the second bonding layer so that the first bonding pad and the first sacrificial plug are connected; forming a first opening exposing the first bonding pad by removing the first sacrificial plug; and forming a first contact plug electrically connected to the first bonding pad in the first opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and Figure 1B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2A and Figure 2B is a cross-sectional view illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 3 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 4A to 4C is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] 5A to 5D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 6A to 6C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] 7A to 7C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 8A to 8G is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 9 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 10 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same, which have a stable structure and improved performance characteristics.

[0017] The integration degree of a semiconductor device is improved by stacking memory cells in a three-dimensional structure. In addition, a semiconductor device having a three-dimensional structure has a stable structure and exhibits improved reliability and performance.

[0018] Hereinafter, embodiments according to the technical concept of the present disclosure are described with reference to the accompanying drawings.

[0019] Figure 1A and Figure 1B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0020] Reference Figure 1AThe semiconductor device may include a first semiconductor structure SS1, a second semiconductor structure SS2, and a bonding structure BS disposed between the first semiconductor structure SS1 and the second semiconductor structure SS2. The semiconductor device may also include at least one contact plug 16, for example, two or more contact plugs 16. For example, the first semiconductor structure SS1 and the second semiconductor structure SS2 may include peripheral circuits and / or memory cell arrays. In embodiments, the first semiconductor structure SS1 may include peripheral circuits. The first semiconductor structure SS1 may also include a first interconnect structure IC1 electrically connected to the peripheral circuits, an interlayer insulating layer, and the like. In embodiments, the second semiconductor structure SS2 may include a memory cell array. The second semiconductor structure SS2 may include a source structure, a gate structure, a channel structure, a second interconnect structure, an interlayer insulating layer, and the like. The memory cell array may include memory cells stacked along the channel structure. In embodiments, the first semiconductor structure SS1 may include a memory cell array, and the second semiconductor structure SS2 may include peripheral circuits.

[0021] The bonding structure BS electrically connects the first semiconductor structure SS1 and the second semiconductor structure SS2 by bonding the first semiconductor structure SS1 and the second semiconductor structure SS2. The bonding structure BS may include a bonding layer B and first and second bonding insulating layers 13 and 14. The bonding layer B may be disposed between the first and second bonding insulating layers 13 and 14. The bonding layer B may include a first bonding layer 11 and a second bonding layer 12. At least one bonding pad 15 (e.g., two or more bonding pads 15) may be disposed within the bonding structure BS.

[0022] The first bonding layer 11 and the second bonding layer 12 may form a bonding interface IF. The first bonding layer 11 may be located above the first semiconductor structure SS1. The first bonding layer 11 may be located on the first bonding insulating layer 13. The second bonding layer 12 may be located between the first bonding layer 11 and the second bonding insulating layer 14. The first bonding insulating layer 13 may be located between the first semiconductor structure SS1 and the first bonding layer 11. The second bonding insulating layer 14 may be located between the second semiconductor structure SS2 and the second bonding layer 12. The bonding interface IF may be located at a portion where the first bonding layer 11 and the second bonding layer 12 contact each other. The first bonding layer 11 and the second bonding layer 12 may be chemically bonded at the bonding interface IF.

[0023] In an embodiment, the first bonding layer 11 and the second bonding layer 12 may include tetraethyl orthosilicate (TEOS), silicon carbon nitride (SiCN), etc. When the first bonding layer 11 and the second bonding layer 12 formed of SiCN layers are bonded, Si-O-Si bonding may be generated on the surfaces of the first bonding layer 11 and the second bonding layer 12, and the bonding interface IF may be changed to an oxide such as tetraethyl orthosilicate (TEOS) by removing carbon and nitrogen from SiCN.

[0024] The first bonding insulating layer 13 may be located between the first semiconductor structure SS1 and the first bonding layer 11 to protect the first bonding layer 11 during the manufacturing process. The first bonding insulating layer 13 may be a single layer. The first bonding insulating layer 13 may be a multilayer. The second bonding insulating layer 14 may be located between the second semiconductor structure SS2 and the second bonding layer 12 to protect the second bonding layer 12 during the manufacturing process. The second bonding insulating layer 14 may be a single layer. The second bonding insulating layer 14 may be a multilayer. The first bonding insulating layer 13 and the second bonding insulating layer 14 may include the same or different insulating materials, such as oxide, nitride, or TEOS.

[0025] The bonding pad 15 may extend into the bonding layer B and may pass through the first bonding layer 11. In an embodiment, the bonding pad 15 may extend through the first bonding layer 11 and the first bonding insulation layer 13 to be electrically connected to the first interconnect structure IC1. The bonding pad 15 may be electrically connected to the peripheral circuit of the first semiconductor structure SS1 through the first interconnect structure IC1.

[0026] The contact plug 16 may extend through the second semiconductor structure SS2 into the bonding layer B and may pass through the second bonding layer 12. In an embodiment, the contact plug 16 may extend through the gate structure, source structure, interlayer insulating layer, etc. of the second semiconductor structure SS2 and may pass through the second bonding insulating layer 14. The contact plug 16 may be electrically connected to the bonding pad 15 at the bonding interface IF.

[0027] Reference Figure 1B Contact plug 16 may include a barrier layer 16A and a metal layer 16B located in barrier layer 16A. Barrier layer 16A may surround the sidewalls of metal layer 16B and may extend between metal layer 16B and bonding pad 15. Barrier layer 16A may contact bonding pad 15. Barrier layer 16A may have a substantially uniform thickness along its entire extent.

[0028] According to the above structure, the bonding structure BS may include the bonding pad 15 corresponding to the first semiconductor structure SS1, and may not include the bonding pad corresponding to the second semiconductor structure SS2. Instead, the contact plug 16 passing through the second semiconductor structure SS2 may be directly connected to the bonding pad 15. The contact plug 16 may pass through the second semiconductor structure SS2, the second bonding insulation layer 14, and the second bonding layer 12, and may be directly connected to the bonding pad 15.

[0029] Figure 2A and Figure 2B is a cross-sectional view illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A and Figure 2B yes Figure 1AAn enlarged view of region A. Hereinafter, descriptions repeated with the above contents may be omitted.

[0030] Reference Figure 2A The semiconductor device may include a first bonding layer 11, a second bonding layer 12, a first bonding insulating layer 13, a second bonding insulating layer 14, a bonding pad 15, and a contact plug 16. The contact plug 16 may pass through the second bonding insulating layer 14 and the second bonding layer 12 and may extend into the first bonding layer 11.

[0031] The lower surface of the contact plug 16 may be in contact with the bonding pad 15. The contact surface between the contact plug 16 and the bonding pad 15 may be flat or may include a curved surface. In an embodiment, the upper surface of the bonding pad 15 may be positioned lower than the upper surface of the first bonding layer 11 and may include a curved surface. This structure may be due to a pit caused during the planarization process. Due to the pit, a step may exist between the upper surface of the bonding pad 15 and the upper surface of the first bonding layer 11, and the step may be filled by the contact plug 16.

[0032] The contact plug 16 may include a through portion 16C and an extended portion 16D. The through portion 16C may pass through the second bonding layer 12 and the second bonding insulation layer 14 and may extend into the second semiconductor structure SS2. The through portion 16C may have a conical or arched cross-section. The extended portion 16D may fill the step between the bonding pad 15 and the first bonding layer 11. The extended portion 16D may extend into the first bonding layer 11 and may have a width greater than that of the through portion 16C. The extended portion 16D may have a flat upper surface at the bonding interface IF, and a lower surface in contact with the bonding pad 15 may include a curved surface.

[0033] Reference Figure 2B The semiconductor device may include a first bonding layer 11, a second bonding layer 12, a first bonding insulating layer 13, a second bonding insulating layer 14, a bonding pad 15, and a contact plug 16. The contact plug 16 may pass through the second bonding insulating layer 14 and the second bonding layer 12 and may extend into the first bonding layer 11.

[0034] Foreign matter 17 may be present between the bonding pad 15 and the second bonding layer 12. Foreign matter 17 may be a byproduct caused by the manufacturing process. In an embodiment, foreign matter 17 may be an etching byproduct or a bonding byproduct, or may be a polymer-based material. Foreign matter 17 may not be present between the bonding pad 15 and the contact plug 16.

[0035] According to the above structure, the contact plug 16 may extend into the first bonding layer 11. The lower surface of the contact plug 16 may include a curved surface and may protrude into the bonding pad 15. Therefore, the contact area between the bonding pad 15 and the contact plug 16 may be increased, and foreign matter 17 may be removed between the bonding pad 15 and the contact plug 16 to improve bonding defects.

[0036] Figure 3 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0037] Reference Figure 3 The semiconductor device may include a first semiconductor structure SS1, a second semiconductor structure SS2, a bonding structure BS, and contact plugs 36A and 36B. The bonding structure BS may be located between the first semiconductor structure SS1 and the second semiconductor structure SS2.

[0038] The first semiconductor structure SS1 may include a substrate 30, peripheral circuits PC1 and PC2, a first interlayer insulating layer IL1, and a first interconnect structure IC1. The first peripheral circuit PC1 may be a page buffer, and the second peripheral circuit PC2 may be a row decoder. The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1. The first interconnect structure IC1 may be electrically connected to the peripheral circuits PC1 and PC2 and may include vias and / or lines.

[0039] The second semiconductor structure SS2 may include a source structure S, a gate structure GST, a channel structure CH, a slit structure SLS, a second interlayer insulating layer IL2, and a second interconnect structure IC2. The gate structure GST may be located on the source structure S and may include gate lines 37 and insulating layers 38 alternately stacked. In embodiments, the gate lines 37 may be source select lines, word lines, and / or drain select lines. Each channel structure CH may extend through the gate structure GST and may be connected to the source structure S. The slit structure SLS may extend through the gate structure GST and may include an insulating material, a semiconductor material, or a conductive material.

[0040] The second interconnect structure IC2 may be located in the second interlayer insulating layer IL2. The second interconnect structure IC2 may be connected to the channel structure CH, the slit structure SLS, the gate line 37, etc., and may include vias and / or lines. In an embodiment, the second interconnect structure IC2 may include one or more bit lines connected to the channel structure CH.

[0041] The bonding structure BS may include a first bonding layer 31, a second bonding layer 32, a first bonding insulating layer 33, a second bonding insulating layer 34, and bonding pads 35A and 35B. Contact plugs 36A and 36B may pass through the second semiconductor structure SS2 and may be directly connected to the bonding pads 35A and 35B. The peripheral circuits PC1 and PC2 and the memory cell array CA may be electrically connected through the contact plugs 36A and 36B and the bonding pads 35A and 35B.

[0042] In an embodiment, the first contact plug 36A may be connected to the bit line through the second interconnect structure IC2 and may extend through the gate structure GST and the source structure S. The first contact plug 36A may pass through the second bonding insulating layer 34 and the second bonding layer 32 to be electrically connected to the first bonding pad 35A. In this case, the bit line of the memory cell array CA and the page buffer of the first peripheral circuit PC1 can be connected through the first contact plug 36A and the first bonding pad 35A.

[0043] In an embodiment, the second contact plug 36B may be connected to the gate line 37 through the second interconnect structure IC2 and may extend through the gate structure GST. The second contact plug 36B may pass through the second bonding insulation layer 34 and the second bonding layer 32 to be electrically connected to the second bonding pad 35B. In this case, the gate line 37 of the memory cell array CA and the row decoder of the second peripheral circuit PC2 can be connected through the second contact plug 36B and the second bonding pad 35B.

[0044] According to the above structure, the contact plugs 36A and 36B passing through the second semiconductor structure SS2 may extend into the bonding structure BS and may be directly connected to the bonding pads 35A and 35B. Therefore, the bonding structure BS may be simplified.

[0045] Figures 4A to 4C 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0046] Reference Figure 4A The semiconductor device may include a first semiconductor structure SS1, a second semiconductor structure SS2, and a third semiconductor structure SS3, a first bonding structure BS1 and a second bonding structure BS2, and contact plugs 36A, 36B1, 36B2, 46A, and 46B. The first bonding structure BS1 may be located between the first semiconductor structure SS1 and the second semiconductor structure SS2. The second bonding structure BS2 may be located between the second semiconductor structure SS2 and the third semiconductor structure SS3.

[0047] The first semiconductor structure SS1 may include a substrate 30, peripheral circuits PC1 and PC2, a first interlayer insulating layer IL1, and a first interconnection structure IC1. The first interlayer insulating layer IL1 may be formed on the substrate 30, and the first interconnection structure IC1 may be formed within the first interlayer insulating layer IL1. The second semiconductor structure SS2 may include a source structure S, a first gate structure GST1, a channel structure CH, a slit structure SLS, a second interlayer insulating layer IL2, and a second interconnection structure IC2. The first gate structure GST1 may include alternately stacked gate lines 37 and insulating layers 38, and may include a first stepped structure.

[0048] The third semiconductor structure SS3 may include a source structure S, a second gate structure GST2, a channel structure CH, a slit structure SLS, a third interlayer insulating layer IL3, and a third interconnect structure IC3. The second gate structure GST2 may be located on the source structure S and may include gate lines 47 and insulating layers 48 alternately stacked. In an embodiment, the gate lines 47 may be source select lines, word lines, or drain select lines. The second gate structure GST2 may include a second stepped structure. The first stepped structure and the second stepped structure may be arranged in a staggered manner so as not to overlap.

[0049] The third interconnect structure IC3 may be located in the third interlayer insulating layer IL3. The third interconnect structure IC3 may be connected to the channel structure CH, the slit structure SLS, the gate line 47, etc., and may include a via and / or a line. In an embodiment, the third interconnect structure IC3 may include a bit line connected to the channel structure CH.

[0050] The first bonding structure BS1 may include first and second bonding layers 31 and 32, first and second bonding insulating layers 33 and 34, and bonding pads 35A, 35B1, and 35B2. The second bonding structure BS2 may include third and fourth bonding layers 41 and 42, third and fourth bonding insulating layers 43 and 44, and bonding pads 45A and 45B.

[0051] Contact plugs 46A and 46B may extend through the third semiconductor structure SS3 and may be directly connected to bonding pads 45A and 45B. The first and second memory cell arrays CA1 and CA2 may be electrically connected through the contact plugs 46A and 46B and the bonding pads 45A and 45B.

[0052] In an embodiment, the third contact plug 46A may be electrically connected to the bit line and may extend through the second gate structure GST2 and the source structure S. The third contact plug 46A may pass through the fourth bonding insulation layer 44 and the fourth bonding layer 42 to be electrically connected to the third bonding pad 45A. The third bonding pad 45A may be connected to the first contact plug 36A through the second interconnect structure IC2. In this case, the third contact plug 46A, the third bonding pad 45A, the first contact plug 36A, and the first bonding pad 35A may be electrically connected. Therefore, the bit line of the second memory cell array CA2 and the bit line of the first memory cell array CA1 may be commonly connected to the page buffer of the first peripheral circuit PC1.

[0053] In an embodiment, the fourth contact plug 46B may be electrically connected to the gate line of the second gate structure GST2 and may extend through the second stepped structure of the second gate structure GST2. The fourth contact plug 46B may pass through the fourth bonding insulation layer 44 and the fourth bonding layer 42 to be electrically connected to the fourth bonding pad 45B. The fourth bonding pad 45B may be connected to the second contact plug 36B2 through the second interconnect structure IC2. In this case, the fourth contact plug 46B, the fourth bonding pad 45B, the second contact plug 36B2, and the second bonding pad 35B2 may be electrically connected. Therefore, the gate line 47 of the second memory cell array CA2 may be connected to the row decoder of the second peripheral circuit PC2.

[0054] Reference Figure 4B , the semiconductor device may include a first semiconductor structure SS1, a first bonding structure BS1, a second semiconductor structure SS2, a second bonding structure BS2, a third semiconductor structure SS3, and contact plugs 36A, 36B, 36C, 46A, 46B, and 46C.

[0055] The first gate structure GST1 of the second semiconductor structure SS2 may include a first stepped structure, and the second gate structure GST2 of the third semiconductor structure SS3 may include a second stepped structure. The first stepped structure and the second stepped structure may be positioned to overlap. The fourth contact plug 46B may extend through the second stepped structure, and the second contact plug 36B may extend through the first stepped structure. The fourth contact plug 46B, the fourth bonding pad 45B, the second contact plug 36B, and the second bonding pad 35B may be commonly connected to the second peripheral circuit PC2. Therefore, the first memory cell array CA1 and the second memory cell array CA2 may share the second peripheral circuit PC2, and the same operating voltage may be applied to the gate lines 37 and 47 located on the same layer.

[0056] The first bonding structure BS1 may further include a fifth bonding pad 35C, and a fifth contact plug 36C passing through the second semiconductor structure SS2 may be electrically connected to the fifth bonding pad 35C. The fifth contact plug 36C may extend through the second interlayer insulating layer IL2 into the first bonding structure BS1 and may be directly connected to the fifth bonding pad 35C.

[0057] The second bonding structure BS2 may further include a sixth bonding pad 45C, and a sixth contact plug 46C passing through the third semiconductor structure SS3 may be electrically connected to the sixth bonding pad 45C. The sixth contact plug 46C may extend through the third interlayer insulating layer IL3 into the second bonding structure BS2 and may be directly connected to the sixth bonding pad 45C. The sixth bonding pad 45C may be electrically connected to the fifth contact plug 36C through the second interconnect structure IC2.

[0058] The first semiconductor structure SS1 may further include a third peripheral circuit PC3. The third semiconductor structure SS3 may further include an uppermost metal line 49. The uppermost metal line 49 may be an external connection pad, a power transmission line, or a signal transmission line. The uppermost metal line 49 and the third peripheral circuit PC3 may be electrically connected to each other via the sixth contact plug 46C, the sixth bonding pad 45C, the fifth contact plug 36C, and the fifth bonding pad 35C. For example, the third peripheral circuit PC3 may be a logic circuit, an analog circuit, an input / output circuit, or the like.

[0059] Reference Figure 4C The semiconductor device may include, in the order described, a first semiconductor structure SS1, a first bonding structure BS1, a second semiconductor structure SS2, a second bonding structure BS2, a third semiconductor structure SS3, a third bonding structure BS3, and a fourth semiconductor structure SS4. The semiconductor device may also include contact plugs 36A, 36B, 36C, 46A, 46B, 46C, 56A, 56B, and 56C.

[0060] The fourth semiconductor structure SS4 may include a source structure S, a third gate structure GST3, a channel structure CH, a slit structure SLS, a fourth interlayer insulating layer IL4, and a fourth interconnect structure IC4. The third gate structure GST3 may be located on the source structure S and may include gate lines 57 and insulating layers 58 alternately stacked. In an embodiment, the gate lines 57 may be source select lines, word lines, or drain select lines. The third gate structure GST3 may include a third stepped structure. The first stepped structure, the second stepped structure, and the third stepped structure may be arranged to overlap.

[0061] The fourth interconnection structure IC4 may be located in the fourth interlayer insulating layer IL4. The fourth interconnection structure IC4 may be connected to the channel structure CH, the slit structure SLS, the gate line 57, etc., and may include a via and / or a line. In an embodiment, the fourth interconnection structure IC4 may include a bit line connected to the channel structure CH.

[0062] The third bonding structure BS3 may include a fifth bonding layer 51, a sixth bonding layer 52, a fifth bonding insulation layer 53, a sixth bonding insulation layer 54, and bonding pads 55A, 55B, and 55C. Contact plugs 56A, 56B, and 56C may extend through the fourth semiconductor structure SS4 and may extend into the third bonding structure BS3 to be directly connected to the bonding pads 55A, 55B, and 55C.

[0063] In an embodiment, the seventh contact plug 56A may be electrically connected to the bit line and may extend through the third gate structure GST3 and the source structure S. The seventh contact plug 56A may pass through the sixth bonding insulating layer 54 and the sixth bonding layer 52 to be electrically connected to the seventh bonding pad 55A. Therefore, the first memory cell array CA1, the second memory cell array CA2, and the third memory cell array CA3 may share the page buffer of the first peripheral circuit PC1.

[0064] In an embodiment, the eighth contact plug 56B may be connected to the gate line 57 of the third memory cell array CA3 and may extend through the third stepped structure of the third gate structure GST3. The eighth contact plug 56B may pass through the sixth bonding insulating layer 54 and the sixth bonding layer 52 to be electrically connected to the eighth bonding pad 55B. Therefore, the first memory cell array CA1, the second memory cell array CA2, and the third memory cell array CA3 may share the row decoder of the second peripheral circuit PC2.

[0065] In an embodiment, the ninth contact plug 56C may pass through the fourth interlayer insulating layer IL4 to be electrically connected to the ninth bonding pad 55C. Thus, the uppermost metal line 59 and the third peripheral circuit PC3 may be electrically connected through the ninth contact plug 56C, the ninth bonding pad 55C, the sixth contact plug 46C, the sixth bonding pad 45C, the fifth contact plug 36C, and the fifth bonding pad 35C. For example, the third peripheral circuit PC3 may be a logic circuit, an analog circuit, an input / output circuit, or the like.

[0066] According to the above structure, three or more semiconductor structures SS1, SS2, SS3, and SS4 can be multi-jointed. Contact plugs 36A, 36B, 36B1, and 36B2 passing through the second semiconductor structure SS2 can extend into the first joint structure BS1 and can be directly connected to the bonding pads 35A, 35B, 35B1, and 35B2. Contact plugs 46A, 46B, and 46C passing through the third semiconductor structure SS3 can extend into the second joint structure BS2 and can be directly connected to the bonding pads 45A, 45B, and 45C. Contact plugs 56A, 56B, and 56C passing through the fourth semiconductor structure SS4 can extend into the third joint structure BS3 and can be directly connected to the bonding pads 55A, 55B, and 55C. Therefore, the joint structures BS1, BS2, and BS3 can be simplified.

[0067] In addition, the peripheral circuits PC1 and PC2 and the memory cell arrays CA1 and CA2 may be electrically connected through the bonding pads 35A, 35B1, 35B2, 45A, 45B, 55A, and 55B and the contact plugs 36A, 36B1, 36B2, 46A, 46B, 56A, and 56B. Therefore, the first memory cell array CA1 and the second memory cell array CA2 may share the peripheral circuits PC1 and PC2.

[0068] 5A to 5D 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0069] Reference Figure 5A , a first wafer WF1 including a first bonding layer 61 and bonding pads 65 may be formed. The first wafer WF1 may also include a first semiconductor structure SS1 such as a peripheral circuit and a memory cell array. The first semiconductor structure SS1 may include a first interconnect structure IC1, and the bonding pads 65 may be connected to the first interconnect structure IC1. The first wafer WF1 may also include a first bonding insulating layer 63 disposed between the first bonding layer 61 and the first semiconductor structure SS1. The bonding pads 65 may pass through the first bonding layer 61 and the first bonding insulating layer 63. The first bonding layer 61 may include SiCN, and the first bonding insulating layer 63 may include an insulating material such as an oxide or a nitride.

[0070] A second wafer WF2 including a second bonding layer 62 and a sacrificial plug 66 may be formed. The second wafer WF2 may also include a second semiconductor structure SS2 such as a peripheral circuit and a memory cell array. The second wafer WF2 may also include a second bonding insulating layer 64, and the sacrificial plug 66 may pass through the second semiconductor structure SS2, the second bonding layer 62, and the second bonding insulating layer 64. The second bonding layer 62 may include SiCN, and the second bonding insulating layer 64 may include an insulating material such as an oxide or a nitride. The sacrificial plug 66 may include a material having a high etching selectivity relative to the second bonding layer 62 and the second bonding insulating layer 64. The sacrificial plug 66 may include a conductive material such as tungsten, polysilicon, titanium nitride, or an insulating material such as a nitride.

[0071] Reference Figure 5B , the first bonding layer 61 and the second bonding layer 62 can be bonded so that the bonding pad 65 and the sacrificial plug 66 are connected. Thus, a bonding structure BS can be formed. Through bonding, the surface of the first bonding layer 61 and the surface of the second bonding layer 62 can be chemically bonded. In an embodiment, the carbon (C) and nitrogen (N) of the SiCN layer can be removed, and a Si-O-Si bond can be generated. The bonding pad 65 and the sacrificial plug 66 can be connected to each other by directly contacting each other without chemical bonding.

[0072] Reference Figure 5C , the sacrificial plug 66 may be removed to form an opening OP. The opening OP may pass through the second semiconductor structure SS2, the second bonding insulating layer 64, and the second bonding layer 62 to at least partially expose the top surface of the bonding pad 65. The opening OP may have a high aspect ratio. In addition, the second bonding layer 62 and the second bonding insulating layer 64 may be exposed through the opening OP.

[0073] Reference Figure 5D A contact plug 67 electrically connected to the bonding pad 65 may be formed in the opening OP. The contact plug 67 may be formed by depositing a conductive material along the surface of the bonding pad 65 and the inner surface of the opening OP. A barrier layer 67A may be formed in the opening OP, and a metal layer 67B may be formed in the barrier layer 67A.

[0074] According to the above-described manufacturing method, after the first wafer WF1 and the second wafer WF2 are bonded, the sacrificial plug 66 may be replaced with the contact plug 67. The bonding pad 65 and the sacrificial plug 66 may not be chemically bonded, and the contact plug 67 may be formed by depositing a conductive material on the bonding pad 65. Therefore, even if the bonding pad 65 and the contact plug 67 are not directly bonded, the bonding pad 65 and the contact plug 67 may be electrically connected.

[0075] In order to directly bond the bonding pads, both the bonding pad 65 and the contact plug 67 need to be formed of copper, but according to embodiments of the present disclosure, the materials of the bonding pad 65 and the contact plug 67 may not be limited to copper. In embodiments, the bonding pad 65 and the contact plug 67 may be formed of a material such as tungsten-tungsten, which is difficult to use due to limitations imposed by thermal processes, or the bonding pad 65 and the contact plug 67 may be formed of a different type of material such as copper-tungsten.

[0076] Figures 6A to 6C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 6A yes Figure 5B An enlarged view of region B, Figure 6B yes Figure 5C An enlarged view of region C, Figure 6C yes Figure 5D Hereinafter, descriptions repeated with the above contents may be omitted.

[0077] Reference Figure 6A , by bonding the first bonding layer 61 and the second bonding layer 62, the bonding pad 65 and the sacrificial plug 66 may be connected. At this time, a gap G may exist between the bonding pad 65 and the sacrificial plug 66. The gap G may be caused by a pit caused in the planarization process for forming the bonding pad 65. Due to the pit, the upper surface of the bonding pad 65 may be positioned lower than the upper surface of the first bonding layer 61. In this case, the first bonding layer 61 and the second bonding layer 62 may contact each other to be bonded to each other, but a gap G may exist between the bonding pad 65 and the sacrificial plug 66, and the first bonding layer 61 and the second bonding layer 62 may not contact each other.

[0078] Reference Figure 6B , the sacrificial plug 66 may be removed to form an opening OP. The opening OP may be connected to the gap G and extend into the first bonding layer 61.

[0079] Reference Figure 6C , a contact plug 67 may be formed in the opening OP. In an embodiment, after forming the barrier layer 67A in the opening OP, the metal layer 67B may be formed. In an embodiment, the opening OP may be filled with the metal layer 67B without forming the barrier layer 67A.

[0080] According to the above-described manufacturing method, the contact plug 67 can be formed after wafer bonding. Therefore, even if a gap G is formed between the bonding pad 65 and the sacrificial plug 66, the gap G can be filled by the contact plug 67. Therefore, the bonding pad 65 and the contact plug 67 can be connected without the gap G, and an ohmic contact can be formed.

[0081] 7A to 7Cis a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 7A yes Figure 5B An enlarged view of region B, Figure 7B yes Figure 5C An enlarged view of region C, Figure 7C yes Figure 5D Hereinafter, descriptions repeated with the above contents may be omitted.

[0082] Reference Figure 7A By bonding the first bonding layer 61 and the second bonding layer 62, the bonding pad 65 and the sacrificial plug 66 can be connected. At this time, foreign matter 71 may be present between the bonding pad 65 and the sacrificial plug 66. The foreign matter 71 may be a byproduct of the manufacturing process and may be etching residue, bonding residue, etc. The foreign matter 71 may be a polymer-based material, and due to the foreign matter 71, the bonding pad 65 and the sacrificial plug 66 may not be directly connected, or the contact area between them may be reduced.

[0083] Reference Figure 7B , the sacrificial plug 66 may be removed to form an opening OP. The foreign matter 71 may be exposed through the opening OP, and at least a portion of the exposed foreign matter 71 may be removed. In an embodiment, the sacrificial plug 66 may be removed by a back-out process, and then the foreign matter 71 may be removed by an etching process. A portion of the foreign matter 71 exposed through the opening OP may be removed, and a portion interposed between the bonding pad 65 and the second bonding layer 62 may remain without being removed.

[0084] Reference Figure 7C , a contact plug 67 may be formed in the opening OP. In an embodiment, after forming the barrier layer 67A in the opening OP, the metal layer 67B may be formed. In an embodiment, the opening OP may be filled with the metal layer 67B without forming the barrier layer 67A.

[0085] According to the above-described manufacturing method, the contact plug 67 can be formed after wafer bonding. Therefore, even when foreign matter 71 exists between the bonding pad 65 and the sacrificial plug 66, the foreign matter 71 can be removed by replacing the sacrificial plug 66 with the contact plug 67. Therefore, the bonding pad 65 and the contact plug 67 can be connected without the foreign matter 71, and an ohmic contact can be formed.

[0086] Figures 8A to 8G 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0087] Reference Figure 8A and Figure 8B , a second wafer WF2 including the first sacrificial plugs 86 and the second bonding layer 81B may be formed.

[0088] First, refer to Figure 8A , a first preliminary bonding structure 81 may be formed on the second substrate 100. The first preliminary bonding structure 81 may include a second bonding layer 81B. The first preliminary bonding structure 81 may also include bonding insulation layers 81A and 81C. The second bonding layer 81B may be interposed between the bonding insulation layers 81A and 81C. The bonding insulation layers 81A and 81C may be made of an insulating material (e.g., oxide or nitride) suitable for protecting the second bonding layer 81B during the manufacturing process. The second bonding layer 81B may form a bonding interface by chemical bonding and may include SiCN.

[0089] Subsequently, a second semiconductor structure SS2 may be formed on the first preliminary bonding structure 81. The second semiconductor structure SS2 may include a first memory cell array CA1. The second semiconductor structure SS2 may include a first sacrificial plug 86, a source structure S, a first gate structure GST1, a channel structure CH, a slit structure SLS, and a second interlayer insulating layer IL2. The gate structure GST may include gate lines 97 and insulating layers 98 alternately stacked. The first sacrificial plug 86 may extend through the first gate structure GST1 and the source structure S, or may extend through the second interlayer insulating layer IL2. The first sacrificial plug 86 may extend into the first preliminary bonding structure 81. In an embodiment, the first sacrificial plug 86 may pass through the second bonding insulating layer 81C and the second bonding layer 81B and contact the top surface of the first bonding insulating layer 81A.

[0090] In an embodiment, the second semiconductor structure SS2 may include a stack instead of the gate structure GST. The stack may include a sacrificial layer instead of the gate line 97. The stack may include alternately stacked sacrificial layers and insulating layers 98. In this case, a sacrificial slit structure may be formed instead of the slit structure SLS.

[0091] Subsequently, a first sacrificial bonding structure 82 may be formed on the second semiconductor structure SS2. The first sacrificial bonding structure 82 may include a first sacrificial bonding layer 82B and may further include a first sacrificial bonding insulating layer 82A, with the first sacrificial bonding insulating layer 82A disposed between the first sacrificial bonding layer 82B and the second interlayer insulating layer IL2. The first sacrificial bonding insulating layer 82A may be formed on the second semiconductor structure SS2.

[0092] Then, refer to Figure 8B , a second sacrificial bonding structure 83 may be formed on the carrier wafer 200. The second sacrificial bonding structure 83 may include a second sacrificial bonding layer 83B, and may further include a second sacrificial bonding insulating layer 83A.

[0093] Subsequently, the first sacrificial bonding layer 82B and the second sacrificial bonding layer 83B may be bonded, and the second substrate 100 and the bonding insulating layer 81A may be removed, thereby forming a second wafer W2 in which the second semiconductor structure SS2 is bonded to the carrier wafer 200 .

[0094] Reference Figure 8C , a first wafer WF1 including first bonding pads 85 and a first bonding layer 84B may be formed. First, a first semiconductor structure SS1 may be formed on a first substrate 300. The first semiconductor structure SS1 may include a peripheral circuit PC, and the peripheral circuit PC may include a page buffer, a row decoder, a logic circuit, an analog circuit, an input / output circuit, etc. The first semiconductor structure SS1 may also include a first interlayer insulating layer IL1 and a first interconnect structure IC1.

[0095] Subsequently, a second preliminary bonding structure 84 may be formed on the peripheral circuit PC. The second preliminary bonding structure 84 may include a first bonding layer 84B and a first bonding pad 85, and may also include a bonding insulation layer 84A. The first bonding pad 85 may pass through the first bonding layer 84B and the bonding insulation layer 84A to be electrically connected to the peripheral circuit PC through the first interconnect structure IC1.

[0096] Subsequently, the first wafer WF1 and the second wafer WF2 can be bonded. The first bonding layer 84B and the second bonding layer 81B can be bonded so that the first sacrificial plug 86 and the first bonding pad 85 are connected. As a result, the surfaces of the first bonding layer 84B and the second bonding layer 81B can be chemically bonded. The first sacrificial plug 86 and the first bonding pad 85 can be in physical contact without being chemically bonded. A gap may exist between the first sacrificial plug 86 and the first bonding pad 85, or foreign matter may be inserted.

[0097] Reference Figure 8D The first preliminary bonding structure 81 and the second preliminary bonding structure 84 may be bonded, thereby forming a first bonding structure BS1. Subsequently, the carrier wafer 200, the second sacrificial bonding structure 83, and the first sacrificial bonding structure 82 may be removed to expose the second semiconductor structure SS2 and the first sacrificial plug 86.

[0098] Subsequently, the first sacrificial plug 86 may be removed by selective etching to form a first opening OP1 . The first opening OP1 is formed to expose the first bonding pad 85 .

[0099] If there is a gap between the first sacrificial plug 86 and the first bonding pad 85 , the gap is exposed through the first opening OP1 . Likewise, if there is foreign matter between the first sacrificial plug 86 and the first bonding pad 85 , the foreign matter is also exposed through the first opening OP1 .

[0100] Reference Figure 8E, a first contact plug 87 may be formed in the first opening OP1. The first contact plug 87 may be electrically connected to the first bonding pad 85. When a gap exists between the first sacrificial plug 86 and the first bonding pad 85, the first contact plug 87 may be formed between the first opening OP1 and the gap. When foreign matter exists between the first sacrificial plug 86 and the first bonding pad 85, the first contact plug 87 may be formed after removing the foreign matter. Thus, bonding defects may be reduced.

[0101] In an embodiment, when the second semiconductor structure SS2 includes a stack and a sacrificial slit structure, the sacrificial slit structure may be removed to form a slit, and the sacrificial layer may be replaced with the gate line 97 through the slit. Subsequently, a slit structure SLS may be formed in the slit. Thus, a gate structure GST may be formed.

[0102] Subsequently, a second interconnect structure IC2 connected to the first contact plug 87, the channel structure CH, the slit structure SLS, etc. may be formed. Subsequently, a third preliminary bonding structure 88 may be formed. The third preliminary bonding structure 88 may include a third bonding layer 88B and a second bonding pad 89, and may also include a bonding insulation layer 88A. The second bonding pad 89 may extend through the third bonding layer 88B and the bonding insulation layer 88A to electrically connect to the second interconnect structure IC2. The second bonding pad 89 may be electrically connected to the first contact plug 87.

[0103] Reference Figure 8F , a third wafer WF3 including a fourth bonding layer 91A and second sacrificial plugs 92 may be formed. The third wafer W3 may include a fourth preliminary bonding structure 91. The fourth preliminary bonding structure 91 may include a fourth bonding layer 91A and may further include a bonding insulation layer 91B.

[0104] The third wafer WF3 may include a third semiconductor structure SS3. The third semiconductor structure SS3 may include a second memory cell array CA2. The third semiconductor structure SS3 may include a second sacrificial plug 92, a source structure S, a second gate structure GST2, a channel structure CH, a slit structure SLS, and a third interlayer insulating layer IL3. The second gate structure GST2 may include alternately stacked gate lines 107 and insulating layers 108. The second sacrificial plug 92 may extend through the second gate structure GST2 and the source structure S, or may extend through the third interlayer insulating layer IL3. The second sacrificial plug 92 may extend into the fourth preliminary bonding structure 91. In an embodiment, the second sacrificial plug 92 may pass through the bonding insulating layer 91B and the fourth bonding layer 91A.

[0105] Subsequently, the third bonding layer 88B and the fourth bonding layer 91A may be bonded to connect the second sacrificial plug 92 and the second bonding pad 89. The third bonding layer 88B and the fourth bonding layer 91A may be bonded to form a second bonding structure BS2. When the third wafer WF3 is bonded, as previously described with reference to FIG. Figures 8A to 8C As depicted, a carrier wafer may be used, and the carrier wafer may be removed to expose the second sacrificial plugs 92 .

[0106] Reference Figure 8G , the second sacrificial plug 92 may be removed to form a second opening OP2 exposing the second bonding pad 89. Subsequently, a second contact plug 93 may be formed in the second opening OP2. The second contact plug 93 may be directly connected to the second bonding pad 89.

[0107] Subsequently, a third interconnection structure IC3 connected to the second contact plug 93 , the channel structure CH, the slit structure SLS, etc. may be formed.

[0108] According to the above-described manufacturing method, a sacrificial plug can be formed when the wafer is formed, and the sacrificial plug can be replaced with a contact plug after the wafer is bonded. Therefore, instead of bonding between bonding pads, the bonding pad and the contact plug can be directly connected. In conventional methods of bonding between two bonding pads, the material of the bonding pad is generally limited to copper. However, according to embodiments of the present disclosure, an expanded range of materials can be used for the bonding pad and the contact plug.

[0109] The structures and manufacturing methods according to the above-described embodiments can be applied to semiconductor devices of various structures. Figure 9 and Figure 10 A schematic configuration of a semiconductor device to which the above-described embodiment is applied is shown.

[0110] Figure 9 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0111] Reference Figure 9 The semiconductor device may include a substrate SUB, a peripheral circuit PC formed over the substrate SUB, and a memory cell array CA formed over the peripheral circuit PC. In the illustrated embodiment, the peripheral circuit PC and the memory cell array CA may be formed over or on the same substrate SUB.

[0112] The substrate SUB may be made of or include a semiconductor material. In embodiments, the semiconductor material may include at least one of a Group IV semiconductor, a Group III-V compound semiconductor, and a Group II-VI compound semiconductor. For example, a Group IV semiconductor may include single crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium (SiGe). A Group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. A Group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0113] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include an organic material. In an embodiment, the substrate SUB may include graphene.

[0114] The substrate SUB may be a bulk wafer or an epitaxial layer grown by a selective epitaxial growth (SEG) method. The substrate SUB may be a layer formed by a metal induced lateral crystallization (MILC) method and may partially include metal. The substrate SUB may have a single crystal, a polycrystalline, or an amorphous state. The substrate SUB may include impurities of Group II, Group III, Group IV, Group V, or Group VI. In an embodiment, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0115] The peripheral circuit PC may be disposed between the substrate SUB and the memory cell array CA. The peripheral circuit PC may include a row decoder, a column decoder, a page buffer, a logic circuit, a control circuit, a sense amplifier, an input / output circuit, and the like. In embodiments, the peripheral circuit PC may include NMOS transistors, PMOS transistors, resistors, capacitors, and the like. The peripheral circuit PC may also include an interconnect structure. The interconnect structure may serve as a path for transmitting an operating voltage and may include contact plugs, wires, and the like.

[0116] The memory cell array CA may include memory cells. In an embodiment, the memory cell array CA may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. In an embodiment, the memory cell array CA may include memory cells connected between word lines and bit lines. The memory cell array CA may also include an interconnect structure.

[0117] Figure 10 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0118] Reference Figure 10The semiconductor device may include a substrate SUB, a peripheral circuit PC, a bonding structure BS, and a memory cell array CA. For example, the peripheral circuit PC and the memory cell array CA may be formed on separate substrates and then bonded. The semiconductor device may also include a support base SP_B.

[0119] The substrate SUB can serve as a support for the process of forming the peripheral circuit PC. The supporting base SP_B can serve as a support for the process of forming the memory cell array CA. In an embodiment, after separately manufacturing a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer can be electrically connected via a bonding structure BS. After bonding, at least a portion of the supporting base SP_B of the first wafer can be removed. The supporting base SP_B can be completely removed or can partially remain on the memory cell array CA.

[0120] The support substrate SP_B may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or the like. The support substrate SP_B may be a bulk wafer, an epitaxial layer grown using a selective epitaxial growth (SEG) method, or a layer formed using a metal-induced lateral crystallization (MILC) method. The support substrate SP_B may be single crystal, polycrystalline, or amorphous. The support substrate SP_B may include impurities of Group II, Group III, Group IV, Group V, or Group VI.

[0121] The bonding structure BS can connect the memory cell array CA and the peripheral circuit PC. In embodiments, the memory cell array CA and the peripheral circuit PC can be bonded using a wafer-on-wafer bonding method, a chip-on-wafer bonding method, a chip-on-chip bonding method, or the like. The bonding structure BS may include a bonding pad, a bonding layer, a bonding interface, and the like. The bonding pad may include a metal and / or alloy such as copper and aluminum. The bonding interface may include a non-metal-non-metal interface, a metal-metal interface, and the like. The memory cell array CA and the peripheral circuit PC may be electrically connected via the bonding structure BS.

[0122] In an embodiment, the interconnect structures included in the memory cell array CA and / or the peripheral circuit PC can be directly connected without requiring a bonding pad. In an embodiment, a bonding layer included in the memory cell array CA and a bonding layer included in the peripheral circuit PC can be bonded to form a bonding interface, and the interconnect structures included in the memory cell array CA and the interconnect structures included in the peripheral circuit PC can be directly connected. Thus, contact plugs, lines, etc. formed on different wafers can be electrically connected without requiring separate bonding pads.

[0123] Other configurations can refer to the above Figure 9 those described are equal or similar.

[0124] The semiconductor device may have the above reference Figure 9 and Figure 10 The structures of the described embodiments may be combined, or may have partially modified structures. Figure 9 and Figure 10 In the described embodiment, the positions of the memory cell array CA and the peripheral circuit PC may be changed. At least one memory cell array CA and / or at least one peripheral circuit PC may be additionally bonded to a reference Figure 9 In an embodiment, a portion of the peripheral circuit PC may be provided in the memory cell array CA.

[0125] Although embodiments of the technical concepts of the present disclosure have been described with reference to the accompanying drawings, this is merely for the purpose of describing embodiments of the concepts of the present disclosure, and the present disclosure is not limited to the aforementioned embodiments. Within the scope of the technical concepts of the present disclosure, those skilled in the art may perform various permutations, modifications, changes, and combinations of the embodiments, which also fall within the scope of the present disclosure. Furthermore, these embodiments may be combined to form additional embodiments.

[0126] CROSS-REFERENCE TO RELATED APPLICATIONS

[0127] This application claims priority from Korean Patent Application No. 10-2024-0032127, filed on March 6, 2024, which is hereby incorporated by reference herein in its entirety.

Claims

1. A semiconductor device, comprising: a first semiconductor structure comprising a peripheral circuit and an interconnect structure electrically connected to the peripheral circuit; a second semiconductor structure; a bonding layer, the bonding layer being located between the first semiconductor structure and the second semiconductor structure; a bonding pad electrically connected to the interconnect structure, the bonding pad extending into the bonding layer; as well as a contact plug extending through the second semiconductor structure into the bonding layer, The contact plug is electrically connected to the bonding pad.

2. The semiconductor device according to claim 1, wherein The bonding layer includes a first bonding layer and a second bonding layer, wherein the second bonding layer is located between the first bonding layer and the second semiconductor structure. wherein the second bonding layer and the first bonding layer form a bonding interface, wherein the bonding pad passes through the first bonding layer, and The contact plug passes through the second bonding layer to be connected to the bonding pad at the bonding interface.

3. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a gate structure, a channel structure extending through the gate structure, and a memory cell stacked along the channel structure, wherein the contact plug extends through the gate structure.

4. The semiconductor device according to claim 3, wherein The second semiconductor structure further includes a source structure located below the gate structure, and wherein the contact plug passes through the source structure.

5. The semiconductor device according to claim 3, wherein The contact plug electrically connects the page buffer of the first semiconductor structure and the bit line of the second semiconductor structure. The semiconductor device according to claim 3 , wherein: The contact plug electrically connects the row decoder of the first semiconductor structure and the gate line of the second semiconductor structure.

7. The semiconductor device according to claim 1, wherein The contact plug includes a barrier layer and a metal layer located in the barrier layer.

8. The semiconductor device according to claim 7, wherein The barrier layer extends between the metal layer and the bond pad.

9. The semiconductor device according to claim 1, wherein The second semiconductor structure includes an interlayer insulating layer and an uppermost metal line, and The contact plug extends through the interlayer insulating layer to be electrically connected to the uppermost metal line.

10. The semiconductor device according to claim 9, wherein The contact plug electrically connects the peripheral circuit of the first semiconductor structure and the uppermost metal line of the second semiconductor structure.

11. The semiconductor device according to claim 2, wherein The contact plug includes: a through portion that passes through the second bonding layer and extends into the second semiconductor structure; and An extending portion extends into the first bonding layer and has a width greater than a width of the penetrating portion.

12. The semiconductor device according to claim 1, wherein A lower surface of the contact plug includes a curved surface.

13. The semiconductor device according to claim 1, further comprising: a first bonding insulating layer, the first bonding insulating layer being located between the first bonding layer and the first semiconductor structure; The bonding pad passes through the first bonding insulation layer.

14. The semiconductor device according to claim 1, further comprising: a second bonding insulating layer, the second bonding insulating layer being located between the second bonding layer and the second semiconductor structure; Wherein, the contact plug passes through the second bonding insulating layer.

15. A semiconductor device comprising: a first bonding layer; a first bonding pad passing through the first bonding layer; a second bonding layer, the second bonding layer forming a bonding interface with the first bonding layer; a first gate structure, the first gate structure being located on the second bonding layer; as well as a first contact plug extending through the first gate structure and the second bonding layer and electrically connected to the first bonding pad, Wherein, the first contact plug comprises: a metal layer; and A barrier layer surrounds sidewalls of the metal layer and extends between the metal layer and the first bonding pad.

16. The semiconductor device according to claim 15, wherein The barrier layer contacts the first bonding pad.

17. The semiconductor device according to claim 15, further comprising: a third bonding layer, the third bonding layer being located on the first gate structure; a second bonding pad passing through the third bonding layer and electrically connected to the first contact plug; a fourth bonding layer, wherein the fourth bonding layer forms a bonding interface with the third bonding layer; a second gate structure, the second gate structure being located on the fourth bonding layer; as well as A second contact plug extends through the second gate structure and the fourth bonding layer and is electrically connected to the second bonding pad.

18. The semiconductor device according to claim 15, further comprising: A page buffer is located under the first bonding layer and is electrically connected to the first contact plug through the first bonding pad.

19. The semiconductor device according to claim 15, further comprising: A row decoder is located under the first bonding layer and is electrically connected to the first contact plug through the first bonding pad.

20. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first wafer including a first bonding layer and a first bonding pad; forming a second wafer including a second bonding layer and a first sacrificial plug; bonding the first bonding layer and the second bonding layer so that the first bonding pad and the first sacrificial plug are connected; forming a first opening exposing the first bonding pad by removing the first sacrificial plug; as well as A first contact plug electrically connected to the first bonding pad is formed in the first opening.

21. The method according to claim 20, wherein The step of forming the first wafer includes the following steps: forming a peripheral circuit on the first substrate; forming the first bonding layer on the peripheral circuit; and The first bonding pad is formed through the first bonding layer and electrically connected to the peripheral circuit.

22. The method according to claim 20, wherein The step of forming the second wafer comprises the following steps: forming the second bonding layer on the second substrate; forming a gate structure on the second bonding layer; and The first sacrificial plug is formed extending through the gate structure and the second bonding layer.

23. The method according to claim 22, wherein The step of forming the second wafer comprises the following steps: forming a sacrificial bonding layer on the gate structure; bonding a carrier wafer to the sacrificial bonding layer; and The second substrate is removed.

24. The method according to claim 23, further comprising the steps of: After bonding the first bonding layer and the second bonding layer, removing the carrier wafer; as well as The sacrificial bonding layer is removed.

25. The method according to claim 20, wherein The step of forming the first contact plug includes the following steps: forming a barrier layer in the first opening; and A metal layer is formed in the barrier layer.

26. The method according to claim 20, wherein When the first bonding layer and the second bonding layer are bonded, the first bonding layer is in contact with the second bonding layer, and a gap exists between the first bonding pad and the first sacrificial plug.

27. The method according to claim 26, wherein The step of forming the first contact plug includes forming the first contact plug in the first opening and the gap.

28. The method according to claim 20, further comprising the steps of: forming a third bonding layer on the first contact plug; forming a second bonding pad passing through the third bonding layer and electrically connected to the first contact plug; forming a third wafer including a second sacrificial plug and a fourth bonding layer; bonding the third bonding layer and the fourth bonding layer so that the second sacrificial plug and the second bonding pad are connected; forming a second opening exposing the second bonding pad by removing the second sacrificial plug; as well as A second contact plug is formed in the second opening.

29. The method according to claim 20, further comprising the steps of: Before forming the first contact plug, foreign matter exposed through the first opening is removed.

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