High-speed clock phase interpolator control method, system, medium and equipment

Abstract

The invention provides a high-speed clock phase interpolator control method and system, a medium and equipment. The high-speed clock phase interpolator control method comprises the following steps: S1, adding weights of adjacent clocks to obtain a first clock phase CLKOi; s2, determining a second clock phase CLKOi45 based on a phase interval of 45 degrees between the two clock phase interpolators; and S3, obtaining a new clock phase CLKiavg based on the first clock phase CLKOi and the second clock phase CLKOi45. According to the novel phase interpolator provided by the invention, the clock phase interval ranges from 5.47 degrees to 5.72 degrees, and the variation range is 0.25 degrees; the method is more suitable for high-speed and high-precision clock design.

Description

Technical Field

[0001] The present invention relates to the technical field of phase interpolator control circuits, and more specifically, to a high-speed clock phase interpolator control method, system, medium and device, and more specifically, to a novel high-linearity high-speed clock phase interpolator control method and system. Background Art

[0002] High-speed clock phase interpolators are widely used in high-speed circuit design. Their principle is to obtain a new clock phase by adding the weights of adjacent clocks. Figure 1 The following figure shows the clock timing. CLK_0, CLK_90, CLK_180, and CLK_270 are the four-phase clock signals. If you want to get more phases, such as a new phase clock CLKO_i located between CLK_0 and CLK_90, you can configure CLK_0 and CLK_90 with different weights and add them together to generate the CLKO_i signal.

[0003] like Figure 2 Figure 2 shows the schematic diagram of a clock phase interpolator. Assuming the total clock weight is 1, to generate CLKO_i, CLK_90 is assigned a weight of a and CLK_0 is assigned a weight of 1-a. The two clocks are added together to generate the new clock CLKO_i. Its phase is arctan(a / (1-a)).

[0004] like Figure 3 FIG. 1 is a schematic diagram of a clock phase interpolator, in which multiplication and addition can be implemented using analog circuits (CML structure) or digital circuits (CMOS structure).

[0005] The advantage of implementing a phase interpolator using this method is its simple structure. However, a disadvantage is that, because different phases are generated through weighted matching, the interpolated clock naturally has poor phase linearity. For example, if 64 clock phases are generated per clock cycle, the ideal clock phase interval is 360 / 64 = 5.625 degrees. However, the actual clock phase interval ranges from 3.8 degrees to 7.1 degrees, with a variation of 3.3 degrees. This variation is unacceptable in high-speed, high-precision clock designs.

[0006] Patent document CN203722593U (application number: 201420045274.8) discloses a phase interpolator control circuit. The input high-speed serial data is sampled by an input sampler. The phase detector module detects the data bits and edge information and determines the phase relationship (lead or lag) between the sampling clock and the data. This phase relationship is used to perform coarse phase adjustment, select a phase interval, and simultaneously perform fine adjustment within the phase interval based on the weight information. If the interpolation is at the edge of the phase interval, only one side of the interval is changed and the weight factor is adjusted in the opposite direction, thereby ensuring continuous phase adjustment. Summary of the Invention

[0007] In view of the defects in the prior art, the object of the present invention is to provide a high-speed clock phase interpolator control method, system, medium and device.

[0008] A high-speed clock phase interpolator control method provided by the present invention includes:

[0009] Step S1: Obtain a first clock phase CLKO_i by adding adjacent clock weights;

[0010] Step S2: Determine the second clock phase CLKO_i45 based on the phase interval of the two clock phase interpolators being 45 degrees;

[0011] Step S3: Obtain a new clock phase CLK_iavg based on the first clock phase CLKO_i and the second clock phase CLKO_i45.

[0012] Preferably, the step S1 adopts:

[0013] CLKO_i=(1-a)CLK_x+aCLK_y

[0014] Where a represents the weight; CLK_x and CLK_y represent adjacent clocks.

[0015] Preferably, the step S2 adopts:

[0016] CLKO_i45=(0.5-a)CLK_x+(a+0.5)CLK_y.

[0017] Preferably, the step S3 adopts:

[0018] CLK_iavg=CLKO_i+CLKO_i45.

[0019] According to the present invention, a high-speed clock phase interpolator control system is provided, comprising:

[0020] Module M1: obtains the first clock phase CLKO_i by adding adjacent clock weights;

[0021] Module M2: Determine the second clock phase CLKO_i45 based on the phase interval of the two clock phase interpolators being 45 degrees;

[0022] Module M3: Obtaining a new clock phase CLK_iavg based on the first clock phase CLKO_i and the second clock phase CLKO_i45.

[0023] Preferably, the module M1 adopts:

[0024] CLKO_i=(1-a)CLK_x+aCLK_y

[0025] Where a represents the weight; CLK_x and CLK_y represent adjacent clocks.

[0026] Preferably, the module M2 adopts:

[0027] CLKO_i45=(0.5-a)CLK_x+(a+0.5)CLK_y.

[0028] Preferably, the module M3 adopts:

[0029] CLK_iavg=CLKO_i+CLKO_i45.

[0030] According to a computer-readable storage medium storing a computer program provided by the present invention, when the computer program is executed by a processor, the steps of the high-speed clock phase interpolator control method described above are implemented.

[0031] According to an electronic device provided by the present invention, the electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The electronic device is characterized in that when the computer program is executed by the processor, the steps of the high-speed clock phase interpolator control method described above are implemented.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The clock phase interval of the novel phase interpolator provided by the present invention is between 5.47 degrees and 5.72 degrees, with a variation range of 0.25 degrees; it is more suitable for high-speed and high-precision clock design;

[0034] 2. The structure of the present invention is simple and reliable. Especially in circuits requiring multi-phase clocks, the use of this structure can greatly simplify circuit design and reduce area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0036] Figure 1 This is the timing diagram of the clock phase interpolator.

[0037] Figure 2 This is the schematic diagram of the clock phase interpolator.

[0038] Figure 3 This is the clock phase interpolator architecture diagram.

[0039] Figure 4 This is the phase change diagram of the traditional phase interpolator clock (64-phase clock).

[0040] Figure 5 This is the schematic diagram of the new clock phase interpolator.

[0041] Figure 6 This is the architecture diagram of the new clock phase interpolator.

[0042] Figure 7 This is the phase change diagram of the new phase interpolator clock (64-phase clock). DETAILED DESCRIPTION

[0043] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0044] Example 1

[0045] According to the present invention, a novel high-linearity high-speed clock phase interpolator control method is provided, comprising:

[0046] like Figure 5 As shown in Figure 1, two clock phase interpolators are used, one to generate CLKO_i and the other to generate CLKO_i45, with a phase interval of 45 degrees between the two. The two phases are then added together to obtain the new clock phase CLK_iavg. The specific architecture diagram is shown in Figure 1. Figure 6 As shown, it can be implemented using analog circuits (CML structure) or digital circuits (CMOS structure).

[0047] Specifically, CLKO_i=(1-a)CLK_x+aCLK_y

[0048] Where a represents the weight; CLK_x and CLK_y represent adjacent clocks.

[0049] CLKO_i45=(0.5-a)CLK_x+(a+0.5)CLK_y

[0050] CLK_iavg=CLKO_i+CLKO_i45.

[0051] From the results, the clock phase interval of the new phase interpolator is between 5.47 degrees and 5.72 degrees, with a variation range of 0.25 degrees, which is only 8% of the original phase. The specific phase change is as follows: Figure 7 shown.

[0052] The present invention also provides a new type of high-linearity, high-speed clock phase interpolator control system. The new type of high-linearity, high-speed clock phase interpolator control system can be implemented by executing the process steps of the new type of high-linearity, high-speed clock phase interpolator control method. That is, those skilled in the art can understand the new type of high-linearity, high-speed clock phase interpolator control method as a preferred implementation of the new type of high-linearity, high-speed clock phase interpolator control system.

[0053] In summary, the phase linearity of the traditional interpolated clock is poor. Taking the example of generating 64 clock phases per clock cycle, the ideal clock phase interval is 360 / 64 = 5.625 degrees. However, the actual clock phase interval ranges from 3.8 degrees to 7.1 degrees, with a variation range of 3.3 degrees. This variation is unacceptable in high-speed, high-precision clock design. The new phase interpolator provided by the present invention has a clock phase interval between 5.47 degrees and 5.72 degrees, with a variation range of 0.25 degrees, which is only 8% of the original, making it more suitable for high-speed, high-precision clock design.

[0054] Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, and units provided by the present invention in purely computer-readable program code, it is entirely possible to implement the same functions of the system and its various devices, modules, and units provided by the present invention in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; the devices, modules, and units for implementing various functions can also be considered as both software modules implementing the method and structures within the hardware component.

[0055] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A high-speed clock phase interpolator control method, characterized in that: include: Step S1: Obtain a first clock phase CLKO_i by adding adjacent clock weights; Step S2: Determine the second clock phase CLKO_i45 based on the phase interval of the two clock phase interpolators being 45 degrees; Step S3: Obtain a new clock phase CLK_iavg based on the first clock phase CLKO_i and the second clock phase CLKO_i45.

2. The high-speed clock phase interpolator control method according to claim 1, wherein: The step S1 adopts: CLKO_i=(1-a)CLK_x+aCLK_y Where a represents the weight; CLK_x and CLK_y represent adjacent clocks.

3. The high-speed clock phase interpolator control method according to claim 1, wherein: The step S2 adopts: CLKO_i45=(0.5-a)CLK_x+(a+0.5)CLK_y.

4. The high-speed clock phase interpolator control method according to claim 1, wherein: The step S3 adopts: CLK_iavg=CLKO_i+CLKO_i45.

5. A high-speed clock phase interpolator control system, characterized in that: include: Module M1: obtains the first clock phase CLKO_i by adding adjacent clock weights; Module M2: Determine the second clock phase CLKO_i45 based on the phase interval of the two clock phase interpolators being 45 degrees; Module M3: Obtaining a new clock phase CLK_iavg based on the first clock phase CLKO_i and the second clock phase CLKO_i45.

6. The high-speed clock phase interpolator control system according to claim 5, characterized in that: The module M1 adopts: CLKO_i=(1-a)CLK_x+aCLK_y Where a represents the weight; CLK_x and CLK_y represent adjacent clocks.

7. The high-speed clock phase interpolator control system according to claim 5, characterized in that: The module M2 adopts: CLKO_i45=(0.5-a)CLK_x+(a+0.5)CLK_y.

8. The high-speed clock phase interpolator control system according to claim 5, characterized in that: The module M3 adopts: CLK_iavg=CLKO_i+CLKO_i45.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the high-speed clock phase interpolator control method according to any one of claims 1 to 4 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by a processor, the steps of the high-speed clock phase interpolator control method according to any one of claims 1 to 4 are implemented.

Images