Multi-stack cascade battery pack dynamic coding method, device and equipment and storage medium

Abstract

The invention discloses a multi-stack cascade battery pack dynamic coding method, device and equipment and a storage medium, and relates to the technical field of battery pack management and control, and the method comprises the steps: transmitting a generated initial detection signal to a first slave battery pack node in a closed loop path, and carrying out the step-by-step forwarding; receiving a feedback signal returned from the battery pack node by the last stage in the closed loop path, wherein the feedback signal comprises hardware identification information corresponding to each battery pack node in the closed loop path; constructing a stacking topological structure mapping table according to the hardware identification information; and carrying out address allocation on each battery pack node one by one based on the stacking topological structure mapping table. According to the application, the initial detection signal is forwarded by each node in the multi-stack cascade battery pack to obtain the hardware identification information of each battery pack, and then address allocation is performed on each battery pack based on the stack topological structure mapping table corresponding to the multi-stack cascade battery pack established based on the hardware identification information, so that address conflicts are avoided, the manual configuration requirement is reduced, and the efficiency is improved. And the dynamic expansion capability is improved.

Description

Technical Field

[0001] The present application relates to the field of battery pack management and control technology, and in particular to a dynamic coding method, device, equipment and storage medium for a multi-stack cascade battery pack. Background Art

[0002] Address coding technology for stacked battery packs has long relied on fixed DIP switches or one-way cascade communication. Early solutions used mechanical terminals to achieve physical connection, but addresses required manual configuration. Furthermore, traditional coding schemes generally lacked effective management of inter-stack communication links, requiring manual intervention during address allocation.

[0003] Therefore, the existing address coding technology for stacked battery packs has problems such as frequent address conflicts, high dependence on manual configuration, and limited dynamic expansion. Summary of the Invention

[0004] The main purpose of this application is to provide a dynamic coding method, device, equipment and storage medium for a multi-stack cascade battery pack, aiming to solve the technical problems of the existing address coding technology of stacked battery packs, such as frequent address conflicts, high dependence on manual configuration, and limited dynamic expansion.

[0005] To achieve the above objectives, the present application proposes a dynamic coding method for a multi-stack cascade battery pack, the method comprising:

[0006] Sending the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding;

[0007] receiving a feedback signal returned by a final slave battery pack node, the feedback signal including hardware identification information corresponding to each battery pack node in the multi-stack cascade battery pack;

[0008] Constructing a stack topology mapping table according to the hardware identification information;

[0009] Addresses are assigned to the battery pack nodes one by one based on the stack topology mapping table.

[0010] In one embodiment, the step of sending the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding includes:

[0011] generating a PWM signal having a first duty cycle parameter as an initial detection signal;

[0012] The initial detection signal is sent to the first slave battery pack node in the closed-loop loop path, and the initial detection signal is forwarded by the first slave battery pack node step by step to the last slave battery pack node in the closed-loop loop path according to the preset physical link, and the hardware identification information of each forwarding battery pack node is superimposed during the signal transmission process.

[0013] In one embodiment, the step of allocating addresses to the battery pack nodes one by one based on the stack topology mapping table includes:

[0014] Determine the current priority to be assigned corresponding to each battery stack based on the stack topology mapping table;

[0015] According to the current priority to be assigned, a coded signal is sent to the target main battery pack node pin of each battery stack one by one, and each battery pack node in each battery stack performs cumulative address allocation according to the coded signal; the coded signal is a PWM signal containing a second duty cycle parameter.

[0016] In one embodiment, there is a preset tolerance threshold between the first duty cycle parameter and the second duty cycle parameter.

[0017] In one embodiment, after allocating addresses to the battery pack nodes one by one based on the stack topology mapping table, the method further includes:

[0018] Periodically broadcasting a topology detection signal in each slave battery stack, wherein each slave battery stack feeds back a topology response signal based on a random delay time after receiving the topology detection signal;

[0019] When a topology change of the cascaded battery group is detected based on the topology response signal, the address allocation result of each battery pack node is updated according to the change type.

[0020] In one embodiment, the step of updating the address allocation result of each battery pack node according to the change type includes:

[0021] When the change type is stack disconnection, the address space of the disconnected battery stack is marked as reserved for reconnection, and the address space of the remaining battery stacks remains unchanged.

[0022] In one embodiment, the step of updating the address allocation result of each battery pack node according to the change type includes:

[0023] When the change type is stack addition, the stack topology structure mapping table is updated according to the newly added battery pack, and the addresses of the battery pack nodes are re-allocated one by one based on the stack topology structure mapping table.

[0024] In addition, to achieve the above-mentioned purpose, the present application also proposes a multi-stack cascade battery pack dynamic encoding device, which is applied to a multi-stack cascade battery pack comprising multiple battery stacks, each battery stack comprising at least one master battery pack node and several slave battery pack nodes, and the master battery pack node and the several slave battery pack nodes within each battery stack are connected in series to form a closed loop path, and the device comprises:

[0025] A detection module, configured to send the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding;

[0026] a signal processing module, configured to receive a feedback signal returned by a final-stage slave battery pack node, the feedback signal including hardware identification information corresponding to each battery pack node in the multi-stack cascade battery pack;

[0027] A topology parsing module, configured to construct a stacking topology structure mapping table according to the hardware identification information;

[0028] An address allocation module is configured to allocate addresses to the battery pack nodes one by one based on the stack topology mapping table.

[0029] In addition, to achieve the above-mentioned purpose, the present application also proposes a dynamic encoding device for a multi-stack cascade battery pack, which includes: a memory, a processor, and a dynamic encoding program for a multi-stack cascade battery pack stored on the memory and runnable on the processor, and the dynamic encoding program for a multi-stack cascade battery pack is configured to implement the steps of the dynamic encoding method for a multi-stack cascade battery pack as described above.

[0030] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, on which a dynamic encoding program for multiple cascaded battery packs is stored. When the dynamic encoding program for multiple cascaded battery packs is executed by a processor, the steps of the dynamic encoding method for multiple cascaded battery packs described above are implemented.

[0031] The present application provides a method, device, equipment and storage medium for dynamic encoding of a multi-stack cascade battery pack. The method is applied to a multi-stack cascade battery pack comprising multiple battery stacks, wherein each battery stack comprises at least one master battery pack node and several slave battery pack nodes, and each battery stack and each master battery pack node and several slave battery pack nodes in each battery stack are connected in series to form a closed loop path. The method comprises: sending the generated initial detection signal to the first slave battery pack node of the multi-stack cascade battery pack for step-by-step forwarding; receiving a feedback signal returned by the last slave battery pack node, the feedback signal comprising the hardware identification information corresponding to each battery pack node in the closed loop path; constructing a stacking topology mapping table based on the hardware identification information; and assigning addresses to each battery pack node one by one based on the stacking topology mapping table. The present application obtains the hardware identification information of each battery pack by forwarding the initial detection signal based on the closed loop path at each node in the multi-stack cascade battery pack, and then assigns addresses to each battery pack based on the stacking topology mapping table corresponding to the multi-stack cascade battery pack established based on the hardware identification information, thereby effectively avoiding address conflicts, reducing the need for manual configuration, and improving dynamic expansion capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 This is a schematic diagram of the multi-stack cascade battery pack structure configuration process according to the first embodiment of the multi-stack cascade battery pack dynamic encoding method of the present application;

[0035] Figure 2 This is a flow chart of the first embodiment of the dynamic encoding method for multi-stack cascaded battery packs of the present application;

[0036] Figure 3 This is a schematic diagram of the address allocation process of the first embodiment of the dynamic encoding method for multi-stack cascaded battery packs of the present application;

[0037] Figure 4 This is a flow chart of the second embodiment of the dynamic coding method for multi-stack cascaded battery packs of the present application;

[0038] Figure 5 This is a schematic diagram of the dynamic management process of the second embodiment of the dynamic coding method for multi-stack cascaded battery packs of the present application;

[0039] Figure 6 This is a schematic diagram of the module structure of a dynamic encoding device for a multi-stack cascaded battery pack according to an embodiment of the present application;

[0040] Figure 7 Schematic diagram of the device structure of the hardware operating environment involved in the dynamic encoding method of multi-stack cascaded battery packs in the embodiment of the present application.

[0041] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0042] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0043] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0044] The main solution of the present application is to propose a dynamic encoding method for a multi-stack cascade battery pack, which is applied to a multi-stack cascade battery pack comprising multiple battery stacks, wherein each battery stack comprises at least one master battery pack node and several slave battery pack nodes, and the battery stacks and the master battery pack nodes and the several slave battery pack nodes in each battery stack are connected in series to form a closed-loop loop path. The method comprises: sending the generated initial detection signal to the first slave battery pack node in the closed-loop loop path for step-by-step forwarding; receiving a feedback signal returned by the last slave battery pack node in the closed-loop loop path, the feedback signal comprising hardware identification information corresponding to each battery pack node in the closed-loop loop path; constructing a stacking topology structure mapping table according to the hardware identification information; and allocating addresses to each battery pack node one by one based on the stacking topology structure mapping table.

[0045] Currently, address encoding technology for stacked battery packs has long relied on fixed DIP switches or one-way cascade communication, resulting in frequent address conflicts. Early solutions used mechanical terminals for physical connection, but these required manual address configuration, which was highly dependent on manual configuration. Furthermore, existing technologies generally lacked effective management of inter-stack communication links, requiring additional wiring or manual intervention during address allocation, limiting dynamic scalability.

[0046] To solve this problem, the present application obtains the hardware identification information of each battery pack by forwarding the initial detection signal based on a closed-loop path at each node in a multi-stack cascade battery pack, and then assigns a unique address to each battery pack based on the stacking topology mapping table corresponding to the multi-stack cascade battery pack established based on the hardware identification information, thereby effectively avoiding address conflicts, reducing the need for manual configuration, and improving dynamic expansion capabilities.

[0047] It should be noted that the existing solutions mostly use unidirectional signal transmission (such as DN→UP unidirectional series connection), and the address allocation between stacks needs to rely on manually specified jumper lengths or pre-planned address space, and hot-swappable automatic addressing cannot be achieved. However, the method proposed in this embodiment is applied to a multi-stack cascade battery group containing multiple battery stacks, each battery stack contains at least one master battery pack node and several slave battery pack nodes, and the battery stacks and the master battery pack nodes and several slave battery pack nodes in each battery stack are connected in series to form a closed loop path. This method is executed by the initial master battery pack node of the battery stack connected to the inverter. The initial master battery pack node can also be represented as a host or a master management device, that is, the execution subject of this embodiment can be a dynamic encoding device for a multi-stack cascade battery group, or a master management device with data processing, network communication, program running functions and energy storage system battery management functions, such as a tablet computer, personal computer, mobile phone, etc., or a battery management system collaborative upgrade device that can realize the above functions, etc. This embodiment does not make specific limitations on this. The following takes the master management device as the execution subject as an example to illustrate this embodiment and the following embodiments.

[0048] For ease of understanding, refer to Figure 1 The configuration process of the multi-stack cascade battery pack structure proposed in this embodiment is explained. Figure 1 This is a schematic diagram of the multi-stack cascade battery pack structure configuration process of the first embodiment of the multi-stack cascade battery pack dynamic coding method of this application. Figure 1 As shown, in the multi-stack cascade battery pack proposed in this embodiment, a DN (output) pin and an UP (input) pin can be configured for each battery pack. That is, each battery pack in the stack contains at least one master battery pack node and several slave battery pack nodes. The master battery pack node is usually the first battery pack node in the stack, and the remaining battery pack nodes in the stack are slave battery pack nodes. A unidirectional signal link is formed between the master battery pack node and the connected slave battery pack nodes, and between the slave battery pack nodes and the slave battery pack nodes through DN→UP series connection;

[0049] When connecting between stacks, the DN pin of the next stack is connected to the UP pin of the previous stack. Therefore, in this embodiment, the DN pin of the last-stage slave battery pack node, that is, the slave battery pack node of the last battery stack, will be connected in series with the UP pin of the main management device located in the first stack, thereby forming a closed-loop signal loop path.

[0050] Furthermore, each device's MCU within the stack features a built-in PWM module and timer capture functionality. It outputs a PWM signal via the DN pin and captures the input signal's duty cycle via the UP pin. This information, combined with the MCU's hardware ID (unique serial number), identifies the stack and battery pack. Inter-stack communication utilizes an RS485 interface and network cables for long-distance transmission, ensuring signal integrity.

[0051] Based on this, the embodiment of the present application provides a dynamic coding method for a multi-stack cascade battery pack, referring to Figure 2 , Figure 2 This is a flow chart of the first embodiment of the dynamic encoding method for multi-stack cascaded battery packs of the present application.

[0052] In this embodiment, the dynamic coding method for a multi-stack cascade battery pack includes steps S10 to S40:

[0053] Step S10, sending the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding;

[0054] Step S20, receiving a feedback signal returned from the battery pack node at the last stage in the closed loop path, wherein the feedback signal includes hardware identification information corresponding to each battery pack node in the closed loop path;

[0055] Step S30, constructing a stack topology mapping table according to the hardware identification information;

[0056] Step S40: allocating addresses to the battery pack nodes one by one based on the stack topology mapping table.

[0057] It should be understood that the master management device is located at the first node of the first battery stack connected to the inverter, the above-mentioned first slave battery pack node can be a slave battery pack node that is located in the same battery stack as the master management device and is connected to the master management device in the closed-loop loop path, and the above-mentioned last-stage slave battery pack node can be a slave battery pack node that is not located in the same battery stack as the master management device and is connected to the master management device in the closed-loop loop path. In order to achieve unique address allocation, this embodiment can make full use of the MCU hardware characteristics, and transmit the device identification information of each battery pack node by transmitting PWM signals between each node in the stack and between each node in the stack, thereby automatically associating the physical topology and logical address of the multi-stack cascade battery group, and performing high-reliability unique address allocation based on the device identification.

[0058] In a feasible implementation, in this embodiment, step S10 may include steps A1 to A2:

[0059] Step A1, generating a PWM signal with a first duty cycle parameter as an initial detection signal;

[0060] Step A2: Send the initial detection signal to the first slave battery pack node in the closed-loop loop path. The initial detection signal is forwarded by the first slave battery pack node step by step to the last slave battery pack node in the closed-loop loop path according to the preset physical link, and the hardware identification information of each forwarding battery pack node is superimposed during the signal transmission process.

[0061] It is understood that the master management device can generate an initial detection signal through its own signal output interface and send this signal to the UP pin of the first slave battery pack node. After receiving the initial detection signal, the first slave battery pack node reads its own hardware identification information and adds it to the initial detection signal. It then transmits the initial detection signal to the next battery pack node through its output pin (DN). The next battery pack node repeats the same operation, continuously forwarding the signal, and so on, so that the initial detection signal is transmitted step by step along the preset physical links within and between battery stacks (i.e., the cascade connection between each node within the stack and each battery stack). When the initial detection signal reaches the final slave battery pack node (i.e., the last battery pack in the last battery stack), the battery pack at that node returns the initial detection signal to the master management device, and the returned signal carries the hardware identification information of itself and all previously forwarded battery pack nodes, generating a feedback signal. The hardware identification information is like an "identity card" for each battery pack, which can be the unique serial number of the battery pack's built-in MCU, etc., and can accurately identify the identity of each battery pack.

[0062] It is easy to understand that to ensure that the initial detection signal sent by the main battery pack node can effectively perform topology detection and accurately carry the hardware identification information of each battery pack node during signal transmission, the signal generator of the main management device can generate a corresponding PWM signal, i.e., the initial detection signal, through PWM modulation technology based on a preset first duty cycle parameter (for example, a duty cycle of approximately 20%, the specific value can be determined based on actual needs and battery pack characteristics). The initial detection signal is like a messenger with a specific mark, and its duty cycle parameter is its "marker", used to identify it as a signal for topology detection.

[0063] For example, the main management device can start the timer and send an initial detection signal, waiting for the loopback signal (timeout threshold 200ms). After each battery node behind the main management device captures the signal, it can extract its own hardware identification information, add it to the initial detection signal, and forward it to the next node, and finally transmit it back to the main management device. The main management device establishes a stacking topology mapping table corresponding to the multi-stack cascade battery group based on the hardware identification information of each battery pack node in the feedback signal, which includes the connection relationship between the nodes within the stack and the connection relationship between the stacks, to mark each battery stack to be encoded.

[0064] In this implementation, a PWM signal containing a first duty cycle parameter is used as the initial detection signal. This first duty cycle parameter is used to identify the signal's purpose, enabling the primary management device to accurately identify the signal as being used for topology detection, thereby improving the signal's reliability and effectiveness. Furthermore, as the signal is forwarded step by step, the hardware identification information of each battery pack node is superimposed, providing the necessary data support for the primary management device to subsequently construct an accurate stack topology mapping table, ensuring accurate address allocation.

[0065] It is easy to understand that the above stacking topology mapping table is like a detailed map, which records the position of the battery pack corresponding to each hardware identifier in the multi-stack cascade battery pack, including which battery stack it belongs to, the specific node position in the battery stack, etc., so that the main management device can clearly know the topology of the entire battery pack. After constructing the stacking topology mapping table, the main management device can follow certain rules (for example, according to the order of the battery stacks, starting from the first battery stack, and assigning addresses to each battery pack in turn) and assign unique addresses to each battery pack node one by one according to the positional relationship recorded in the mapping table. This address is like assigning an exclusive "house number" to each battery pack, which facilitates their subsequent management and control.

[0066] In a feasible implementation, in this embodiment, step S40 may include steps B1 to B2:

[0067] Step B1, determining the current priority to be allocated corresponding to each battery stack based on the stack topology mapping table;

[0068] Step B2: sending a coding signal to the target main battery pack node pin of each battery stack one by one according to the current priority to be assigned, and each battery pack node in each battery stack performs cumulative address allocation according to the coding signal; the coding signal is a PWM signal containing a second duty cycle parameter.

[0069] It is easy to understand that in a multi-stack parallel scenario, a single duty cycle encoding may cause duplicate addresses to be generated from battery pack nodes of different stacks, that is, the risk of coding conflicts is high, and the existing technology has not proposed an effective conflict detection and recovery mechanism. To avoid this problem, this embodiment proposes a dual duty cycle coding protocol for topology detection and address allocation. Exemplarily, the above-mentioned initial detection signal can be a PWM signal with a duty cycle of (address + 1) * 200 (corresponding to the first duty cycle parameter), which is used for topology detection and conflict detection; the above-mentioned coding signal can be a PWM signal with a duty cycle of (address + 1) * 300 (corresponding to the second duty cycle parameter), which is used for formal address allocation. After each battery pack node in the multi-stack cascade battery group captures the initial detection signal, it forwards it to the next node and records its own hardware identification information, and finally transmits it back to the main management device to form a closed-loop feedback; and after each battery pack node receives the coding signal, it performs cumulative address allocation and reports the status through RS485.

[0070] It should be noted that the main management device can effectively analyze the position and connection relationship of each battery stack in the entire multi-stack cascade battery group based on the constructed stacking topology mapping table, and then determine the priority of the current address to be assigned for each battery stack according to certain rules (for example, according to the order of the battery stack in the cascade physical structure, or according to certain priority attributes of the battery stack, such as the power level of the battery stack, frequency of use, etc.). The current priority to be assigned determines the order of address assignment for each battery stack.

[0071] The main management device can then send a coded signal to the target main battery pack node pin of each battery stack (i.e., the UP pin of the main battery pack node in each battery stack other than the stack in which it is located, which is used to receive the address allocation signal) in sequence according to the determined priority order. During this process, this embodiment can add an optoelectronic isolator to the inter-stack link to improve the system's anti-interference capability. This coded signal is like a "command" sent to each battery stack to notify the main battery pack node in each stack to start address allocation.

[0072] It is understandable that after the main battery pack node in each battery stack receives the coded signal, the various battery pack nodes in the stack perform cumulative address allocation according to certain rules (for example, starting from the first node, each node is assigned an address that is a certain value larger than the previous node). This process is like being on a chain, where each node assigns itself an adjacent address based on the address of the previous node, ensuring that each node has a unique, continuous address. The initial address for cumulative allocation in each battery stack can be determined by the main management device according to the stacking topology mapping table and then distributed to the main battery pack nodes of each battery stack through a coded signal.

[0073] For example, referring to Figure 3 The following example illustrates the address allocation process. Figure 3 This is a schematic diagram of the address allocation process of the first embodiment of the dynamic encoding method for multi-stack cascaded battery packs of this application. Figure 3 As shown, in this embodiment, the main management device (with a fixed address of 1) can continuously poll and send an initial detection signal with a duty cycle of (address+1)*200, which is used for topology detection and conflict detection, and waits for the response of the second stack. After that, each battery pack node captures the signal and forwards it to the next battery pack node in the closed-loop loop path, and attaches its own hardware identification information, and finally transmits the feedback signal back to the main management device to form a closed-loop feedback. If the main management device receives the feedback signal, the main management device establishes a stacking topology mapping table based on the hardware identification information of all battery pack nodes contained in the feedback signal and its own hardware identification information. Then, the main management device sends coded signals with a duty cycle of (address+1)*300 one by one according to the topological order in the stacking topology mapping table, and controls each slave stack (that is, each battery stack except the stack where the main management device is located) to complete the address allocation in turn. Each slave stack accumulates its address and transmits an acknowledgment signal (ACK) after the accumulated encoding is complete. If the master management device receives the acknowledgment signal within the specified acknowledgment time determined by the mapping table, it marks the encoding as complete. If the master management device does not receive the acknowledgment signal within the specified acknowledgment time, a timeout retransmission is triggered, determining the presence of a new stack and triggering a topology update. Furthermore, if the initial detection signal does not receive a loopback signal from another stack within the feedback timeout, i.e., the feedback times out, it is determined that no additional stack exists and single-stack encoding mode is entered. At this point, a PWM signal of (address + 1) * 300 can be sent to the next slave battery pack node in the current stack. After receiving it, the slave battery pack node encodes it as 2. This signal is then sent incrementally to the next slave battery pack node, which encodes it as 3, and so on. This logic will continue to loop.

[0074] In this implementation, by determining the priority of the battery stack to be allocated, the order of address allocation can be properly arranged, avoiding conflicts and confusion that may arise when multiple battery stacks are allocated addresses simultaneously. By using a PWM signal containing a second duty cycle parameter as the encoding signal, each battery pack node can accurately identify the address allocation signal and allocate addresses in a cumulative manner, ensuring that each node obtains a unique and reasonable address, thereby improving the efficiency and accuracy of address allocation.

[0075] In a feasible implementation manner, in this embodiment, there is a preset tolerance threshold between the first duty cycle parameter and the second duty cycle parameter.

[0076] It is easy to understand that both the initial detection signal and the coded signal are in the form of PWM signals. Although this embodiment pre-sets different first and second duty cycle parameters to distinguish signals for different purposes, to further ensure that the initial detection signal and the coded signal can be accurately distinguished and identified during transmission and avoid errors caused by signal confusion, in this embodiment, a preset tolerance threshold, such as approximately 10%, can be pre-set when generating the initial detection signal and the coded signal. This means that the difference between the duty cycle parameter of the initial detection signal and the duty cycle parameter of the coded signal must be greater than this tolerance threshold.

[0077] For example, if the duty cycle of the initial detection signal is 20%, then the duty cycle of the coded signal should be at least 10% greater (i.e., 30%) or 10% less (i.e., 10%) than 20% (e.g., 180-220 for the detection signal and 280-320 for the coded signal) to ensure signal parsing reliability. This ensures that there is sufficient difference between the two signals so that the main management device can accurately identify and distinguish the two signals, avoiding the error of mistaking the initial detection signal for the coded signal or vice versa.

[0078] In this embodiment, by setting a preset tolerance threshold, a clear boundary can be established between the initial detection signal and the encoding signal, thereby improving the accuracy and reliability of signal recognition, reducing errors caused by signal confusion, and ensuring the smooth progress of the entire dynamic encoding process.

[0079] In this embodiment, the MCU's built-in PWM module and timer capture function can be utilized to reduce reliance on additional hardware. Addresses are automatically assigned by sending an initial detection signal and constructing a stack topology mapping table, effectively avoiding the errors and tedious operations that may occur when manually configuring addresses, reducing the need for manual configuration. Furthermore, this embodiment can dynamically identify the topology of multi-stack cascaded battery packs without the need for manual intervention or pre-planning of address space. Compared to traditional one-way cascade communication solutions, dynamic expansion efficiency is increased by over 50%, significantly improving dynamic expansion capabilities.

[0080] This embodiment also combines each node's unique hardware identification information with a dual-duty-cycle protocol to ensure unique address allocation for each stack. An adaptive timeout adjustment algorithm (initial 200ms → incremental retransmission) works in conjunction with the ACK confirmation mechanism to ensure automatic recovery after signal loss. Furthermore, by effectively physically distinguishing the initial detection signal from the coded signal, address conflicts are reduced, avoiding address duplication in multi-stack parallel scenarios.

[0081] The present embodiment provides a method for dynamic encoding of a multi-stack cascade battery pack, which is applied to a multi-stack cascade battery pack comprising a plurality of battery stacks, wherein each battery stack comprises at least one master battery pack node and a plurality of slave battery pack nodes, and the battery stacks and the master battery pack nodes and the slave battery pack nodes in each battery stack are connected in series to form a closed loop path, and the method comprises: generating a PWM signal with a first duty cycle parameter as an initial detection signal; sending the initial detection signal to the first slave battery pack node in the closed loop path, and the initial detection signal is forwarded by the first slave battery pack node step by step according to a preset physical link to the last slave battery pack node in the closed loop path; The system comprises a battery pack node and superimposes the hardware identification information of each forwarding battery pack node during signal transmission; receives a feedback signal returned by the final slave battery pack node, the feedback signal including the hardware identification information corresponding to each battery pack node in a multi-stack cascaded battery pack; constructs a stacking topology mapping table based on the hardware identification information; determines the current priority level to be assigned corresponding to each battery stack based on the stacking topology mapping table; sends a coded signal to the target master battery pack node pin of each battery stack one by one based on the current priority level to be assigned, and each battery pack node in each battery stack performs cumulative address assignment based on the coded signal; the coded signal is a PWM signal including a second duty cycle parameter. A preset tolerance threshold exists between the first duty cycle parameter and the second duty cycle parameter. This embodiment automatically assigns addresses by sending an initial detection signal and constructing a stacking topology mapping table, effectively avoiding errors and tedious operations that may occur in manual address configuration, thereby reducing the need for manual configuration. Furthermore, this embodiment can dynamically identify the topology of a multi-stack cascaded battery pack without the need for manual intervention or pre-planning of address space. Compared to traditional one-way cascade communication solutions, dynamic scalability is significantly improved. Furthermore, this embodiment combines each node's unique hardware identification information with a dual-duty-cycle protocol to ensure unique address assignment for each stack. Furthermore, by effectively physically distinguishing the initial detection signal from the coded signal, address conflicts are reduced, avoiding address duplication in multi-stack parallel scenarios. Therefore, this embodiment effectively avoids address conflicts, reduces the need for manual configuration, and improves dynamic scalability.

[0082] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction and will not be repeated later.

[0083] Understandably, traditional approaches lack inter-stack feedback mechanisms and are unable to proactively identify newly added stacks. This results in the need for manual re-addressing when topology changes occur, resulting in insufficient system real-time performance and flexibility. Furthermore, traditional technologies lack dynamic timeout adjustment and periodic detection capabilities, resulting in inability to promptly recover from signal loss or topology changes, impacting system stability and reliability.

[0084] To solve this problem, based on the first embodiment, please refer to Figure 4 , Figure 4 This is a flow chart of a second embodiment of the dynamic coding method for a multi-stack cascaded battery pack of the present application. In this embodiment, step S40 is followed by steps S50 to S60:

[0085] Step S50, periodically broadcasting a topology detection signal to each slave battery stack, and each slave battery stack feeds back a topology response signal based on a random delay time after receiving the topology detection signal;

[0086] Step S60 : When a topology change of the cascaded battery group is detected based on the topology response signal, the address allocation result of each battery pack node is updated according to the change type.

[0087] It is understandable that in this embodiment, the master management device may have a built-in timer to generate and send a topology detection signal (the topology detection signal is actually also a PWM signal containing a first duty cycle parameter, which is used here to distinguish it from the initial detection signal) to each slave battery stack (which may be referred to as a slave stack for short) at a certain time interval (for example, 5 seconds). The slave battery stack is the battery stack other than the stack where the master management device is located in the multi-stack cascade battery group. This topology detection signal can be regarded as a "greeting" sent periodically by the master management device to inquire about the current status of each slave battery stack.

[0088] After receiving the topology detection signal, each slave battery stack does not immediately feedback. Instead, it generates a random delay time based on its own hardware identification information (such as hardware ID). The random delay time can be the result of a modulo operation of the value corresponding to the hardware ID, such as delay time = hardware ID% 50ms. For example, the last two hexadecimal digits of the hardware UID (Unique Identifier) ​​are converted to decimal and then modulo 50. For example, if the UID ends in 0xAB, the delay time = 171% 50 = 21ms. The purpose of this is to avoid signal conflicts and interference caused by multiple slave battery stacks simultaneously feeding back signals, ensuring that each slave battery stack has enough time to send its own response signal.

[0089] It should be understood that after receiving the topology response signals fed back by each slave battery stack, the master management device will compare the new topology mapping table generated based on the topology response signals with the previously constructed stack topology mapping table. If the comparison finds a topology change such as a new battery stack or a disconnected battery stack, the master management device can update the address allocation results of each battery pack node based on the specific type of change (new or disconnected).

[0090] In a feasible implementation, in this embodiment, step S60 may include step C1:

[0091] Step C1: When the change type is stack disconnection, the address space of the disconnected battery stack is marked as a reserved reconnection state, and the address space of the remaining battery stacks remains unchanged.

[0092] It is easy to understand that if the main management device detects through the topology response signal that a battery stack has been disconnected, that is, the corresponding change type is a stack disconnection, the address space corresponding to the disconnected battery stack will be marked as reserved for reconnection in the stacking topology mapping table. This mark is like putting a "temporarily reserved, waiting for reconnection" label on this address space, which means that this address space is temporarily reserved and will not be reallocated to other battery stacks to prevent address conflicts. In addition to the disconnected battery stack, the address space of other battery stacks that are still normally connected can maintain the original allocation status unchanged, so as to avoid unnecessary interference to the normally operating battery stacks and ensure that they can continue to operate stably.

[0093] This processing method effectively avoids the address conflict problem caused by stack disconnection, and reserves the address space of the disconnected battery stack, preparing for possible subsequent reconnection. It also ensures the stable operation of other normal battery stacks and improves the stability and resource utilization of the entire battery pack management system.

[0094] In another feasible implementation, in this embodiment, step S60 may include step C2:

[0095] Step C2: When the change type is stack addition, a stack topology mapping table is constructed and updated according to the newly added battery pack, and addresses of the battery pack nodes are re-allocated one by one based on the stack topology mapping table.

[0096] It is understandable that if the main management device detects that a new battery stack has been added, that is, the corresponding change type is stack addition, it will obtain relevant information of the new battery pack (including hardware identification information, etc.) and update the original stacking topology mapping table based on this information, that is, accurately add the new battery stack and its nodes to the original stacking topology mapping table to construct a new updated stacking topology mapping table, so that the main management device can clearly understand the position and connection relationship of the new battery stack in the entire multi-stack cascade battery group based on the updated stacking topology mapping table.

[0097] It's easy to understand that after updating the mapping table, the main management device reassigns addresses to all battery pack nodes according to the new topology it represents. This process is similar to reorganizing a list of newly added members and assigning each member a new, unique seat number (address), ensuring that the newly added battery stack and its nodes can be properly integrated into the entire battery pack management system and work in conjunction with other battery stacks.

[0098] In this embodiment, by timely updating the stack topology mapping table and re-assigning addresses, newly added battery stacks and their nodes can be effectively incorporated into the address management system, enabling them to function normally without manual intervention. Therefore, this embodiment improves the scalability and flexibility of the battery pack management system and adapts to the dynamic changes that may occur in battery packs during actual applications.

[0099] In the specific implementation, refer to Figure 5 Explain the above dynamic management mechanism. Figure 5 This is a schematic diagram of the dynamic management process of the second embodiment of the dynamic coding method for multi-stack cascaded battery packs of this application. Figure 5 As shown, the master management device broadcasts a topology detection signal every 5 seconds. Each slave battery stack responds after a random delay based on its hardware identification information to avoid signal conflicts. The master management device compares the current topology with historical records to detect the addition or removal of a stack and trigger renumbering. If a stack is detected to be disconnected, the master management device marks the stack address space as "reserved," preserving the address range until it is reconnected. If a new stack is detected, renumbering is triggered, and the stack automatically joins the topology via the detection signal, without manual intervention.

[0100] This implementation combines a periodic detection mechanism with a randomized delay response strategy to achieve real-time awareness of topology changes. Compared to existing solutions that rely on manual triggering, the topology update response time is shortened to within 3 seconds, enhancing the battery pack's topology awareness and adaptability.

[0101] Furthermore, this embodiment automatically reserves address space when disconnecting a stack, and automatically adds a new stack to the topology via a detection signal. Compared to existing technologies that require manual reset, hot-swap operations take 80% less time, significantly improving system availability.

[0102] This embodiment discloses periodically broadcasting a topology detection signal in each slave battery stack, and each slave battery stack feeds back a topology response signal based on a random delay time after receiving the topology detection signal; when a topology change of the cascaded battery pack is detected based on the topology response signal, when the change type is a stack disconnection, the address space of the disconnected battery stack is marked as a reserved reconnection state, and the address space of the remaining battery stacks remains unchanged. When the change type is a new stack addition, an updated stacking topology mapping table is constructed based on the newly added battery pack, and the addresses of each battery pack node are re-assigned one by one based on the stacking topology mapping table. This embodiment achieves real-time perception of topology changes by combining a periodic detection mechanism with a random delay response strategy. Compared with existing solutions that rely on manual triggering, the topology update response time is shortened to within 3 seconds, thereby enhancing the topology perception and adaptability of the battery pack.

[0103] Furthermore, this embodiment automatically reserves address space when disconnecting a stack, and automatically adds a new stack to the topology via a detection signal. Compared to existing technologies that require manual reset, hot-swap operations take 80% less time, significantly improving system availability.

[0104] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the dynamic encoding method of the multi-stack cascade battery pack of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0105] The present application also provides a multi-stack cascade battery pack dynamic encoding device, which is applied to a multi-stack cascade battery pack comprising multiple battery stacks, each battery stack comprising at least one master battery pack node and several slave battery pack nodes, and the master battery pack nodes and the slave battery pack nodes within each battery stack are connected in series to form a closed loop path. Figure 6 , Figure 6 This is a schematic diagram of the module structure of a dynamic encoding device for a multi-stack cascaded battery pack according to an embodiment of the present application. In this embodiment, the dynamic encoding device for a multi-stack cascaded battery pack includes:

[0106] The detection module 601 is used to send the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding;

[0107] A signal processing module 602 is configured to receive a feedback signal returned by a final stage slave battery pack node, the feedback signal including hardware identification information corresponding to each battery pack node in the multi-stack cascade battery pack;

[0108] A topology parsing module 603 is configured to construct a stack topology mapping table according to the hardware identification information;

[0109] The address allocation module 604 is configured to allocate addresses to the battery pack nodes one by one based on the stack topology mapping table.

[0110] As an implementable method, in this embodiment, the detection module 601 is also used to generate a PWM signal with a first duty cycle parameter as an initial detection signal; the initial detection signal is sent to the first slave battery pack node in the closed-loop loop path, and the initial detection signal is forwarded by the first slave battery pack node to the last slave battery pack node in the closed-loop loop path step by step according to a preset physical link, and the hardware identification information of each forwarding battery pack node is superimposed during the signal transmission process.

[0111] As an implementable embodiment, in this embodiment, the address allocation module 604 is also used to determine the current priority to be allocated corresponding to each battery stack based on the stacking topology mapping table; send a coded signal to the target main battery pack node pin of each battery stack one by one according to the current priority to be allocated, and each battery pack node in each battery stack performs cumulative address allocation according to the coded signal; the coded signal is a PWM signal containing a second duty cycle parameter.

[0112] As an implementable method, in this embodiment, there is a preset tolerance threshold between the first duty cycle parameter in the PWM signal generated by the detection module 601 and the second duty cycle parameter in the coded signal sent by the address allocation module.

[0113] As an implementable embodiment, in this embodiment, the detection module 601 is also used to periodically broadcast a topology detection signal in each slave battery stack, and each slave battery stack feeds back a topology response signal based on a random delay time after receiving the topology detection signal; the address allocation module is also used to update the address allocation results of each battery pack node according to the change type when a topology structure change of the cascaded battery group is detected based on the topology response signal.

[0114] As an implementable method, in this embodiment, the address allocation module 604 is further configured to mark the address space of the disconnected battery stack as a reserved reconnection state when the change type is stack disconnection, and the address space of the remaining battery stacks remains unchanged.

[0115] As an implementable embodiment, in this embodiment, the address allocation module 604 is also used to build and update the stacking topology mapping table according to the newly added battery pack when the change type is stack addition, and re-allocate addresses for each battery pack node one by one based on the stacking topology mapping table.

[0116] The dynamic encoding device for multi-stack cascaded battery packs provided in this application utilizes the dynamic encoding method described in the aforementioned embodiments, resolving the technical issues of frequent address conflicts, high reliance on manual configuration, and limited dynamic expansion in the prior art. Compared to the prior art, the device provided in this application achieves the same beneficial effects as the aforementioned method embodiments, and its other technical features are the same as those disclosed in the aforementioned methods, which are not further elaborated here.

[0117] The present application provides a dynamic encoding device for a multi-stack cascade battery pack, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the dynamic encoding method for the multi-stack cascade battery pack in the above-mentioned embodiment one.

[0118] Reference below Figure 7 , which shows a structural schematic diagram of a multi-stack cascade battery pack dynamic encoding device suitable for implementing an embodiment of the present application.

[0119] The multi-stack cascade battery pack dynamic encoding device in the embodiment of the present application is applied to a multi-stack cascade battery pack comprising multiple battery stacks, each battery stack comprising at least one master battery pack node and several slave battery pack nodes, and the battery stacks and the master battery pack nodes and the several slave battery pack nodes in each battery stack are connected in series to form a closed loop path. The multi-stack cascade battery pack dynamic encoding device can be a device serving as the master battery pack node in the first battery end connected to the inverter in the multi-stack cascade battery pack.

[0120] The above-mentioned multi-stack cascade battery pack dynamic encoding device may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The multi-stack cascade battery pack dynamic encoding device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0121] like Figure 7As shown, the multi-stack cascade battery dynamic encoding device may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM: Read Only Memory) 1002 or the program loaded from the storage device 1003 to the random access memory (RAM: Random Access Memory) 1004. In the random access memory 1004, various programs and data required for the operation of the multi-stack cascade battery dynamic encoding device are also stored. The processing device 1001, the read-only memory 1002 and the random access memory 1004 are connected to each other via a bus 1005. The input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the multi-stack cascade battery pack dynamic encoding device to communicate wirelessly or wired with other devices to exchange data. Although the figure shows a multi-stack cascade battery pack dynamic encoding device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have instead.

[0122] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a multi-stack cascade battery pack dynamic encoding program product, which includes a multi-stack cascade battery pack dynamic encoding program carried on a computer-readable medium, and the multi-stack cascade battery pack dynamic encoding program contains program code for executing the method shown in the flowchart. In such an embodiment, the multi-stack cascade battery pack dynamic encoding program can be downloaded and installed from the network through a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the multi-stack cascade battery pack dynamic encoding program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0123] The multi-stack cascade battery pack dynamic encoding device provided in this application adopts the multi-stack cascade battery pack dynamic encoding method of the above-mentioned embodiment, which can solve the technical problems of dynamic encoding of multi-stack cascade battery packs. Compared with the existing technology, the beneficial effects of the multi-stack cascade battery pack dynamic encoding device provided in this application are the same as the beneficial effects of the multi-stack cascade battery pack dynamic encoding method provided in the above-mentioned embodiment. The other technical features of the multi-stack cascade battery pack dynamic encoding device are the same as those disclosed in the above-mentioned embodiment method, and are not further described here.

[0124] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0125] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0126] The present application provides a storage medium having computer-readable program instructions (i.e., a dynamic encoding program for a multi-stack cascade battery pack) stored thereon, and the computer-readable program instructions are used to execute the dynamic encoding method for a multi-stack cascade battery pack in the above-mentioned embodiment.

[0127] The storage medium provided in this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the storage medium can be any tangible medium that contains or stores a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the storage medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0128] The above-mentioned storage medium may be included in the dynamic encoding device of the multi-stack cascade battery pack; or may exist independently without being assembled into the dynamic encoding device of the multi-stack cascade battery pack.

[0129] The storage medium carries one or more programs. When the one or more programs are executed by the multi-stack cascade battery pack dynamic encoding device, the multi-stack cascade battery pack dynamic encoding device is enabled: multi-stack cascade battery pack dynamic encoding.

[0130] The multi-stack cascade battery pack dynamic coding program code for performing the operations of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0131] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and multi-stack cascade battery pack dynamic coding program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0132] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0133] The readable storage medium provided in this application is a storage medium that stores computer-readable program instructions for executing the above-mentioned multi-stack cascade battery pack dynamic encoding method (i.e., a multi-stack cascade battery pack dynamic encoding program), which can solve the technical problems of dynamic encoding of multi-stack cascade battery packs. Compared with the prior art, the beneficial effects of the storage medium provided in this application are the same as those of the multi-stack cascade battery pack dynamic encoding method provided in the above-mentioned embodiment, and will not be repeated here.

[0134] The above are only some embodiments of the present application and are not intended to limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A dynamic coding method for a multi-stack cascade battery pack, characterized in that: The method is applied to a multi-stack cascade battery pack comprising a plurality of battery stacks, wherein each battery stack comprises at least one master battery pack node and a plurality of slave battery pack nodes, and the master battery pack node and the plurality of slave battery pack nodes within each battery stack are connected in series to form a closed loop path. The method comprises: Sending the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding; receiving a feedback signal returned by a battery pack node at the last stage in the closed-loop path, the feedback signal including hardware identification information corresponding to each battery pack node in the closed-loop path; Constructing a stack topology mapping table according to the hardware identification information; Addresses are assigned to the battery pack nodes one by one based on the stack topology mapping table.

2. The dynamic coding method for a multi-stack cascade battery pack according to claim 1, wherein: The step of sending the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding includes: generating a PWM signal having a first duty cycle parameter as an initial detection signal; The initial detection signal is sent to the first slave battery pack node in the closed-loop loop path, and the initial detection signal is forwarded by the first slave battery pack node step by step to the last slave battery pack node in the closed-loop loop path according to the preset physical link, and the hardware identification information of each forwarding battery pack node is superimposed during the signal transmission process.

3. The dynamic coding method for a multi-stack cascade battery pack according to claim 2, wherein: The step of allocating addresses to the battery pack nodes one by one based on the stack topology mapping table includes: Determine the current priority to be assigned corresponding to each battery stack based on the stack topology mapping table; Sending a coded signal to the target main battery pack node pin of each battery stack one by one according to the current priority to be allocated, and each battery pack node in each battery stack performs cumulative address allocation according to the coded signal; The coded signal is a PWM signal including a second duty cycle parameter.

4. The dynamic coding method for a multi-stack cascade battery pack according to claim 3, wherein: There is a preset tolerance threshold between the first duty cycle parameter and the second duty cycle parameter.

5. The dynamic coding method for a multi-stack cascade battery pack according to claim 1, wherein: After allocating addresses to the battery pack nodes one by one based on the stack topology mapping table, the method further includes: Periodically broadcasting a topology detection signal in each slave battery stack, wherein each slave battery stack feeds back a topology response signal based on a random delay time after receiving the topology detection signal; When a topology change of the cascaded battery group is detected based on the topology response signal, the address allocation result of each battery pack node is updated according to the change type.

6. The dynamic coding method for a multi-stack cascade battery pack according to claim 5, characterized in that: The step of updating the address allocation result of each battery pack node according to the change type includes: When the change type is stack disconnection, the address space of the disconnected battery stack is marked as reserved for reconnection, and the address space of the remaining battery stacks remains unchanged.

7. The dynamic coding method for a multi-stack cascade battery pack according to claim 5, characterized in that: The step of updating the address allocation result of each battery pack node according to the change type includes: When the change type is stack addition, the stack topology structure mapping table is updated according to the newly added battery pack, and the addresses of the battery pack nodes are re-allocated one by one based on the stack topology structure mapping table.

8. A dynamic coding device for a multi-stack cascade battery pack, characterized in that: The device is applied to a multi-stack cascade battery pack comprising multiple battery stacks, each battery stack comprising at least one master battery pack node and a plurality of slave battery pack nodes, and the battery stacks and the master battery pack nodes and the plurality of slave battery pack nodes within each battery stack are connected in series to form a closed loop path. The device comprises: A detection module, configured to send the generated initial detection signal to the first slave battery pack node in the closed loop path for step-by-step forwarding; a signal processing module, configured to receive a feedback signal returned by a battery pack node at the last stage in the closed-loop path, the feedback signal including hardware identification information corresponding to each battery pack node in the closed-loop path; A topology parsing module, configured to construct a stacking topology structure mapping table according to the hardware identification information; An address allocation module is configured to allocate addresses to the battery pack nodes one by one based on the stack topology mapping table.

9. A multi-stack cascade battery pack dynamic encoding device, characterized in that: The device includes: a memory, a processor, and a dynamic encoding program for a multi-stack cascade battery pack stored in the memory and executable on the processor, wherein the dynamic encoding program for a multi-stack cascade battery pack is configured to implement the steps of the dynamic encoding method for a multi-stack cascade battery pack as described in any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium stores a dynamic coding program for multiple cascaded battery packs, which, when executed by a processor, implements the steps of the dynamic coding method for multiple cascaded battery packs according to any one of claims 1 to 7.

Images