Circuit board and method for manufacturing the same

Abstract

The application relates to the technical field of printed wiring boards, and discloses a wiring board and a manufacturing method thereof. The wiring board comprises a buried embedding layer, a buffer layer and a compression layer. The interior of the buried embedding layer is provided with a heat dissipation seat, and the heat dissipation seat is provided with a power device on the side facing the compression layer. The buffer layer is provided with a containing groove. The normal projection of the buffer layer on the side of the compression wiring layer away from the buffer layer and the normal projection of the heat dissipation seat on the side of the compression wiring layer away from the buffer layer have an overlapping part, and the power device is lower than or flush with the surface of the buffer layer away from the buried embedding layer. The compression layer comprises a compression wiring layer and a compression connecting layer. Part of the compression connecting layer is located between the compression wiring layer and the buffer layer. The compression connecting layer is provided with a first hole, and the interior of the first hole is provided with a first conductive part. The wiring board and the manufacturing method thereof provided by the application are used for solving the problem that the power device is easily damaged in the process of compressing the buried embedding layer and the compression layer together in the related art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of printed wiring boards, and in particular to a printed wiring board and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of the electronic communication industry and vehicle-mounted electronic technology, they tend to be miniaturized and multifunctional, and therefore the requirements for related printed wiring boards are also increasingly high. Not only do they need to meet the use requirements in a large-current working environment, have super-high voltage resistance, and excellent CAF (Conductive Anodic Filament) resistance, but also need to realize high-density interconnection and have excellent heat dissipation performance. Therefore, printed wiring boards for embedding power devices (such as power chips) are born.

[0003] In the related art, the power device is generally first fixed on the heat dissipation seat, the power device is fixed on the surface of the heat dissipation seat, and then the heat dissipation seat and the power device are embedded in the embedding layer of the printed wiring board as a whole, and the embedding layer and the compression layer are compressed together. However, the power device is easily damaged in the compression process, resulting in the scrapping of the printed wiring board. SUMMARY

[0004] The present application provides a printed wiring board and a manufacturing method thereof, which are used to solve the problem that the power device is easily damaged in the process of compressing the embedding layer and the compression layer together in the related art.

[0005] In a first aspect, an embodiment of the present application provides a printed wiring board, comprising an embedding layer, a buffer layer and a compression layer which are stacked, the buffer layer is located between the embedding layer and the compression layer;

[0006] The embedding layer is internally provided with a heat dissipation seat, and the heat dissipation seat is provided with a power device on the side facing the compression layer;

[0007] The buffer layer is provided with a receiving groove, the receiving groove penetrates through the buffer layer, the power device is located in the receiving groove, the buffer layer has a projection on the side of the compression layer away from the buffer layer, and the heat dissipation seat has a projection on the side of the compression layer away from the buffer layer, the projections of the buffer layer and the heat dissipation seat coincide, and the power device is lower than or flush with the surface of the buffer layer away from the embedding layer;

[0008] The compression layer comprises a compression circuit layer and a compression connection layer, part of the compression connection layer is located between the compression circuit layer and the buffer layer, part of the compression connection layer fills the gap between the sidewall of the receiving groove and the power device, the compression connection layer is provided with a first hole, the first hole is internally provided with a first conductive part, and part of the compression circuit layer is connected to the power device through the first conductive part and electrically conductive.

[0009] In some embodiments, the buffer layer comprises a buffer core plate and a buffer connecting layer, the accommodating groove penetrates through the buffer core plate and the buffer connecting layer, part of the buffer connecting layer is located between the buffer core plate and the embedded layer, and part of the buffer connecting layer fills the gap between the sidewall of the accommodating groove and the power device.

[0010] In some embodiments, the buffer connecting layer has a projection that overlaps with the projection of the heat dissipation seat on the side of the press-fit circuit layer away from the press-fit connecting layer; and / or, the buffer core plate has a projection that overlaps with the projection of the heat dissipation seat on the side of the press-fit circuit layer away from the press-fit connecting layer.

[0011] In some embodiments, the buffer layer comprises an inner circuit layer, the inner circuit layer is provided with a space for avoiding location, so that the inner circuit layer is spaced apart from the power device, and the accommodating groove penetrates through the space for avoiding location.

[0012] In some embodiments, the surface of the embedded layer towards the press-fit layer is higher than the surface of the heat dissipation seat towards the press-fit layer, and the thickness of the buffer layer is greater than or equal to the height of the power device.

[0013] Alternatively, the surface of the embedded layer towards the press-fit layer is flush with the surface of the heat dissipation seat towards the press-fit layer, and the thickness of the buffer layer is greater than or equal to the height of the power device.

[0014] In some embodiments, the buffer layer is provided with a connecting hole, the connecting hole is provided with a connecting part inside, the press-fit connecting layer is provided with a second hole, the second hole is provided with a second conductive part inside, and part of the press-fit circuit layer is connected to the heat dissipation seat through the second conductive part and the connecting part in sequence and is electrically conductive.

[0015] In some embodiments, the buffer layer comprises an inner circuit layer, the inner circuit layer is provided with a space for avoiding location, so that the inner circuit layer is spaced apart from the power device, and the accommodating groove penetrates through the space for avoiding location.

[0016] In some embodiments, the press-fit connecting layer comprises a glass cloth, the glass cloth comprises glass filaments, and the diameter of the glass filaments is less than or equal to 4 μm.

[0017] In some embodiments, the distance between the sidewall of the accommodating groove and the power device is 0.15 mm-0.25 mm.

[0018] In some embodiments, a plurality of the power devices and the accommodating grooves are provided, and the power devices and the accommodating grooves are provided in one-to-one correspondence.

[0019] In some embodiments, the plurality of the power devices are distributed in a non-central symmetric structure.

[0020] In some embodiments, two of the buffer layers and the compression layers are provided, and the buffer layers and the compression layers are provided in one-to-one correspondence, and the embedding layer is located between the two buffer layers.

[0021] In a second aspect, the embodiments of the present application provide a manufacturing method of a circuit board, which is used to manufacture the circuit board of the first aspect, and the manufacturing method comprises the following steps:

[0022] The embedding layer, the buffer layer and the processing board are sequentially and laminatedly placed, so that the power device is accommodated in the accommodating groove, and the processing board comprises an insulating connecting layer and a conductive layer which are laminatedly arranged, and the insulating connecting layer is located between the conductive layer and the buffer layer.

[0023] The embedding layer, the buffer layer and the processing board are subjected to compression processing, so that part of the insulating connecting layer fills the gap between the sidewall of the accommodating groove and the power device.

[0024] A first functional hole penetrating through the conductive layer and a first hole penetrating through the insulating connecting layer are processed, the first hole is coaxially arranged with the first functional hole, and the insulating connecting layer forms the compression connecting layer.

[0025] The first conductive part is arranged in the first hole, and a first filling part is arranged in the first functional hole, the first filling part is connected with the first conductive part and is electrically conductive, the first filling part and the conductive layer form the compression circuit layer, and the processing board forms the compression layer.

[0026] In some embodiments, the embedding layer comprises a first core board and a first insulating layer which are laminatedly arranged, the embedding layer is provided with a mounting groove, and the mounting groove penetrates through the first core board and the first insulating layer; when the embedding layer, the buffer layer and the processing board are sequentially and laminatedly placed, the first insulating layer is located between the first core board and the buffer layer; after the embedding layer, the buffer layer and the processing board are subjected to the compression processing, the first insulating layer forms a first dielectric layer, part of the first dielectric layer is located between the first core board and the buffer layer, and part of the first dielectric layer fills the gap between the sidewall of the mounting groove and the heat dissipation seat.

[0027] In some embodiments, the embedded layer includes a second core plate and a second insulating layer stacked together, the second insulating layer being located between the first core plate and the second core plate, and the mounting groove penetrating the second core plate and the second insulating layer; after the embedded layer, the buffer layer and the processing plate are pressed together, the second insulating layer forms a second dielectric layer, a portion of the second dielectric layer being located between the first core plate and the second core plate, and a portion of the second dielectric layer filling the gap between the sidewall of the mounting groove and the heat sink.

[0028] The circuit board provided in this application has the following advantages: Since it includes a stacked embedded layer, a buffer layer, and a lamination layer, the buffer layer is located between the embedded layer and the lamination layer. The buffer layer is provided with a receiving groove that penetrates the buffer layer. The power device is located in the receiving groove. The orthographic projection of the buffer layer on the side of the lamination layer away from the buffer layer and the orthographic projection of the heat sink on the side of the lamination layer away from the buffer layer have an overlap. The power device is lower than the surface of the buffer layer away from the embedded layer or flush with the surface of the buffer layer away from the embedded layer. Therefore, when the embedded layer, buffer layer, and lamination layer are obtained by lamination, the buffer layer can buffer and protect the periphery of the power device in the receiving groove, preventing the lamination layer from damaging the power device.

[0029] The advantages of the circuit board manufacturing method provided in this application compared to the prior art can be found in the description of the advantages of the circuit board provided in this application compared to the prior art, which will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the circuit board structure in related technologies;

[0032] Figure 2 This is another schematic diagram of a circuit board structure in related technologies;

[0033] Figure 3 This is a flowchart of the circuit board manufacturing method in the first embodiment of this application;

[0034] Figure 4 This is a schematic diagram of the embedded layer, buffer layer, and processing plate in the first embodiment of this application;

[0035] Figure 5 Yes Figure 4The diagram shows the embedded layer, buffer layer and processing plate being laminated, and the first functional hole penetrating the conductive layer and the first hole penetrating the insulating connection layer being processed.

[0036] Figure 6 Is Figure 5 The schematic diagram of the circuit board obtained after setting a first conductive part in the first hole and setting a first filling part in the first functional hole is shown.

[0037] Figure 7 This is a schematic diagram of the circuit board structure in the second embodiment of this application;

[0038] Figure 8 This is a schematic diagram of the circuit board structure in the third embodiment of this application;

[0039] Figure 9 yes Figure 8 The top view of the heat sink, power devices and buffer core board in the circuit board shown;

[0040] Figure 10 This is a schematic diagram of the circuit board structure in the fourth embodiment of this application.

[0041] The markings in the diagram mean:

[0042] 1. Embedded layer; 2. Heat sink; 3. Power chip; 4. Prepreg; 5. Circuit layer;

[0043] 10. Embedded layer;

[0044] 101. Mounting slot; 11. First core board; 12. First dielectric layer; 120. First insulating layer; 13. Second core board; 14. Second dielectric layer; 140. Second insulating layer;

[0045] 20. Buffer layer;

[0046] 201. Receiving groove; 21. Buffer core board; 210. First connecting hole; 211. First connecting part; 212. Inner circuit layer; 2121. Clearance groove; 2122. Clearance space; 22. Buffer connecting layer; 220. Second connecting hole; 221. Second connecting part;

[0047] 30. Pressed layer;

[0048] 301, Processing board; 3011, Conductive layer; 3012, Insulating connection layer; 31, Press-fit circuit layer; 3101, First functional hole; 3102, Second functional hole; 32, Press-fit connection layer; 3201, First hole; 3202, Second hole; 321, First conductive part; 322, Second conductive part;

[0049] 40. Heat sink;

[0050] 50. Power devices. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0054] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0055] To illustrate the technical solution of this application, the following description is provided in conjunction with specific accompanying drawings and embodiments.

[0056] With the continuous development of the electronic communication industry and automotive electronics technology, both are trending towards miniaturization and multifunctionality. As a result, the requirements for related circuit board products are becoming increasingly stringent. They not only need to meet the requirements of high-current operating environments, possess ultra-high voltage withstand performance and excellent resistance to CAF (Conductive Anodic Filament), but also need to achieve high-density interconnection and have excellent heat dissipation performance. Therefore, printed circuit boards for embedded power devices (such as power chips) have emerged.

[0057] Currently, there are two common types of heat sinks used for power devices: metal heat sinks, most commonly made of copper blocks, and ceramic blocks as the base. When using copper blocks as heat sinks, the copper block is usually hollowed out by mechanical depth control or etching, and then the power device is fixed in the copper block groove. The other type uses ceramic blocks as heat sinks. Since it is impossible to make grooves in ceramic blocks by mechanical depth control or etching, the power chip is usually fixed directly on the surface of the ceramic block, so that the power chip is completely exposed on one side of the ceramic base.

[0058] Please refer to Figure 1 In related technologies, it is generally necessary to first fix the power device (such as the power chip 3) on the heat sink 2, and then embed both of them into the embedded layer 1 of the circuit board. Then, the embedded layer 1 and the lamination layer are pressed together. The lamination layer generally includes a circuit layer 5 made of copper foil. During the lamination process, because the support performance of the semi-cured sheet 4 between the embedded layer 1 and the lamination layer is weak, the periphery of the power device is not protected. The pressure of the press is directly applied to the position of the power device, which can easily damage the power device and cause the circuit board to be scrapped.

[0059] Please refer to Figure 2 On the other hand, there is a risk of insufficient adhesive filling when pressing the embedded layer 1 and the laminating layer together. Since the power device is usually smaller than the heat sink 2, and one or more power devices are usually welded to one ceramic base heat sink 2, the overall area of ​​the power device is smaller than the heat sink 2. The heat sink 2 is on the side facing the power device, and the opening of the prepreg 4 is larger than the heat sink 2. The laminating layer in the area other than the power device is in a suspended state. Therefore, after the power device is mounted on the heat sink 2, the adhesive in the prepreg 4 will flow during lamination, which needs to fill the gap between the heat sink 2 and the embedded layer. In addition to the gap between the windows of the core board, the non-power device mounting area on the top of the heat sink 2 also needs to be filled. Therefore, multiple prepreg sheets 4 are required. However, even with the addition of multiple prepreg sheets for lamination, due to the large gap in the embedded area of ​​the power device, a large amount of adhesive needs to be flowed to fill the embedded area during lamination. After lamination, the uniformity of the dielectric layer of the whole board is poor, which will still lead to the problem of depression in the embedded area of ​​the power device. This will make it difficult to control the laser blind hole processing parameters of the embedded area of ​​the power device, and it will also be difficult to set the electroplating filling parameters, making it difficult to manufacture the outer circuit layer 5.

[0060] In view of this, this application provides a circuit board and its manufacturing method. Since it includes a stacked embedded layer, a buffer layer and a lamination layer, the buffer layer is located between the embedded layer and the lamination layer. The buffer layer is provided with a receiving groove that penetrates the buffer layer. The power device is located in the receiving groove. The orthographic projection of the buffer layer on the side of the lamination circuit layer away from the buffer layer and the orthographic projection of the heat sink on the side of the lamination circuit layer away from the buffer layer have an overlap. The power device is lower than the surface of the buffer layer away from the embedded layer or flush with the surface of the buffer layer away from the embedded layer. Therefore, when the embedded layer, buffer layer and lamination layer are obtained by lamination, the buffer layer can buffer and protect the periphery of the power device in the receiving groove, so as to avoid the lamination layer from damaging the power device.

[0061] Please refer to Figures 3 to 6 The first embodiment of this application provides a circuit board including an embedded layer 10, a buffer layer 20 and a lamination layer 30 stacked together, wherein the buffer layer 20 is located between the embedded layer 10 and the lamination layer 30.

[0062] The embedded layer 10 has a heat sink 40 inside, and a power device 50 is provided on the side of the heat sink 40 facing the lamination layer 30.

[0063] The heat sink 40 can be a metal block (such as a copper block) or a ceramic block. When the heat sink 40 is a copper block, there is no need to create grooves through mechanical depth control or etching, thus reducing the cost of creating grooves for the heat sink 40. The power device 50 can be a power chip, etc.

[0064] The buffer layer 20 is provided with a receiving groove 201, which penetrates the buffer layer 20. The power device 50 is located in the receiving groove 201. The orthographic projection of the buffer layer 20 on the side of the pressed circuit layer 31 away from the buffer layer 20 overlaps with the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 away from the buffer layer 20. The power device 50 is lower than the surface of the buffer layer 20 away from the embedded layer 10 or flush with the surface of the buffer layer 20 away from the embedded layer 10.

[0065] For example, the power device 50 has a thickness of 0.2 mm, and the buffer layer 20 is 0.1 mm higher than the surface of the embedded layer 10.

[0066] The buffer layer 20 may include a core board and / or a dielectric layer. The length and width dimensions of the receiving groove 201 are both smaller than those of the heat sink 40. The power device 50 may be clearance-fitted with the receiving groove 201. Since the buffer layer 20 is closer to the power device 50, when the embedded layer 10, the buffer layer 20, and the press-fit layer 30 are obtained by pressing, the buffer layer 20 can buffer and protect the periphery of the power device 50 in the receiving groove 201, preventing the press-fit layer 30 from damaging the power device 50.

[0067] The lamination layer 30 includes a lamination circuit layer 31 and a lamination connection layer 32. Part of the lamination connection layer 32 is located between the lamination circuit layer 31 and the buffer layer 20. Part of the lamination connection layer 32 fills the gap between the side wall of the receiving groove 201 and the power device 50. The lamination connection layer 32 is provided with a first hole 3201. A first conductive part 321 is provided inside the first hole 3201. Part of the lamination circuit layer 31 is connected to the power device 50 through the first conductive part 321 and is electrically conductive.

[0068] The laminated circuit layer 31 can be a copper layer, a silver layer, or an aluminum layer, etc. The laminated connection layer 32 can be obtained by laminating and curing one or more sheets of PP, etc. The material of the first conductive part 321 can be copper, silver, or aluminum, etc. Multiple laminated circuit layers 31 and laminated connection layers 32 can be provided.

[0069] The method for manufacturing a circuit board provided in the above embodiments includes:

[0070] S100: The embedded layer 10, the buffer layer 20 and the processing board 301 are placed sequentially and stacked, so that the power device 50 is housed in the receiving groove 201. The processing board 301 includes an insulating connection layer 3012 and a conductive layer 3011 stacked together. The insulating connection layer 3012 is located between the conductive layer 3011 and the buffer layer 20.

[0071] S200: The embedded layer 10, the buffer layer 20 and the processing board 301 are pressed together so that part of the insulating connection layer 3012 fills the gap between the side wall of the receiving groove 201 and the power device 50.

[0072] Since the orthographic projection of the buffer layer 20 on the side of the pressed circuit layer 31 away from the buffer layer 20 overlaps with the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 away from the buffer layer 20, and the power device 50 is lower than or flush with the surface of the buffer layer 20 away from the embedded layer 10, the buffer core plate 21 and the buffer connecting layer 22 provide buffer protection for the periphery of the power device 50 in the receiving groove 201 during pressing, thus playing a buffering role, dispersing the pressure of the press, and preventing the pressure from concentrating on the power device 50, thereby avoiding damage to the power device 50.

[0073] S300: A first functional hole 3101 penetrating the conductive layer 3011 and a first hole 3201 penetrating the insulating connection layer 3012 are processed. The first hole 3201 and the first functional hole 3101 are coaxially arranged. The insulating connection layer 3012 forms a press-fit connection layer 32.

[0074] The first functional hole 3101 penetrating the conductive layer 3011 and the first hole 3201 penetrating the insulating connection layer 3012 can be processed by mechanical drilling or laser drilling.

[0075] S400: A first conductive part 321 is provided in the first hole 3201, and a first filling part is provided in the first functional hole 3101. The first filling part is connected to the first conductive part 321 and is electrically conductive. The first filling part and the conductive layer 3011 form a press-fit circuit layer 31, and the processing board 301 forms a press-fit layer 30.

[0076] The first conductive part 321 can be provided in the first hole 3201 by electroplating filling, and the first filling part can be provided in the first functional hole 3101. At the same time, the conductive layer 3011 can be thickened by electroplating.

[0077] As can be seen from the above, the circuit board and its manufacturing method provided in this application include a stacked embedded layer 10, a buffer layer 20 and a lamination layer 30. The buffer layer 20 is located between the embedded layer 10 and the lamination layer 30. The buffer layer 20 is provided with a receiving groove 201 that penetrates the buffer layer 20. The power device 50 is located in the receiving groove 201. The orthographic projection of the buffer layer 20 on the side of the lamination circuit layer 31 away from the buffer layer 20 overlaps with the orthographic projection of the heat sink 40 on the side of the lamination circuit layer 31 away from the buffer layer 20. The power device 50 is lower than the surface of the buffer layer 20 away from the embedded layer 10 or flush with the surface of the buffer layer 20 away from the embedded layer 10. Therefore, when the embedded layer 10, the buffer layer 20 and the lamination layer 30 are obtained by lamination, the buffer layer 20 can buffer and protect the periphery of the power device 50 in the receiving groove 201, so as to prevent the lamination layer 30 from damaging the power device 50.

[0078] In the first embodiment, the buffer layer 20 includes a buffer core plate 21 and a buffer connecting layer 22. The receiving groove 201 penetrates the buffer core plate 21 and the buffer connecting layer 22. A portion of the buffer connecting layer 22 is located between the buffer core plate 21 and the embedded layer 10. A portion of the buffer connecting layer 22 fills the gap between the sidewall of the receiving groove 201 and the power device 50.

[0079] By adopting the above scheme, the buffer core plate 21 and the buffer connection layer 22 can better buffer and protect the periphery of the power device 50 in the receiving groove 201, thereby playing a better buffering role and dispersing the pressure of the press.

[0080] It is understood that the buffer core board 21 can be a bare core board or a double-sided copper-clad board. In the first embodiment, the buffer core board 21 is an FR-4 bare core board, which can be obtained by etching away the copper on both sides of the double-sided copper-clad board. The type of fiberglass in the bare core board can be freely selected, or a bare core board without fiberglass can be chosen. The buffer core board 21 is relatively hard and can provide good cushioning. The buffer connecting layer 22 can be obtained by laminating and curing one or more sheets of PP (Prepreg). The receiving groove 201 can be machined by mechanical milling or laser engraving.

[0081] It is also understandable that the thickness of the buffer layer 20 will decrease after lamination. For example, if the thickness of the power device 50 is 0.2mm, the thickness of the buffer layer 20 needs to be designed to be around 0.25mm-0.3mm. Therefore, a buffer core board 21 with a thickness of about 0.15mm can be selected, and two PP sheets with a thickness of about 0.075mm are selected for the buffer connection layer 22. The total thickness before lamination is about 0.3mm. After lamination, the thickness of the PP will decrease by about 0.05mm due to adhesive flow. After lamination, the thickness of the buffer layer 20 will be above 0.25mm. This design can ensure that the pressure of the press is applied to the position of the buffer core board 21 during lamination, and also meet the thickness requirements of the buffer connection layer 22 as a dielectric layer. At the same time, it can also improve the uniformity of the thickness of the corresponding layer of buffer connection layer 22, thereby improving the subsequent laser drilling and electroplating filling processes.

[0082] Among them, the orthographic projection of the buffer connection layer 22 on the side of the pressed circuit layer 31 opposite to the pressed connection layer 32 overlaps with the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 opposite to the pressed connection layer 32; and / or, the orthographic projection of the buffer core board 21 on the side of the pressed circuit layer 31 opposite to the pressed connection layer 32 overlaps with the orthographic projection of the heat sink 40 on the side of the pressed circuit layer 31 opposite to the pressed connection layer 32.

[0083] This configuration provides better buffer protection for the periphery of the power device 50 within the accommodating slot 201, resulting in a better buffering effect and dispersing the pressure of the press.

[0084] Please refer to Figure 6 Optionally, the surface of the embedded layer 10 facing the press-fit layer 30 is higher than the surface of the heat sink 40 facing the press-fit layer 30, and the thickness of the buffer layer 20 is greater than or equal to the height of the power device 50.

[0085] By adopting the above scheme, it is easy to make the power device 50 lower than the buffer layer 20 and away from the surface of the embedded layer 10.

[0086] In other embodiments, the surface of the embedded layer 10 facing the press-fit layer 30 is flush with the surface of the heat sink 40 facing the press-fit layer 30, and the thickness of the buffer layer 20 is greater than or equal to the height of the power device 50.

[0087] This configuration allows the power device to be positioned below the surface of the buffer layer 20 away from the embedded layer 10 or flush with the surface of the buffer layer 20 away from the embedded layer 10.

[0088] In the first embodiment, the surface of the embedded layer 10 facing the press-fit layer 30 is higher than the surface of the heat sink 40 facing the press-fit layer 30, and the sum of the thicknesses of the buffer core plate 21 and the buffer connection layer 22 is greater than or equal to the height of the power device 50; and / or, the surface of the embedded layer 10 facing the press-fit layer 30 is flush with the surface of the heat sink 40 facing the press-fit layer 30, and the sum of the thicknesses of the buffer core plate 21 and the buffer connection layer 22 is greater than or equal to the height of the power device 50.

[0089] Optionally, the buffer layer 20 is provided with a connection hole, and a connection part is provided inside the connection hole. The press-fit connection layer 32 is provided with a second hole 3202, and a second conductive part 322 is provided inside the second hole 3202. Part of the press-fit circuit layer 31 is connected to the heat sink 40 and electrically conductive through the second conductive part 322 and the connection part in sequence.

[0090] This configuration allows a portion of the laminated circuit layer 31 to be connected to the heat sink 40 via the second conductive part 322 and the connecting part, and to conduct electricity through the heat sink 40. The heat from the heat sink 40 is also dissipated through this portion of the laminated circuit layer 31.

[0091] In the first embodiment, the connection hole includes a first connection hole 210 disposed in the buffer core plate 21 and a second connection hole 220 disposed in the buffer connection layer 22. The connection part includes a first connection part 211 disposed inside the first connection hole 210 and a second connection part 221 disposed inside the second connection hole 220. The first connection part 211 and the second connection part 221 are connected. The partially pressed circuit layer 31 is connected to the heat sink 40 and electrically conductive through the second conductive part 322, the first connection part 211 and the second connection part 221 in sequence.

[0092] It is understood that the materials of the first connecting part 211, the second connecting part 221, and the second conductive part 322 can all be copper, silver, or aluminum, etc. When the first conductive part 321 is provided in the first hole 3201 by electroplating and the first filling part is provided in the first functional hole 3101, the first connecting part 211, the second connecting part 221, and the second conductive part 322 can be electroplated and filled in the first connecting hole 210, the second connecting hole 220, and the second hole 3202, respectively.

[0093] It should be noted that the laminated circuit layer 31 may include a control network and a heat dissipation network. The control network is connected to the power device 50 through the first conductive part 321 and is electrically conductive. The heat dissipation network is connected to the heat sink 40 through the second conductive part 322, the first connecting part 211 and the second connecting part 221 and is electrically conductive.

[0094] Please refer to Figures 4 to 6In the first embodiment, the embedded layer 10 includes a first core plate 11 and a first insulating layer 120 stacked together. The embedded layer 10 is provided with a mounting groove 101, which penetrates the first core plate 11 and the first insulating layer 120. When the embedded layer 10, the buffer layer 20 and the processing plate 301 are placed sequentially and stacked, the first insulating layer 120 is located between the first core plate 11 and the buffer layer 20. After the embedded layer 10, the buffer layer 20 and the processing plate 301 are pressed together, the first insulating layer 120 forms a first dielectric layer 12. Part of the first dielectric layer 12 is located between the first core plate 11 and the buffer layer 20, and part of the first dielectric layer 12 fills the gap between the side wall of the mounting groove 101 and the heat sink 40.

[0095] By adopting the above solution, the gap between the side wall of the mounting groove 101 and the heat sink 40 can be filled by the first medium layer 12, ensuring that the gap between the side wall of the mounting groove 101 and the heat sink 40 is fully filled, thereby better fixing the heat sink 40.

[0096] It should be noted that in some embodiments, the buffer layer 20 includes a buffer core plate 21, a buffer connection layer 22 and a first dielectric layer 12 as an integral structure.

[0097] Optionally, the embedded layer 10 includes a second core plate 13 and a second insulating layer 140 stacked together. The second insulating layer 140 is located between the first core plate 11 and the second core plate 13. The mounting groove 101 penetrates the second core plate 13 and the second insulating layer 140. After the embedded layer 10, the buffer layer 20 and the processing plate 301 are pressed together, the second insulating layer 140 forms a second dielectric layer 14. Part of the second dielectric layer 14 is located between the first core plate 11 and the second core plate 13, and part of the second dielectric layer 14 fills the gap between the side wall of the mounting groove 101 and the heat sink 40.

[0098] This configuration allows the first dielectric layer 12 and the second dielectric layer 14 to jointly fill the gap between the side wall of the mounting groove 101 and the heat sink 40, ensuring that the gap between the side wall of the mounting groove 101 and the heat sink 40 is fully filled, thereby better securing the heat sink 40.

[0099] It should be noted that both the first core board 11 and the second core board 13 can be bare core boards, single-sided copper-clad core boards, or double-sided copper-clad core boards, etc., and one or more of the first core board 11, the first insulating layer 120, the second insulating layer 140, and the second core board 13 can be provided. Both the first insulating layer 120 and the second insulating layer 140 can be made of PP.

[0100] Optionally, a portion of the buffer connection layer 22 fills the gap between the sidewall of the mounting groove 101 and the heat sink 40.

[0101] This configuration allows the first dielectric layer 12, the second dielectric layer 14, and the buffer connection layer 22 to jointly fill the gap between the side wall of the mounting groove 101 and the heat sink 40, ensuring that the gap between the side wall of the mounting groove 101 and the heat sink 40 is fully filled, thereby better securing the heat sink 40.

[0102] In related technologies, the press-fit connection layer 32 requires multiple sheets of PP to fill the gap between the sidewall of the buffer connection layer 22 filling accommodating groove 201 and the power device 50, and also to fill the perimeter of the heat sink 40. Therefore, multiple sheets of PP are required. Thicker PP is usually selected. However, thicker PP has coarser glass fibers and less adhesive content. Laser drilling will cause glass fiber residue in the hole, affecting subsequent hole filling electroplating and bringing reliability risks. At the same time, less adhesive content may also lead to insufficient adhesive filling between gaps.

[0103] Therefore, please refer to Figure 6 In the first embodiment, the press-fit bonding layer 32 includes a fiberglass cloth, which includes fiberglass filaments, and the diameter of the fiberglass filaments is less than or equal to 4 μm.

[0104] By adopting the above solution, glass fiber residue can be avoided in the first hole 3201 and the second hole 3202 during processing, thereby avoiding its impact on the subsequent setting of the first conductive part 321 and the second conductive part 322 in the first hole 3201 and the second hole 3202 respectively.

[0105] It should be noted that the buffer connection layer 22 includes fiberglass cloth, which comprises fiberglass filaments, and the diameter of the fiberglass filaments is less than or equal to 4μm. This design can prevent fiberglass residue inside the second connection hole 220 from affecting subsequent hole-filling electroplating.

[0106] Optionally, the distance between the sidewall of the receiving groove 201 and the power device 50 is 0.15mm-0.25mm, such as 0.15mm, 0.18mm, 0.20mm, 0.22mm, 0.23mm or 0.25mm.

[0107] This configuration effectively protects the periphery of the power device 50 within the receiving groove 201 through the buffer core plate 21 and the buffer connection layer 22, while also preventing the gap between the side wall of the receiving groove 201 and the power device 50 from being too large and thus unable to be filled by the buffer connection layer 22 and the pressing connection layer 32.

[0108] Please refer to Figure 7 In the second embodiment, the buffer layer 20 includes an inner circuit layer 212, and the inner circuit layer 212 is provided with a clearance space 2122 so that the inner circuit layer 212 and the power device 50 are spaced apart, and the receiving groove 201 passes through the clearance space 2122.

[0109] By adopting the above solution, electrical conduction between the inner circuit layer 212 and the power device 50 can be avoided, thus preventing a short circuit.

[0110] Optionally, the buffer layer 20 includes an inner circuit layer 212, the inner circuit layer 212 is provided with a relief groove 2121, the connection hole penetrates the bottom wall of the relief groove 2121, and the connection part and the second conductive part 322 are both spaced apart from the side wall of the relief groove 2121.

[0111] This design prevents the connecting part and the second conductive part 322 from being electrically connected to the inner circuit layer 212, thus avoiding a short circuit.

[0112] It is understandable that the inner circuit layer 212 can be located on the buffer core board 21.

[0113] Optionally, the inner circuit layer 212 is also provided with a clearance window, which is opposite to the heat sink 40 and larger than the heat sink 40, such as 0.1mm larger, to prevent the subsequent conduction problem between the pressed circuit layer 31 and the heat sink 40.

[0114] Please refer to Figure 8 and Figure 9 In the third embodiment, multiple power devices 50 and accommodating slots 201 are provided, and the power devices 50 and accommodating slots 201 are provided in a one-to-one correspondence.

[0115] By adopting the above solution, the gap between adjacent power devices 50 can be filled with glue, avoiding defects such as insufficient glue in the layer and board surface depression, and reducing the difficulty of the circuit process of the lamination circuit layer 31.

[0116] Understandably, some buffer core boards 21 are located between adjacent power devices 50, which can reduce the amount of filler between adjacent power devices 50. Each gap is filled with sufficient buffer connection layer 22 and pressing connection layer 32, which solves the problem of insufficient filler causing pressing voids that affect product reliability, as well as a series of abnormal problems such as poor outer circuit film due to board surface depression leading to circuit corrosion and scrapping.

[0117] Optionally, the multiple power devices 50 are distributed in a non-centrosymmetric structure.

[0118] With this setup, the power device 50 and the heat sink base can be checked for reversed positions through the receiving slot 201 of the buffer layer 20.

[0119] It should be noted that the multiple power devices 50 are distributed in a non-centrosymmetric structure. That is, the initial arrangement shape of the multiple power devices 50 is the first shape, and the arrangement shape after the multiple power devices 50 are rotated around the center line of the multiple power devices 50 by any angle is the second shape. The first shape and the second shape are different.

[0120] It is understandable that the multiple accommodating slots 201 are distributed in a non-centrally symmetrical structure.

[0121] For example, multiple power devices 50 and a heat sink 40 constitute a power module, such as a power module with a ceramic block as the base, especially a regularly shaped ceramic block. Because the ceramic block has poor machinability, it is difficult to distinguish the orientation of the power module by the shape of the ceramic block. In related technologies, the opening of the prepreg is larger than the overall heat sink 40. When the power module is embedded in the pressing process, it is impossible to identify whether it is placed backwards by the shape of the heat sink 40.

[0122] In this embodiment, after the power module is placed in the mounting slot 101, the buffer layer 20 can be used to check whether the power module is placed in the wrong direction. By visually comparing the positions of the power device 50 and the receiving slot 201, if they coincide, the power module is not placed in the wrong direction; if they are misaligned, the power module is placed in the wrong direction and its orientation needs to be readjusted. After the power module is checked and found to be in the correct direction, the embedded layer 10 and the buffer layer 20 are riveted together.

[0123] For example, embedded openings can be made in the first core board 11, the second core board 13, the first dielectric layer 12, and the second dielectric layer 14, which are approximately 0.1 mm larger than the heat sink 40. These openings are then used to form the mounting groove 101. The first core board 11 and the second core board 13 are fabricated into inner layer circuitry using conventional methods. Two sets of riveting holes are designed for the first core board 11, the second core board 13, the first dielectric layer 12, and the second dielectric layer 14. The first set of riveting holes is used for riveting the first core board 11, the second core board 13, the first dielectric layer 12, and the second dielectric layer 14. The second set of riveting holes is used for riveting the first core board 11, the second core board 13, the first dielectric layer 12, the second dielectric layer 14, the buffer connection layer 22, and the buffer core board 21.

[0124] The power chip can be first bonded into the heat sink 40 to form a power module, then the power module is moved into the browning fixture and browned, and then baked on a plate.

[0125] Fusion and riveting: The first core plate 11, the second core plate 13, the first dielectric layer 12 and the second dielectric layer 14 are pressed and stacked in sequence, fused and then riveted. The first set of riveting holes is selected for riveting.

[0126] Install the power module: After riveting, apply a high-temperature film to one side of the embedded layer 10 away from the buffer layer 20, and then place the power module into the mounting groove 101 formed by the embedded window in the previous process. Pay attention to the direction of placement and do not place it backwards.

[0127] Secondary riveting: Before this process, the buffer layer 20 needs to be used to check whether the power module is placed in the wrong direction. If it is misaligned, the power module needs to be readjusted. After the power module is checked and found to be in the correct direction, the embedded layer 10 and the buffer layer 20 are riveted together for the second time. This riveting requires the use of the second set of riveting holes.

[0128] Both the buffer core plate 21 and the buffer connecting layer 22 can be machined with windows by mechanical milling or laser cutting. The windows on the buffer core plate 21 and the windows on the buffer connecting layer 22 form a receiving groove 201.

[0129] Pre-lamination and lamination: The embedded layer 10, buffer layer 20, power module and processing board 301 are formed into a whole. After lamination, the first dielectric layer 12 of the embedded layer 10, the buffer connection layer 22 of the buffer layer 20 and the insulating connection layer 3012 of the processing board 301 are partially filled with adhesive into the gap between the side wall of the receiving groove 201 and the power device 50. The buffer connection layer 22 of the buffer layer 20 and the insulating connection layer 3012 of the processing board 301 partially fill the gap area between adjacent chips with adhesive, so that the power device 50 is fixed in the embedded layer 10 and the buffer layer 20, and each area has enough adhesive to fill.

[0130] Laser drilling: The laser processing parameters are set according to the thickness of the insulating bonding layer 3012. Because fine glass fiber is selected and the uniformity of the insulating bonding layer 3012 in this area is good, the processing parameters for this process are relatively easy to set, and there will be no quality problems such as glass fiber residue in laser blind holes or residual adhesive at the bottom of the hole.

[0131] Plasma: Select the corresponding processing parameters according to the type of material, and control the remaining requirements according to the normal embedded power chip production requirements.

[0132] Copper plating: Production is carried out normally according to standard processing parameters.

[0133] Hole filling: The hole filling electroplating parameters are set according to the thickness of the press-fit bonding layer 32 and the diameter of the laser hole. Because the thickness uniformity of the press-fit bonding layer 32 is good, the processing difficulty of hole filling electroplating is reduced, and there will be no abnormalities such as hole opening depression of the first functional hole 3101 and the second functional hole 3102, or core wrapping of the first hole 3201 and the second hole 3202 in local positions.

[0134] Outer layer circuit: The outer layer of the laminated circuit layer 31 is fabricated by lamination, exposure, development and etching. Due to the sufficient lamination and filling of adhesive, there are no local depressions on the board surface, the lamination process is normal, and there is no abnormality in the etching of the circuit by chemical corrosion.

[0135] AOI (Automated Optical Inspection): AOI inspection is performed using conventional methods.

[0136] Solder resist / characters: Solder resist / characters are applied using standard methods.

[0137] Molding: The molding process is completed using conventional methods, dividing the large panel into multiple unit panels.

[0138] Electrical testing: Test according to the requirements of the embedded power chip.

[0139] OSP (Organic Solderability Preservative): Fabricated according to the requirements of embedded power chips.

[0140] Quality inspection / packaging and shipping: Quality inspection is completed through standard methods until packaging and shipping.

[0141] Please refer to Figure 10 In the fourth embodiment, two buffer layers 20 and two pressing layers 30 are provided, and the buffer layers 20 and the pressing layers 30 are provided in a one-to-one correspondence, with the embedded layer 10 located between the two buffer layers 20.

[0142] By adopting the above scheme, the embedded layer 10 can be located inside the circuit board, thus obtaining a fully embedded circuit board.

[0143] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: An embedded layer, a buffer layer, and a processing board are stacked sequentially. A heat sink is provided inside the embedded layer, and a power device is positioned on the side of the heat sink facing the processing board. The embedded layer includes a first core board and a first insulating layer stacked together. The first insulating layer is located between the first core board and the buffer layer. The buffer layer has a receiving groove that penetrates the buffer layer, allowing the power device to be housed within it. Multiple power devices and receiving grooves are provided, with each power device and receiving groove corresponding to a specific one. The buffer layer includes a buffer core board and a buffer connecting layer, with the receiving groove penetrating both the buffer core board and the buffer connecting layer. The buffer connection layer is located between the buffer core board and the embedded layer. Part of the buffer core board and part of the buffer connection layer are located between adjacent power devices. The buffer core board is a bare core board or a double-sided copper-clad core board. The processing board includes an insulating connection layer and a conductive layer stacked together. The insulating connection layer is located between the conductive layer and the buffer layer. The orthographic projection of the buffer layer on the side of the conductive layer away from the buffer layer overlaps with the orthographic projection of the heat sink on the side of the conductive layer away from the buffer layer. The power device is lower than the surface of the buffer layer away from the embedded layer or flush with the surface of the buffer layer away from the embedded layer. The embedded layer, the buffer layer, and the processing board are pressed together so that a portion of the insulating connection layer and a portion of the buffer connection layer fill the gap between the sidewall of the receiving groove and the power device. The first insulating layer forms a first dielectric layer, and a portion of the first dielectric layer is located between the first core board and the buffer layer. A first functional hole penetrating the conductive layer and a first hole penetrating the insulating connection layer are processed, the first hole and the first functional hole are coaxially arranged, and the insulating connection layer forms a press-fit connection layer; A first conductive part is provided in the first hole, and a first filling part is provided in the first functional hole. The first filling part is connected to the first conductive part and is electrically conductive. The first filling part and the conductive layer form a press-fit circuit layer, and the processing board forms a press-fit layer.

2. The method for manufacturing a circuit board according to claim 1, characterized in that, The embedded layer is provided with an installation groove, which penetrates the first core board and the first insulating layer; after the embedded layer, the buffer layer and the processing board are pressed together, part of the first dielectric layer fills the gap between the side wall of the installation groove and the heat sink.

3. The method for manufacturing a circuit board according to claim 2, characterized in that, The embedded layer includes a second core plate and a second insulating layer stacked together. The second insulating layer is located between the first core plate and the second core plate. The mounting groove penetrates the second core plate and the second insulating layer. After the embedded layer, the buffer layer and the processing plate are pressed together, the second insulating layer forms a second dielectric layer. Part of the second dielectric layer is located between the first core plate and the second core plate, and part of the second dielectric layer fills the gap between the sidewall of the mounting groove and the heat sink.

4. A circuit board, characterized in that, The circuit board is manufactured by the method of manufacturing a circuit board as described in any one of claims 1 to 3, wherein the circuit board includes an embedded layer, a buffer layer and a laminating layer stacked together, and the buffer layer is located between the embedded layer and the laminating layer; A heat sink is provided inside the embedded layer, and a power device is provided on the side of the heat sink facing the laminated layer; The buffer layer is provided with a receiving groove that penetrates the buffer layer. The power device is located in the receiving groove. The orthographic projection of the buffer layer on the side of the laminated circuit layer away from the buffer layer and the orthographic projection of the heat sink on the side of the laminated circuit layer away from the buffer layer have an overlapping portion. The power device is lower than the surface of the buffer layer away from the embedded layer or flush with the surface of the buffer layer away from the embedded layer. The buffer layer includes a buffer core board and a buffer connecting layer. The receiving groove penetrates the buffer core board and the buffer connecting layer. Part of the buffer connecting layer is located between the buffer core board and the embedded layer. Part of the buffer connecting layer fills the gap between the sidewall of the receiving groove and the power device. The buffer core board is a bare core board or a double-sided copper-clad core board. The lamination layer includes a lamination circuit layer and a lamination connection layer. A portion of the lamination connection layer is located between the lamination circuit layer and the buffer layer. A portion of the lamination connection layer fills the gap between the sidewall of the receiving groove and the power device. The lamination connection layer is provided with a first hole, and a first conductive part is provided inside the first hole. A portion of the lamination circuit layer is connected to the power device through the first conductive part and is electrically conductive.

5. The circuit board according to claim 4, characterized in that, The orthographic projection of the buffer connecting layer on the side of the pressed circuit layer opposite to the pressed connecting layer overlaps with the orthographic projection of the heat sink on the side of the pressed circuit layer opposite to the pressed connecting layer; and / or, the orthographic projection of the buffer core plate on the side of the pressed circuit layer opposite to the pressed connecting layer overlaps with the orthographic projection of the heat sink on the side of the pressed circuit layer opposite to the pressed connecting layer.

6. The circuit board according to claim 4, characterized in that, The buffer layer includes an inner circuit layer, which has a clearance space so that the inner circuit layer is spaced apart from the power device, and the receiving slot extends through the clearance space.

7. The circuit board according to claim 4, characterized in that, The surface of the embedded layer facing the lamination layer is higher than the surface of the heat sink facing the lamination layer, and the thickness of the buffer layer is greater than or equal to the height of the power device; Alternatively, the surface of the embedded layer facing the lamination layer is flush with the surface of the heat sink facing the lamination layer, and the thickness of the buffer layer is greater than or equal to the height of the power device.

8. The circuit board according to claim 4, characterized in that, The buffer layer is provided with a connection hole, and a connection part is provided inside the connection hole. The press-fit connection layer is provided with a second hole, and a second conductive part is provided inside the second hole. Part of the press-fit circuit layer is connected to the heat sink in sequence through the second conductive part and the connection part and is electrically conductive.

9. The circuit board according to claim 8, characterized in that, The buffer layer includes an inner circuit layer, which is provided with a clearance groove. The connecting hole penetrates the bottom wall of the clearance groove, and the connecting part and the second conductive part are both spaced apart from the side wall of the clearance groove.

10. The circuit board according to claim 4, characterized in that, The press-fit bonding layer includes fiberglass cloth, which includes fiberglass filaments, and the diameter of the fiberglass filaments is less than or equal to 4 μm.

11. The circuit board according to any one of claims 4 to 10, characterized in that, The distance between the sidewall of the receiving groove and the power device is 0.15mm-0.25mm.

12. The circuit board according to claim 4, characterized in that, The power devices are distributed in a non-centrosymmetric structure.

13. The circuit board according to any one of claims 4 to 10, characterized in that, Two buffer layers and two pressing layers are provided, and the buffer layers and the pressing layers are provided in a one-to-one correspondence. The embedded layer is located between the two buffer layers.

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