Semiconductor structure and preparation method thereof, storage system and electronic equipment
By forming the first and second connection holes simultaneously and forming the connection with the bit line in the same process step, the problem of low production yield of dynamic random access memory is solved, and higher production yield and connection reliability are achieved.
Patent Information
- Application Number
- CN202410255757.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-06
- Publication Date
- 2025-09-09
AI Technical Summary
In the prior art, the production yield of dynamic random access memory is low, especially when forming the connection holes of the gate layer, shielding layer and bit line, there is a risk of cutting the bit line, and the gate layer cannot be led out through the array connection column.
A method of simultaneously forming the first connection hole and the second connection hole is adopted to connect to the gate layer and the shielding layer respectively, and a third connection hole is formed in the same process step to connect to the bit line. By adjusting the etching rate and the opening shape, the risk of over-etching is reduced and the reliability of the connection is improved.
Without reducing production efficiency, the production yield of the semiconductor structure is improved, the risk of the bit line being cut is reduced, and it is ensured that the gate layer and the shielding layer can be effectively led out.
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Figure CN120614802A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a storage system, and an electronic device. Background Art
[0002] Dynamic Random Access Memory (DRAM) consists of multiple memory cells, each of which is composed of a capacitor controlled by a transistor. In other words, a DRAM is a memory cell consisting of one transistor and one capacitor (1T1C). Improving the production yield of DRAM is a current challenge. Summary of the Invention
[0003] In one aspect, a method for preparing a semiconductor structure is provided. The method for preparing a semiconductor structure comprises:
[0004] An intermediate semiconductor structure is formed; the intermediate semiconductor structure includes a plurality of active pillars, a plurality of gate layers, and a plurality of shielding layers. A first interlayer insulating layer is formed; along a third direction, the first interlayer insulating layer covers a surface of one side of the intermediate semiconductor structure. A first connection hole and a second connection hole are simultaneously formed. The first connection hole penetrates the first interlayer insulating layer and stops at the gate layer; the second connection hole penetrates the first interlayer insulating layer and stops at the shielding layer. A first connection column and a second connection column are formed in the first connection hole and the second connection hole, respectively. The first connection column is connected to the gate layer, and the second connection column is connected to the shielding layer.
[0005] In some embodiments, a shape of an opening of the first connection hole at one end away from the gate layer is the same as a shape of an opening of the second connection hole at one end away from the shielding layer.
[0006] In some embodiments, an opening area of the first connection hole at one end away from the gate layer is smaller than or equal to an opening area of the second connection hole at one end away from the shielding layer.
[0007] In some embodiments, the plurality of active pillars are arranged in multiple rows and columns along a first direction and a second direction, the first direction and the second direction intersecting each other. The intermediate semiconductor structure further comprises a plurality of bit lines, each bit line being connected to a column of the active pillars.
[0008] The manufacturing method further includes forming a third connection hole; the third connection hole penetrates the first interlayer insulating layer and stops at the bit line. During the process of forming the first connection column and the second connection column in the first connection hole and the second connection hole, respectively, a third connection column is formed in the third connection hole. The third connection column is connected to the bit line.
[0009] In some embodiments, after the first and second connection holes are simultaneously formed, a third connection hole is formed. Forming the third connection hole includes: filling the first and second connection holes with a sacrificial material. Forming a mask layer on a side of the first interlayer insulating layer away from the intermediate semiconductor structure. The mask layer has a first opening that overlaps the bit line along a third direction. The first direction and the second direction are both perpendicular to the third direction. Using the mask layer as a mask, the first interlayer insulating layer is etched until the bit line is exposed. Removing the sacrificial material from the mask layer, the first connection hole, and the second connection hole.
[0010] In some embodiments, an opening area of the third connection hole at one end away from the bit line is greater than or equal to an opening area of the first connection hole at one end away from the gate layer.
[0011] In another aspect, a semiconductor structure is provided, comprising a plurality of active pillars, a plurality of gate layers, a plurality of bit lines, a plurality of first connecting pillars, and a plurality of third connecting pillars. The plurality of active pillars are arranged in a plurality of rows and columns along a first direction and a second direction, wherein the first direction and the second direction intersect. The gate layer is located between two adjacent rows of active pillars. One of the bit lines is connected to one column of the active pillars. The first connecting pillar is connected to the gate layer. The third connecting pillar is connected to the bit line.
[0012] The third connecting pillar and the first connecting pillar are extended to the same side of the plurality of active pillars along a third direction. The first direction and the second direction are both perpendicular to the third direction. The area of a surface of the third connecting pillar at an end away from the bit line is greater than or equal to the area of a surface of the first connecting pillar at an end away from the gate layer.
[0013] In some embodiments, the semiconductor structure further includes a plurality of shielding layers and a plurality of second connecting pillars. The shielding layer is located between two adjacent rows of active pillars. The gate layer and the shielding layer are located on opposite sides of a row of active pillars. The second connecting pillars are connected to the shielding layer. Furthermore, along the third direction, the first connecting pillar and the second connecting pillar extend to the same side of the plurality of active pillars.
[0014] In some embodiments, the plurality of gate layers are divided into a plurality of gate structures, each of the gate structures comprising two gate layers arranged in the second direction. The plurality of gate structures and the plurality of shielding layers are alternately arranged in the second direction and are respectively located between two adjacent rows of active pillars.
[0015] In some embodiments, along the first direction, the first connecting pillar is connected to the gate layer on one side of the multiple active pillars; two first connecting pillars respectively connected to the two gate layers of the same gate structure are located on opposite sides of the multiple active pillars.
[0016] In some embodiments, a shape of a surface of the first connecting pillar away from the gate layer is the same as a shape of a surface of the second connecting pillar away from the shielding layer.
[0017] In some embodiments, an area of a surface of the first connecting pillar away from the gate layer is smaller than or equal to an area of a surface of the second connecting pillar away from the shielding layer.
[0018] In some embodiments, along the first direction, the second connecting pillars are connected to the shielding layer at one side of the plurality of active pillars. Two second connecting pillars respectively connected to two adjacent shielding layers are located on opposite sides of the plurality of active pillars.
[0019] In some embodiments, along the second direction, the third connecting pillar is connected to the bit line at one side of the plurality of active pillars. Two third connecting pillars respectively connected to two adjacent bit lines are located on opposite sides of the plurality of active pillars.
[0020] In another aspect, a storage system is provided, comprising a controller and a memory, wherein the memory comprises the semiconductor structure according to some of the above embodiments, and the controller is coupled to the memory to control the memory to store data.
[0021] In another aspect, an electronic device is provided, comprising the storage system and the processor according to the above embodiment, wherein the storage system is connected to the processor. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.
[0023] Figure 1 is a three-dimensional structural diagram of a memory according to some embodiments;
[0024] Figure 2 is a cross-sectional view of a memory according to some embodiments;
[0025] Figure 3 for Figure 1 A structural diagram of a storage unit in ;
[0026] Figure 4 for Figure 3 The equivalent circuit diagram of the memory cell shown;
[0027] Figure 5 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;
[0028] Figure 6 is a top view of an intermediate semiconductor structure or a semiconductor structure according to some embodiments;
[0029] Figure 7 is a diagram of steps for preparing a semiconductor structure according to some embodiments;
[0030] Figure 8 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;
[0031] Figures 9 to 15 is a diagram showing the steps of a method for preparing a semiconductor structure according to some embodiments;
[0032] Figure 16 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;
[0033] Figure 17 and Figure 18 is a diagram showing the steps of a method for preparing a semiconductor structure according to some embodiments;
[0034] Figure 19 is a bottom view of a semiconductor structure according to some embodiments;
[0035] Figure 20 is a cross-sectional view of a semiconductor structure according to some embodiments;
[0036] Figure 21 is another cross-sectional view of a semiconductor structure according to some embodiments;
[0037] Figure 22 is another cross-sectional view of a semiconductor structure according to some embodiments;
[0038] Figure 23 is another cross-sectional view of a semiconductor structure according to some embodiments;
[0039] Figure 24 is a block diagram of a storage system according to some embodiments;
[0040] Figure 25 is a block diagram of a storage system according to some other embodiments;
[0041] Figure 26 is a block diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION
[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.
[0043] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.
[0044] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0046] When describing some embodiments, the terms "connected" and "coupled," and their derivatives, may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
[0047] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.
[0048] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.
[0049] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.
[0050] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).
[0051] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.
[0052] The term "overlap" or "overlapping" means that a first object may be above or below or to the side of a second object, and vice versa. Additionally, the term "overlap" may include stacking, stacking, facing, extending over, covering, or partially covering, or any other suitable term that would be appreciated and understood by one of ordinary skill in the art.
[0053] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.
[0054] In the present disclosure, the first electrode is one of the source and drain of a transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the present disclosure can be structurally indistinguishable.
[0055] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.
[0056] Figure 1 is a three-dimensional structural diagram of a memory according to some embodiments, Figure 2 is a cross-sectional view of a memory according to some embodiments, Figure 3 for Figure 1 The structural diagram of a storage unit in Figure 4 for Figure 3 The equivalent circuit diagram of the memory cell is shown.
[0057] See also Figure 1 and Figure 2 Some embodiments of the present disclosure provide a memory 10 including a semiconductor device 100 and a peripheral device 200 . The peripheral device 200 may be disposed on one side of the semiconductor device 100 .
[0058] like Figure 2 As shown, the semiconductor device 100 may include a memory cell array 110 and a common layer GD. The peripheral device 200 may be disposed on a side of the memory cell array 110 away from the common layer GD.
[0059] See also Figure 2 and Figure 3 The common layer GD can be connected to a first reference voltage, which can be a ground voltage or other voltage. The common layer GD can be made of, for example, a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, and metal silicide. Other suitable materials are also possible, and are not specifically limited in the present disclosure.
[0060] See also Figure 1and Figure 2 , the memory cell array 110 includes a plurality of memory cells 111 arranged in an array. Figure 3 and Figure 4 The memory cell 111 includes a first transistor T1 and a capacitor C. The first electrode of the first transistor T1 can be connected to a bit line BL, for example. The second electrode of the first transistor T1 can be connected to one plate of the capacitor C, for example. The other plate of the capacitor C can be connected to a common layer GD, for example. The gate of the first transistor T1 can be, for example, part of the gate layer 40. In this way, a voltage applied through the gate layer 40 can control the first transistor T1 to be turned on or off. When the first transistor T1 is turned on, the bit line BL performs a read or write operation on the first transistor T1.
[0061] On this basis, if Figure 2 As shown, the semiconductor device 100 may further include a shielding layer 50 . The shielding layer 50 is disposed between two adjacent first transistors T1 to reduce electromagnetic interference generated between the adjacent first transistors T1 .
[0062] See also Figure 2 and Figure 3 The shielding layer 50 can be connected to a second reference voltage, which can be, for example, a ground voltage or a negative voltage, or other voltages. The shielding layer 50 can be made of a conductive material, such as titanium nitride, or other suitable materials, which are not specifically limited in the present disclosure.
[0063] In some embodiments, see Figure 2 The semiconductor device 100 may further include an array interconnect layer 120 , which may be connected to the memory cell 111 to enable transmission of electrical signals between the memory cell 111 and an external circuit (such as the peripheral circuit mentioned below).
[0064] For example, Figure 2 As shown, the array interconnection layer 120 may include an array interconnection conductor layer 121, a first interlayer insulating layer 122, and a plurality of array connection pillars 123. The array interconnection conductor layer 121 may be configured to provide interconnection traces on the same layer. The gate layer 40, the shielding layer 50, and the bit line BL may be respectively led out of the array interconnection conductor layer 121 through the array connection pillars 123. Different array interconnection conductor layers 121 may be connected through the array connection pillars 123.
[0065] The array interconnect conductor layer 121 and the array connection pillar 123 may be made of a conductive material. For example, the conductive material may include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and may also include other suitable materials. This embodiment of the present disclosure does not specifically limit this.
[0066] The material of the first interlayer insulating layer 122 can be an insulating material. For example, the insulating material can include at least one of silicon oxide, silicon nitride, and a high dielectric constant insulating material, and can also include other suitable materials, which is not specifically limited in the embodiment of the present disclosure.
[0067] like Figure 2 As shown, the peripheral device 200 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed-signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random-access memories (SRAMs)).
[0068] In some embodiments, as Figure 2 As shown, the peripheral device 200 may include a substrate 210, a second transistor T2 disposed on the substrate 210, and a peripheral interconnection layer 220 disposed on the substrate 210. The peripheral circuit may include the second transistor T2.
[0069] The substrate 210 may be made of single crystal silicon or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film. The peripheral interconnect layer 220 is connected to the second transistor T2 to enable electrical signal transmission between the second transistor T2 and the peripheral interconnect layer 220.
[0070] For example, Figure 2 As shown, the peripheral interconnection layer 220 may include a peripheral interconnection conductor layer 221, a second interlayer insulating layer 222, and a plurality of peripheral connection pillars 223. The peripheral interconnection conductor layer 221 may be configured to provide interconnection traces on the same layer, and different peripheral interconnection conductor layers 221 may be connected via the peripheral connection pillars 223.
[0071] The material of the peripheral interconnect conductor layer 221 and the peripheral connection pillar 223 can be a conductive material, which can include at least one of tungsten, cobalt, copper, aluminum, and metal silicide, and can also include other suitable materials, which is not specifically limited in the embodiments of the present disclosure.
[0072] The material of the second interlayer insulating layer 222 is an insulating material. For example, the insulating material may include at least one of silicon oxide, silicon nitride, and a high dielectric constant insulating material, and may also include other suitable materials, which are not specifically limited in the embodiments of the present disclosure.
[0073] In some embodiments, as Figure 2 As shown, the peripheral interconnect layer 220 can be connected to the array interconnect layer 120, so that the semiconductor device 100 is connected to the peripheral device 200. Since the peripheral interconnect layer 220 is connected to the array interconnect layer 120, the peripheral circuit in the peripheral device 200 can be connected to the memory cell 111 in the semiconductor device 100, so as to realize the transmission of electrical signals between the peripheral circuit and the memory cell 111.
[0074] In some possible implementations, such as Figure 2 As shown, the peripheral interconnect layer 220 and the array interconnect layer 120 are bonded, so that the peripheral interconnect conductor layer 221 in the peripheral interconnect layer 220 contacts the corresponding array interconnect conductor layer 121 in the array interconnect layer 120, thereby enabling the peripheral circuit in the peripheral device 200 to be connected to the memory cell 111 in the semiconductor device 100.
[0075] In related technologies, in order to improve the production efficiency of semiconductor devices, the array connection columns that connect the gate layer, the shielding layer and the bit line respectively, the connection holes corresponding to the array connection columns connected to the bit line and the array connection columns connected to the gate layer are formed in the same process step.
[0076] However, in the process of forming the connection hole, there is a high risk of the bit line being cut, and the connection hole fails to expose the gate layer, resulting in the gate layer being unable to be led out through the array connection pillar, and the production yield of the semiconductor device is low.
[0077] Based on this, see Figure 5 Some embodiments of the present disclosure provide a method for preparing a semiconductor structure 400 , including S100 to S400 .
[0078] Among them, such as Figure 2 As shown, the semiconductor structure 400 may include the memory 10, for example, the semiconductor structure 400 includes the semiconductor device 100 and the peripheral device 200. Exemplarily, the semiconductor structure 400 may also be a part of the memory 10, for example, the semiconductor structure 400 is the semiconductor device 100 in the memory 10, which is not specifically limited in the embodiments of the present disclosure.
[0079] S100: See Figure 6 , forming an intermediate semiconductor structure 400 ′.
[0080] In the above steps, the intermediate semiconductor structure 400 ′ includes a plurality of active pillars 30 , a plurality of gate layers 40 and a plurality of shielding layers 50 .
[0081] For example, Figure 6 and Figure 7 As shown, multiple active pillars 30 extend along the third direction Z, and multiple active pillars 30 are arranged in multiple rows and columns along the first direction X and the second direction Y, each row includes one or more active pillars 30 arranged along the first direction X, and each column includes one or more active pillars 30 arranged along the second direction Y.
[0082] Among them, see Figure 7 The active column 30 includes a first electrode 31 , a channel 32 and a second electrode 33 of the first transistor T1 . The first electrode 31 and the second electrode 33 are opposite ends of the active column 30 in the third direction Z. The channel 32 is located between the first electrode 31 and the second electrode 33 .
[0083] It should be noted that the first direction X and the second direction Y intersect and are both perpendicular to the third direction Z. For example, the first direction X and the second direction Y are perpendicular and may be two orthogonal directions in the plane where the common layer GD is located, which is not specifically limited in the embodiment of the present disclosure.
[0084] On this basis, if Figure 6 As shown, the gate layer 40 and the shielding layer 50 may be located between two adjacent rows of active pillars 30 , and the gate layer 40 and the shielding layer 50 are respectively located on opposite sides of a row of active pillars 30 .
[0085] For example, see Figure 6 The multiple gate layers 40 are divided into multiple gate structures 410, each of which includes two gate layers 40 arranged in the second direction Y. The multiple gate structures 410 and the multiple shielding layers 50 are alternately arranged in the second direction Y and are respectively located between two adjacent rows of active pillars 30. In this case, the two gate layers 40 in the same gate structure 410 can be prepared in the same process step, which can simplify the process flow, improve production efficiency, and achieve higher storage density.
[0086] In some embodiments, see Figure 8 , S100 includes S110 to S130.
[0087] S110: See Figure 9 , a plurality of first trenches 601 and a plurality of second trenches 602 are formed in the substrate 60 , and the target trenches 60M are filled with insulating material.
[0088] In the above steps, the first trench 601 extends along the first direction X, and the second trench 602 extends along the second direction Y. Moreover, the first trench 601 and the second trench 602 intersect, so that the semiconductor layer 513 is patterned into a plurality of active pillars 30 arranged in an array. Figure 9 The target trench 60M is filled with insulating material. The target trench 60M is the portion of the first trench 601 and the second trench 602 that is not between two adjacent rows of active pillars 30. The insulating material fills the portion outside the two adjacent rows of active pillars 30 to insulate the two adjacent active pillars 30 and to provide flatness and support.
[0089] It should be noted that the widths of the plurality of first trenches 601 in the second direction Y may be unequal, which is not specifically limited in the present embodiment. Furthermore, the first trenches 601 and the second trenches 602 do not penetrate the substrate 60 , and the unetched portion of the substrate 60 forms the substrate 70 .
[0090] S120: See Figure 6 and Figure 9 , along the second direction Y, in two adjacent first trenches 601 , a gate structure 410 is formed in one first trench 601 , and an isolation structure 510 is formed in the other first trench 601 .
[0091] like Figure 6 and Figure 7 As shown, the gate structure 410 may include, for example, two gate layers 40 and a first insulating structure 420. Along the second direction Y, the two gate layers 40 are oppositely disposed and located between two ends of adjacent active pillars 30 in the third direction Z at both ends.
[0092] The first insulating structure 420 is located between the two gate layers 40 and between the gate layer 40 and an adjacent row of active pillars 30, and covers both ends of the gate layer 40 in the third direction Z. Along the third direction Z, the surfaces of both ends of the first insulating structure 420 may be flush with the surfaces of both ends of the active pillars 30 in the third direction Z, so as to provide flatness and support.
[0093] like Figure 6 and Figure 7 As shown, the isolation structure 510 may include, for example, a shielding layer 50 and a second insulating structure 520. The two ends of the shielding layer 50 in the third direction Z are located between the two ends of any adjacent gate layer 40 in the third direction Z, so as to avoid the risk of the shielding layer 50 causing leakage current or cutoff of the first transistor T1.
[0094] The second insulating structure 520 is located between the shielding layer 50 and two adjacent rows of active pillars 30, and covers both ends of the shielding layer 50 in the third direction Z. Along the third direction Z, the surfaces of both ends of the second insulating structure 520 can be flush with the surfaces of both ends of the active pillars 30 in the third direction Z, so as to provide flatness and support.
[0095] S130: See Figure 7 and Figure 9 , the substrate 70 is removed so that the active pillars 30 are exposed.
[0096] In the above steps, the substrate 70 may be removed by any one of a dry etching process, a wet etching process, or a planarization process. For example, the substrate 70 may be removed by chemical mechanical polishing until the active pillars 30 are exposed.
[0097] In some embodiments, see Figure 6 and Figure 7 The middle semiconductor structure 400' further includes a plurality of bit lines BL, and one bit line BL is connected to one column of active pillars 30. At this time, S100 further includes S140.
[0098] S140: See Figure 6 and Figure 7 , forming a bit line BL.
[0099] In the above steps, the bit line BL is connected to a column of active pillars 30. The bit line BL can be formed by, for example, forming a silicon layer using a deposition process, and then doping the silicon layer with nickel using a doping process to form a nickel-silicon layer. The portion of the nickel-silicon layer between two adjacent columns of active pillars is then removed, and the remaining portion of the nickel-silicon layer serves as the bit line BL. It should be understood that a thinner silicon layer improves the uniformity of nickel diffusion. In other words, a thinner bit line BL improves its conductivity and reduces the parasitic capacitance between adjacent bit lines BL.
[0100] S200: See Figure 7 and Figure 10 , forming a first interlayer insulating layer 122.
[0101] In the above steps, along the third direction Z, the first interlayer insulating layer 122 covers the surface of one side of the intermediate semiconductor structure 400 ′.
[0102] The first interlayer insulating layer 122 may be formed by a thin film deposition process or a coating process. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).
[0103] S300: See Figure 11 and Figure 12 , the first connection hole 81 and the second connection hole 82 are formed simultaneously.
[0104] In the above steps, the first connection hole 81 penetrates the first interlayer insulating layer 122 and stops at the gate layer 40. The second connection hole 82 penetrates the first interlayer insulating layer 122 and stops at the shielding layer 50. The first connection hole 81 and the second connection hole 82 can be removed by dry etching and / or wet etching, which is not specifically limited in the present embodiment.
[0105] It should be noted that, in the third direction Z, the first connection hole 81 also penetrates the first insulating structure 420 located between the gate layer 40 and the first interlayer insulating layer 122 (see Figure 10 ), the second connection hole 82 also penetrates the second insulating structure 520 located between the shielding layer 50 and the first interlayer insulating layer 122 (see Figure 10 ).
[0106] For some examples, see Figure 11 The shape of the opening of the first connection hole 81 at the end away from the gate layer 40 is the same as the shape of the opening of the second connection hole 82 at the end away from the shield layer 50; for example, the shape of the opening of the first connection hole 81 at the end away from the gate layer 40 and the shape of the opening of the second connection hole 82 at the end away from the shield layer 50 are both circular. This arrangement facilitates adjusting the etching rate of the first connection hole 81 and the etching rate of the second connection hole 82 during the etching process. Furthermore, the opening shapes of the mask used in the etching process are consistent, which can reduce the difficulty of manufacturing the mask.
[0107] The shape of the opening of the first connection hole 81 away from the gate layer 40 and the shape of the opening of the second connection hole 82 away from the shielding layer 50 can also be polygonal, elliptical or other irregular shapes, which are not specifically limited in the embodiment of the present disclosure. Figure 13 As shown, the opening of the second connection hole 82 at one end away from the shielding layer 50 is elliptical, and the major axis of the ellipse is arranged along the second direction Y, which facilitates the alignment of the second connection hole 82 and the corresponding shielding layer 50.
[0108] For some examples, see Figure 12 and Figure 13, the area of the opening of the first connection hole 81 at the end away from the gate layer 40 is less than or equal to the area of the opening of the second connection hole 82 at the end away from the shielding layer 50. At this time, during the process of forming the first connection hole 81 and the second connection hole 82 through the etching process, for the same material, the etching rate of the first connection hole 81 is less than or equal to the etching rate of the second connection hole 82.
[0109] Because both ends of the shielding layer 50 in the third direction Z are located between both ends of any adjacent gate layer 40 in the third direction Z, the depth of the first connection hole 81 in the third direction Z is less than the depth of the second connection hole 82 in the third direction Z. In this way, when the etching rate of the first connection hole 81 is less than or equal to the etching rate of the second connection hole 82, the second connection hole 82 can be connected to the corresponding shielding layer 50 while causing a small amount of overetching of the gate layer 40 by the first connection hole 81.
[0110] In some embodiments, see Figure 5 , the above preparation method also includes S500.
[0111] S500: See Figure 14 and Figure 15 , forming a third connection hole 83.
[0112] In the above steps, the third connection hole 83 penetrates the first interlayer insulating layer 122 and stops at the bit line BL. The third connection hole 83 can be removed by dry etching and / or wet etching, which is not specifically limited in the embodiment of the present disclosure.
[0113] The shape of the opening of the third connection hole 83 away from the gate layer 40 can be polygonal, circular, elliptical or other irregular shapes. Figure 18 As shown, the opening of the third connection hole 83 away from the gate layer 40 is elliptical, and the major axis of the ellipse is arranged along the first direction X, which facilitates the alignment of the third connection hole 83 with the corresponding bit line BL.
[0114] It should be understood that S500 is before or after S300. For example, S500 is after S300. Figure 16 , S500 includes S510 to S540.
[0115] S510: See Figure 12 and Figure 17 , the first connection hole 81 and the second connection hole 82 are filled with sacrificial material.
[0116] In the above steps, a thin film deposition process can be used to fill the first connection hole 81 and the second connection hole 82 with sacrificial material, and then any one of a dry etching process, a wet etching process or a planarization process can be used to remove the sacrificial material outside the first connection hole 81 and the second connection hole 82.
[0117] It should be noted that the sacrificial material includes at least one of spin-on dielectrics (SOD), spin-on carbon (SOC), a fluid organic material, or a fluid inorganic material. Exemplarily, the sacrificial material includes spin-on carbon.
[0118] S520: See Figure 12 and Figure 17 A mask layer 90 is formed on a side of the first interlayer insulating layer 122 away from the intermediate semiconductor structure 400 ′.
[0119] In the above steps, the mask layer 90 is provided with a first opening 91 , which overlaps the bit line BL along the third direction Z. The mask layer 90 can be formed by sequentially applying coating, exposure, and development processes, and the material of the mask layer 90 includes photoresist.
[0120] S530: See Figure 12 and Figure 17 , using the mask layer 90 as a mask, the first interlayer insulating layer 122 is etched until the bit line BL is exposed.
[0121] In the above steps, a wet etching process may be used to etch the first interlayer insulating layer 122 through the first opening 91 until the bit line BL is exposed, thereby forming the third connection hole 83 .
[0122] S540: See Figure 12 and Figure 17 , remove the sacrificial material in the mask layer 90, the first connection hole 81 and the second connection hole 82.
[0123] In the above steps, the mask layer 90 and the sacrificial materials in the first connection hole 81 and the second connection hole 82 may be removed by an etching process.
[0124] It is understood that the third connection hole 83 is prepared separately without considering the depth of other connection holes (such as the first connection hole 81). During the process of forming the third connection hole 83 through the etching process, the etching depth is easy to control, and the etching rate of the third connection hole 83 can be set according to actual conditions. In other words, the third connection hole 83 can be set according to actual conditions.
[0125] For example, see Figure 15 and Figure 18The area of the opening of the third connection hole 83 at the end away from the bit line BL is greater than or equal to the area of the opening of the first connection hole 81 at the end away from the gate layer 40. In this way, the etching rate of the etching process for forming the third connection hole 83 is relatively fast, which is not only conducive to improving production efficiency; moreover, the third connection column 1233 (see FIG. 1 ) formed in the third connection hole 83 in the subsequent process is not only conducive to improving production efficiency, but also Figure 20 ) has a larger overlapping area with the bit line BL, which is beneficial for the alignment and connection between the third connecting column 1233 and the corresponding bit line BL.
[0126] It should be understood that, in the process of forming the third connection hole 83 through the etching process, over-etching of the bit line BL should be avoided as much as possible to reduce the risk of the bit line BL being cut.
[0127] In addition, in S110, the first groove 601 is formed by an etching process, and the depth uniformity of the multiple first grooves 601 in the third direction Z is poorer than that of the parts closer to the two ends, resulting in poor height uniformity in the third direction Z at the two ends of the gate layer 40 formed in S120.
[0128] Based on this, in order to enable all the first connection holes 81 to expose the corresponding gate layer 40, and all the second connection holes 82 to expose the corresponding shielding layer 50, in the process of forming the first connection holes 81 and the second connection holes 82 through an etching process, the gate layer 40 and the shielding layer 50 need to be over-etched to a preset value.
[0129] In summary, the process of forming the first connection hole 81 and the second connection hole 82 by the etching process both requires an over-etching design, and the process of forming the third connection hole 83 by the etching process needs to avoid an over-etching design. In this case, the first connection hole 81 and the second connection hole 82 are formed simultaneously in the same process step. Compared with the related art (the first connection hole and the third connection hole are prepared in the same process), the risk of the first connection hole 81 being over-etched and causing the third connection hole 83 to break the bit line BL can be reduced, and the risk of the third connection hole 83 being designed to avoid over-etching and causing part of the first connection hole 81 to fail to expose the gate layer 40, thereby causing the gate layer to be unable to be led out can be reduced. That is, the preparation method of the semiconductor structure 400 provided in the embodiment of the present disclosure can improve the production yield without reducing the production efficiency.
[0130] S400: See Figure 18 、 Figure 19 and Figure 20 A first connecting column 1231 and a second connecting column 1232 are formed in the first connecting hole 81 and the second connecting hole 82 , respectively.
[0131] In the above steps, the first connecting pillar 1231 is connected to the gate layer 40 , and the second connecting pillar 1232 is connected to the shielding layer 50 .
[0132] The first connection pillars 1231 and the second connection pillars 1232 can be formed in the same process step. For example, a thin film deposition process can be used to fill the first connection holes 81 and the second connection holes 82, and a planarization process can be used to remove the portions outside the first connection holes 81 and the second connection holes 82.
[0133] In the case that S500 is located before S300 or between S300 and S400, during the process of S400, refer to Figure 18 、 Figure 19 and Figure 20 , a third connection column 1233 can also be formed in the third connection hole 83 to improve production efficiency.
[0134] The third connection pillar 1233 is connected to the bit line BL. For example, a thin film deposition process may be used to fill the first connection hole 81, the second connection hole 82, and the third connection hole 83, and a planarization process may be used to remove the portions outside the first connection hole 81, the second connection hole 82, and the third connection hole 83.
[0135] See also Figure 6 、 Figure 19 and Figure 20 Some embodiments of the present disclosure provide a semiconductor structure 400, which can be prepared by, for example, using the preparation method of any of the above embodiments.
[0136] For example, see Figure 6 and Figure 20 The semiconductor structure 400 includes a plurality of active pillars 30 , a plurality of gate layers 40 , a plurality of bit lines BL, a plurality of first connection pillars 1231 and a plurality of third connection pillars 1233 .
[0137] like Figure 6 As shown, a plurality of active pillars 30 are arranged in a plurality of rows and columns along a first direction X and a second direction Y. Each row includes one or more active pillars 30 arranged along the first direction X, and each column includes one or more active pillars 30 arranged along the second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.
[0138] like Figure 6 、 Figure 19 and Figure 22As shown, the gate layer 40 is located between two adjacent rows of active pillars 30, and the first connecting pillars 1231 are connected to the gate layer 40. Along the first direction X, the first connecting pillars 1231 can, for example, be connected to the gate layer 40 on one side of the plurality of active pillars 30. Furthermore, the two first connecting pillars 1231, respectively connected to the two gate layers 40 of the same gate structure 410, are located on opposite sides of the plurality of active pillars 30 to reduce the risk of shorting between two adjacent gate layers 40.
[0139] like Figure 6 、 Figure 19 and Figure 21 As shown, a bit line BL is connected to a column of active pillars 30, and a third connecting pillar 1233 is connected to the bit line BL. Along the second direction Y, the third connecting pillar 1233 can be connected to the bit line BL on one side of the plurality of active pillars 30, for example. Furthermore, the two third connecting pillars 1233, each connected to two adjacent bit lines BL, are located on opposite sides of the plurality of active pillars 30 to reduce the risk of shorting between the two adjacent bit lines BL.
[0140] On this basis, along the third direction Z, the third connecting pillar 1233 and the first connecting pillar 1231 are extended to the same side of the multiple active pillars 30. Furthermore, the surface area of the end of the third connecting pillar 1233 away from the bit line BL is greater than or equal to the surface area of the end of the first connecting pillar 1231 away from the gate layer 40. This increases the overlap area between the third connecting pillar 1233 and the bit line BL, facilitating alignment and connection between the third connecting pillar 1233 and the corresponding bit line BL, and reducing process difficulty. It should be noted that both the first direction X and the second direction Y are perpendicular to the third direction Z.
[0141] In some embodiments, see Figure 6 and Figure 21 The semiconductor structure 400 further includes a plurality of shielding layers 50, which are located between two adjacent rows of active pillars 30. The gate layer 40 and the shielding layer 50 are located on opposite sides of a row of active pillars 30 to reduce electromagnetic interference between adjacent first transistors T1.
[0142] For example, Figure 6 and Figure 21 As shown, the gate layer 40 is divided into a plurality of gate structures 410, and each gate structure 410 includes two gate layers 40 arranged in the second direction Y. The plurality of gate structures 410 and the plurality of shielding layers 50 are alternately arranged in the second direction Y and are respectively located between two adjacent rows of active pillars 30. In this case, the two gate layers 40 in the same gate structure 410 can be prepared in the same process step, which can simplify the process flow, improve production efficiency, and achieve a higher storage density.
[0143] On this basis, if Figure 6 、 Figure 19 and Figure 23 As shown, the semiconductor structure 400 further includes a plurality of second connecting pillars 1232 , which are connected to the shielding layer 50 . Along the third direction Z, the first connecting pillars 1231 and the second connecting pillars 1232 are led out to the same side of the plurality of active pillars 30 .
[0144] Among them, see Figure 6 、 Figure 19 and Figure 23 Along the first direction X, the second connecting pillars 1232 can be connected to the shielding layer 50 on one side of the plurality of active pillars 30. Furthermore, the two second connecting pillars 1232 respectively connected to two adjacent shielding layers 50 are located on opposite sides of the plurality of active pillars 30 to reduce the risk of short circuits between adjacent shielding layers 50.
[0145] In some embodiments, see Figure 19 The shape of the surface of the first connecting pillar 1231 away from the gate layer 40 is the same as the shape of the surface of the second connecting pillar 1232 away from the shielding layer 50. This facilitates adjusting the proportional relationship between the etching rate of the first connecting hole 81 corresponding to the first connecting pillar 1231 and the etching rate of the second connecting hole 82 corresponding to the second connecting pillar 1232. The opening shapes of the mask used in the etching process are consistent, which can reduce the difficulty of manufacturing the mask.
[0146] In some embodiments, see Figure 19 The area of the surface of the first connecting pillar 1231 away from the gate layer 40 is less than or equal to the area of the surface of the second connecting pillar 1232 away from the shielding layer 50. At this time, during the process of forming the first connecting hole 81 corresponding to the first connecting pillar 1231 and the second connecting hole 82 corresponding to the second connecting pillar 1232 through an etching process, for the same material, the etching rate of the first connecting hole 81 is less than or equal to the etching rate of the second connecting hole 82.
[0147] Because both ends of the shielding layer 50 in the third direction Z are located between both ends of any adjacent gate layer 40 in the third direction Z, the depth of the first connection hole 81 in the third direction Z is less than the depth of the second connection hole 82 in the third direction Z. In this way, when the etching rate of the first connection hole 81 is less than or equal to the etching rate of the second connection hole 82, the second connection hole 82 can be connected to the corresponding shielding layer 50 while causing a small amount of overetching of the gate layer 40 by the first connection hole 81.
[0148] In some embodiments, as Figure 19 and Figure 20As shown, along the first direction X, the first connecting pillar 1231 is connected to the gate layer 40 on one side of the multiple active pillars 30 , and two first connecting pillars 1231 respectively connected to two gate layers 40 of the same gate structure 410 are located on opposite sides of the multiple active pillars 30 .
[0149] Furthermore, the second connecting pillars 1232 are connected to the shielding layer 50 at one side of the active pillars 30 along the first direction X. The two second connecting pillars 1232 respectively connected to two adjacent shielding layers 50 are located on opposite sides of the active pillars 30 .
[0150] In addition, along the second direction Y, the third connecting pillars 1233 are connected to the bit lines BL at one side of the plurality of active pillars 30. The two third connecting pillars 1233 respectively connected to two adjacent bit lines BL are located on opposite sides of the plurality of active pillars 30.
[0151] Based on the above, the first connecting pillar 1231, the second connecting pillar 1232 and the third connecting pillar 1233 are arranged on the upper side, the lower side, the left side and the right side of the storage array, which can not only reduce the risk of short circuit between adjacent bit lines BL and adjacent gate layers 40 and shielding layers 50, but also improve the space utilization of the semiconductor structure 400, which is conducive to improving the storage density of the semiconductor structure 400.
[0152] On this basis, two adjacent third connecting pillars 1233 may be staggered in the first direction X to further reduce the risk of shorting between two adjacent bit lines BL. Two adjacent first connecting pillars 1231 may be staggered in the second direction Y to further reduce the risk of shorting between different gate layers 40.
[0153] In some embodiments, see Figure 20 The semiconductor structure 400 further includes a protective layer 430 , which is located between the first interlayer insulating layer 122 and the plurality of active pillars 30 and covers the region where the gate layer 40 is located to prevent damage to the gate layer 40 during the preparation of the bit lines BL.
[0154] Figure 24 is a block diagram of a storage system according to some embodiments; Figure 25 is a block diagram of a storage system according to some other embodiments.
[0155] See Figure 24 and Figure 25 Some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 20 and a memory 10. The memory 10 includes the semiconductor structure 400 according to some of the above embodiments. The controller 20 is coupled to the memory 10 to control the memory 10 to store data.
[0156] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.
[0157] In some embodiments, see Figure 24 The storage system 1000 includes a controller 20 and a memory 10, and the storage system 1000 can be integrated into a memory card.
[0158] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.
[0159] In other embodiments, see Figure 25 The storage system 1000 includes a controller 20 and a plurality of memories 10. The storage system 1000 is integrated into a solid state drive (SSD).
[0160] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.
[0161] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.
[0162] In some embodiments, the controller 20 may be configured to manage data stored in the memory 10 and communicate with an external device (eg, a host).
[0163] In some embodiments, the controller 20 may also be configured to control operations of the memory 10 , such as read, erase, and program operations.
[0164] In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the memory 10 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.
[0165] In some embodiments, the controller 20 is further configured to process error correction codes on data read from or written to the memory 10 .
[0166] Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10 ; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.
[0167] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.
[0168] Figure 26 is a block diagram of an electronic device according to some embodiments.
[0169] See Figure 26 Some embodiments of the present disclosure further provide an electronic device 2000. The electronic device 2000 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, and the like.
[0170] The electronic device 2000 may include, for example, the aforementioned storage system 1000 and processor 1100. The storage system 1000 and processor 1100 are connected, and the processor 1100 is configured to control the storage system 1000. The processor 1100 may be, for example, a central processing unit (CPU). Furthermore, the electronic device 2000 may further include a cache, etc., which is not specifically limited in the present embodiment.
[0171] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: forming an intermediate semiconductor structure; the intermediate semiconductor structure comprising a plurality of active pillars, a plurality of gate layers, and a plurality of shielding layers; forming a first interlayer insulating layer; Along the third direction, the first interlayer insulating layer covers a surface of one side of the middle semiconductor structure; forming a first connection hole and a second connection hole simultaneously; wherein the first connection hole penetrates the first interlayer insulating layer and stops at the gate layer; The second connecting hole passes through the first interlayer insulating layer and stops at the shielding layer; A first connecting column and a second connecting column are formed in the first connecting hole and the second connecting hole, respectively; the first connecting column is connected to the gate layer, and the second connecting column is connected to the shielding layer.
2. The preparation method according to claim 1, characterized in that The shape of the opening of the first connection hole at one end away from the gate layer is the same as the shape of the opening of the second connection hole at one end away from the shielding layer.
3. The preparation method according to claim 1, characterized in that An opening area of the first connection hole at one end away from the gate layer is smaller than or equal to an opening area of the second connection hole at one end away from the shielding layer.
4. The preparation method according to any one of claims 1 to 3, characterized in that The plurality of active pillars are arranged in a plurality of rows and columns along a first direction and a second direction, wherein the first direction and the second direction intersect; The intermediate semiconductor structure further includes a plurality of bit lines, wherein one bit line is connected to a column of active pillars; and the manufacturing method further includes: forming a third connection hole; wherein the third connection hole penetrates the first interlayer insulating layer and stops at the bit line; During the process of forming the first connecting pillar and the second connecting pillar in the first connecting hole and the second connecting hole, respectively, a third connecting pillar is further formed in the third connecting hole; the third connecting pillar is connected to the bit line.
5. The preparation method according to claim 4, characterized in that After the first connection hole and the second connection hole are formed simultaneously, forming a third connection hole; The forming of the third connection hole comprises: Filling the first connection hole and the second connection hole with a sacrificial material; forming a mask layer on a side of the first interlayer insulating layer away from the intermediate semiconductor structure; the mask layer is provided with a first opening, and the first opening overlaps the bit line along a third direction; the first direction and the second direction are both perpendicular to the third direction; Using the mask layer as a mask, etching the first interlayer insulating layer until the bit line is exposed; The sacrificial material in the mask layer, the first connection hole, and the second connection hole is removed.
6. The preparation method according to claim 4, characterized in that An opening area of the third connection hole at one end away from the bit line is greater than or equal to an opening area of the first connection hole at one end away from the gate layer.
7. A semiconductor structure, characterized in that include: A plurality of active pillars are arranged in a plurality of rows and columns along a first direction and a second direction, wherein the first direction and the second direction intersect; a plurality of gate layers, wherein the gate layers are located between two adjacent rows of active pillars; a plurality of bit lines, wherein one bit line is connected to a column of active pillars; a plurality of first connecting pillars, wherein the first connecting pillars are connected to the gate layer; A plurality of third connecting pillars are connected to the bit lines; and along a third direction, the third connecting pillars and the first connecting pillars are led out to the same side of the plurality of active pillars; the first direction and the second direction are both perpendicular to the third direction; the area of the surface of one end of the third connecting pillar away from the bit line is greater than or equal to the area of the surface of one end of the first connecting pillar away from the gate layer.
8. The semiconductor structure according to claim 7, wherein: Also includes: A plurality of shielding layers, wherein the shielding layers are located between two adjacent rows of active pillars; the gate layer and the shielding layer are located on opposite sides of a row of active pillars; A plurality of second connecting pillars are connected to the shielding layer; and along the third direction, the first connecting pillar and the second connecting pillar are led out to the same side of the plurality of active pillars.
9. The semiconductor structure according to claim 8, wherein: The plurality of gate layers are divided into a plurality of gate structures, each of the gate structures comprising two gate layers arranged in the second direction; The plurality of gate structures and the plurality of shielding layers are alternately arranged in the second direction and are respectively located between two adjacent rows of active pillars.
10. The semiconductor structure according to claim 9, wherein: Along the first direction, the first connecting pillar is connected to the gate layer on one side of the multiple active pillars; two first connecting pillars respectively connected to the two gate layers of the same gate structure are located on opposite sides of the multiple active pillars.
11. The semiconductor structure according to claim 8, wherein: The shape of the surface of the first connecting pillar away from the gate layer is the same as the shape of the surface of the second connecting pillar away from the shielding layer.
12. The semiconductor structure according to claim 8, wherein: An area of a surface of the first connecting pillar away from the gate layer is smaller than or equal to an area of a surface of the second connecting pillar away from the shielding layer.
13. The semiconductor structure according to claim 8, wherein: Along the first direction, the second connecting pillars are connected to the shielding layer at one side of the plurality of active pillars; and the two second connecting pillars respectively connected to two adjacent shielding layers are located at opposite sides of the plurality of active pillars.
14. The semiconductor structure according to any one of claims 7 to 13, characterized in that: Along the second direction, the third connecting pillar is connected to the bit line at one side of the plurality of active pillars; and two third connecting pillars respectively connected to two adjacent bit lines are located on opposite sides of the plurality of active pillars.
15. A storage system, characterized in that: include: A memory comprising the semiconductor structure according to any one of claims 7 to 14; The controller is coupled to the memory and controls the memory to store data.
16. An electronic device, characterized in that: include: The storage system according to claim 15; A processor is connected to the storage system.