Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device includes a lower structure and an upper structure on the lower structure. The upper structure includes a first substrate, an upper wiring on the first substrate, a lower power line in a lower portion of the first substrate, and a first bond pad between the lower power line and the lower structure. The lower power line and the first bond pad are electrically connected to each other. The upper structure is electrically connected to the lower structure through the first bond pad.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0032132 filed on March 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor and a method of manufacturing the semiconductor memory device. Background Art

[0003] As semiconductor memory device design rules continue to simplify, manufacturing processes are also constantly improving to increase the integration density, operating speed, and yield of semiconductor memory devices. Therefore, transistors with vertical channels have been proposed to increase their integration density, resistance, current driving capability, and other characteristics. Summary of the Invention

[0004] Some embodiments of the inventive concept provide a semiconductor memory device having improved electrical performance and increased integration.

[0005] The embodiments of the inventive concept are not limited to the above-mentioned embodiments, and other embodiments not mentioned above will be clearly understood by those skilled in the art from the following description.

[0006] According to some embodiments of the present invention, a semiconductor memory device may include: a lower structure; and an upper structure on the lower structure. The upper structure may include: a first substrate; an upper wiring on the first substrate; a lower power line in a lower portion of the first substrate; and a first bonding pad between the lower power line and the lower structure. The lower power line and the first bonding pad may be electrically connected to each other. The upper structure may be electrically connected to the lower structure via the first bonding pad.

[0007] According to some embodiments of the present invention, a semiconductor memory device may include: a lower structure; and an upper structure on the lower structure. The upper structure may include: a first substrate; an upper wiring on the first substrate; a lower power line in a lower portion of the first substrate; and a first bonding pad between the lower power line and the lower structure. The lower structure may include: a second substrate including a cell region; and a second bonding pad on the cell region. The first bonding pad may be exposed through a rear surface of the upper structure. The second bonding pad may be exposed through a front surface of the lower structure. The front surface of the lower structure may contact a rear surface of the upper structure. The first bonding pad and the second bonding pad may be in direct contact with each other.

[0008] According to some embodiments of the present invention, a semiconductor memory device may include: a lower structure; an upper structure on the lower structure; and a bonding structure between the lower structure and the upper structure. The upper structure may include: a first substrate; an upper wiring on the first substrate; a lower power supply line in a lower portion of the first substrate; and a backside via extending through the first substrate and connecting the upper wiring to the lower power supply line. The lower structure may include: a second substrate including a cell region; and a lower wiring layer on the cell region. The bonding structure may include: a first portion in a lower portion of the upper structure; and a second portion in an upper portion of the lower structure. The bonding structure may electrically connect the lower power supply line and the lower wiring layer to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0010] Figure 2 is a simplified perspective view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0011] Figure 3A is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0012] Figure 3B is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0013] Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0014] Figures 5A to 5E and 6A to 6D is a cross-sectional view illustrating a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept.

[0015] Figure 7 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0016] Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10 、 Figure 11 and Figure 12 is a cross-sectional view illustrating a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept.

[0017] Figure 13 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0018] Some embodiments of the present invention will be described below with reference to the accompanying drawings. Throughout this specification, similar reference numerals may indicate similar components. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. It should be understood that although the terms "first", "second", "upper", "lower" and the like can be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first element or component discussed below can be referred to as the second element or component. It should be noted that the various aspects described for an embodiment can be incorporated into different embodiments, although not specifically described in this regard. That is, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination.

[0019] Figure 1 is a block diagram illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0020] refer to Figure 1 , a semiconductor memory device may include a memory cell array 1 , a row decoder 2 , a sense amplifier 3 , a column decoder 4 and a control logic 5 .

[0021] The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each of the memory cells MC may be connected between a word line WL and a bit line BL intersecting each other.

[0022] Each memory cell MC may include a selection element TR and a data storage element DS, and the selection element TR and the data storage element DS may be electrically connected in series. The selection element TR may be connected between the data storage element DS and a word line WL, and the data storage element DS may be connected to a bit line BL through the selection element TR. The selection element TR may be a field effect transistor (FET), and the data storage element DS may be a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the selection element TR may include a transistor, the gate electrode of the transistor may be connected to the word line WL, and the source / drain terminals of the transistor may be connected to the bit line BL and the data storage element DS.

[0023] The row decoder 2 can decode an address input from the outside and can select one of the word lines WL of the memory cell array 1. The address decoded in the row decoder 2 can be provided to a row driver (not shown), and in response to a control operation of a control circuit, the row driver can provide a specific voltage to the selected word line WL and each unselected word line WL.

[0024] In response to an address decoded from the column decoder 4 , the sense amplifier 3 may detect and amplify a voltage difference between a selected bit line BL and a reference bit line, and may then output the amplified voltage difference.

[0025] The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller), and may decode an externally input address and select one of the bit lines BL.

[0026] The control logic 5 may generate control signals that control operations of writing data to the memory cell array 1 and / or reading data from the memory cell array 1 .

[0027] Figure 2 is a simplified perspective view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0028] refer to Figure 2 The semiconductor memory device may include a peripheral circuit structure PS on a semiconductor substrate 100, and may further include a cell array structure CS on the peripheral circuit structure PS. For example, the peripheral circuit structure PS may be located between the semiconductor substrate 100 and the cell array structure CS in a third direction D3 perpendicular to the top surface of the semiconductor substrate 100. In this specification, the third direction D3 may be referred to as a vertical direction.

[0029] The peripheral circuit structure PS may include core / peripheral circuits formed on the semiconductor substrate 100. The core / peripheral circuits may include Figure 1 The row decoder, column decoder, sense amplifier, and control logic discussed in [1].

[0030] The cell array structure CS may include bit lines BL, word lines WL, and Figure 1 storage unit MC. Figure 1 The memory cells MC may be two-dimensionally or three-dimensionally arranged on a plane defined by a first direction D1 and a second direction D2 intersecting each other. Figure 1 Each of the memory cells MC may include a selection element TR and a data storage element DS.

[0031] For example, the selection element TR may include a vertical channel transistor (VCT). A channel of the vertical channel transistor may have a shape extending in a direction (eg, third direction D3) perpendicular to the top surface of the semiconductor substrate 100. The data storage element DS may be a capacitor.

[0032] However, the present invention is not limited thereto. The semiconductor memory device may include a cell array structure CS on a semiconductor substrate 100 and may further include a peripheral circuit structure PS on the cell array structure CS. For example, the cell array structure CS may be located between the semiconductor substrate 100 and the peripheral circuit structure PS.

[0033] Figure 3A and Figure 3B is a plan view illustrating a semiconductor memory device according to some embodiments of the inventive concept. Figure 4 is a cross-sectional view illustrating a semiconductor memory device according to some embodiments of the inventive concept.

[0034] refer to Figure 3A 、 Figure 3B and Figure 4 , the semiconductor memory device 1000 may include a lower structure LS and an upper structure US. The upper structure US may be disposed on the lower structure LS. A rear surface USa of the upper structure US may be in contact with a front surface LSa of the lower structure LS.

[0035] Will refer to Figure 3B and Figure 4 The superstructure US is discussed in further detail.

[0036] The upper structure US may include a semiconductor substrate 100 (hereinafter referred to as a first substrate). The first substrate 100 may be a silicon substrate, but the present invention is not limited thereto. A cell region and a peripheral region may be provided on the first substrate 100. For example, a peripheral region R including a transistor TR may be provided on the first substrate 100. The peripheral region R may be a region where a signal is provided to the cell region through the transistor.

[0037] An active pattern AP may be located on the first substrate 100. The active pattern AP may be defined by an isolation pattern STI. The isolation pattern STI may include a dielectric material. The transistor TR and the source / drain pattern SD may be disposed on the active pattern AP. The source / drain pattern SD may be disposed on opposite sides of the transistor TR. The source / drain pattern SD may be disposed in an upper portion of the active pattern AP.

[0038] The first substrate 100 may include a deep device isolation pattern DTI that penetrates or extends vertically (ie, in a D3 direction) through the first substrate 100. The deep device isolation pattern DTI may define a cell region or a peripheral region R. Figure 4 As shown, the width of the deep device isolation pattern DTI in the first direction D1 may decrease with increasing distance from the top surface of the first substrate 100 in the vertical direction D3.

[0039] The deep device isolation pattern DTI may penetrate the first substrate 100. A top surface of the deep device isolation pattern DTI may be coplanar with the top surface of the first substrate 100. A bottom surface of the deep device isolation pattern DTI may be coplanar with the bottom surface of the first substrate 100. The deep device isolation pattern DTI may include a dielectric material.

[0040] A first interlayer dielectric layer 110 may be disposed on a first substrate 100. An upper wiring layer 111 may be disposed in the first interlayer dielectric layer 110. The upper wiring layer 111 may include an active contact AC, an upper wiring W1, and an upper via VI. The active contact AC may be electrically connected to the source / drain pattern SD. The active contact AC may electrically connect the source / drain pattern SD and the upper wiring W1. The active contact AC, the upper wiring W1, and the upper via VI may each include a metal material.

[0041] The second interlayer dielectric layer 120, the third interlayer dielectric layer 130, and the fourth interlayer dielectric layer 140 may be sequentially disposed on the upper wiring layer 111. For example, the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, the third interlayer dielectric layer 130, and the fourth interlayer dielectric layer 140 may include a silicon oxide layer. For another example, one or more of the second interlayer dielectric layer 120, the third interlayer dielectric layer 130, and the fourth interlayer dielectric layer 140 may be omitted. For another example, at least one interlayer dielectric layer may be formed on the fourth interlayer dielectric layer 140.

[0042] The first metal layer M1 may be disposed in the second interlayer dielectric layer 120. The first metal layer M1 may include a first wiring. According to some embodiments of the present inventive concept, the lower substrate 80 may include power lines in the form of power lines VPR1 and VPR2, which are configured to supply power to the semiconductor memory device 1000. Therefore, the power lines may be omitted from the first metal layer M1. The first metal layer M1 may be electrically connected to the active contact AC and the upper wiring W1.

[0043] A second metal layer M2 may be provided in the third interlayer dielectric layer 130. The second metal layer M2 may include a second wiring. The second wiring may be electrically connected to the first wiring of the first metal layer M1.

[0044] A third metal layer M3 may be provided in the fourth interlayer dielectric layer 140. The third metal layer M3 may include a third wiring. The third wiring may be electrically connected to the second wiring of the second metal layer M2.

[0045] A first support substrate 300 may be formed on the fourth interlayer dielectric layer 140. The first support substrate 300 may be a silicon substrate, but embodiments of the inventive concept are not limited thereto.

[0046] A first lower dielectric layer 90 may be disposed under the first substrate 100. A lower substrate 80 may be disposed under the first lower dielectric layer 90. In other embodiments, the first lower dielectric layer 90 may be omitted. Alternatively, at least one lower interlayer dielectric layer may be formed between the first lower dielectric layer 90 and the lower substrate 80.

[0047] A first lower power line VPR1 and a second lower power line VPR2 may be provided in the lower substrate 80. The first lower power line VPR1 and the second lower power line VPR2 may extend in parallel along a second direction D2 (see FIG. 1 ). Figure 3B The peripheral region R may be located between the first lower power line VPR1 and the second lower power line VPR2. The first lower power line VPR1 and the second lower power line VPR2 may include at least one material selected from copper, molybdenum, tungsten, and ruthenium.

[0048] A power delivery network layer (PDL) may be provided in the lower substrate 80. The power delivery network layer (PDL) may be provided below the first lower power line VPR1 and the second lower power line VPR2 (in the vertical direction D3). The power delivery network layer (PDL) may include a plurality of lower wirings electrically connected to the first lower power line VPR1 and the second lower power line VPR2.

[0049] The first lower power via PVI1 may be disposed between the power delivery network layer PDL and the first and second lower power lines VPR1 and VPR2. The first lower power via PVI1 may electrically connect the power delivery network layer PDL to the first and second lower power lines VPR1 and VPR2.

[0050] The power delivery network layer (PDL) may apply voltages to the first lower power line VPR1 and the second lower power line VPR2. For example, the power delivery network layer (PDL) may provide the first lower power line VPR1 and the second lower power line VPR2 with at least one voltage selected from VSS, VDD, VBB, VBL, VEQ, VREFA, VINTY, VREFBB, VPP_DIV, VBB1_DIV, VTG_MON1, VREFY, VLANG, VINTA, VREF, VREFPP, VREFLANG, VREFLP, and VPP.

[0051] For example, the power delivery network layer PDL may include a wiring network for applying a source voltage VSS to the first lower power line VPR1 , and a wiring network for applying a drain voltage VDD to the second lower power line VPR2 .

[0052] The upper structure US may include a backside via BVI that vertically (i.e., in the D3 direction) penetrates or extends through the deep device isolation pattern DTI. The backside via BVI can vertically (i.e., in the D3 direction) electrically connect the upper wiring layer 111 on the first substrate 100 to the first lower power line VPR1 and the second lower power line VPR2. For example, the first backside via BVI1 can vertically (i.e., in the D3 direction) electrically connect the upper wiring W1 of the upper wiring layer 111 to the first lower power line VPR1. The second backside via BVI2 can vertically (i.e., in the D3 direction) electrically connect the upper wiring W1 of the upper wiring layer 111 to the second lower power line VPR2. The first backside via BVI1 and the second backside via BVI2 can each be electrically connected to the active contact AC through the upper wiring W1.

[0053] The first backside via BVI1 and the second backside via BVI2 may each have a first width WD1 in the first direction D1. The first width WD1 may decrease as the distance from the top surface of the first lower power line VPR1 and the second lower power line VPR2 in the vertical direction D3 increases. The first backside via BVI1 and the second backside via BVI2 may include a metal material.

[0054] Will refer to Figure 3A and Figure 4 The substructure LS is discussed in further detail.

[0055] The lower structure LS may include a second substrate 200. The second substrate 200 may be a silicon substrate, but the present inventive concept is not limited thereto.

[0056] The first lower interlayer dielectric layer 50 may be disposed on the second substrate 200. The first lower interlayer dielectric layer 50 may include a dielectric material. For example, the first lower interlayer dielectric layer 50 may include a plurality of dielectric layers.

[0057] A memory cell region 51 may be provided in the first lower interlayer dielectric layer 50. For example, a vertical channel transistor DRAM may be provided on the second substrate 200, but the present inventive concept is not limited thereto. Figure 4 The memory cell region 51 may correspond to the Figure 3A A cross-sectional view taken along line AA'.

[0058] A peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS may be provided on the second substrate 200. The peripheral circuit structure PS may include a core circuit, a lower dielectric layer covering the core circuit, a lower contact plug, and a circuit line.

[0059] The core circuit may include NMOS transistors and PMOS transistors. The core circuit may be electrically connected to the bit lines BL and word lines WL through circuit lines, which will be discussed below.

[0060] The cell array structure CS may include bit lines BL, channel patterns CP, word lines WL, mold dielectric patterns IL, landing pads LP, and data storage patterns DSP.

[0061] On the second substrate 200, the bit lines BL may extend along a first direction D1 and may be spaced apart from each other in a second direction D2. For example, the bit lines BL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or any combination thereof. The bit lines BL may each be formed of a single layer or multiple layers. The bit lines BL may include a carbon-based two-dimensional material (e.g., graphene), a carbon-based three-dimensional material (e.g., carbon nanotubes), or any combination thereof.

[0062] The mold dielectric patterns IL may be disposed on the bit lines BL. Each of the mold dielectric patterns IL may extend along the second direction D2 while crossing the bit lines BL. The mold dielectric patterns IL may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectrics.

[0063] The channel patterns CP may be located on the bit lines BL. The channel patterns CP may be spaced apart from each other in the second direction D2 between the mold dielectric patterns IL. Each of the channel patterns CP may have a U-shaped cross-section. The width of each channel pattern CP in the second direction D2 may be greater than the width of each bit line BL in the second direction D2.

[0064] The channel pattern CP may include, for example, an oxide semiconductor. The oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Snz O, Yb x Ga y Zn z O、In x Ga y O or any combination thereof. In other embodiments, the channel patterns CP may include indium gallium zinc oxide (IGZO). The channel patterns CP may each be formed of a single layer including one oxide semiconductor or a multilayer including different oxide semiconductors. The channel patterns CP may include an amorphous, crystalline, or polycrystalline oxide semiconductor. The channel patterns CP may each have a bandgap energy greater than that of silicon. For example, the channel patterns CP may each have a bandgap energy of approximately 1.5 eV to approximately 5.6 eV, and may exhibit desired channel performance when the bandgap energy is within a range of approximately 2.0 eV to approximately 4.0 eV.

[0065] The word line WL may be located on the channel pattern CP. The word line WL may extend in the second direction D2 while crossing the bit line BL and the channel pattern CP.

[0066] For example, word lines WL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or any combination thereof. Word lines WL may each be formed of a single layer or multiple layers comprising different materials. Word lines WL may include carbon-based two-dimensional materials (e.g., graphene), carbon-based three-dimensional materials (e.g., carbon nanotubes), or any combination thereof.

[0067] The first dielectric patterns 115 may be disposed between a pair of word lines WL. Each of the first dielectric patterns 115 may be located between a corresponding pair of word lines WL. Each of the first dielectric patterns 115 may extend along the second direction D2. The first dielectric patterns 115 may be spaced apart from each other in the first direction D1. The first dielectric patterns 115 and the mold dielectric patterns IL may be alternately arranged along the first direction D1.

[0068] The landing pads LP may be located on the corresponding word lines WL. The landing pads LP may be in contact with the channel pattern CP and the molded dielectric pattern IL. When viewed in a plan view, each of the landing pads LP may have a circular shape, but the inventive concept is not limited thereto. For example, when viewed in a plan view, each of the landing pads LP may have an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, or any other suitable shape. The landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. The landing pads LP may include, for example, doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or any combination thereof.

[0069] The data storage patterns DSP may be located on the landing pads LP. The data storage patterns DSP may be electrically connected to the channel patterns CP through the landing pads LP. When viewed in a plan view, each of the data storage patterns DSP may overlap with a corresponding one of the landing pads LP. For example, the data storage patterns DSP may be spaced apart from each other in the first direction D1 and the second direction D2.

[0070] For example, each of the data storage patterns DSP may be a capacitor. In this case, the data storage pattern DSP may include a bottom electrode, a top electrode, and a dielectric layer between the bottom and top electrodes. The bottom electrode may be in contact with the landing pad LP. In other embodiments, each of the data storage patterns DSP may be a variable resistor pattern whose two resistance states can be switched by an electrical pulse applied to the storage element. In this case, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystalline state changes based on the amount of current.

[0071] Multiple wiring lines may be provided in the first lower interlayer dielectric layer 50. For example, a first connection line 52 and a second connection line 53 may be provided in the first lower interlayer dielectric layer 50. The first connection line 52 may be provided below the data storage pattern DSP (i.e., in the direction D3) and electrically connected to the data storage pattern DSP. The second connection line 53 may be provided above the first connection line 52 and may be electrically connected to the first connection line 52 via a first through-hole TVI1. The second connection line 53 may be electrically connected to the lower wiring layer 61 via a second through-hole TVI2, which will be discussed below. In other embodiments, the connection lines 52 and 53 and the through-holes TVI1 and TVI2 may be provided differently. Alternatively, at least one additional wiring line may be provided in the first lower interlayer dielectric layer 50.

[0072] A second lower interlayer dielectric layer 60 may be formed on the memory cell region 51. A lower wiring layer 61 may be formed in the second lower interlayer dielectric layer 60. The lower wiring layer 61 may include a plurality of wirings. The data storage pattern DSP may be electrically connected to the lower wiring layer 61 through the wiring in the first lower interlayer dielectric layer 50. For example, the data storage pattern DSP may be electrically connected to the lower wiring layer 61 through the first connection line 52, the first through-via TVI1, the second connection line 53, and the second through-via TVI2.

[0073] A third lower interlayer dielectric layer 70 may be disposed on the second lower interlayer dielectric layer 60. The third lower interlayer dielectric layer 70 may include a dielectric material.

[0074] A bonding structure BD may be provided between the lower structure LS and the upper structure US. The bonding structure BD may be provided at the boundary between the lower structure LS and the upper structure US. The top surface of the bonding structure BD may be located at a height higher than that of the rear surface USa of the upper structure US (i.e., in the D3 direction). The bottom surface of the bonding structure BD may be located at a height lower than that of the front surface LSa of the lower structure LS (i.e., in the D3 direction).

[0075] The bonding structure BD may include a first bonding pad 85 and a second bonding pad 75. The first bonding pad 85 may be buried in the lower portion of the upper structure US. For example, the first bonding pad 85 may be buried in the lower substrate 80. The second bonding pad 75 may be buried in the upper portion of the lower structure LS. For example, the second bonding pad 75 may be buried in the third lower interlayer dielectric layer 70 of the lower structure LS. The first bonding pad 85 may be exposed through the rear surface USa of the upper structure US. The second bonding pad 75 may be exposed through the front surface LSa of the lower structure LS.

[0076] The first bonding pad 85 and the second bonding pad 75 may comprise the same material. The first bonding pad 85 and the second bonding pad 75 may comprise a metal material. For example, the first bonding pad 85 and the second bonding pad 75 may comprise copper (Cu). The first bonding pad 85 and the second bonding pad 75 may be in direct contact with each other. The first bonding pad 85 and the second bonding pad 75 may be integrally bonded into a single unitary piece or monolithic member. No interface may exist between the first bonding pad 85 and the second bonding pad 75.

[0077] The first bonding pad 85 can electrically connect the power delivery network layer PDL to the lower power lines VPR1 and VPR2. For example, the first bonding pad 85 can be electrically connected to the power delivery network layer PDL vertically (i.e., in the direction D3) through the second lower power via PVI2. In this configuration, the first bonding pad 85 can be electrically connected to the lower power lines VPR1 and VPR2 through the first lower power via PVI1, the power delivery network layer PDL, and the second lower power via PVI2.

[0078] The second bonding pad 75 may be electrically connected to the lower wiring layer 61. For example, the second bonding pad 75 may be electrically connected to the wiring of the lower wiring layer 61 through the lower via 73. In this configuration, the second bonding pad 75 may be electrically connected to the data storage pattern DSP through the lower wiring layer 61 and the connection lines 52 and 53 in the first lower interlayer dielectric layer 50.

[0079] The bonding structure BD may electrically connect the upper structure US and the lower structure LS to each other. For example, the bonding structure BD may electrically connect the lower power lines VPR1 and VPR2 to the lower wiring layer 61. The upper structure US may be electrically connected to the lower structure LS through the first bonding pad 85 and the second bonding pad 75.

[0080] The nitride patterns 71 and 81 may be disposed on the boundary between the upper structure US and the lower structure LS. The first nitride pattern 81 may be disposed on the rear surface USa of the upper structure US. For example, the first nitride pattern 81 may be disposed on the bottom surface of the lower substrate 80. The second nitride pattern 71 may be disposed on the front surface LSa of the lower structure LS. For example, the second nitride pattern 71 may be disposed on the top surface of the third lower interlayer dielectric layer 70.

[0081] The first nitride pattern 81 may extend in the first direction D1 along the bottom surface of the lower substrate 80. The second nitride pattern 71 may extend in the first direction D1 along the top surface of the third lower interlayer dielectric layer 70. The first nitride pattern 81 and the second nitride pattern 71 may overlap each other vertically (i.e., in the D3 direction). The first nitride pattern 81 and the second nitride pattern 71 may bond the upper structure US and the lower structure LS to each other.

[0082] The first and second nitride patterns 81 and 71 may include nitride. For example, the first and second nitride patterns 81 and 71 may include silicon nitride (SiN). The first and second nitride patterns 81 and 71 may be disposed on one side of the bonding structure BD. The thickness of each of the first and second nitride patterns 81 and 71 may be less than the thickness of the bonding structure BD.

[0083] According to some embodiments of the present invention, the upper structure US and the lower structure LS can be bonded to each other. The upper structure US and the lower structure LS can be bonded to each other using a hybrid bonding method. The term "hybrid bonding" can mean that two components comprising the same material are merged at the interface between them. Since the first bonding pad 85 and the second bonding pad 75 are bonded into a single integral piece, the upper structure US and the lower structure LS can be stably bonded to each other.

[0084] Furthermore, since the power supply lines of the upper structure US are buried in the lower portion of the first substrate 100, resistance between the wiring of the upper structure US can be reduced. The lower power supply lines VPR1 and VPR2 of the upper structure US can be electrically connected to the bonding structure BD. Therefore, the upper structure US and the lower structure LS are stably bonded via the bonding structure BD. At the same time, the bonding structure BD and the power supply lines can be electrically connected to reduce resistance and increase wiring freedom. In summary, the semiconductor memory device can achieve improved electrical performance.

[0085] Figures 5A to 5E and 6A to 6D are diagrams illustrating a method of manufacturing a semiconductor memory device according to some embodiments of the inventive concept. Figures 5A to 5E is a cross-sectional view illustrating a method of manufacturing the upper structure US according to some embodiments of the inventive concept. 6A to 6D is a cross-sectional view illustrating a method of manufacturing a lower structure LS according to some embodiments of the present inventive concept.

[0086] refer to Figure 5A , a peripheral region R may be formed on the first substrate 100. In other embodiments, a cell region may be formed on the first substrate 100. A deep device isolation pattern DTI may be formed on the first substrate 100. Forming the deep device isolation pattern DTI may include: forming a hard mask pattern on the first substrate 100, etching the first substrate 100 using the hard mask pattern as a mask to form a deep device trench DTR, and at least partially filling the deep device trench DTR with a dielectric material.

[0087] Isolation patterns STI may be formed on the first substrate 100. The maximum vertical depth (i.e., in the D3 direction) of the isolation patterns STI may be less than the maximum vertical depth of the deep device isolation patterns DTI. Forming the isolation patterns STI may include forming a hard mask pattern on the first substrate 100, etching an upper portion of the first substrate 100 using the hard mask pattern as a mask to form a trench, and at least partially filling the trench with a dielectric material.

[0088] The isolation pattern STI may define an active pattern AP. A transistor TR and a source / drain pattern SD may be formed on the active pattern AP. The transistor TR may correspond to Figure 1 The selection element TR. The source / drain pattern SD may be formed on opposite sides of the transistor TR. Forming the source / drain pattern SD may include implanting impurities into an upper portion of the active pattern AP.

[0089] A first interlayer dielectric layer 110 may be formed on a first substrate 100. An upper wiring layer 111 may be formed in the first interlayer dielectric layer 110. The upper wiring layer 111 may include active contacts AC, upper wirings W1, and upper vias V1. Each active contact AC may be electrically connected vertically (i.e., in the direction D3) to a corresponding source / drain pattern SD. The upper vias V1 may be disposed below the upper wirings W1. The upper wirings W1 may be connected to the active contacts AC through the upper vias V1.

[0090] refer to Figure 5BA second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer. A first metal layer M1 may be formed in the second interlayer dielectric layer 120. The first metal layer M1 may be electrically connected to at least one of the active contact AC and the upper wiring W1.

[0091] A third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120. A second metal layer M2 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. A third metal layer M3 may be formed in the fourth interlayer dielectric layer 140. A first support substrate 300 may be formed on the fourth interlayer dielectric layer 140. The first support substrate 300 may be a silicon substrate, but the present inventive concept is not limited thereto.

[0092] refer to Figure 5C After the back-end (BEOL) process is completed, the first substrate 100 may be flipped over to expose the bottom surface of the first substrate 100. A silicon grinding process and / or a chemical mechanical polishing (CMP) process may be used to reduce the thickness of the first substrate 100. For example, Figure 5C The thickness of the first substrate 100 shown in FIG may be less than Figure 5B The thickness of the first substrate 100 shown in FIG. The thickness reduction of the first substrate 100 may at least partially expose the bottom surface of the deep device isolation pattern DTI. The thickness reduction of the first substrate 100 may remove a portion of the deep device isolation pattern DTI.

[0093] refer to Figure 5D A first lower dielectric layer 90 may be formed on the bottom surface of the first substrate 100. A backside contact hole BCH may be formed in the first lower dielectric layer 90, the first substrate 100, and the first interlayer dielectric layer 110. The backside contact hole BCH may penetrate or extend through the first lower dielectric layer 90 and the deep device isolation pattern DTI. The backside contact hole BCH may at least partially expose the upper wiring W1 in the first interlayer dielectric layer 110. The width of the backside contact hole BCH in the first direction D1 may increase as the distance from the exposed top surface of the upper wiring W1 in the vertical direction D3 (i.e., the D3 direction) increases.

[0094] Forming the backside contact hole BCH may include, for example, forming a mask pattern on the first lower dielectric layer 90 , and etching the first lower dielectric layer 90 , the deep device isolation pattern DTI, and the first interlayer dielectric layer 110 using the mask pattern as a mask.

[0095] refer to Figure 5E The backside contact hole BCH may be at least partially filled with a metal material to form a backside via BVI. For example, the backside via BVI may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt.

[0096] refer to Figure 4 A lower substrate 80 may be formed on the first lower dielectric layer 90. The lower substrate 80 may include a dielectric material. A first lower power line VPR1 and a second lower power line VPR2 may be formed in the lower substrate 80. The first lower power line VPR1 and the second lower power line VPR2 may be connected to the backside via BVI.

[0097] A first lower power via PVI1 and a power delivery network layer (PDL) may be formed on the first lower power line VPR1 and the second lower power line VPR2. The power delivery network layer (PDL) may be configured to apply a voltage to the first lower power line VPR1 and the second lower power line VPR2. For example, the power delivery network layer (PDL) may apply a source voltage VSS or a drain voltage VDD to the first lower power line VPR1 and the second lower power line VPR2.

[0098] A first nitride pattern 81, a second lower power via PVI2, and a first bonding pad 85 may be sequentially formed in the lower substrate 80. Forming the first nitride pattern 81 may include conformally forming a nitride layer on a top surface of the lower substrate 80 and performing a chemical mechanical polishing (CMP) process to reduce the thickness of the nitride layer.

[0099] Forming the first bonding pad 85 may include forming a mask pattern on a top surface of the lower substrate 80 , etching an upper portion of the lower substrate 80 using the mask pattern as a mask, and at least partially filling the etched upper portion of the lower substrate 80 with a metal material (eg, copper (Cu)).

[0100] refer to Figure 6A , a peripheral circuit structure PS including a core circuit may be formed on the first preliminary substrate 10 .

[0101] A bit line BL may be formed on the peripheral circuit structure PS. A mold dielectric pattern IL may be formed on the bit line BL. The mold dielectric patterns IL may extend along the second direction D2 and may be spaced apart from each other in the first direction D1. The mold dielectric pattern IL may at least partially expose a portion of the bit line BL. The mold dielectric pattern IL may include, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0102] A channel layer may be formed to at least partially cover the mold dielectric pattern IL. The channel layer may be formed to have a uniform thickness. The channel layer may contact a portion of the bit line BL. The channel layer may be formed using at least one process selected from physical vapor deposition (PVD), a thermal chemical deposition process (thermal CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and atomic layer deposition (ALD). For example, the channel layer may include a semiconductor material, an oxide semiconductor material, or a two-dimensional semiconductor material, or may include silicon, germanium, silicon germanium, or indium gallium zinc oxide (IGZO).

[0103] An etching process may be performed on the channel layer. A portion of the channel layer may be removed so that the channel layer may be formed into a channel pattern CP. After forming the channel pattern CP, a word line WL may be formed on the channel pattern CP. The top surface of the word line WL may be lower than (i.e., lower in the D3 direction) the top surface of the channel pattern CP.

[0104] Thereafter, first dielectric patterns 115 may be formed between a pair of word lines WL located on one channel pattern CP. Each of the first dielectric patterns 115 may at least partially fill between the pair of word lines WL.

[0105] Landing pads LP may be formed on the channel pattern CP and the word line WL. The landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. The data storage pattern DSP may be correspondingly formed on the landing pads LP. When the data storage pattern DSP includes a capacitor, a bottom electrode, a capacitor dielectric layer, and a top electrode may be sequentially formed. The bottom electrode may be electrically connected to the corresponding landing pad LP.

[0106] A first lower interlayer dielectric layer 50 may be formed on the first preliminary substrate 10. A plurality of wirings may be formed in the first lower interlayer dielectric layer 50. For example, wirings electrically connected to the data storage pattern DSP may be formed. For example, a first connection line 52, a second connection line 53, and a first through-hole TVI1 may be formed on the first preliminary substrate 10. The first connection line 52, the second connection line 53, and the first through-hole TVI1 may be formed using a photoresist process. For another example, the plurality of wirings may be formed differently in the first lower interlayer dielectric layer 50.

[0107] refer to Figure 6B , a second substrate 200 may be formed on the first lower interlayer dielectric layer 50. The second substrate 200 may be a silicon substrate, but the present inventive concept is not limited thereto.

[0108] refer to Figure 6C, the first preliminary substrate 10 may be turned over to at least partially expose the bottom surface of the first preliminary substrate 10. A silicon grinding process and / or a chemical mechanical polishing (CMP) process may be used to remove the first preliminary substrate 10. The first preliminary substrate 10 may be removed to expose the top surface of the first lower interlayer dielectric layer 50.

[0109] refer to Figure 6D , a second lower interlayer dielectric layer 60 may be formed on the first lower interlayer dielectric layer 50. A second through hole TVI2 may be formed in the first lower interlayer dielectric layer 50. A lower wiring layer 61 may be formed in the second lower interlayer dielectric layer 60. The second through hole TVI2 may electrically connect the lower wiring layer 61 to the second connection line 53.

[0110] A third lower interlayer dielectric layer 70 may be formed on the second lower interlayer dielectric layer 60. A second nitride pattern 71, a lower via hole 73, and a second bonding pad 75 may be formed in the third lower interlayer dielectric layer 70. Forming the second nitride pattern 71 may include forming a nitride layer on a top surface of the third lower interlayer dielectric layer 70 and performing a chemical mechanical polishing (CMP) process to reduce the thickness of the nitride layer.

[0111] Forming the second bonding pad 75 may include forming a mask pattern on the third lower interlayer dielectric layer 70, etching an upper portion of the third lower interlayer dielectric layer 70 using the mask pattern as a mask, and at least partially filling the etched upper portion of the third lower interlayer dielectric layer 70 with a metal material. The second bonding pad 75 may be electrically connected to the lower wiring layer 61 through the lower via 73.

[0112] Reference again Figure 4 , the upper structure US and the lower structure LS may overlap vertically (i.e., in the D3 direction) to be bonded to each other. The rear surface USa of the upper structure US may be in contact with the front surface LSa of the lower structure LS. The first nitride pattern 81 of the upper structure US may be in contact with the second nitride pattern 71 of the lower structure LS. The first nitride pattern 81 and the second nitride pattern 71 may bond the upper structure US and the lower structure LS to each other. The first bonding pad 85 and the second bonding pad 75 may overlap vertically (i.e., in the D3 direction) to be in contact with each other.

[0113] An annealing process may be performed on the upper structure US and the lower structure LS. The annealing process may directly bond the first bonding pad 85 and the second bonding pad 75 to each other. For example, the first bonding pad 85 and the second bonding pad 75 may form a single integral piece or monolithic piece.

[0114] The first bonding pad 85 and the second bonding pad 75 may be formed of the same material (e.g., copper (Cu)). The first bonding pad 85 and the second bonding pad 75 may be bonded together by a metal-to-metal hybrid bonding process caused by surface activation at the interface between the first bonding pad 85 and the second bonding pad 75 in contact with each other. When the first bonding pad 85 and the second bonding pad 75 are bonded together, perfect bonding may not be achieved.

[0115] Figure 7 is a cross-sectional view showing a semiconductor memory device according to some embodiments of the present invention. Figure 4 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0116] refer to Figure 7 , the upper structure US may be disposed on the lower structure LS. The lower structure LS may include a power wiring layer PDN. The power wiring layer PDN may be disposed on the lower wiring layer 61. The power wiring layer PDN may include a first power wiring dielectric layer PL1 and a second power wiring dielectric layer PL2. The second power wiring dielectric layer PL2 may be disposed on the first power wiring dielectric layer PL1. A first bonding pattern PBa may be disposed between the first power wiring dielectric layer PL1 and the second power wiring dielectric layer PL2. The first bonding pattern PBa may include the same material as the first nitride pattern 81 and the second nitride pattern 71 described above. The first bonding pattern PBa may bond the first power wiring dielectric layer PL1 and the second power wiring dielectric layer PL2 to each other.

[0117] The power delivery network layer PDL may be disposed in the first power wiring dielectric layer PL1 , and the first lower power via PVI1 may be disposed below the power delivery network layer PDL. The power delivery network layer PDL may be electrically connected to the lower wiring layer 61 through the first lower power via PVI1 .

[0118] The first lower power line VPR1 and the second lower power line VPR2 may be disposed in the second power routing dielectric layer PL2. A second lower power via PVI2 may be disposed below the first lower power line VPR1 and the second lower power line VPR2 (i.e., in the direction D3). The second lower power via PVI2 may connect the first lower power line VPR1 to the power delivery network layer PDL. The second lower power via PVI2 may connect the second lower power line VPR2 to the power delivery network layer PDL.

[0119] The lower substrate 80 may be omitted in the upper structure US. The first lower dielectric layer 90 of the upper structure US may be disposed on the second power wiring dielectric layer PL2 of the lower structure LS.

[0120] The second bonding pattern PBb and the third bonding pattern PBc may be interposed between the second lower wiring dielectric layer PL2 and the first lower dielectric layer 90. The second bonding pattern PBb may be disposed on the front surface LSa of the lower structure LS. The third bonding pattern PBc may be disposed on the rear surface USa of the upper structure US. The second bonding pattern PBb and the third bonding pattern PBc may be the same as the first nitride pattern 81 and the second nitride pattern 71 described above.

[0121] The first backside through-hole BVI1 and the second backside through-hole BVI2 may be provided on the first substrate 100 of the upper structure US. The first backside through-hole BVI1 and the second backside through-hole BVI2 may each have a second width WD2 in the first direction D1. The second width WD2 may increase as the distance from the rear surface USa of the upper structure US in the vertical direction D3 increases.

[0122] According to the present invention, the power wiring layer PDN can be provided in the lower structure LS. Therefore, the resistance between the wirings in the lower structure LS can be reduced. In other embodiments, Figure 4 The joining structure BD may be provided on a boundary between the upper structure US and the lower structure LS.

[0123] Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10 、 Figure 11 and Figure 12 FIG is a diagram illustrating a method of manufacturing a semiconductor memory device according to some embodiments of the present invention. 5A to 6D The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0124] refer to Figure 8A , a peripheral region R may be formed on the first substrate 100. In other embodiments, a cell region may be formed on the first substrate 100. A deep device isolation pattern DTI, an isolation pattern STI, a transistor TR, and a source / drain pattern SD may be formed on the first substrate 100. A first interlayer dielectric layer 110 may be formed on the first substrate 100. Active contacts AC may be formed in the first interlayer dielectric layer 110.

[0125] refer to Figure 8B The first substrate 100 may be flipped over to at least partially expose the bottom surface of the first substrate 100. A silicon grinding process and / or a chemical mechanical polishing (CMP) process may be used to reduce the thickness of the first substrate 100. The reduced thickness of the first substrate 100 may at least partially expose the bottom surface of the deep device isolation pattern DTI.

[0126] A first lower dielectric layer 90 may be formed on the bottom surface of the first substrate 100. A third bonding pattern PBc may be formed on the first lower dielectric layer 90. Forming the third bonding pattern PBc may include conformally forming a nitride layer on the first lower dielectric layer 90 and performing a chemical mechanical polishing (CMP) process to reduce the thickness of the nitride layer. Through these processes, an upper structure US may be formed.

[0127] refer to Figure 9A A first lower interlayer dielectric layer 50 may be formed on the second substrate 200. A memory cell region 51, connection lines 52 and 53, and vias TVI1 and TVI2 may be formed in the first lower interlayer dielectric layer 50. A second lower interlayer dielectric layer 60 may be formed on the first lower interlayer dielectric layer 50. A lower wiring layer 61 may be formed in the second lower interlayer dielectric layer 60.

[0128] A first power wiring dielectric layer PL1 may be formed on the second lower interlayer dielectric layer 60. Second lower power vias PVI2 and a power delivery network layer PDL may be sequentially formed in the first power wiring dielectric layer PL1. A first bonding pattern PBa may be formed on the first power wiring dielectric layer PL1. Forming the first bonding pattern PBa may include conformally forming a nitride layer on the first power wiring dielectric layer PL1 and performing a chemical mechanical polishing (CMP) process to reduce the thickness of the nitride layer.

[0129] refer to Figure 9B A second power wiring dielectric layer PL2 may be formed on the first power wiring dielectric layer PL1. The first power wiring dielectric layer PL1 and the second power wiring dielectric layer PL2 may be joined by a first bonding pattern PBa. A first lower power via PVI1 and a first lower power line VPR1 and a second lower power line VPR2 may be sequentially formed in the second power wiring dielectric layer PL2. The first lower power via PVI1 may penetrate the first bonding pattern PBa.

[0130] A second bonding pattern PBb may be formed on the second power wiring dielectric layer PL2. Forming the second bonding pattern PBb may include conformally forming a nitride layer on the second power wiring dielectric layer PL2 and performing a chemical mechanical polishing (CMP) process to reduce the thickness of the nitride layer. Through these processes, the lower structure LS may be formed.

[0131] refer to Figure 10 , the upper structure US and the lower structure LS can be bonded to each other. The rear surface USa of the upper structure US can be in contact with the front surface LSa of the lower structure LS. The upper structure US and the lower structure LS can be combined by the second bonding pattern PBb and the third bonding pattern PBc.

[0132] A backside contact hole BCH may be formed in the upper structure US. The backside contact hole BCH may penetrate or extend through the first interlayer dielectric layer 110, the first substrate 100, and the first lower dielectric layer 90 to at least partially expose the first lower power line VPR1 and the second lower power line VPR2 of the lower structure LS. The backside contact hole BCH may penetrate or extend through the second bonding pattern PBb and the third bonding pattern PBc. The width of the backside contact hole BCH in the first direction D1 may decrease as the distance from the top surface of the first interlayer dielectric layer 110 in the vertical direction D3 increases.

[0133] Forming the backside contact hole BCH may include, for example, forming a mask pattern on the first interlayer dielectric layer 110 and etching the first interlayer dielectric layer 110 , the first substrate 100 , and the first lower dielectric layer 90 using the mask pattern as a mask.

[0134] refer to Figure 11 The backside contact hole BCH may be at least partially filled with a metal material to form a backside via BVI. For example, the backside via BVI may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt.

[0135] refer to Figure 12 , an upper wiring W1 and an upper via VI may be formed in the first interlayer dielectric layer 110. The transistor TR and the source / drain pattern SD may be electrically connected to the wiring W1 through the active contact AC. The backside via BVI may vertically electrically connect the upper wiring W1 to the first and second lower power lines VPR1 and VPR2. The active contact AC may be electrically connected to the backside via BVI through the upper wiring W1.

[0136] refer to Figure 7 A second interlayer dielectric layer 120, a third interlayer dielectric layer 130, and a fourth interlayer dielectric layer 140 may be formed on the first interlayer dielectric layer 110. A first metal layer M1 may be formed in the second interlayer dielectric layer 120. A second metal layer M2 may be formed in the third interlayer dielectric layer 130. A third metal layer M3 may be formed in the fourth interlayer dielectric layer 140. A first supporting substrate 300 may be formed on the fourth interlayer dielectric layer 140. In other embodiments, the first supporting substrate 300 may be omitted.

[0137] Figure 13 is a cross-sectional view showing a semiconductor memory device according to some embodiments of the present invention. Figure 4 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0138] refer to Figure 13, the channel pattern CP may be disposed on the bit line BL. The channel pattern CP may extend from the top surface of the bit line BL in the vertical direction D3. The word line WL may be disposed between a pair of channel patterns CP adjacent to each other. The word lines WL may be spaced apart from each other in the second direction D2. The mold dielectric pattern IL may be disposed between a pair of channel patterns CP adjacent to each other. The mold dielectric patterns IL may be spaced apart from each other in the second direction D2. The word lines WL and the mold dielectric patterns IL may be alternately disposed between the channel patterns CP. The bit line BL may extend in the first direction D1, and the word line WL may extend in the second direction D2.

[0139] In a semiconductor memory device according to some embodiments of the present invention, a lower structure and an upper structure may be combined by a bonding structure. The upper structure may include a lower power supply line buried in a lower portion of a substrate, and the lower power supply line may be electrically connected to the bonding structure. The upper structure may be electrically connected to the lower structure by the bonding structure.

[0140] The bonding structure may include a first bonding pad buried in the lower portion of the upper structure and a second bonding pad buried in the upper portion of the lower structure. The first bonding pad and the second bonding pad may be made of the same material and may constitute a single integral piece or monolithic piece. Thus, the lower structure and the upper structure may be connected to each other, and at the same time, the lower power line of the upper structure and the bonding structure may be electrically connected, which may increase the degree of freedom of wiring. In summary, the semiconductor memory device may improve the desired electrical performance.

[0141] Although the present invention has been described in conjunction with the embodiments of the present invention shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and basic features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all aspects and not restrictive.

Claims

1. A semiconductor memory device comprising: Substructure; as well as a superstructure, on said substructure, Wherein, the superstructure comprises: a first substrate; upper wiring, on the first substrate; a lower power supply line in a lower portion of the first substrate; and a first bonding pad between the lower power line and the lower structure, wherein the lower power line and the first bonding pad are electrically connected to each other, and The upper structure is electrically connected to the lower structure through the first bonding pad.

2. The semiconductor memory device according to claim 1, wherein The lower structure includes a second bonding pad, The first bonding pad and the second bonding pad are in direct contact with each other.

3. The semiconductor memory device according to claim 2, wherein The lower structure further comprises: a second substrate; a data storage pattern on the second substrate; a landing pad on the data storage pattern; a channel pattern on the landing pad, wherein the landing pad electrically connects the channel pattern and the data storage pattern to each other; a word line adjacent to the channel pattern; and bit lines, on the channel pattern, The bit lines extend along a first direction, and The word line extends along a second direction intersecting with the first direction.

4. The semiconductor memory device according to claim 3 , further comprising a lower wiring between the bit line and the second bonding pad, in, The lower wiring is electrically connected to the second bonding pad. 5 . The semiconductor memory device according to claim 1 , further comprising a deep device isolation pattern extending through the first substrate.

6. The semiconductor memory device according to claim 5, further comprising a backside via extending through the deep device isolation pattern, in, The backside via electrically connects the upper wiring and the lower power line to each other.

7. The semiconductor memory device according to claim 6, wherein The width of the backside through hole decreases as the distance extending away from the lower structure in a direction perpendicular to the top surface of the lower power line increases.

8. The semiconductor memory device according to claim 6, further comprising: a transistor on the first substrate; a plurality of source / drain patterns on opposite sides of the transistor; as well as an active contact electrically connected to each of the source / drain patterns, Wherein, the active contact is electrically connected to the backside through hole.

9. The semiconductor memory device according to claim 1, further comprising a power delivery network layer between the lower power line and the lower structure, in, The power delivery network layer is configured to apply a voltage to the lower power line. 10 . The semiconductor memory device according to claim 1 , further comprising a nitride pattern between the upper structure and the lower structure.

11. A semiconductor memory device comprising: Substructure; as well as a superstructure, on said substructure, Wherein, the superstructure comprises: a first substrate; upper wiring, on the first substrate; a lower power supply line in a lower portion of the first substrate; and a first bonding pad between the lower power line and the lower structure, Wherein, the lower structure comprises: a second substrate including a cell region; and a second bonding pad on the cell region, wherein the first bonding pad is exposed through the rear surface of the upper structure, wherein the second bonding pad is exposed through the front surface of the lower structure, wherein the front surface of the lower structure contacts the rear surface of the upper structure, and The first bonding pad and the second bonding pad are in direct contact with each other. 12 . The semiconductor memory device according to claim 11 , further comprising a backside via extending through the first substrate and electrically connecting the upper wiring to the lower power supply line.

13. The semiconductor memory device according to claim 11, wherein The first bonding pad is electrically connected to the lower power line, and The second bonding pad is electrically connected to a lower wiring on the cell region.

14. The semiconductor memory device according to claim 11, wherein The unit area of ​​the lower structure includes: a data storage pattern on the second substrate; a landing pad on the data storage pattern; a channel pattern on the landing pad, wherein the landing pad electrically connects the channel pattern and the data storage pattern to each other; a word line adjacent to the channel pattern; and bit lines, on the channel pattern, The bit lines extend along a first direction, and The word line extends along a second direction intersecting with the first direction.

15. The semiconductor memory device according to claim 11, further comprising a power delivery network layer between the lower power line and the lower structure, in, The power delivery network layer is configured to apply a voltage to the lower power line.

16. A semiconductor memory device comprising: Substructure; a superstructure on the substructure; as well as a joining structure, between the lower structure and the upper structure, Wherein, the superstructure comprises: a first substrate; upper wiring, on the first substrate; a lower power supply line in a lower portion of the first substrate; and a backside via extending through the first substrate and connecting the upper wiring to the lower power line, Wherein, the lower structure comprises: a second substrate including a cell region; and The lower wiring layer, on the cell area, Wherein, the bonding structure comprises: a first portion in a lower portion of the superstructure; and The second part, in the upper part of the substructure, The bonding structure electrically connects the lower power line and the lower wiring layer to each other.

17. The semiconductor memory device according to claim 16, further comprising: a transistor on the first substrate; a plurality of source / drain patterns on opposite sides of the transistor; as well as an active contact electrically connected to each of the source / drain patterns, Wherein, the active contact is electrically connected to the backside through hole.

18. The semiconductor memory device according to claim 16, wherein At least one selected from the upper structure and the lower structure further comprises: a data storage pattern on a corresponding substrate; a landing pad on the data storage pattern; a channel pattern on the landing pad, wherein the landing pad electrically connects the channel pattern and the data storage pattern to each other; a word line adjacent to the channel pattern; and bit lines, on the channel pattern, The bit lines extend along a first direction, and The word line extends along a second direction intersecting with the first direction.

19. The semiconductor memory device according to claim 16, further comprising a power delivery network layer between the lower power line and the lower structure, in, The power delivery network layer is configured to apply a voltage to the lower power line. 20 . The semiconductor memory device of claim 16 , further comprising a deep device isolation pattern extending through the first substrate.

Images