Semiconductor device

Abstract

A semiconductor device includes: a bit line structure; a plurality of back gate structures on the bit line structures; the first channel layer and the second channel layer are arranged among the plurality of back gate structures; a first word line and a second word line between the first channel layer and the second channel layer, where the first word line is adjacent to the first channel layer and the second word line is adjacent to the second channel layer; and an insulating structure on side surfaces of the first word line and the second word line and upper surfaces of the first word line and the second word line, in which the insulating structure includes a core region between the first word line and the second word line, and an insulating liner between the core region and the first word line and the second word line, a side surface of the first word line and a side surface of the second word line face each other, in which the insulating liner extends to a height higher than a height of the first word line and the second word line.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0032013 filed on March 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device having an insulating structure. Background Art

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration of semiconductor devices is increasing. When fine-patterned semiconductor devices are manufactured in response to the trend of high integration of semiconductor devices, it may be necessary to realize patterns with fine widths or fine pitches. Summary of the Invention

[0004] One aspect of a technical problem to be solved by the technical concept of the present inventive concept is to provide a semiconductor device having an insulating structure including an air gap or a low-κ dielectric material disposed between word lines.

[0005] According to aspects of the present invention, a semiconductor device includes: a bit line structure; a back gate structure on the bit line structure; a first channel layer and a second channel layer between the back gate structure along a first direction, wherein the first channel layer and the second channel layer extend along a second direction; a first word line and a second word line between the first channel layer and the second channel layer along the first direction, wherein the first word line is adjacent to the first channel layer and the second word line is adjacent to the second channel layer; and an insulating structure on a side surface of the first word line, a side surface of the second word line, an upper surface of the first word line, and an upper surface of the second word line, wherein the insulating structure includes a core region between the first word line and the second word line along the first direction, and an insulating liner between the core region and the first word line along the first direction and between the core region and the second word line along the first direction, wherein the side surface of the first word line and the side surface of the second word line face each other along the first direction, wherein the insulating liner extends to a height higher than the height of the first word line and the second word line, wherein the first direction is parallel to a lower surface of the bit line structure, and wherein the second direction is perpendicular to the lower surface of the bit line structure.

[0006] According to aspects of the present invention, a semiconductor device includes: a bit line structure; a channel layer on the bit line structure, wherein the channel layer extends along a first direction; a back gate structure facing a first side surface of the channel layer along a second direction; a word line facing a second side surface of the channel layer along the second direction, the second side surface of the channel layer being opposite to the first side surface of the channel layer; a gate dielectric layer between the channel layer and the word line along the second direction; and an insulation structure on the word line, wherein the gate dielectric layer includes a vertical portion contacting the first side surface of the word line and the side surface of the insulation structure, and a horizontal portion contacting the lower surface of the word line and the lower surface of the insulation structure, wherein the insulation structure includes a core region spaced apart from the word line, and an insulating liner extending between the core region and the second side surface of the word line along the second direction and between the horizontal portion and the core region along the first direction, wherein the first side surface of the word line is opposite to the second side surface of the word line along the second direction, wherein the first direction is perpendicular to the lower surface of the bit line structure, and wherein the second direction is parallel to the lower surface of the bit line structure.

[0007] According to aspects of the present invention, a semiconductor device includes: a bit line structure; a back gate structure on the bit line structure; a first channel layer and a second channel layer between the back gate structure along a first direction, wherein the first channel layer and the second channel layer extend along a second direction; a first word line and a second word line between the first channel layer and the second channel layer along the first direction, wherein the first word line is adjacent to the first channel layer and the second word line is adjacent to the second channel layer; an insulating structure in contact with a side surface of the first word line, a side surface of the second word line, an upper surface of the first word line, and an upper surface of the second word line; a gate dielectric layer between the first channel layer and the first word line along the first direction, between the first channel layer and a first upper region of the insulating structure along the first direction, between the second channel layer and the second word line along the first direction, and between the second channel layer and the insulating structure along the first direction. a second upper region of the bit line structure; a contact pattern electrically connected to the first channel layer and the second channel layer; and an information storage structure on the contact pattern, wherein the insulating structure includes a core region spaced apart from the first word line and the second word line, and an insulating liner between a side surface of the first word line and the core region and between a side surface of the second word line and the core region and extending to a height higher than a height of the first word line and the second word line, wherein the core region has a dielectric constant lower than a dielectric constant of silicon oxide, wherein the first upper region of the insulating structure is on the first word line, wherein the second upper region of the insulating structure is on the second word line, wherein the side surface of the first word line and the side surface of the second word line face each other along a first direction, wherein the first direction is parallel to a lower surface of the bit line structure, and wherein the second direction is perpendicular to the lower surface of the bit line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings: Figure 1 is a plan view of a semiconductor device according to example embodiments; Figure 2 It is along Figure 1 A cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II′; Figure 3 yes Figure 2 An enlarged view of a portion of the semiconductor device shown in FIG. Figures 4 to 19 are cross-sectional views shown according to process order to explain a method of manufacturing a semiconductor device according to example embodiments; and Figures 20 to 25 is a cross-sectional view of a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0009] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0010] Figure 1 is a plan view of a semiconductor device according to example embodiments. Figure 2 It is along Figure 1 1 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II′. Figure 3 yes Figure 2 FIG. 1 is an enlarged view of a portion of a semiconductor device shown in FIG. Figure 3 Can be used with Figure 2 corresponds to area A.

[0011] Reference Figures 1 to 3 The semiconductor device 100 according to example embodiments of the present disclosure may include a lower insulating layer 101 , a bit line structure 110 , a back gate structure 120 , a channel layer 140 , a word line 152 , an insulating structure 160 , a contact pattern 170 , and an information storage structure 180 .

[0012] The semiconductor device 100 may include a channel layer 140, a bit line structure 110 electrically connected to the channel layer 140, and a vertical channel transistor consisting of a word line 152 disposed on at least one side of the channel layer 140. It will be understood that when an element or layer is referred to as being "on," "responsive to," "connected to," or "coupled to" another element or layer, it may be directly on, responsive to, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly responsive to," "directly connected to," or "directly coupled to" another element, there are no intervening elements. Furthermore, "electrically connected" conceptually includes both direct and indirect physical connections.

[0013] The semiconductor device 100 may be applied to, for example, a cell array of a dynamic random access memory (DRAM), but the inventive concept is not limited thereto.

[0014] The lower insulating layer 101 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiCN), etc.

[0015] The bit line structure 110 may extend along the X direction on the lower insulating layer 101. In an example embodiment, the bit line structure 110 may be buried within the lower insulating layer 101. The bit line structure 110 may be electrically connected to the channel layer 140.

[0016] Multiple bitline structures 110 may be provided, and the multiple bitline structures 110 may be spaced apart from each other along the Y direction and extend parallel to the X direction. The X and Y directions may be parallel to the upper surface of the lower insulating layer 101 (or the lower surface of the bitline structures 110). The X and Y directions may intersect with each other. For example, the X and Y directions may be perpendicular to each other. The Z direction may be perpendicular to the upper surface of the lower insulating layer 101 (or the lower surface of the bitline structures 110).

[0017] The bit line structure 110 may include, for example, doped polysilicon, a metal, a conductive metal nitride, a metal semiconductor compound, a conductive metal oxide, conductive graphene, carbon nanotubes, and / or combinations thereof. For example, the bit line structure 110 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, and / or combinations thereof. In an example embodiment, the bit line structure 110 may include a first conductive pattern 110a, a second conductive pattern 110b, and a third conductive pattern 110c sequentially stacked on the lower insulating layer 101. The first conductive pattern 110a may include, for example, a metal material (such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al)), the second conductive pattern 110b may include, for example, a metal nitride (such as titanium nitride (TiN)) or a silicide material (such as titanium silicide (TiSi)), and the third conductive pattern 110c may include, for example, a semiconductor material (such as polysilicon). The third conductive pattern 110c may be a layer doped with impurities. However, according to example embodiments, the materials, number of layers, and thicknesses forming the bit line structure 110 may vary. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] The back gate structure 120 may intersect (overlap) the bit line structure 110. For example, the back gate structures 120 may extend along the Y direction and may be spaced apart from each other along the X direction.

[0019] The back gate structure 120 may include a back gate dielectric layer 122, a back gate electrode 124, an upper capping layer 126, and a lower capping layer 128. The back gate electrodes 124 may extend along the Y direction and may be spaced apart from each other along the X direction. The back gate electrode 124 may be used to remove charges trapped in the channel layer 140. The channel layer 140 may be a floating body, and the back gate electrode 124 may be a structure that supplements the floating channel layer 140 to prevent or minimize performance degradation of the semiconductor device 100 due to the floating body effect of the channel layer 140.

[0020] The back gate electrode 124 may include, for example, doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, graphene, carbon nanotubes and / or combinations thereof. For example, the back gate electrode 124 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiAlC, TaAlC, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes and / or combinations thereof, but the present invention is not limited thereto. The back gate electrode 124 may be formed of a single layer or multiple layers of the above materials.

[0021] In an example embodiment, the back gate electrode 124 may include (eg, may be formed of) the same material as the word line 152 , but is not limited thereto and may include other materials.

[0022] The back-gate dielectric layer 122 may extend in the Y-direction along both side surfaces (e.g., opposite side surfaces) of the back-gate electrode 124. The length (vertical length) of the back-gate dielectric layer 122 (in the Z-direction) may be greater than the length (vertical length) of the back-gate electrode 124 (in the Z-direction). For example, the upper surface of the back-gate dielectric layer 122 may be located at a higher level than the upper surface of the back-gate electrode 124, and the lower surface of the back-gate dielectric layer 122 may be located at a lower level than the lower surface of the back-gate electrode 124. The lower surface of the back-gate dielectric layer 122 may contact the third conductive pattern 110c. Each back-gate dielectric layer 122 may include, for example, silicon oxide and / or a high-κ dielectric. A high-κ dielectric (high-κ dielectric material) may refer to a material having a higher dielectric constant than that of silicon oxide. Here, the height may be a relative position (e.g., distance) from the lower surface of the lower insulating layer 101 (or the lower surface of the bit line structure 110) in a vertical direction (e.g., along the Z direction). A greater distance from the lower surface of the lower insulating layer 101 (or from the lower surface of the bit line structure 110) may indicate a higher height. A closer distance from the lower surface of the lower insulating layer 101 (or from the lower surface of the bit line structure 110) may indicate a lower height.

[0023] An upper capping layer 126 may be disposed on the back-gate electrode 124. The upper surface of the upper capping layer 126 may be coplanar with the upper surface of the back-gate dielectric layer 122. In one exemplary embodiment, the back-gate structure 120 may further include a back-gate liner 127 on the lower and side surfaces of the upper capping layer 126 (e.g., covering or overlapping the lower and side surfaces of the upper capping layer 126). The back-gate liner 127 may be formed on the side surfaces of the back-gate dielectric layer 122 and the upper surface of the back-gate electrode 124 (formed conformally along the side surfaces of the back-gate dielectric layer 122 and the upper surface of the back-gate electrode 124). The upper capping layer 126 and the back-gate liner 127 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-κ dielectric material, and / or combinations thereof. For example, the upper capping layer 126 and the back-gate liner 127 may include silicon nitride. A low-κ dielectric (low-κ dielectric material) may refer to a material having a dielectric constant lower than that of silicon oxide.

[0024] The lower capping layer 128 may be disposed under the back gate electrode 124. For example, the lower capping layer 128 may be on a lower surface of the back gate electrode 124. The lower surface of the lower capping layer 128 may be located at a lower height than that of the back gate dielectric layer 122.

[0025] The channel layer 140 may be disposed on (in) the bitline structure 110 and may extend in a vertical direction (e.g., the Z direction). In some embodiments, the channel layer 140 may extend within at least a portion of the bitline structure 110 (e.g., the third conductive pattern 110 c). In a plan view, the channel layers 140 may be disposed on both sides of the back gate structure 120 (e.g., opposite sides along the X direction). The channel layers 140 may be spaced apart from each other (in a plan view) along the X and Y directions. The upper surface of the channel layer 140 may be coplanar with the upper surface of the back gate structure 120. The lower surface of the channel layer 140 may contact the third conductive pattern 110 c and may be located at a height lower than the lower surface of the back gate dielectric layer 122. In some embodiments, the lower surface of the back gate dielectric layer 122 may contact the upper surface of the bitline structure 110 (e.g., the upper surface of the third conductive pattern 110 c).

[0026] Each channel layer 140 may include a first source / drain region contacting the bit line structure 110 and a second source / drain region connected (e.g., electrically connected) to the contact pattern 170. In an example embodiment, the first source / drain region and the second source / drain region may have an N-type conductivity.

[0027] In one example embodiment, the channel layer 140 may include a single crystal semiconductor material. The single crystal semiconductor material may include a Group IV semiconductor, a Group III-V compound semiconductor, and / or a Group II-VI compound semiconductor, and may be, for example, a single crystal including silicon, silicon carbide, germanium, and / or silicon germanium.

[0028] However, according to example embodiments, the channel layer 140 may include a polycrystalline semiconductor material layer, an oxide semiconductor material layer such as indium gallium zinc oxide (IGZO), and / or a two-dimensional material layer such as MoS 2 , among others.

[0029] The oxide semiconductor material layer may include indium gallium zinc oxide (IGZO). However, example embodiments of the oxide semiconductor material layer are not limited thereto. For example, the oxide semiconductor material layer may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO). , indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and / or indium gallium silicon oxide (InGaSiO).

[0030] The two-dimensional material layer may include, for example, a TMD material layer (transition metal dichalcogenide material layer), a black phosphorus material layer, and / or an hBN material layer (hexagonal boron nitride material layer) that may have semiconductor properties. For example, the two-dimensional material layer may include BiOSe, Cr1, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and / or Janus 2D materials that may form a two-dimensional material.

[0031] The word lines 152 may be disposed on the bitline structure 110 and on both sides (e.g., opposite sides) of the back gate structure 120. The word lines 152 may be spaced apart from each other along the X-direction. In a plan view, the word lines 152 may extend around (e.g., encircle) at least a portion of the channel layer 140, and the channel layer 140 may be disposed between the back gate structure 120 and the word lines 152. The word lines 152 may include a first word line 152_1 and a second word line 152_2 disposed between two adjacent back gate structures 120 (along the X-direction). The channel layer 140 may include a first channel layer 140_1 and a second channel layer 140_2 disposed between two adjacent back gate structures 120 (along the X-direction), and the first word line 152_1 and the second word line 152_2 may be disposed between the first channel layer 140_1 and the second channel layer 140_2 (along the X-direction). The first word line 152_1 may be adjacent to the first channel layer 140_1 , and the second word line 152_2 may be adjacent to the second channel layer 140_2 .

[0032] Word line 152 may include, for example, doped polysilicon, a metal, a conductive metal nitride, a metal semiconductor compound, a conductive metal oxide, conductive graphene, carbon nanotubes, and / or combinations thereof. For example, word line 152 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, and / or combinations thereof, but is not limited thereto. Word line 152 may include a single layer or multiple layers of the above materials.

[0033] The semiconductor device 100 may further include a gate dielectric layer 150 and an insulating structure 160. The gate dielectric layer 150 may be disposed (along the X-direction) between the word line 152 and the channel layer 140 and may have a U-shape or similar shape in a cross-sectional view. For example, the gate dielectric layer 150 may be disposed below (above) the lower surface of the insulating structure 160 and may extend (along the X-direction and / or the Y-direction) between the first channel layer 140_1 and the first word line 152_1 and between the second channel layer 140_2 and the second word line 152_2 (including portions extending (along the X-direction and / or the Y-direction) between the first channel layer 140_1 and the first word line 152_1 and between the second channel layer 140_2 and the second word line 152_2). In some embodiments, in a plan view, the gate dielectric layer 150 may include a portion extending between the back gate structure 120 and the word line 152 (the first word line 152_1 or the second word line 152_2 ), without the channel layer 140 (the first channel layer 140_1 or the second channel layer 140_2 ) between the back gate structure 120 and the word line 152 .

[0034] The gate dielectric layer 150 may include a first gate dielectric layer 150_1 and a second gate dielectric layer 150_2. The first gate dielectric layer 150_1 may include a first vertical portion 150_1a and a first horizontal portion 150_1b. The first vertical portion 150_1a may include at least a portion extending in the Z direction between the first channel layer 140_1 and the first word line 152_1. In some embodiments, the first vertical portion 150_1a may include a portion extending in the Z direction between the first channel layer 140_1 and a first gate capping layer 162a (described later) on the first word line 152_1. For example, the first vertical portion 150_1a may contact side surfaces of the first channel layer 140_1, side surfaces of the first word line 152_1, and / or side surfaces of the first gate capping layer 162a. In some embodiments, the upper surface of the first vertical portion 150_1a may be a portion of the upper surface (e.g., the uppermost surface) of the gate dielectric layer 150 (e.g., the upper surface (e.g., the uppermost surface) of the first gate dielectric layer 150_1). The lower surface of the first vertical portion 150_1a may be a portion of the lower surface of the gate dielectric layer 150 (e.g., a portion of the lower surface of the first gate dielectric layer 150_1) or may be in contact with the first horizontal portion 150_1b. The first horizontal portion 150_1b may extend along the X-direction between the first channel layer 140_1 and the second horizontal portion 150_2b (to be described later), or between the first vertical portion 150_1a and the second horizontal portion 150_2b. The first horizontal portion 150_1b may include a portion disposed along the Z-direction between the first word line 152_1 and the bit line structure 110 (or the lower insulating pattern 130 (to be described later)). The lower surface of the first horizontal portion 150_1b may be part of the lower surface of the gate dielectric layer 150 (e.g., part of the lower surface of the first gate dielectric layer 150_1). In some embodiments, the first horizontal portion 150_1b may contact the lower surface of the first word line 152_1 and the lower surface of the insulation structure 160 (e.g., the lower surface of the insulation liner 164, which will be described later). The second gate dielectric layer 150_2 may include a second vertical portion 150_2a and a second horizontal portion 150_2b. The second vertical portion 150_2a may include at least a portion extending in the Z direction between the second channel layer 140_2 and the second word line 152_2. In some embodiments, the second vertical portion 150_2a may include a portion extending in the Z direction between the second channel layer 140_2 and the second gate cap layer 162b (described later) on the second word line 152_2. For example, the second vertical portion 150_2 a may make contact with a side surface of the second channel layer 140_2 , a side surface of the second word line 152_2 , and / or a side surface of the second gate capping layer 162 b .In some embodiments, the upper surface of the second vertical portion 150_2a may be a portion of the upper surface (e.g., the uppermost surface) of the gate dielectric layer 150 (e.g., the upper surface (e.g., the uppermost surface) of the second gate dielectric layer 150_2). The lower surface of the second vertical portion 150_2a may be a portion of the lower surface of the gate dielectric layer 150 (e.g., a portion of the lower surface of the second gate dielectric layer 150_2) or may be in contact with the second horizontal portion 150_2b. The second horizontal portion 150_2b may extend along the X-direction between the second channel layer 140_2 and the first horizontal portion 150_1b, or between the second vertical portion 150_2a and the first horizontal portion 150_1b. The second horizontal portion 150_2b may include a portion disposed along the Z-direction between the second word line 152_2 and the bit line structure 110 (or the lower insulating pattern 130). The lower surface of the second horizontal portion 150_2b may be part of the lower surface of the gate dielectric layer 150 (e.g., part of the lower surface of the second gate dielectric layer 150_2). In some embodiments, the second horizontal portion 150_2b may contact the lower surface of the second word line 152_2 and the lower surface of the insulation structure 160 (e.g., the lower surface of the insulation liner 164, which will be described later). In some embodiments, the upper surface (e.g., the uppermost surface) of the gate dielectric layer 150 may be coplanar with the upper surface of the channel layer 140. The first vertical portion 150_1a, the first horizontal portion 150_1b, the second vertical portion 150_2a, and the second horizontal portion 150_2b may form an integrated, unitary structure (gate dielectric layer 150) with no visible boundaries therebetween.

[0035] In one example, each gate dielectric layer 150 may be a tunnel dielectric layer that does not include an information storage layer. For example, each gate dielectric layer 150 may include, for example, silicon oxide and / or a high-κ dielectric material. The high-κ dielectric material may include a metal oxide and / or a metal oxynitride. For example, the high-κ dielectric material may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, and / or combinations thereof, but the present disclosure is not limited thereto. Each gate dielectric layer 150 may be formed of a single layer or multiple layers of the above materials.

[0036] In another example, each gate dielectric layer 150 may include an information storage layer and a dielectric layer. For example, each gate dielectric layer 150 may have polarization characteristics in response to an electric field and may include a ferroelectric layer that has remanent polarization due to a dipole even in the absence of an external electric field. The polarization state within the ferroelectric layer can be used to record data. Therefore, each gate dielectric layer 150 may include a ferroelectric layer, which may be referred to as an information storage layer. The ferroelectric layer, which may be an information storage layer, may include, for example, an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound. For example, the Hf-based compound may include an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer, which may be an information storage layer, may include a ferroelectric material doped with impurities (e.g., C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and / or Sr). For example, the ferroelectric layer, which may be an information storage layer, may include a material in which HfO2, ZrO2, and / or HzrO are doped with impurities such as C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and / or Sr.

[0037] In the gate dielectric layer 150 , the information storage layer is not limited to the types of the above-mentioned materials and may include a material that can store information.

[0038] In a cross-sectional view, the insulating structure 160 may be disposed between (adjacent) back gate structures 120 (along the X-direction). For example, the insulating structure 160 (each insulating structure 160) may include at least a portion extending in the Y-direction between adjacent word lines 152 (along the X-direction) and may be spaced apart from each other in the X-direction. For example, at least a portion of the insulating structure 160 may extend in the Y-direction between the first word line 152_1 and the second word line 152_2. The insulating structure 160 may be disposed on the word lines 152 and may extend between the word lines 152. For example, the insulating structure 160 may contact the facing side surfaces of the first and second word lines 152_1, 152_2 (along the X-direction) and the top surfaces of the first and second word lines 152_1, 152_2.

[0039] In one exemplary embodiment, the insulating structure 160 may include a core region, a gate capping layer 162, an insulating liner 164, and a capping pattern 166. The core region may include a region disposed between the first word line 152_1 and the second word line 152_2 (along the X-direction). The gate capping layer 162 may overlap the word line 152 vertically (e.g., along the Z-direction) and may contact the gate dielectric layer 150. The gate capping layer 162 may include a first gate capping layer 162a and a second gate capping layer 162b. The first gate capping layer 162a is disposed on the first word line 152_1 (e.g., overlapping the first word line 152_1 along the Z-direction), and the second gate capping layer 162b is disposed on the second word line 152_2 (e.g., overlapping the second word line 152_2 along the Z-direction). In some embodiments, the core region may include a region disposed between the first gate capping layer 162a and the second gate capping layer 162b.

[0040] An insulating liner 164 may extend between the gate capping layers 162 (e.g., between the first gate capping layer 162a and the second gate capping layer 162b) and between the word lines 152 (e.g., between the first word line 152_1 and the second word line 152_2). The insulating liner 164 may be disposed between the core region and the first word line 152_1 and may extend to a height higher than that of the first word line 152_1. The insulating liner 164 may also be disposed between the core region and the second word line 152_2 and may extend to a height higher than that of the second word line 152_2. For example, the insulating liner 164 may have a U-shape in a cross-sectional view and may contact the side surfaces of the gate capping layer 162 (e.g., the first gate capping layer 162a and the second gate capping layer 162b), the side surfaces of the word lines 152 (e.g., the first word line 152_1 and the second word line 152_2), and the gate dielectric layer 150 (e.g., the first horizontal portion 150_1b and the second horizontal portion 150_2b). The insulating liner 164 may extend from between the core region and the first word line 152_1 to between the core region and the first gate capping layer 162a. The insulating liner 164 may also extend from between the core region and the second word line 152_2 to between the core region and the second gate capping layer 162b. For example, the insulating liner 164 may extend along the Z-direction between the core region and the first gate capping layer 162a and between the core region and the first word line 152_1. The insulating liner 164 may extend along the Z-direction between the core region and the second gate cap layer 162b, and between the core region and the second word line 152_2. The insulating liner 164 may extend from between the core region and the first word line 152_1 and between the core region and the second word line 152_2 to between the core region and the gate dielectric layer 150. For example, the insulating liner 164 may extend along the Z-direction between the core region and the gate dielectric layer 150 (e.g., the first horizontal portion 150_1b and / or the second horizontal portion 150_2b), and along the X-direction between the first word line 152_1 and the second word line 152_2.

[0041] A capping pattern 166 may be disposed between the gate capping layers 162 in the core region (e.g., between the first gate capping layer 162a and the second gate capping layer 162b along the X-direction) and may contact the insulating liner 164. For example, the capping pattern 166 may contact the upper region of the inner surface 164a of the insulating liner 164. The outer surface 164b of the insulating liner 164 may contact the word lines 152 (e.g., the first word line 152_1 and the second word line 152_2) and the gate capping layers 162 (e.g., the first gate capping layer 162a and the second gate capping layer 162b). The insulating liner 164 may extend between the capping pattern 166 and the first gate capping layer 162a and between the capping pattern 166 and the second gate capping layer 162b. The lower surface of the insulating liner 164 may contact the gate dielectric layer 150. The thickness of the insulating liner 164 may be greater than 0 angstroms (Å) and less than or equal to 10 Å. In one example embodiment, the lower surface of the capping pattern 166 may be convex (e.g., protruding toward the core region (in the Z direction)). Here, the upper region of an element may refer to a portion of the region of the element that is "disposed farther from the lower surface of the lower insulating layer 101 than the center portion of the element in the Z direction." The lower region of an element may refer to a portion of the region of the element that is "disposed closer to the lower surface of the lower insulating layer 101 than the center portion of the element in the Z direction."

[0042] The gate cap layer 162, the insulating liner 164, and the capping pattern 166 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-κ dielectric material, and / or combinations thereof. In some embodiments, the insulating liner 164 may include the same material as the back gate liner 127 (e.g., silicon nitride).

[0043] In one exemplary embodiment, the insulating structure 160 may further include an air gap (AG) therein. For example, the core region may include (or may include) an air gap AG. The air gap AG may represent an empty (substantially empty) space or a space including (filled with) air and / or gas. The air gap AG may be defined by the insulating liner 164 and the capping pattern 166. For example, the lateral limits (in the X direction) and the lower limit (in the Z direction) of the air gap AG may be defined by the insulating liner 164, and the upper limit (in the Z direction) of the air gap AG may be defined by the capping pattern 166. For example, the air gap AG may be surrounded by the insulating liner 164 and the capping pattern 166. In some exemplary embodiments, the insulating structure 160 may include a low-κ dielectric material having a lower dielectric constant than silicon oxide. For example, the core region may include a low-k dielectric material.

[0044] Because insulating structure 160 (e.g., the core region) includes an air gap AG or a low-κ dielectric material, the core region can have a dielectric constant lower than that of silicon oxide, and the capacitance between adjacent first and second word lines 152_1, 152_2 can be reduced. Therefore, when one of first and second word lines 152_1, 152_2 operates, voltage changes in the other word line (e.g., the other of first and second word lines 152_1, 152_2) can be reduced or prevented. In other words, coupling noise between adjacent word lines 152 (e.g., first and second word lines 152_1, 152_2) and coupling noise between adjacent channel layers 140 (e.g., first and second channel layers 140_1, 140_2) can be reduced. Consequently, when semiconductor device 100 operates, leakage current can be prevented from increasing in unselected transistors adjacent to a selected transistor. Furthermore, when the air gap AG or low-κ dielectric material is included in the insulating structure 160 , the capacitance of the insulating structure 160 is reduced, and thus the distance between the first word line 152_1 and the second word line 152_2 can be reduced, so that the semiconductor device 100 can be implemented with a smaller design rule.

[0045] The gate capping layer 162 , the insulating liner 164 , and the capping pattern 166 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-κ dielectric material, and / or combinations thereof. For example, the gate capping layer 162 , the insulating liner 164 , and the capping pattern 166 may include silicon nitride.

[0046] The semiconductor device 100 may further include a lower insulating pattern 130 disposed between the channel layers 140 (along the X-direction) and below the word lines 152. The lower insulating pattern 130 may contact the upper surface of the third conductive pattern 110 c, the side surfaces of the channel layer 140, and the lower surface of the gate dielectric layer 150. The lower surface of the lower insulating pattern 130 may be located at a height higher than the lower surface of the channel layer 140. The lower insulating pattern 130 may be on the third conductive pattern 110 c, and the gate dielectric layer 150 may be on the lower insulating pattern 130. The lower insulating pattern 130 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-κ dielectric material, and / or combinations thereof. For example, the lower insulating pattern 130 may include silicon oxide.

[0047] The contact pattern 170 may be disposed on the channel layer 140 and may be electrically connected to the channel layer 140. The contact pattern 170 may electrically connect the channel layer 140 and the information storage structure 180.

[0048] The lower surface of the contact pattern 170 is shown as being in contact with the channel layer 140 and the gate dielectric layer 150. However, according to example embodiments, the lower surface of the contact pattern 170 may also be in contact with the insulating structure 160 and / or the upper capping layer 126. The lower surface of the contact pattern 170 may be in contact with the back gate structure 120. In some embodiments, the contact pattern 170 may overlap with the back gate structure 120, the channel layer 140, the gate dielectric layer 150, and / or the insulating structure 160 along the Z direction.

[0049] The contact pattern 170 may include a conductive material (e.g., doped single-crystal silicon, doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotubes, and / or combinations thereof). In one example embodiment, the contact pattern 170 may include a first contact layer 170a, a second contact layer 170b, a third contact layer 170c, and a fourth contact layer 170d stacked sequentially. For example, the first contact layer 170a may include undoped polycrystalline silicon, the second contact layer 170b may include doped polycrystalline silicon, the third contact layer 170c may include a silicide material, and the fourth contact layer 170d may include a metal. However, the number of layers and material types of the contact pattern 170 may vary depending on the example embodiment.

[0050] The semiconductor device 100 may further include upper insulating patterns 175 disposed between the contact patterns 170 (along the X-direction). Each upper insulating pattern 175 may extend vertically (along the Z-direction) and may contact the insulating structure 160 and / or the upper capping layer 126. The upper insulating patterns 175 may spatially separate the contact patterns 170 and electrically insulate the contact patterns 170. For example, the upper insulating patterns 175 and the contact patterns 170 may be alternately arranged along the X-direction.

[0051] The information storage structure 180 may include a first electrode 182 electrically connected to the contact pattern 170 , a second electrode 186 on (overlapping or covering) the first electrode 182 , and a dielectric layer 184 between the first electrode 182 and the second electrode 186 .

[0052] In one example embodiment, the information storage structure 180 may be a capacitor for storing information in a DRAM. For example, the dielectric layer 184 of the information storage structure 180 may be a capacitor dielectric layer of the DRAM, and the dielectric layer 184 may include a high-κ dielectric material, silicon oxide, silicon nitride, silicon oxynitride, and / or combinations thereof.

[0053] According to example embodiments, the information storage structure 180 may be a structure for storing information in DRAM or other memory devices. For example, the dielectric layer 184 of the information storage structure 180 may be a capacitor dielectric layer of a ferroelectric random access memory (FeRAM). In this case, the dielectric layer 184 may be a ferroelectric layer that can record data using polarization states. In example embodiments, the dielectric layer 184 may include a lower dielectric layer including silicon oxide and / or a high-κ dielectric, and a ferroelectric layer disposed on the lower dielectric layer.

[0054] Figures 4 to 19 are cross-sectional views shown according to process sequence to explain a method of fabricating a semiconductor device according to example embodiments.

[0055] Reference Figure 4 A mask layer M may be formed on a semiconductor substrate 10. In one example embodiment, the semiconductor substrate 10 may be a silicon-on-insulator (SOI) substrate. The semiconductor substrate 10 may include a lower semiconductor layer 11, an insulating layer 12, and an upper semiconductor layer 13. For example, the upper semiconductor layer 13 and the lower semiconductor layer 11 may include single crystal silicon. In some example embodiments, the semiconductor substrate 10 may be a bulk silicon substrate.

[0056] Reference Figure 5 , a back gate trench T1 may be formed in the semiconductor substrate 10. The back gate trench T1 may vertically penetrate the mask layer M, the upper semiconductor layer 13, and the insulating layer 12 (along the Z direction) and expose the upper surface of the lower semiconductor layer 11. The back gate trenches T1 may extend along the Y direction and may be spaced apart from each other along the X direction.

[0057] A dielectric material layer 122p may be conformally formed along the inner wall of the back gate trench T1. The dielectric material layer 122p may be on the side surfaces of the mask layer M, the upper semiconductor layer 13, and the insulating layer 12 (e.g., covering the side surfaces of the mask layer M, the upper semiconductor layer 13, and the insulating layer 12), and may be on the upper surface of the lower semiconductor layer 11 (e.g., covering the upper surface of the lower semiconductor layer 11).

[0058] Reference Figure 6 A back-gate electrode 124 and a preliminary capping layer 126p may be formed on the dielectric material layer 122p. The back-gate electrode 124 may fill the lower portion of the back-gate trench T1, and the preliminary capping layer 126p may be disposed on the back-gate electrode 124 (which may fill the upper portion of the back-gate trench T1). In one exemplary embodiment, the back-gate electrode 124 may include a metal nitride (such as TiN or polysilicon).

[0059] The preliminary capping layer 126p may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or combinations thereof. In an example embodiment, the preliminary capping layer 126p may include silicon oxide.

[0060] Reference Figure 7 , gate trenches T2 may be formed in the upper semiconductor layer 13. The gate trenches T2 may be formed by anisotropically etching the upper semiconductor layer 13 to expose the upper surface of the insulating layer 12. The gate trenches T2 may extend along the Y direction and may be spaced apart from each other along the X direction. The upper semiconductor layer 13 patterned by the etching process of the gate trenches T2 may be referred to as a channel layer 140. In some embodiments, the back gate trenches T1 and the gate trenches T2 may be spaced apart from each other along the X direction. For example, the back gate trenches T1 and the gate trenches T2 may be arranged alternately along the X direction.

[0061] After the etching process of the gate trench T2, the channel layer 140 may be further patterned along the X direction. Figure 1 As shown in , the patterned channel layers 140 may be spaced apart from each other along the Y direction along the back gate electrode 124 .

[0062] A lower insulating pattern 130 may be formed between the channel layers 140. The lower insulating pattern 130 may be on (or may contact) a lower region of a side surface of the channel layer 140. The lower insulating pattern 130 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a combination thereof. In one example embodiment, the lower insulating pattern 130 may include silicon oxide.

[0063] Reference Figure 8 , a dielectric material layer 150 p may be conformally formed along the inner wall of the gate trench T2 . The dielectric material layer 150p may be formed on (e.g., covering the mask layer M (e.g., the side surface and upper surface (upper end) of the mask layer M), the dielectric material layer 122p (e.g., the upper surface (upper end) of the dielectric material layer 122p), the preliminary covering layer 126p (e.g., the upper surface (upper end) of the preliminary covering layer 126p), the lower insulating pattern 130 (e.g., the upper surface of the lower insulating pattern 130), and the channel layer 140 (e.g., the side surface of the channel layer 140)).

[0064] Reference Figure 9 , a word line 152, a sacrificial layer 160p, and a gate cap layer 162 may be formed. The word line 152 may be formed on the dielectric material layer 150p within the gate trench T2. For example, the word line 152 may be formed on the side surface and the upper surface of the dielectric material layer 150p exposed by the gate trench T2. The word line 152 may be formed by depositing a conductive material on the dielectric material layer 150p and anisotropically etching the conductive material. Figure 1 As shown in FIG, the word lines 152 may extend along the back gate electrode 124 in the Y direction and may be spaced apart from each other in the X direction.

[0065] A gate capping layer 162 may be formed on the word line 152. In one exemplary embodiment, the gate capping layer 162 may be formed by forming an insulating material on a conductive material and anisotropically etching the insulating material together with the conductive material. For example, the gate capping layer 162 may be on the upper surface of the word line 152 and the side surface of the dielectric material layer 150p.

[0066] A sacrificial layer 160p may be formed between the word lines 152 and between the gate capping layers 162 (along the X direction). The sacrificial layer 160p may include a material having an etch selectivity relative to the material of the gate capping layer 162. For example, the gate capping layer 162 may include silicon nitride, and the sacrificial layer 160p may include silicon oxide. In some example embodiments, the sacrificial layer 160p may include the same material as the gate capping layer 162 and may be formed integrally with the gate capping layer 162.

[0067] A planarization process may be performed to remove the mask layer M and expose the upper surface of the channel layer 140. Upper portions of the dielectric material layer 122p and the dielectric material layer 150p may be removed to form a back gate dielectric layer 122 and a gate dielectric layer 150, respectively.

[0068] Reference Figure 10 , the sacrificial layer 160p may be removed, and the word line 152 may be exposed. For example, the sacrificial layer 160p between the gate capping layers 162 may be selectively removed by a wet etching process. In one example embodiment, the preliminary capping layer 126p may also be removed by an etching process, and the back gate electrode 124 may be exposed. In some example embodiments, the preliminary capping layer 126p may include a material having an etching selectivity relative to the sacrificial layer 160p, and this material may not be removed. In one example embodiment, the upper portions of the back gate dielectric layer 122 and the gate dielectric layer 150 may be (partially) etched.

[0069] Reference Figure 11, a liner material layer 164p may be formed. The liner material layer 164p may be on the side surfaces (and / or top surfaces) of the back gate dielectric layer 122 and the top surface of the back gate electrode 124 (e.g., covering the side surfaces (and / or top surfaces) of the back gate dielectric layer 122 and the top surface of the back gate electrode 124). The liner material layer 164p may also be on the side surfaces of the word lines 152, the side surfaces (and / or top surfaces) of the gate cap layer 162, and the top surface of the gate dielectric layer 150 (e.g., covering the side surfaces of the word lines 152, the side surfaces (and / or top surfaces) of the gate cap layer 162, and the top surface of the gate dielectric layer 150). The liner material layer 164p may include, for example, silicon nitride and may cover the word lines 152 to prevent oxidation of the word lines 152. The top surface of a component may include the topmost surface of the component and a top surface of the component lower than the topmost surface of the component. For example, the liner material layer 164 p may be on the uppermost surface of the gate dielectric layer 150 , and on an upper surface of the gate dielectric layer 150 that is lower than the uppermost surface of the gate dielectric layer 150 .

[0070] Reference Figure 12 , a capping material layer 166p may be formed. The capping material layer 166p may be on the upper surface of the channel layer 140 (e.g., covering the upper surface of the channel layer 140) and (at least partially) fill the space between the back gate dielectric layers 122. A portion of the capping material layer 166p may be disposed between the gate capping layers 162 and may define an air gap AG. The capping material layer 166p may partially fill the space between adjacent gate capping layers 162 along the X-direction. For example, the air gap AG may be disposed (along the X-direction) between adjacent word lines 152 and (along the Z-direction) between the capping material layer 166p (which will become the capping pattern 166 in a later process) and the liner material layer 164p (which will become the insulating liner 164).

[0071] Reference Figure 13 The liner material layer 164p and the capping material layer 166p may be etched back to form the back gate liner 127, the insulating liner 164, and the capping pattern 166. The capping pattern 166 may define the upper limit of the air gap AG, and the insulating liner 164 may define the lower limit and lateral limits (along the X-direction) of the air gap AG. The portion of the capping material layer 166p that (at least partially) fills the space between the back gate dielectric layers 122 (e.g., between the back gate liners 127) may be referred to as the upper capping layer 126. The upper surface of the channel layer 140 may be exposed through an etch-back process.

[0072] Reference Figure 14, a contact material layer 170' may be formed on the channel layer 140. The contact material layer 170' may include a first contact material layer 170a', a second contact material layer 170b', a third contact material layer 170c', and a fourth contact material layer 170d', which are sequentially stacked.

[0073] Reference Figure 15 The contact material layer 170' may be patterned to form a contact pattern 170. The contact pattern 170 may include a first contact layer 170a, a second contact layer 170b, a third contact layer 170c, and a fourth contact layer 170d stacked sequentially. The contact pattern 170 may be electrically connected to the channel layer 140.

[0074] Upper insulating patterns 175 may be formed between contact patterns 170. Upper insulating patterns 175 may be formed by patterning contact material layer 170' and filling contact material layer 170' with an insulating material. Upper insulating patterns 175 may electrically separate contact patterns 170 from each other. For example, upper insulating patterns 175 and contact patterns 170 may be alternately arranged along the X-direction.

[0075] An information storage structure 180 including a first electrode 182, a dielectric layer 184, and a second electrode 186 may be formed on the contact pattern 170. The first electrode 182 may contact the fourth contact layer 170d of the contact pattern 170.

[0076] Reference Figure 16 , reversible Figure 15 The resulting structure is formed so that the information storage structure 180 faces downwardly toward the lower semiconductor layer 11, and a grinding process may be performed. Through the grinding process, the lower semiconductor layer 11 and the insulating layer 12 may be removed, and the lower insulating pattern 130 and the channel layer 140 may be exposed. The back gate dielectric layer 122 and the back gate electrode 124 may also be partially etched to be coplanar with the channel layer 140.

[0077] Reference Figure 17 , a portion of the back gate electrode 124 may be removed, and a lower capping layer 128 may be formed in the space of the removed portion of the back gate electrode 124. The back gate electrode 124 may be disposed between the upper capping layer 126 and the lower capping layer 128, and may not be exposed.

[0078] Reference Figure 18 , a cleaning process may be performed. Through the cleaning process, the oxide film formed on the channel layer 140 may be removed. Through the cleaning process, the back gate dielectric layer 122 and the lower insulating pattern 130 may be partially etched, and the side surface (upper region) of the channel layer 140 may be exposed.

[0079] Reference Figure 2 and Figure 19The bit line structure 110 and the lower insulating layer 101 may be formed on the channel layer 140 so that the semiconductor device 100 may be manufactured. The bit line structure 110 may include a third conductive pattern 110c, a second conductive pattern 110b, and a first conductive pattern 110a sequentially stacked on the channel layer 140.

[0080] In an example embodiment, a peripheral circuit structure including a peripheral circuit element electrically connected to at least one of the bit line structures 110 may be disposed on the lower insulating layer 101 .

[0081] Figures 20 to 25 is a cross-sectional view of a semiconductor device according to example embodiments.

[0082] Reference Figure 20 The insulating structure 160 of the semiconductor device 100a may include a gate capping layer 162, a capping pattern 166a, an air gap AG, and an insulating liner 164. The capping pattern 166a and the insulating liner 164 may define the air gap AG. In one example embodiment, the lower surface of the capping pattern 166a, which defines the upper limit of the air gap AG, may be concave (e.g., may be concave in the Z direction). The capping pattern 166a may be concave in the Z direction toward the upper insulating pattern 175.

[0083] Reference Figure 21 , the insulating structure 260 of the semiconductor device 100b may include a gate cap layer 162, an insulating liner 164, a capping pattern 166, and a low-κ dielectric material 266 disposed on the insulating liner 164. For example, the low-κ dielectric material 266 may be disposed on the inner surface 164a (and / or outer surface 164b) of the insulating liner 164. In an example embodiment, the low-κ dielectric material 266 may be disposed in the core region and completely fill the space within the insulating liner 164 along the X direction. The low-κ dielectric material 266 may be disposed in the core region with reference to FIG. Figure 12 The capping material layer 166p is formed between the word lines 152 during the process described. The upper surface of the low-κ dielectric material 266 may be coplanar with the upper surface of the insulating liner 164 and the upper surface of the gate cap layer 162.

[0084] Reference Figure 22 The back gate structure 120 of the semiconductor device 100c may include a back gate dielectric layer 122, a back gate electrode 124, an upper capping layer 126c on the back gate electrode 124, and a lower capping layer 128. In one example embodiment, Figure 3Unlike the embodiment shown in FIG, the back gate liner 127 may be omitted. For example, the upper cover layer 126 c may be on the upper surface of the back gate electrode 124 and the side surfaces of the back gate dielectric layer 122 (may contact the upper surface of the back gate electrode 124 and the side surfaces of the back gate dielectric layer 122) (without the back gate liner 127 between the upper cover layer 126 c and the upper surface of the back gate electrode 124 and the side surfaces of the back gate dielectric layer 122).

[0085] In reference Figure 10 In the wet etching process described above, the preliminary covering layer 126p may include a material having an etching selectivity relative to the sacrificial layer 160p and may not be removed. For example, the preliminary covering layer 126p may include silicon nitride. Figure 11 In the process of forming the liner material layer 164p described above, the liner material layer 164p may be formed on the preliminary capping layer 126p and may not contact the back gate electrode 124. Figure 13 The preliminary capping layer 126 p after the described etch-back process may be referred to as an upper capping layer 126 c .

[0086] Reference Figure 23 The back gate structure 120 of the semiconductor device 100d may include a back gate dielectric layer 122, a back gate electrode 124, an upper cap layer 126, a back gate liner 127 and a lower cap layer 128. Figure 10 In the described wet etching process, at least one of the upper portion of the back gate dielectric layer 122 and the upper portion of the gate dielectric layer 150 may be etched.

[0087] In one exemplary embodiment, the horizontal width (along the X-direction) of the back-gate dielectric layer 122 may decrease upward. The upper end of the back-gate dielectric layer 122 may be located at a height lower than the upper surface of the channel layer 140. The horizontal width (along the X-direction) of the upper cover layer 126 may decrease downward. A portion of the upper cover layer 126 may vertically overlap the back-gate dielectric layer 122 (along the Z-direction). A portion of the back-gate liner 127 may contact the channel layer 140.

[0088] The semiconductor device 100d may further include an insulating layer 163d disposed on (e.g., in contact with) the side surfaces of the insulating structure 160 and the upper surface (e.g., the uppermost surface) of the gate dielectric layer 150. The insulating layer 163d may contact the side surfaces of the channel layer 140 and the side surfaces of the gate cap layer 162. The insulating layer 163d may also contact the upper surface of the gate dielectric layer 150. The insulating layer 163d may include, for example, silicon nitride.

[0089] Reference Figure 24The back gate structure 120 of the semiconductor device 100e may include a back gate dielectric layer 122, a back gate electrode 124, a first upper cover layer 126e1 on the back gate electrode 124, a second upper cover layer 126e2 disposed on both side surfaces (opposite side surfaces along the X direction) of the first upper cover layer 126e1, a back gate liner 127e on the side surfaces and lower surface of the second upper cover layer 126e2 (e.g., covering the side surfaces and lower surface of the second upper cover layer 126e2), and a lower cover layer 128. The back gate liner 127e may contact the side surfaces of the first upper cover layer 126e1. The first upper cover layer 126e1, the second upper cover layer 126e2, and the back gate liner 127e may include, for example, silicon nitride. The semiconductor device 100e may include an insulating layer 163d, which is included in Figure 23 In the semiconductor device 100d.

[0090] Reference Figure 25 , the insulating structure 360 ​​of the semiconductor device 100f may include a capping pattern 366, an insulating liner 364, and an air gap AG. In an example embodiment, Figure 3 Unlike the embodiment shown in FIG, the gate capping layer 162 may be omitted. For example, the gate capping layer 162 may include the same material as the sacrificial layer 160p, and in reference to FIG. Figure 10 In the described wet etching process, the gate cap layer 162 may be removed together with the sacrificial layer 160 p .

[0091] The insulating liner 364 may contact the upper and side surfaces of the word line 152 and the side surface of the gate dielectric layer 150. A portion of the capping pattern 366 may overlap the word line 152 in the vertical direction (along the Z direction). The lower end of the capping pattern 366 may be located at a height lower than the upper surface of the word line 152. The capping pattern 366 may have a horizontal width (along the X direction) greater than the horizontal width (along the X direction) of the air gap AG.

[0092] As described above, according to exemplary embodiments of the present invention, since an air gap or a low-κ dielectric material is provided between word lines, coupling noise between adjacent word lines can be reduced or prevented. Therefore, when a semiconductor device is operating, it is possible to prevent leakage current from being generated in unselected transistors.

[0093] Various and advantageous advantages and effects of the present inventive concept are not limited to the above description and can be more easily understood in the course of describing specific embodiments of the present inventive concept.

[0094] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: bit line structure; multiple back gate structures on the bit line structure; A first channel layer and a second channel layer are located between the plurality of back gate structures along a first direction, wherein the first channel layer and the second channel layer extend along a second direction; a first word line and a second word line between the first channel layer and the second channel layer along a first direction, wherein the first word line is adjacent to the first channel layer and the second word line is adjacent to the second channel layer; and The insulating structure is provided on the side surface of the first word line, the side surface of the second word line, the upper surface of the first word line, and the upper surface of the second word line. The insulating structure includes: a core region between the first word line and the second word line along the first direction; and an insulating liner between the core region and the first word line along the first direction and between the core region and the second word line along the first direction. wherein side surfaces of the first word line and the second word line face each other along a first direction, wherein the insulating liner extends to a height higher than that of the first word line and the second word line, The first direction is parallel to the lower surface of the bit line structure, and The second direction is perpendicular to the bottom surface of the bit line structure.

2. The semiconductor device according to claim 1, wherein The insulating structure further includes: a first gate covering layer on the upper surface of the first word line; and a second gate covering layer on the upper surface of the second word line, and The insulating liner is between the core region and the first gate covering layer along the first direction, and between the core region and the second gate covering layer along the first direction.

3. The semiconductor device according to claim 2, wherein The insulating structure further comprises: a covering pattern, on the core region, and The insulating liner is between the covering pattern and the first gate covering layer along the first direction, and between the covering pattern and the second gate covering layer along the first direction.

4. The semiconductor device according to claim 3, wherein The lower surface of the covering pattern is convex toward the core area.

5. The semiconductor device according to claim 1, wherein The core region includes the air gap.

6. The semiconductor device according to claim 1, further comprising: a gate dielectric layer, beneath the lower surface of the insulating structure, The gate dielectric layer is between the first word line and the first channel layer along the first direction, and between the second word line and the second channel layer along the first direction, and The insulating liner is located between the core region and the gate dielectric layer along the second direction.

7. The semiconductor device according to claim 1, wherein Each of the plurality of back gate structures includes: a back gate electrode; an upper cover layer on the back gate electrode; and a back gate liner on a lower surface and side surfaces of the upper cover layer.

8. The semiconductor device according to claim 7, wherein The back gate liner includes the same material as that of the insulating liner.

9. The semiconductor device according to claim 7, wherein The horizontal width of the upper cover layer along the first direction decreases as the upper cover layer extends toward the back gate electrode along the second direction.

10. The semiconductor device according to claim 9, wherein Each of the plurality of back gate structures further includes a back gate dielectric layer on a side surface of the back gate electrode and a side surface of the upper cover layer, and The horizontal width of the back gate dielectric layer along the first direction decreases as the back gate dielectric layer extends farther from the lower surface of the bit line structure.

11. The semiconductor device according to claim 1, wherein The insulating structure further comprises: a covering pattern, on the core region, and The lower surface of the covering pattern is concave along the second direction.

12. The semiconductor device according to claim 1, wherein The core region includes a low-κ dielectric material having a dielectric constant lower than that of silicon oxide.

13. The semiconductor device according to claim 1, wherein Each of the plurality of back gate structures includes: a back gate electrode; a first upper cover layer on the back gate electrode; a back gate dielectric layer on a side surface of the back gate electrode; and a second upper cover layer on opposite side surfaces of the first upper cover layer in a first direction.

14. The semiconductor device according to claim 1, wherein The insulating structure also includes: a covering pattern, on the core area, wherein a portion of the covering pattern overlaps the first word line and the second word line along the second direction, The lower end of the covering pattern is closer to the lower surface of the bit line structure than the upper surface of the first word line and the upper surface of the second word line along the second direction, and The insulating structure contacts a side surface of the first word line, a side surface of the second word line, an upper surface of the first word line, and an upper surface of the second word line.

15. The semiconductor device according to claim 14, wherein An insulating liner is on an upper surface of the first word line and an upper surface of the second word line.

16. A semiconductor device comprising: bit line structure; a channel layer on the bit line structure, wherein the channel layer extends along a first direction; a back gate structure facing the first side surface of the channel layer along the second direction; a word line facing a second side surface of the channel layer along a second direction, the second side surface of the channel layer being opposite to the first side surface of the channel layer; a gate dielectric layer between the channel layer and the word line along the second direction; and Insulation structure, on the word line, The gate dielectric layer includes: a vertical portion in contact with a first side surface of the word line and a side surface of the insulating structure; and a horizontal portion in contact with a lower surface of the word line and a lower surface of the insulating structure. The insulating structure includes: a core region spaced apart from the word line; and an insulating liner extending between the core region and the second side surface of the word line along the second direction and between the horizontal portion and the core region along the first direction. The first side surface of the word line is opposite to the second side surface of the word line along the second direction. The first direction is perpendicular to the lower surface of the bit line structure, and The second direction is parallel to the bottom surface of the bit line structure.

17. The semiconductor device according to claim 16, wherein The insulating structure further includes a covering pattern in contact with an upper area of ​​the inner surface of the insulating liner, and The core region includes the air gap.

18. The semiconductor device according to claim 16, wherein The back gate structure further includes: a back gate electrode; and a back gate dielectric layer between the back gate electrode and the channel layer along the second direction, and The lower surface of the back gate dielectric layer is farther from the lower surface of the bit line structure than the lower surface of the channel layer.

19. The semiconductor device according to any one of claims 16 to 18, further comprising: The insulating pattern is between the bit line structure and the gate dielectric layer along a first direction.

20. A semiconductor device comprising: bit line structure; Back gate structure, on the bit line structure; A first channel layer and a second channel layer are located between the back gate structures along a first direction, wherein the first channel layer and the second channel layer extend along a second direction; a first word line and a second word line between the first channel layer and the second channel layer along a first direction, wherein the first word line is adjacent to the first channel layer, and the second word line is adjacent to the second channel layer; an insulating structure in contact with a side surface of the first word line, a side surface of the second word line, an upper surface of the first word line, and an upper surface of the second word line; a gate dielectric layer between the first channel layer and the first word line along the first direction, between the first channel layer and the first upper region of the insulation structure along the first direction, between the second channel layer and the second word line along the first direction, and between the second channel layer and the second upper region of the insulation structure along the first direction; a contact pattern electrically connected to the first channel layer and the second channel layer; and Information storage structure, on the contact pattern, The insulating structure includes: a core region spaced apart from the first word line and the second word line; and an insulating liner between a side surface of the first word line and the core region and between a side surface of the second word line and the core region, and extending to a height higher than that of the first word line and the second word line. The core region has a dielectric constant lower than that of silicon oxide. Wherein, the first upper region of the insulating structure is on the first word line, The second upper region of the insulating structure is on the second word line. wherein side surfaces of the first word line and the second word line face each other along a first direction, The first direction is parallel to the lower surface of the bit line structure, and The second direction is perpendicular to the bottom surface of the bit line structure.

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