Semiconductor device

Abstract

A semiconductor device includes: a first structure including a memory region and a first peripheral circuit region; and a second structure vertically overlapping the first structure and including a core circuit region and a second peripheral circuit region, in which the memory region includes: a first cell vertical active pattern; a first word line having a side surface facing a first side surface of the first cell vertical active pattern; and a first cell gate dielectric layer between the first cell vertical active pattern and the first word line, in which the first peripheral circuit region includes: a first peripheral vertical active pattern disposed at substantially the same level as the first cell vertical active pattern; a first peripheral gate electrode having a side surface facing a first side surface of the first peripheral vertical active pattern; and a first peripheral gate dielectric layer between the first peripheral vertical active pattern and the first peripheral gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0033051 filed on March 8, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0004] Research has been conducted to reduce the size of elements included in semiconductor devices and improve their performance. For example, in DRAM, research has been conducted to reliably and stably form elements with reduced size, but the performance of semiconductor devices deteriorates as the size of elements is reduced. Summary of the Invention

[0005] Example embodiments of the present disclosure are directed to providing a semiconductor device that can increase integration density and improve performance.

[0006] Example embodiments of the present disclosure are directed to providing a method of manufacturing the semiconductor device.

[0007] According to an example embodiment, a semiconductor device includes: a first structure including a storage area and a first peripheral circuit area; and a second structure vertically overlapping the first structure and including a core circuit area and a second peripheral circuit area, wherein the storage area includes: a first unit vertical active pattern; a first word line having a side surface facing the first side surface of the first unit vertical active pattern; and a first unit gate dielectric layer between the first unit vertical active pattern and the first word line, wherein the first peripheral circuit area includes: a first peripheral vertical active pattern arranged at substantially the same level as the first unit vertical active pattern; a first peripheral gate electrode having a side surface facing the first side surface of the first peripheral vertical active pattern; and a first peripheral gate dielectric layer between the first peripheral vertical active pattern and the first peripheral gate electrode.

[0008] According to an example embodiment, a semiconductor device includes: a first structure including a first storage area and a second storage area spaced apart from each other, and a first peripheral circuit area between the first storage area and the second storage area; and a second structure vertically overlapping with the first structure and joined to the first structure, wherein the second structure includes: a first core circuit area vertically overlapping with the first storage area; a second core circuit area vertically overlapping with the second storage area; and a second peripheral circuit area vertically overlapping with the first peripheral circuit area, wherein each of the first storage area and the second storage area includes a cell transistor and a data storage structure electrically connected to the cell transistor, wherein the cell transistor includes: a cell vertical active pattern; a word line having a side surface facing at least a portion of a side surface of the cell vertical active pattern; and a cell gate dielectric layer between the cell vertical active pattern and the word line.

[0009] According to an example embodiment, a semiconductor device includes: a storage area including a cell transistor and a data storage structure; a first peripheral circuit area disposed outside the storage area and including a first peripheral circuit transistor; a core circuit area vertically overlapping with the storage area and including a core circuit transistor; and a second peripheral circuit area disposed outside the core circuit area, vertically overlapping with the first peripheral circuit area, and including a second peripheral circuit transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various aspects, features, and advantages of example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B is a diagram illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 2A is an enlarged view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0013] Figure 2B is an enlarged view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0014] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E and Figure 3F is an enlarged cross-sectional view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0015] Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D are enlarged cross-sectional views illustrating various examples of transistors in a semiconductor device according to example embodiments of the present disclosure;

[0016] Figure 5A and Figure 5B are plan views illustrating various examples of transistors in a semiconductor device according to example embodiments of the present disclosure;

[0017] Figure 6A and Figure 6B is a diagram illustrating an inverter in a semiconductor device according to an example embodiment of the present disclosure;

[0018] Figure 7 is an enlarged cross-sectional view illustrating an insulating structure of a semiconductor device according to an example embodiment of the present disclosure;

[0019] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 8E and Figure 8F are plan views illustrating various examples of semiconductor devices according to example embodiments of the present disclosure;

[0020] Figure 9A is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0021] Figure 9B is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0022] Figure 10 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0023] Figure 11 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0024] Figure 12 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0025] Figure 13 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0026] Figure 14 is a perspective view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0027] Figure 15 is a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure; and

[0028] 16A to 16H and Figure 17 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Below, the example embodiments of the present disclosure will be described with reference to the accompanying drawings as follows. Hereinafter, terms such as "upper", "middle", "middle", "lower" etc. can be replaced with other terms such as "first", "second", "third", etc. to describe the elements of this specification. Terms such as "first", "second" and "third" can be used to describe various elements, but these elements are not limited by these terms in terms of order or relative position, and the element referred to as "first element" can be equivalently referred to as "second element". In the specification, terms such as "lower", "upper", "upper end" and "lower end" can be terms described with reference to the accompanying drawings. The vertical length of the first element can refer to the distance from the lower surface to the upper surface of the first element.

[0030] Will refer to Figure 1A and Figure 1B Examples of semiconductor devices according to example embodiments are described. Figure 1A is a cross-sectional view illustrating a semiconductor device according to example embodiments, and Figure 1B It shows Figure 1A Magnified images of area "A" and area "B".

[0031] refer to Figure 1A and Figure 1B , a semiconductor device 1 according to example embodiments may include a first structure CH1 and a second structure CH2 vertically overlapping the first structure CH1. The first structure CH1 may be disposed on the second structure CH2. The first structure CH1 may be bonded to the second structure CH2.

[0032] The first structure CH1 may include a first memory region MR1 and a first peripheral circuit region PR_U disposed outside the first memory region MR1 .

[0033] The first structure CH1 may further include a second memory region MR2 disposed at the same level as that of the first memory region MR1 .

[0034] The first peripheral circuit region PR_U may be disposed between the first and second memory regions MR1 ​​and MR2. The first and second memory regions MR1 ​​and MR2 may have substantially the same structure.

[0035] Each of the first storage region MR1 and the second storage region MR2 may include cell transistors c_TRa and c_TRb. For example, the first storage region MR1 may include a first cell transistor c_TRa, and the second storage region MR2 may include a second cell transistor c_TRb. The cell transistors c_TRa and c_TRb may also be referred to as cell vertical channel transistors.

[0036] The first memory region MR1 may include a cell vertical active pattern 109m1 included in the first cell transistor c_TRa, a word line 139m1, and a cell gate dielectric layer FOc between the cell vertical active pattern 109m1 and the word line 139m1.

[0037] The unit vertical active pattern 109m1 may include a first unit vertical active pattern 109m1a and a second unit vertical active pattern 109m1b adjacent to and spaced apart from each other.

[0038] The word line 139m1 may include a first word line 139m1a having a side surface facing the first side surface of the first cell vertical active pattern 109m1a and a second word line 139m1b having a side surface facing the second side surface of the second cell vertical active pattern 109m1b.

[0039] The cell gate dielectric layer FOc may be disposed between the first cell vertical active pattern 109m1a and the first word line 139m1a, and between the second cell vertical active pattern 109m1b and the second word line 139m1b.

[0040] The first memory region MR1 may further include a cell back-gate electrode 121m1, and a cell back-gate dielectric layer BOc between the cell back-gate electrode 121m1 and the cell vertical active pattern 109m1. For example, the cell back-gate electrode 121m1 may be disposed between the first cell vertical active pattern 109m1a and the second cell vertical active pattern 109m1b that are adjacent to each other, and the cell back-gate dielectric layer BOc may be disposed between the first cell vertical active pattern 109m1a and the cell back-gate electrode 121m1, and between the second cell vertical active pattern 109m1b and the cell back-gate electrode 121m1.

[0041] The first word line 139m1a may have a side surface facing the first side surface of the first cell vertical active pattern 109m1a, the first word line 139m1b may have a side surface facing the second side surface of the second cell vertical active pattern 109m1b, and the cell back gate electrode 121m1 may be arranged between the third side surface of the first cell vertical active pattern 109m1a and the fourth side surface of the second cell vertical active pattern 109m1b, and the third side surface and the fourth side surface face each other.

[0042] The first cell vertical active pattern 109m1a, the cell back gate electrode 121m1, and the second cell vertical active pattern 109m1b may be disposed between the first word line 139m1a and the second word line 139m1b.

[0043] Each cell vertical active pattern 109m1 may include a lower cell source / drain region 148m, an upper cell source / drain region 187m on the lower cell source / drain region 148m, and a cell channel region CHm between the lower cell source / drain region 148m and the upper cell source / drain region 187m.

[0044] The lower cell source / drain region 148m and the upper cell source / drain region 187m may have N-type conductivity.

[0045] The first word line 139m1a may have a side surface facing the cell channel region CHm of the first cell vertical active pattern 109m1a. The first word line 139m1b may have a side surface facing the cell channel region CHm of the second cell vertical active pattern 109m1b.

[0046] The second storage region MR2 and the first storage region MR1 may have substantially the same structure, so that the second storage region MR2 may include a cell vertical active pattern 109m2, a word line 139m2 and a cell back gate electrode 121m2 corresponding to the cell vertical active pattern 109m1, the word line 139m1 and the cell back gate electrode 121m1 of the first storage region MR1, respectively.

[0047] The cell back-gate electrodes 121m1 and 121m2 can control charges accumulated in the cell channel region CHm of the cell vertical active patterns 109m1 and 109m2. Accordingly, the cell channel region CHm can be configured as a floating body disposed between the lower cell source / drain region 148m and the upper cell source / drain region 187m. The cell back-gate electrodes 121m1 and 121m2 can prevent the performance of the cell transistors c_TRa and c_TRb from being degraded due to the floating body effect, thereby improving the performance of the cell transistors c_TRa and c_TRb. Accordingly, the cell back-gate electrodes 121m1 and 121m2 can prevent charges (e.g., holes) from accumulating in the floating body of the cell channel region CHm during operation of the cell transistors c_TRa and c_TRb and changing the threshold voltage of the cell transistors c_TRa and c_TRb. Accordingly, the cell back-gate electrodes 121m1 and 121m2 may enable the cell transistors c_TRa and c_TRb to operate stably, and the performance of the semiconductor device 1 may be improved.

[0048] The first peripheral circuit region PR_U may include first peripheral circuit transistors N_TRa and P_TRa disposed at substantially the same level as the cell transistors c_TRa and c_TRb. For example, the first peripheral circuit region PR_U may include a first peripheral NMOS transistor N_TRa and a first peripheral PMOS transistor P_PRa.

[0049] The first peripheral circuit region PR_U may include peripheral gate electrodes 139p1 and 139p2 included in the first peripheral circuit transistors N_TRa and P_TRa, peripheral vertical active patterns 109p1 and 109p2, and peripheral gate dielectric layers FOn and FOp. The peripheral vertical active patterns 109p1 and 109p2 may include an NMOS vertical active pattern 109p1 and a PMOS vertical active pattern 109p2.

[0050] The cell vertical active patterns 109m1 and 109m2 and the peripheral vertical active patterns 109p1 and 109p2 may include a material that functions as a transistor channel (e.g., a semiconductor material). For example, each of the cell vertical active patterns 109m1 and 109m2 and the peripheral vertical active patterns 109p1 and 109p2 may include at least one of a silicon layer that functions as a channel region, an oxide semiconductor layer, and a two-dimensional material layer having semiconductor properties. For example, each of the cell vertical active patterns 109m1 and 109m2 and the peripheral vertical active patterns 109p1 and 109p2 may include single crystal silicon or polycrystalline silicon.

[0051] The peripheral gate electrodes 139p1 and 139p2 may include an NMOS gate electrode 139p1 and a PMOS gate electrode 139p2. The peripheral gate dielectric layers FOn and FOp may include an NMOS gate dielectric layer FOn and a PMOS gate dielectric layer FOp.

[0052] The word lines 139m1 and 139m2, the NMOS gate electrode 139p1, and the PMOS gate electrode 139p2 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments are not limited thereto. Each of the word lines 139m1 and 139m2, the NMOS gate electrode 139p1, and the PMOS gate electrode 139p2 may include a single layer or multiple layers formed of the aforementioned conductive materials. In example embodiments, the NMOS gate electrode 139p1 and the PMOS gate electrode 139p2 may include conductive materials having different work functions.

[0053] The NMOS vertical active pattern 109 p 1 may include a first NMOS vertical active pattern 109 p 1 a and a second NMOS vertical active pattern 109 p 1 b adjacent to and spaced apart from each other.

[0054] In an example, a spacing distance between the cell vertical active patterns 109m1 adjacent to each other with the cell back gate electrode 121m1 interposed therebetween may be substantially the same as a spacing distance between the first and second NMOS vertical active patterns 109p1a and 109p1b adjacent to each other.

[0055] The NMOS gate electrode 139p1 may have a first NMOS gate electrode 139p1a having a side surface facing a first side surface of the first NMOS vertical active pattern 109p1a and a second NMOS gate electrode 139p1b having a side surface facing a second side surface of the second NMOS vertical active pattern 109p1b.

[0056] An NMOS gate dielectric layer FOn may be disposed between the first NMOS vertical active pattern 109p1a and the first NMOS gate electrode 139p1a, and between the second NMOS vertical active pattern 109p1b and the second NMOS gate electrode 139p1b.

[0057] The PMOS vertical active pattern 109p2 may include a first PMOS vertical active pattern 109p2a and a second PMOS vertical active pattern 109p2b adjacent to and spaced apart from each other.

[0058] In an example, a spacing distance between the cell vertical active patterns 109m1 adjacent to each other with the cell back gate electrode 121m1 interposed therebetween may be substantially the same as a spacing distance between the first and second PMOS vertical active patterns 109p2a and 109p2b adjacent to each other.

[0059] The PMOS gate electrode 139p2 may have a first PMOS gate electrode 139p2a having a side surface facing a first side surface of the first PMOS vertical active pattern 109p2a and a second PMOS gate electrode 139p2b having a side surface facing a second side surface of the second PMOS vertical active pattern 109p2b.

[0060] A PMOS gate dielectric layer FOp may be disposed between the first PMOS vertical active pattern 109p2a and the first PMOS gate electrode 139p2a, and between the second PMOS vertical active pattern 109p2b and the second PMOS gate electrode 139p2b.

[0061] The NMOS gate electrode 139 p 1 may have a vertical length H 1 that is substantially the same as vertical lengths of the word lines 139 m 1 and 139 m 2 .

[0062] The PMOS gate electrode 139 p 2 may have a vertical length H1 substantially the same as vertical lengths of the word lines 139 m 1 and 139 m 2 .

[0063] The first peripheral circuit region PR_U may further include third peripheral gate electrodes 121 p 1 and 121 p 2 and third peripheral gate dielectric layers BOn and BOp.

[0064] The third peripheral gate electrodes 121p1 and 121p2 may be configured as peripheral back gate electrodes. Similar to the cell back gate electrodes 121m1 and 121m2, the third peripheral gate electrodes 121p1 and 121p2 (which may be peripheral back gate electrodes) may stabilize the operation of the peripheral circuit transistors N_TRa and P_TR, thereby improving the performance of the semiconductor device 1.

[0065] The cell back-gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may include at least one conductive material. For example, each of the cell back-gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but example embodiments are not limited thereto. Each of the cell back-gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may include a single layer or multiple layers formed of the aforementioned materials.

[0066] In an example, the cell back gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may include a different material from the word lines 139m1 and 139m2.

[0067] In another example, the cell back gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may include the same material as the word lines 139m1 and 139m2.

[0068] In an example, the cell back-gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may have the same vertical length.

[0069] In an example, vertical lengths of the cell back gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may be different from vertical lengths of the word lines 139m1 and 139m2 and the peripheral gate electrodes 139p1 and 139p2, respectively.

[0070] In another example, vertical lengths of the cell back gate electrodes 121m1 and 121m2 and the third peripheral gate electrodes 121p1 and 121p2 may be the same as vertical lengths of the word lines 139m1 and 139m2 and the peripheral gate electrodes 139p1 and 139p2, respectively.

[0071] The third peripheral gate electrodes 121p1 and 121p2 may include a third NMOS gate electrode 121p1 disposed between the first and second NMOS vertical active patterns 109p1a and 109p1b adjacent to each other, and a third PMOS gate electrode 121p2 disposed between the first and second PMOS vertical active patterns 109p2a and 109p2b adjacent to each other.

[0072] The third peripheral gate dielectric layers BOn and BOp may include a third NMOS gate dielectric layer BOn and a third PMOS gate dielectric layer BOp.

[0073] A third NMOS gate dielectric layer BOn may be disposed between the first NMOS vertical active pattern 109p1a and the third NMOS gate electrode 121p1, and between the second NMOS vertical active pattern 109p1b and the third NMOS gate electrode 121p1.

[0074] A third PMOS gate dielectric layer BOp may be disposed between the first PMOS vertical active pattern 109p2a and the third PMOS gate electrode 121p2, and between the second PMOS vertical active pattern 109p2b and the third PMOS gate electrode 121p2.

[0075] The first NMOS gate electrode 139p1a may have a side surface facing the first side surface of the first NMOS vertical active pattern 109p1a, the second NMOS gate electrode 139p1b may have a side surface facing the second side surface of the second NMOS vertical active pattern 109p1b, and the third NMOS gate electrode 121p1 may be arranged between the third side surface of the first NMOS vertical active pattern 109p1a and the fourth side surface of the second NMOS vertical active pattern 109p1b, and the third side surface and the fourth side surface face each other.

[0076] The first NMOS vertical active pattern 109p1a, the third NMOS gate electrode 121p1, and the second NMOS vertical active pattern 109p1b may be disposed between the first NMOS gate electrode 139p1a and the second NMOS gate electrode 139p1b.

[0077] In example embodiments, the third NMOS gate electrode 121 p 1 may be configured as an NMOS back-gate electrode.

[0078] The first PMOS gate electrode 139p2a may have a side surface facing the first side surface of the first PMOS vertical active pattern 109p2a, the second PMOS gate electrode 139p2b may have a side surface facing the second side surface of the second PMOS vertical active pattern 109p2b, and the third PMOS gate electrode 121p2 may be arranged between the third side surface of the first PMOS vertical active pattern 109p2a and the fourth side surface of the second PMOS vertical active pattern 109p2b, and the third side surface and the fourth side surface face each other.

[0079] The first PMOS vertical active pattern 109p2a, the third PMOS gate electrode 121p2, and the second PMOS vertical active pattern 109p2b may be disposed between the first PMOS gate electrode 139p2a and the second PMOS gate electrode 139p2b.

[0080] In example embodiments, the third PMOS gate electrode 121 p 2 may be configured as a PMOS back gate electrode.

[0081] Each NMOS vertical active pattern 109p1 may include a lower NMOS source / drain region 148p1, an upper NMOS source / drain region 187p1 on the lower NMOS source / drain region 148p1, and an NMOS channel region CHp1 between the lower NMOS source / drain region 148p1 and the upper NMOS source / drain region 187p1.

[0082] Lower NMOS source / drain region 148p1 and upper NMOS source / drain region 187p1 may have N-type conductivity.

[0083] In an example, the lower NMOS source / drain region 148p1 and the upper NMOS source / drain region 187p1 may have substantially the same impurity concentration as that of the lower cell source / drain region 148m and the upper cell source / drain region 187m.

[0084] In another example, the lower NMOS source / drain region 148p1 and the upper NMOS source / drain region 187p1 may have an impurity concentration higher than that of the lower cell source / drain region 148m and the upper cell source / drain region 187m.

[0085] Each PMOS vertical active pattern 109p2 may include a lower PMOS source / drain region 148p2, an upper PMOS source / drain region 187p2 on the lower PMOS source / drain region 148p2, and a PMOS channel region CHp2 between the lower PMOS source / drain region 148p2 and the upper PMOS source / drain region 187p2.

[0086] Lower PMOS source / drain region 148p2 and upper PMOS source / drain region 187p2 may have P-type conductivity.

[0087] The first NMOS gate electrode 139p1a may have a side surface facing the NMOS channel region CHp1 of the first NMOS vertical active pattern 109p1a. The second NMOS gate electrode 109p1b may have a side surface facing the NMOS channel region CHp1 of the second NMOS vertical active pattern 109p1b.

[0088] The first PMOS gate electrode 139p2a may have a side surface facing the PMOS channel region CHp2 of the first PMOS vertical active pattern 109p2a. The second PMOS gate electrode 139p2b may have a side surface facing the PMOS channel region CHp2 of the second PMOS vertical active pattern 109p2b.

[0089] Each of the first and second memory regions MR1 ​​and MR2 may further include data storage structures DS1 and DS2.

[0090] The data storage structures DS1 and DS2 may be disposed on the cell transistors c_TRa and c_TRb. The data storage structures DS1 and DS2 may be electrically connected to the cell transistors c_TRa and c_TRb. The data storage structures DS1 and DS2 may include a first data storage structure DS1 in the first storage region MR1 and a second data storage structure DS2 in the second storage region MR2.

[0091] The data storage structures DS1 and DS2 may be configured as memory cell capacitors that can store data in a memory (e.g., DRAM), but example embodiments are not limited thereto. For example, the data storage structures DS1 and DS2 may be configured as data storage structures of an MRAM or a FeRAM.

[0092] Each of the data storage structures DS1 and DS2 may include first electrodes 163 extending in a vertical direction Z, second electrodes 169 on side and upper surfaces of each first electrode 163 , and a dielectric layer 166 between the first and second electrodes 163 and 169 .

[0093] Each of the first and second storage regions MR1 ​​and MR2 may further include cell contact structures 161a and 161b between the cell transistors c_TRa and c_TRb and the data storage structures DS1 and DS2. The cell contact structures 161a and 161b may be disposed on the cell transistors c_TRa and c_TRb. The cell contact structures 161a and 161b may be electrically connected to the upper cell source / drain regions 187m of the cell transistors c_TRa and c_TRb.

[0094] The cell contact structures 161a and 161b may include a first cell contact structure 161a and a second cell contact structure 161b, the first cell contact structure 161a may electrically connect the first cell transistor c_TRa to the first data storage structure DS1 in the first storage region MR1, and the second cell contact structure 161b may electrically connect the second cell transistor c_TRb to the second data storage structure DS2 in the second storage region MR2.

[0095] Each of the first and second cell contact structures 161a and 161b may include cell plug patterns 154m1 and 154m2, and cell pad patterns 160m1 and 160m2 on the cell plug patterns 154m1 and 154m2. The vertical center axes of the cell pad patterns 160m1 and 160m2 may not be aligned with the vertical center axes of the cell plug patterns 154m1 and 154m2.

[0096] The cell plug patterns 154m1 and 154m2 may be connected to the upper cell source / drain region 187m. The cell pad patterns 160m1 and 160m2 may be connected to the first electrode 163.

[0097] The first peripheral circuit region PR_U may further include peripheral vertical active patterns 109 p 1 and 109 p 2 on peripheral contact structures 154 p 1 and 154 p 2 , and peripheral contact structures 154 p 1 and 154 p 2 on upper peripheral wirings 160 pa and 160 pb .

[0098] The peripheral contact structures 154p1 and 154p2 may be disposed at substantially the same level as the cell plug pattern 154m1. The peripheral contact structures 154p1 and 154p2 and the cell plug pattern 154m1 may include the same conductive material.

[0099] The peripheral contact structures 154p1 and 154p2 may include an NMOS contact structure 154p1 electrically connected to the upper NMOS source / drain region 187p1 and a PMOS contact structure 154p2 electrically connected to the upper PMOS source / drain region 187p2.

[0100] The upper peripheral wirings 160pa and 160pb may be disposed at substantially the same level as the cell pad pattern 160m1. The upper peripheral wirings 160pa and 160pb and the cell pad pattern 160m1 may include the same conductive material.

[0101] The upper peripheral wirings 160 pa and 160 pb may include a first upper peripheral wiring 160 pa and a second upper peripheral wiring 160 pb.

[0102] The first memory region MR1 may further include a first bit line 190m1 under the cell transistor c_TRa, and the second memory region MR2 may further include a second bit line 190m2 under the cell transistor c_TRb.

[0103] A first bit line 190m1 may be connected to the lower cell source / drain region 148m of the cell vertical active pattern 109m1 in the first storage region MR1, and a second bit line 190m2 may be connected to the lower cell source / drain region 148m of the cell vertical active pattern 109m2 in the second storage region MR2.

[0104] The first peripheral circuit region PR_U may further include lower peripheral wirings 190p1 and 190p2 disposed at substantially the same level as the first and second bit lines 190m1 and 190m2 and under the peripheral circuit transistors N_TRa and P_TRa.

[0105] The lower peripheral wirings 190 p 1 and 190 p 2 may include a first lower peripheral wiring 190 p 1 connected to the NMOS vertical active pattern 109 p 1 , and a second lower peripheral wiring 190 p 2 connected to the PMOS vertical active pattern 109 p 2 .

[0106] Each of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2 may include at least one conductive material layer. For example, each of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2 may include doped polysilicon, a metal, a conductive metal nitride, a metal semiconductor compound, a conductive metal oxide, conductive graphene, a carbon nanotube, or a combination thereof. For example, each of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, a carbon nanotube, or a combination thereof, but example embodiments are not limited thereto. Each of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2 may include a single layer or multiple layers formed of the aforementioned conductive material. For example, each of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2 may include a first conductive layer 190a and a second conductive layer 190b below the first conductive layer 190a.

[0107] The first conductive layer 190 a of the first lower peripheral wiring 190 p 1 may include polysilicon having N-type conductivity, and the first conductive layer 190 a of the second lower peripheral wiring 190 p 2 may include polysilicon having P-type conductivity.

[0108] The first structure CH1 may further include a first routing wiring structure 192 disposed at a level lower than the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2, and a first bonding pad 196 disposed at a level lower than the first routing wiring structure 192.

[0109] The first routing wiring structure 192 may include a plurality of wirings disposed at different levels, and a plurality of vias respectively connected to upper and lower surfaces of the plurality of wirings.

[0110] The first routing wiring structure 192 may be electrically connected to the bit lines 190m1 and 190m2. In example embodiments, the first routing wiring structure 192 may be electrically connected to the lower peripheral wirings 190p1 and 190p2.

[0111] The first structure CH1 may further include a connection contact plug 194 disposed between the first routing wiring structure 192 and the first upper peripheral wiring 160 pa and electrically connecting the first routing wiring structure 192 to the first upper peripheral wiring 160 pa.

[0112] The connection contact plug 194 may make contact with a lower surface of the first upper peripheral wiring 160 pa , may extend downward, and may be connected to one of the plurality of wirings of the first routing wiring structure 192 .

[0113] The first structure CH1 may include a first insulating structure 198 , a second insulating structure INS, a third insulating structure 151 , a fourth insulating structure 157 , and a fifth insulating structure 175 .

[0114] The first insulating structure 198 may have a lower surface coplanar with a lower surface of the first bonding pad 196 and may have an upper surface coplanar with upper surfaces of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2. The first insulating structure 198 may include a plurality of insulating layers.

[0115] The second insulating structure INS may have a lower surface coplanar with lower surfaces of the cell vertical active patterns 109m1 and 109m2, the NMOS vertical active pattern 109p1, and the PMOS vertical active pattern 109p2, and an upper surface coplanar with upper surfaces of the cell vertical active patterns 109m1 and 109m2, the NMOS vertical active pattern 109p1, and the PMOS vertical active pattern 109p2. The second insulating structure INS may include a plurality of insulating layers.

[0116] The third insulation structure 151 may be disposed on side surfaces of the cell plug pattern 154m1 and the peripheral contact structures 154p1 and 154p2.

[0117] A fourth insulating structure 157 may be disposed on side surfaces of the cell pad pattern 160m1 and the upper peripheral wirings 160pa and 160pb.

[0118] A fifth insulating structure 175 may be disposed on the data storage structures DS1 and DS2 and the upper peripheral wirings 160 pa and 160 pb.

[0119] The first structure CH1 may further include a cell contact plug 178 m on the second electrode 169 of the data storage structures DS1 and DS2 , and a peripheral contact plug 178 p on the second upper peripheral wiring 160 pb .

[0120] The cell contact plugs 178 m may penetrate the fifth insulating structure 175 and may be electrically connected to the second electrodes 169 of the data storage structures DS1 and DS2 .

[0121] The peripheral contact plug 178 p may penetrate the fifth insulation structure 175 and may be electrically connected to the second upper peripheral wiring 160 pb.

[0122] The first structure CH1 may further include an upper cell wiring 184m on the cell contact plug 178m and a third upper peripheral wiring 184p on the peripheral contact plug 178p. The upper cell wiring 184m and the third upper peripheral wiring 184p may be disposed at substantially the same level.

[0123] The first structure CH1 may further include an upper insulating structure 181 on the fifth insulating structure 175 , the cell upper wiring 184 m , and the third peripheral upper wiring 184 p .

[0124] The second structure CH2 may include a first core circuit region CR1 vertically overlapping the first memory region MR1 and a second peripheral circuit region PR_L vertically overlapping the first peripheral circuit region PR_U.

[0125] The second structure CH2 may further include a second core circuit region CR2 vertically overlapping the second memory region MR2. The second peripheral circuit region PR_L may be disposed between the first core circuit region CR1 and the second core circuit region CR2.

[0126] The second structure CH2 may include a substrate 5, and a device isolation region 10s defining an active region 10a on the substrate 5. The substrate 5 may be configured as a semiconductor substrate.

[0127] The second structure CH2 may also include lower peripheral circuit transistors 25a, 25b and 25c set on the substrate 5, a second routing wiring structure 30 electrically connected to the lower peripheral circuit transistors 25a, 25b and 25c on the lower peripheral circuit transistors 25a, 25b and 25c, a second bonding pad 35 electrically connected to the second routing wiring structure 30 on the second routing wiring structure 30, and a lower insulating structure 40.

[0128] Each of the lower peripheral circuit transistors 25a, 25b, and 25c may include peripheral gate structures 15a and 15b disposed on the active region 10a, and peripheral source / drain regions 20sd disposed on both sides of the peripheral gate structures 15a and 15b and within the active region 10a. The peripheral gate structures 15a and 15b may include a peripheral gate dielectric layer 15a and a peripheral gate electrode 15b stacked sequentially.

[0129] The lower peripheral circuit transistors 25a, 25b, and 25c may include a first core circuit transistor 25a in the first core circuit region CR1, a second core circuit transistor 25b in the second core circuit region CR2, and a second peripheral circuit transistor 25c in the second peripheral circuit region PR_L.

[0130] The first core circuit region CR1 may include a first core circuit transistor 25 a , which may be electrically connected to a first bit line 190 m 1 through a second routing wiring structure 30 , a second bonding pad 35 , a first bonding pad 196 , and a first routing wiring structure 192 .

[0131] The second core circuit region CR2 may include a second core circuit transistor 25 b that is electrically connected to a second bit line 190 m 2 through a second routing wiring structure 30 , a second bonding pad 35 , a first bonding pad 196 , and a first routing wiring structure 192 .

[0132] The first core circuit transistor 25 a may vertically overlap the first data storage structure DS1 , and the second core circuit transistor 25 b may vertically overlap the second data storage structure DS2 .

[0133] The first and second peripheral circuit regions PR_U and PR_L may not vertically overlap with the first and second data storage structures DS1 and DS2.

[0134] The lower insulating structure 40 may be disposed on the substrate 5 and may have an upper surface coplanar with an upper surface of the second bonding pad 35 .

[0135] An upper surface of the second bonding pad 35 may be bonded to a lower surface of the first bonding pad 196, and an upper surface of the lower insulating structure 40 may be bonded to a lower surface of the first insulating structure 198. Accordingly, a bonding surface JSa may be formed between the first and second structures CH1 and CH2.

[0136] In the following description, reference will be made to Figure 2A Examples of semiconductor devices according to example embodiments are described. Figure 2A It shows Figure 1B An enlarged view of region A is provided, and further illustrates that alternative Figure 1B Region B' in region B.

[0137] Referring to the region A, the cell vertical active patterns 109 m 1 described above, which are adjacent to each other with the cell back gate electrode 121 m 1 interposed therebetween, may be spaced apart from each other by a first distance D 1 .

[0138] In an example, the first NMOS vertical active patterns ( Figure 1B 109p1a in) and the second NMOS vertical active pattern ( Figure 1BThe first NMOS vertical active pattern 109p1a' and the second NMOS vertical active pattern 109p1b' may be replaced with a first NMOS vertical active pattern 109p1a' and a second NMOS vertical active pattern 109p1b' spaced apart from each other by a second distance D2. The second distance D2 may be different from the first distance D1. The second distance D2 may be greater than the first distance D1.

[0139] In an example, the first PMOS vertical active patterns ( Figure 1B 109p2a in) and the second PMOS vertical active pattern ( Figure 1B The first PMOS vertical active pattern 109p2a′ and the second PMOS vertical active pattern 109p2b′ may be replaced with a first PMOS vertical active pattern 109p2a′ and a second PMOS vertical active pattern 109p2b′ spaced apart from each other by a second distance D2.

[0140] In an example, the first NMOS vertical active patterns ( Figure 1B 109p1a in) and the second NMOS vertical active pattern ( Figure 1B The third NMOS gate electrode (109p1b) between Figure 1B The first NMOS vertical active pattern 109p1a′ and the second NMOS vertical active pattern 109p1b′ may be replaced with a third NMOS gate electrode 121p1a and a fourth NMOS gate electrode 121p1b spaced apart from each other between the first NMOS vertical active pattern 109p1a′ and the second NMOS vertical active pattern 109p1b′.

[0141] In an example, the third NMOS gate electrode 121 p 1 a and the fourth NMOS gate electrode 121 p 1 b may be the aforementioned peripheral back gate electrodes.

[0142] In an example, the third NMOS gate electrode 121p1a and the fourth NMOS gate electrode 121p1b may be biased the same as the bias of the first NMOS gate electrode 139p1a and the second NMOS gate electrode 139p1b. Accordingly, a first NMOS transistor N_TRa' using the third NMOS gate electrode 121p1a and the fourth NMOS gate electrode 121p1b and the first NMOS gate electrode 139p1a and the second NMOS gate electrode 139p1b as NMOS gate electrodes may be provided. For example, the first NMOS transistor N_TRa' may include the first NMOS gate electrode 139p1a and the third NMOS gate electrode 121p1a to which the same bias is applied so as to function as NMOS gate electrodes on both sides of the first NMOS vertical active pattern 109p1a.

[0143] In an example, the first PMOS vertical active patterns ( Figure 1B 109p2a in) and the second PMOS vertical active pattern ( Figure 1BThe third PMOS gate electrode (109p2b) between Figure 1B The gate electrode 121p2 in the first and second PMOS vertical active patterns 109p2a′ and 109p2b′ may be replaced with a third PMOS gate electrode 121p2a and a fourth PMOS gate electrode 121p2b spaced apart from each other in the first and second PMOS vertical active patterns 109p2a′ and 109p2b′.

[0144] In an example, the third PMOS gate electrode 121p2a and the fourth PMOS gate electrode 121p2b may be the aforementioned peripheral back-gate electrodes.

[0145] In an example, the third PMOS gate electrode 121p2a and the fourth PMOS gate electrode 121p2b may be applied with the same bias as the first PMOS gate electrode 139p2a and the second PMOS gate electrode 139p2b. Accordingly, a first PMOS transistor P_TRa' using the third PMOS gate electrode 121p2a and the fourth PMOS gate electrode 121p2b and the first PMOS gate electrode 139p2a and the second PMOS gate electrode 139p2b as PMOS gate electrodes may be provided. For example, the first PMOS transistor P_TRa' may include the first PMOS gate electrode 139p2a and the third PMOS gate electrode 121p2a to which the same bias is applied so as to function as PMOS gate electrodes on both sides of the first PMOS vertical active pattern 109p2a.

[0146] In the following description, reference will be made to Figure 2B Regions A' and B" in FIG. 1 describe an example of a semiconductor device according to an example embodiment. Regions A' and B" are enlarged views showing that a semiconductor device may be substituted for a semiconductor device. Figure 1A and Figure 1B The area "A" and the area "B".

[0147] Reference A' and area B', you can not set the reference Figure 1A and Figure 1B The cell back gate electrode 121m1 and the cell back gate dielectric layer BOc described above may not be provided. Figure 1A and Figure 1B The third NMOS gate electrode 121p1, the third NMOS gate dielectric layer BOn, the third PMOS gate electrode 121p2 and the third PMOS gate dielectric layer BOp are described.

[0148] In the following description, reference will be made to Figures 3A to 3F Example embodiments of various types of first peripheral circuit transistors or peripheral contact plugs included in the first peripheral circuit region PR_U are described above. Figures 3A to 3F In the example, region B1 may correspond to Figure 1B The area B1 in the figure and the area B2 may correspond to Figure 1B For example, in the area B2 Figures 3A to 3F In the example, the region B1 may be a region in which a peripheral NMOS transistor is provided, and the region B2 may be a region in which a peripheral PMOS transistor is provided. Figures 3A to 3F In, with Figure 1B The same reference numerals may indicate Figure 1B Components of the same form as described in . Figures 3A to 3F In the Figure 1B The components in the Figure 1B Components that have been replaced by components in .

[0149] In the example, refer to Figure 3A , can be set with a ratio of word line ( Figure 1B The peripheral NMOS gate electrode 139p11 has a vertical length H2 smaller than the vertical length H1 of the word line (139m1). Figure 1B The peripheral PMOS gate electrode 139p21 has a vertical length H2 smaller than the vertical length H1 of the word line (139m1). Figure 1B The third NMOS gate electrode 121p11 has a vertical length H2 smaller than the vertical length H1 of the word line (139m1). Figure 1B The third PMOS gate electrode 121p21 has a vertical length H2 that is smaller than the vertical length H1 of the third PMOS gate electrode 121p21 (139m1).

[0150] A second peripheral NMOS transistor N_TRb may be provided, with Figure 1B The second peripheral NMOS transistor N_TRb includes a peripheral NMOS gate electrode 139p11 having a smaller vertical length than the first peripheral NMOS transistor N_TRa. A second peripheral PMOS transistor P_TRb may be provided. Figure 1B Compared to the first peripheral PMOS transistor P_TRa in FIG. 1 , the second peripheral PMOS transistor P_TRb includes a peripheral PMOS gate electrode 139p21 having a reduced vertical length.

[0151] In the example, refer to Figure 3B , can be set with a ratio of word line ( Figure 1B The peripheral NMOS gate electrode 139p12 has a vertical length H3 greater than the vertical length H1 of the word line (139m1). Figure 1B The peripheral PMOS gate electrode 139p22 has a vertical length H3 greater than the vertical length H1 of the word line (139m1). Figure 1BThe third NMOS gate electrode 121p12 has a vertical length H3 greater than the vertical length H1 of the word line (139m1). Figure 1B The third PMOS gate electrode 121p22 has a vertical length H3 greater than the vertical length H1 of 139m1 in FIG.

[0152] A third peripheral NMOS transistor N_TRc may be provided, with Figure 1B The third peripheral NMOS transistor N_TRc includes a peripheral NMOS gate electrode 139p12 having a larger vertical length than the first peripheral NMOS transistor N_TRa. A third peripheral PMOS transistor P_TRc may be provided. Figure 1B Compared with the first peripheral PMOS transistor P_TRa in FIG. 1 , the third peripheral PMOS transistor P_TRc includes a peripheral PMOS gate electrode 139p22 having a larger vertical length.

[0153] In the example, refer to Figure 3C , you can set the thickness ratio Figure 1B The NMOS gate dielectric layer in Figure 1B The thickness of the NMOS gate dielectric layer FOna is smaller than that of FOn. Figure 2A The PMOS gate dielectric layer in Figure 1B The thickness of the PMOS gate dielectric layer FOpa is small (FOp in ).

[0154] A fourth peripheral NMOS transistor N_TRd may be provided, with Figure 1B The fourth peripheral NMOS transistor N_TRd includes a NMOS gate dielectric layer FOna of smaller thickness than the first peripheral NMOS transistor N_TRa. A fourth peripheral PMOS transistor P_TRd may be provided. Figure 1B Compared with the first peripheral PMOS transistor P_TRa in FIG. 1 , the fourth peripheral PMOS transistor P_TRd includes a PMOS gate dielectric layer FOpa with a smaller thickness.

[0155] In the example, refer to Figure 3D , you can set the thickness ratio Figure 1B The NMOS gate dielectric layer in Figure 1B The thickness of the NMOS gate dielectric layer FOnb is larger than FOn in the figure. Figure 1B The PMOS gate dielectric layer in Figure 1B The thickness of the PMOS gate dielectric layer FOpb is large.

[0156] A fifth peripheral NMOS transistor N_TRe may be provided, with Figure 1BThe fifth peripheral NMOS transistor N_TRe includes a larger thickness of the NMOS gate dielectric layer FOnb than the first peripheral NMOS transistor N_TRa in FIG. A fifth peripheral PMOS transistor P_TRe may be provided. Figure 1B Compared with the first peripheral PMOS transistor P_TRa in FIG. 1 , the fifth peripheral PMOS transistor P_TRe includes a PMOS gate dielectric layer FOpb with a larger thickness.

[0157] In the example, refer to Figure 3E , the additional NMOS source / drain region 188p1 can be arranged as follows Figure 1B The additional PMOS source / drain region 188p2 may be provided on the upper NMOS source / drain region 187p1 as shown. Figure 1B On the upper PMOS source / drain region 187p2 shown.

[0158] The additional NMOS source / drain region 188p1 may have an upper surface in contact with a lower surface of the peripheral NMOS contact structure 154p1. The additional PMOS source / drain region 188p2 may have an upper surface in contact with a lower surface of the peripheral PMOS contact structure 154p2.

[0159] The additional NMOS source / drain region 188p1 may be formed of silicon having N-type conductivity, and the additional PMOS source / drain region 188p2 may be formed of silicon having P-type conductivity. The additional NMOS source / drain region 188p1 may be formed of polycrystalline silicon having N-type conductivity or epitaxial silicon having N-type conductivity. The additional PMOS source / drain region 188p2 may be formed of polycrystalline silicon having P-type conductivity or epitaxial silicon having P-type conductivity.

[0160] A sixth peripheral NMOS transistor N_TRf including an additional NMOS source / drain region 188p1 may be provided instead of the Figure 1B A sixth peripheral PMOS transistor P_TRf including an additional PMOS source / drain region 188p2 may be provided instead of the first peripheral NMOS transistor N_TRa shown. Figure 1B The first peripheral PMOS transistor P_TRa is shown.

[0161] In the example, refer to Figure 3F , Figure 3E The illustrated additional NMOS source / drain region 188 p 1 may be replaced with a merged NMOS source / drain region 188 p 1 a connected to the NMOS vertical active patterns 109 p 1 adjacent to each other. Figure 3E The illustrated additional PMOS source / drain region 188p2 may be replaced with a merged PMOS source / drain region 188p2a connected to the PMOS vertical active patterns 109p2 adjacent to each other.

[0162] The merged NMOS source / drain region 188p1a may vertically overlap the third NMOS gate electrode 121p1. The merged PMOS source / drain region 188p2a may vertically overlap the third PMOS gate electrode 121p2.

[0163] Merged NMOS source / drain region 188p1a may be formed of silicon having N-type conductivity, and merged PMOS source / drain region 188p2a may be formed of silicon having P-type conductivity. Merged NMOS source / drain region 188p1a may be formed of polycrystalline silicon having N-type conductivity or epitaxial silicon having N-type conductivity. Merged PMOS source / drain region 188p2a may be formed of polycrystalline silicon having P-type conductivity or epitaxial silicon having P-type conductivity.

[0164] Instead of the seventh peripheral NMOS transistor N_TRg further including the merged NMOS source / drain region 188p1a, a seventh peripheral NMOS transistor N_TRg may be provided. Figure 1B A seventh peripheral PMOS transistor P_TRg may be provided that further includes a merged PMOS source / drain region 188p2a, instead of the first peripheral NMOS transistor N_TRa shown. Figure 1B The first peripheral PMOS transistor P_TRa is shown.

[0165] In the above Figures 1A to 3F In the embodiment, the first peripheral circuit region PR_U may include at least one of the first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, and N_TRg, and may include at least one of the first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf, and P_TRg. Accordingly, the first peripheral circuit region PR_U may form various peripheral circuits using the first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, and N_TRg, and the first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf, and P_TRg.

[0166] In the following description, reference will be made to Figures 4A to 4DExample embodiments of various circuits are described having a cross-sectional structure using the first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, N_TRg, the first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf and P_TRg, the third peripheral NMOS gate electrode 121p1 and the third peripheral PMOS gate electrode 121p2 in the first peripheral circuit region PR_U. Figures 4A to 4D are enlarged views illustrating various examples included in a circuit in a semiconductor device according to example embodiments.

[0167] In the example, refer to Figure 4A The first NMOS vertical active pattern nACT1 and the second NMOS vertical active pattern nACT2 may be disposed adjacent to each other. The first NMOS vertical active pattern nACT1 may include a first lower NMOS source / drain region nSD_L1, a first upper NMOS source / drain region nSD_U1 on the first lower NMOS source / drain region nSD_L1, and a first NMOS channel region nCH_1 between the first lower NMOS source / drain region nSD_L1 and the first upper NMOS source / drain region nSD_U1. The second NMOS vertical active pattern nACT2 may include a second lower NMOS source / drain region nSD_L2, a second upper NMOS source / drain region nSD_U2 on the second lower NMOS source / drain region nSD_L2, and a second NMOS channel region nCH_2 between the second lower NMOS source / drain region nSD_L2 and the second upper NMOS source / drain region nSD_U2.

[0168] The first NMOS vertical active pattern nACT1 and the second NMOS vertical active pattern nACT2 may be connected to Figure 1B The NMOS vertical active pattern 109p1 shown in FIG. 1 is substantially the same.

[0169] The NMOS gate electrode nFG may be disposed between the first NMOS channel region nCH_1 of the first NMOS vertical active pattern nACT1 and the second NMOS channel region nCH_2 of the second NMOS vertical active pattern nACT2 .

[0170] A first NMOS gate dielectric layer nFOx1 may be disposed between the first NMOS vertical active pattern nACT1 and the NMOS gate electrode nFG, and a second NMOS gate dielectric layer nFOx2 may be disposed between the second NMOS vertical active pattern nACT2 and the NMOS gate electrode nFG.

[0171] The first NMOS back-gate electrode nBG1 and the second NMOS back-gate electrode nBG2 may be disposed opposite to each other. The first NMOS channel region nCH_1, the NMOS gate electrode nFG, and the second NMOS channel region nCH_2 may be disposed between the first NMOS back-gate electrode nBG1 and the second NMOS back-gate electrode nBG2.

[0172] A first NMOS back gate dielectric layer nBOx1 may be disposed between the first NMOS back gate electrode nBG1 and the first NMOS vertical active pattern nACT1 , and a second NMOS back gate dielectric layer nBOx2 may be disposed between the second NMOS back gate electrode nBG2 and the second NMOS vertical active pattern nACT2 .

[0173] In the example, refer to Figure 4B The first PMOS vertical active pattern pACT1 and the second PMOS vertical active pattern pACT2 may be disposed adjacent to each other. The first PMOS vertical active pattern pACT1 may include a first lower PMOS source / drain region pSD_L1, a first upper PMOS source / drain region pSD_U1 on the first lower PMOS source / drain region pSD_L1, and a first PMOS channel region pCH_1 between the first lower PMOS source / drain region pSD_L1 and the first upper PMOS source / drain region pSD_U1. The second PMOS vertical active pattern pACT2 may include a second lower PMOS source / drain region pSD_L2, a second upper PMOS source / drain region pSD_U2 on the second lower PMOS source / drain region pSD_L2, and a second PMOS channel region pCH_2 between the second lower PMOS source / drain region pSD_L2 and the second upper PMOS source / drain region pSD_U2.

[0174] The first PMOS vertical active pattern pACT1 and the second PMOS vertical active pattern pACT2 may be connected to Figure 1B The PMOS vertical active pattern 109p2 shown in FIG. 1 is substantially the same.

[0175] The PMOS gate electrode pFG may be disposed between the first PMOS channel region pCH_1 of the first PMOS vertical active pattern pACT1 and the second PMOS channel region pCH_2 of the second PMOS vertical active pattern pACT2 .

[0176] A first PMOS gate dielectric layer pFOx1 may be disposed between the first PMOS vertical active pattern pACT1 and the PMOS gate electrode pFG, and a second PMOS gate dielectric layer pFOx2 may be disposed between the second PMOS vertical active pattern pACT2 and the PMOS gate electrode pFG.

[0177] The first PMOS back-gate electrode pBG1 and the second PMOS back-gate electrode pBG2 may be disposed opposite to each other. The first PMOS channel region pCH_1 , the PMOS gate electrode pFG, and the second PMOS channel region pCH_2 may be disposed between the first PMOS back-gate electrode pBG1 and the second PMOS back-gate electrode pBG2 .

[0178] A first PMOS back gate dielectric layer pBOx1 may be disposed between the first PMOS back gate electrode pBG1 and the first PMOS vertical active pattern pACT1 , and a second PMOS back gate dielectric layer pBOx2 may be disposed between the second PMOS back gate electrode pBG2 and the second PMOS vertical active pattern pACT2 .

[0179] In the example, refer to Figure 4C The NMOS vertical active pattern nACT and the PMOS vertical active pattern pACT may be disposed adjacent to each other. The NMOS vertical active pattern nACT may include a lower NMOS source / drain region nSD_L, an upper NMOS source / drain region nSD_U above the lower NMOS source / drain region nSD_L, and an NMOS channel region nCH between the lower NMOS source / drain region nSD_L and the upper NMOS source / drain region nSD_U. The PMOS vertical active pattern pACT may include a lower PMOS source / drain region pSD_L, an upper PMOS source / drain region pSD_U above the lower PMOS source / drain region pSD_L, and a PMOS channel region pCH between the lower PMOS source / drain region pSD_L and the upper PMOS source / drain region pSD_U.

[0180] The shared back gate electrode BG may be disposed between the NMOS channel region nCH of the NMOS vertical active pattern nACT and the PMOS channel region pCH of the PMOS vertical active pattern pACT.

[0181] An NMOS back gate dielectric layer nBOx may be disposed between the NMOS vertical active pattern nACT and the shared back gate electrode BG, and a PMOS back gate dielectric layer pBOx may be disposed between the PMOS vertical active pattern pACT and the shared back gate electrode BG.

[0182] The NMOS gate electrode nFG and the PMOS gate electrode pFG may be disposed opposite to each other, and the NMOS channel region nCH, the shared back gate electrode BG, and the PMOS channel region pCH may be disposed between the NMOS gate electrode nFG and the PMOS gate electrode pFG.

[0183] An NMOS gate dielectric layer nFOx may be disposed between the NMOS gate electrode nFG and the NMOS vertical active pattern nACT, and a PMOS gate dielectric layer pFOx may be disposed between the PMOS gate electrode pFG and the PMOS vertical active pattern pACT.

[0184] In the example, refer to Figure 4D , the NMOS vertical active pattern nACT and the PMOS vertical active pattern pACT may be set as follows Figure 4C Shown adjacent to each other.

[0185] The shared gate electrode FG may be disposed between the NMOS channel region nCH of the NMOS vertical active pattern nACT and the PMOS channel region pCH of the PMOS vertical active pattern pACT.

[0186] An NMOS gate dielectric layer nFOx may be disposed between the NMOS vertical active pattern nACT and the shared gate electrode FG, and a PMOS gate dielectric layer pFOx may be disposed between the PMOS vertical active pattern pACT and the shared gate electrode FG.

[0187] The NMOS back gate electrode nBG and the PMOS back gate electrode pBG may be disposed opposite to each other, and the NMOS channel region nCH, the shared gate electrode FG, and the PMOS channel region pCH may be disposed between the NMOS back gate electrode nBG and the PMOS back gate electrode pBG.

[0188] An NMOS back gate dielectric layer nBOx may be disposed between the NMOS back gate electrode nBG and the NMOS vertical active pattern nACT, and a PMOS back gate dielectric layer pBOx may be disposed between the PMOS back gate electrode pBG and the PMOS vertical active pattern pACT.

[0189] In the following description, reference will be made to Figure 5A and Figure 5B Example embodiments of planar shapes of various circuits that can be formed using the first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, and N_TRg, the first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf, and P_TRg, the third peripheral NMOS gate electrode 121p1, and the third peripheral PMOS gate electrode 121p2 in the first peripheral circuit region PR_U are described. Figure 5A and Figure 5B are plan views illustrating various examples included in a circuit in a semiconductor device according to example embodiments.

[0190] In the example, refer to Figure 5A , the first NMOS vertical active pattern nACT1 and the second NMOS vertical active pattern nACT2 may be disposed adjacent to each other in the second horizontal direction Y.

[0191] The plurality of first NMOS vertical active patterns nACT1 may be sequentially arranged in the first horizontal direction X. The plurality of second NMOS vertical active patterns nACT2 may be sequentially arranged in the first horizontal direction.

[0192] The first NMOS vertical active pattern nACT1 and the second NMOS vertical active pattern nACT2 may be connected to Figure 1B The NMOS vertical active patterns 109p1 in FIG. 1 are substantially the same.

[0193] The back gate electrode nBG may be disposed between the first NMOS vertical active pattern nACT1 and the second NMOS vertical active pattern nACT2. Figure 1B The third peripheral NMOS gate electrode 121p1 in is substantially the same.

[0194] The first and second NMOS gate electrodes nFG1 and nFG2 may be disposed opposite each other. The first and second NMOS vertical active patterns nACT1 and nACT2 and the back gate electrode nBG may be disposed between the first and second NMOS gate electrodes nFG1 and nFG2.

[0195] The routing wiring structure nCNT can be electrically connected to each of the back gate electrode nBG, the first NMOS gate electrode nFG1, and the second NMOS gate electrode nFG2. The routing wiring structure nCNT can operate the back gate electrode nBG, the first NMOS gate electrode nFG1, and the second NMOS gate electrode nFG2 as gate electrodes. Accordingly, an NMOS transistor can be provided that uses the back gate electrode nBG, the first NMOS gate electrode nFG1, and the second NMOS gate electrode nFG2 as gate electrodes.

[0196] In the example, refer to Figure 5B , the first PMOS vertical active pattern pACT1 and the second PMOS vertical active pattern pACT2 may be disposed adjacent to each other in the second horizontal direction Y.

[0197] The plurality of first PMOS vertical active patterns pACT1 may be sequentially arranged in the first horizontal direction X. The plurality of second PMOS vertical active patterns pACT2 may be sequentially arranged in the first horizontal direction X.

[0198] The first PMOS vertical active pattern pACT1 and the second PMOS vertical active pattern pACT2 may be connected to Figure 1B The PMOS vertical active patterns 109p1 in FIG. 1 are substantially the same.

[0199] The back gate electrode pBG may be disposed between the first PMOS vertical active pattern pACT1 and the second PMOS vertical active pattern pACT2. Figure 1B The third peripheral PMOS gate electrode 121p2 in is substantially the same.

[0200] The first and second PMOS gate electrodes pFG1 and pFG2 may be disposed opposite each other. The first and second PMOS vertical active patterns pACT1 and pACT2 and the back gate electrode pBG may be disposed between the first and second PMOS gate electrodes pFG1 and pFG2.

[0201] The routing wiring structure pCNT can be electrically connected to each of the back gate electrode pBG, the first PMOS gate electrode pFG1, and the second PMOS gate electrode pFG2. The routing wiring structure pCNT can operate the back gate electrode pBG, the first PMOS gate electrode pFG1, and the second PMOS gate electrode pFG2 as gate electrodes. Accordingly, a PMOS transistor using the back gate electrode pBG, the first PMOS gate electrode pFG1, and the second PMOS gate electrode pFG2 as gate electrodes can be provided.

[0202] In the following description, reference will be made to Figure 6A and Figure 6B An example embodiment of an inverter formed using first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, and N_TRg, first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf, and P_TRg, a third peripheral NMOS gate electrode 121p1, and a third peripheral PMOS gate electrode 121p2 in the first peripheral circuit region PR_U is described. Figure 6A is a plan view illustrating an example embodiment of an inverter in a semiconductor device according to an example embodiment, and Figure 6B is shown along Figure 6A The line I-I' in the Figure 1B A cross-sectional view of the area corresponding to area "B" in FIG.

[0203] In the example, refer to Figure 6A and Figure 6B, the inverter INT may be configured using at least one of the first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, and N_TRg in the above-mentioned first peripheral circuit region PR_U, at least one of the first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf, and P_TRg, the third peripheral NMOS gate electrode 121p1, and the third peripheral PMOS gate electrode 121p2. For example, the inverter INT may include a reference Figure 1A and Figure 1B The first peripheral NMOS transistor N_TRa and the first peripheral PMOS transistor P_TRa, and the third NMOS peripheral gate electrode 121p1 and the third peripheral PMOS gate electrode 121p2 are described.

[0204] The inverter INT may include first and second NMOS vertical active patterns 109p1a and 109p1b adjacent to each other in the second horizontal direction Y, and first and second PMOS vertical active patterns 109p2a and 109p2b adjacent to each other in the second horizontal direction Y.

[0205] A plurality of first NMOS vertical active patterns 109p1a may be arranged in the first horizontal direction X and spaced apart from each other. A plurality of second NMOS vertical active patterns 109p1b may be arranged in the first horizontal direction X and spaced apart from each other.

[0206] A plurality of first PMOS vertical active patterns 109p2a may be arranged in the first horizontal direction X and spaced apart from each other. A plurality of second PMOS vertical active patterns 109p2b may be arranged in the first horizontal direction X and spaced apart from each other.

[0207] Inverter INT can include reference Figure 1B The first lower peripheral wiring 190p1 and the second lower peripheral wiring 190p2 are described. Figure 1B The first lower peripheral wiring 190p1 described may be connected to the lower surface of the first NMOS vertical active pattern 109p1a, and refer to Figure 1B The depicted second lower peripheral wiring 190 p 2 may be connected to a lower surface of the first PMOS vertical active pattern 109 p 2 a .

[0208] The inverter INT may further include a gate contact structure G_C, which will be referred to as Figure 1BThe first NMOS gate electrode 139p1a, the second NMOS gate electrode 139p1b, the first PMOS gate electrode 139p2a, and the second PMOS gate electrode 139p2b are electrically connected to each other.

[0209] The inverter INT may further include an NMOS back gate contact structure n_BC electrically connected to the third NMOS gate electrode 121 p 1 , and a PMOS back gate contact structure p_BC electrically connected to the third PMOS gate electrode 121 p 2 .

[0210] Inverter INT can include reference Figure 1B The NMOS contact plug 154p1 is connected to the upper surface of the first NMOS vertical active pattern 109p1a, and the PMOS contact plug 154p2 is connected to the upper surface of the first PMOS vertical active pattern 109p2a.

[0211] The inverter INT may include a common upper wiring 160pba disposed on and electrically connected to the NMOS contact plug 154p1 and the PMOS contact plug 154p2. The common upper wiring 160pba may be electrically connected to the upper NMOS source / drain region 187p1 of the first NMOS vertical active pattern 109p1a and the upper PMOS source / drain region 187p2 of the first PMOS vertical active pattern 109p2a through the NMOS contact plug 154p1 and the PMOS contact plug 154p2.

[0212] Using the first peripheral NMOS transistor N_TRa and the first peripheral PMOS transistor P_TRa, by applying a negative bias to the third NMOS gate electrode 121p1 and a positive bias to the third PMOS gate electrode 121p2, the performance of the inverter INT can be improved during operation of the inverter INT. The third NMOS gate electrode 121p1 can be configured as an NMOS back gate electrode, and the third PMOS gate electrode 121p2 can be configured as a PMOS back gate electrode.

[0213] In the following description, reference will be made to Figure 7 right Figure 1B An embodiment of the second insulation structure INS, the cell gate dielectric layer FOc, the cell back gate dielectric layer BOc, the NMOS gate dielectric layer FOn, the PMOS gate dielectric layer FOp, the third NMOS gate dielectric layer BOn and the third PMOS gate dielectric layer BOp is described. Figure 7 is shown with Figure 1A and Figure 1B An enlarged cross-sectional view of the region corresponding to region "A" and region "B".

[0214] In the example, refer to Figure 7 The second insulating structure INS may include an upper gate capping insulating layer 145 , an upper back gate capping insulating layer 189 , a buffer insulating layer 133 , and a gap-filling insulating layer 142 .

[0215] The upper gate capping insulating layer 145 may be provided at a reference Figure 1B The upper back gate capping insulating layer 189 may be provided on the upper surface of the word line 139m1 and the peripheral gate electrodes 139p1 and 139p2. Figure 1B 1 and 12. A buffer insulating layer 133 may be disposed on the upper surfaces of the bit lines 190m1 and 190m2, the lower peripheral wirings 190p1 and 190p2, and the first insulating structure 198. A gap-fill insulating layer 142 may be disposed between adjacent word lines 139m1 without interposing the cell vertical active pattern 109m1 therebetween, and may be disposed between adjacent peripheral gate electrodes 139p1 and 139p2 without interposing the peripheral vertical active pattern 109p1 and 109p2 therebetween.

[0216] refer to Figure 1B The described cell gate dielectric layer FOc can extend from a portion set between the cell vertical active pattern 109m1 and the word line 139m1 to an area between the cell vertical active pattern 109m1 and the upper gate capping insulating layer 145, between the lower surface of the word line 139m1 and the buffer insulating layer 133, and between the lower surface of the gap-fill insulating layer 142 and the buffer insulating layer 133.

[0217] refer to Figure 1B The depicted cell back gate dielectric layer BOc may extend from a portion disposed between the cell vertical active pattern 109m1 and the cell back gate electrode 121m1 to an area between the cell vertical active pattern 109m1 and the upper back gate capping insulating layer 189 and between a lower surface of the cell back gate electrode 121m1 and the buffer insulating layer 133 .

[0218] refer to Figure 1B The described NMOS gate dielectric layer FOn and PMOS gate dielectric layer FOp can extend from the portion arranged between the peripheral vertical active patterns 109p1 and 109p2 and the peripheral gate electrodes 139p1 and 139p2 to the area between the peripheral vertical active patterns 109p1 and 109p2 and the upper gate capping insulating layer 145, between the lower surface of the peripheral vertical active patterns 109p1 and 109p2 and the buffer insulating layer 133, and between the lower surface of the gap-filling insulating layer 142 and the buffer insulating layer 133.

[0219] refer to Figure 1B The described third gate dielectric layers BOn and BOp may extend from a portion disposed between the peripheral vertical active patterns 109p1 and 109p2 and the third peripheral gate electrodes 121p1 and 121p2 to an area between the peripheral vertical active patterns 109p1 and 109p2 and the upper back gate capping insulating layer 189, and between the lower surface of the third peripheral gate electrodes 121p1 and 121p2 and the buffer insulating layer 133.

[0220] In the following description, reference will be made to Figures 8A to 8F Example embodiments are described of planar shapes of various circuits configured using the first to seventh peripheral NMOS transistors N_TRa, N_TRb, N_TRc, N_TRd, N_TRe, N_TRf, and N_TRg, the first to seventh peripheral PMOS transistors P_TRa, P_TRb, P_TRc, P_TRd, P_TRe, P_TRf, and P_TRg, and the third peripheral NMOS gate electrode 121p1 and the third peripheral PMOS gate electrode 121p2 in the first peripheral circuit region PR_U. Figures 8A to 8F are plan views illustrating various examples of configuring circuits in a semiconductor device according to example embodiments.

[0221] In the example, refer to Figure 8A , the peripheral vertical active patterns ACT may be arranged in a first horizontal direction X and a second horizontal direction Y that are perpendicular to each other. Each peripheral vertical active pattern ACT may have a stripe shape extending in the first horizontal direction X.

[0222] The peripheral vertical active pattern ACT may be a reference Figure 1A and Figure 1B The NMOS vertical active pattern 109p1 described or reference Figure 1A and Figure 1B A PMOS vertical active pattern 109p2 is depicted.

[0223] In the following description, it will be described that the peripheral vertical active pattern ACT is Figure 1A and Figure 1B An example of the NMOS vertical active pattern 109p1 described in .

[0224] The peripheral gate electrode GE may correspond to the reference Figure 1A and Figure 1B For example, the third peripheral gate electrode BG (which may correspond to the back gate electrode) may correspond to the reference Figure 1A and Figure 1B The third peripheral gate electrode 121p1 is described.

[0225] Each of the third peripheral gate electrodes BG may extend in the first horizontal direction X. The third peripheral gate electrodes BG may be parallel to each other.

[0226] A pair of the peripheral gate electrodes GE among the peripheral gate electrodes GE may be disposed between a pair of third peripheral gate electrodes BG adjacent to each other.

[0227] The lower peripheral wiring 190_A may correspond to the reference Figure 1A and Figure 1B The first lower peripheral wiring 190p1 is described. Each of the lower peripheral wirings 190_A may have a linear shape extending in the second horizontal direction Y. The lower peripheral wirings 190_A may be parallel to each other.

[0228] The peripheral contact structure 154_A may correspond to the reference Figure 1A and Figure 1B The first peripheral contact structure 154p1 is described. The peripheral contact structures 154_A may be connected to the peripheral vertical active patterns ACT, respectively. For example, the peripheral contact structures 154_A may be connected to the peripheral vertical active patterns ACT.

[0229] In another example, reference Figure 8B ,refer to Figure 8A The described peripheral contact structure 154_A may be modified as follows Figure 8B The peripheral contact structures 154_B in the embodiment of the present invention may be connected to the plurality of peripheral vertical active patterns ACT. For example, the peripheral contact structures 154_B may be connected to the plurality of peripheral vertical active patterns ACT, respectively. In other words, the peripheral contact structures 154_B may be connected to the plurality of peripheral vertical active patterns ACT. The peripheral contact structures 154_B may be spaced apart from each other. Each peripheral contact structure 154_B may have a circular or quadrilateral shape.

[0230] In another example, reference Figure 8C ,refer to Figure 8A The described peripheral contact structure 154_A may be modified as follows Figure 8C For example, each peripheral contact structure 154_C may have a linear shape extending in the second horizontal direction Y and may be connected to the peripheral vertical active pattern ACT. The peripheral contact structure 154_C may vertically overlap the lower peripheral wiring 190_A.

[0231] In another example, reference Figure 8D ,refer to Figure 8A The described peripheral contact structure 154_A may be modified as follows Figure 8DFor example, each peripheral contact structure 154_D may have a linear shape extending in the first horizontal direction X and may be connected to the peripheral vertical active pattern ACT. The peripheral contact structure 154_D may have a linear shape extending in a direction intersecting the lower peripheral wiring 190_A.

[0232] In another example, reference Figure 8E , Figures 8A to 8D The lower peripheral wiring 190_A in the embodiment may be modified as follows Figure 8E The lower peripheral wiring 190_B in.

[0233] The lower peripheral wiring 190_B may be configured as a conductive plate connected to the entire peripheral vertical active pattern ACT.

[0234] In another example, reference Figure 8F , Figures 8A to 8D The lower peripheral wiring 190_A in the embodiment may be modified as follows Figure 8F The lower peripheral wiring 190_C in.

[0235] Each of the lower peripheral wirings 190_C may extend in the first horizontal direction X and may be connected to the peripheral vertical active pattern ACT. The lower peripheral wirings 190_C may be parallel to each other.

[0236] In the following description, reference will be made to Figure 9A Description Reference Figure 1A and Figure 1B An example of the upper peripheral wirings 160 pa and 160 pb of the first peripheral circuit region PR_U is described. Figure 9A It can be shown as Figure 1A An example of the upper peripheral wirings 160 pa and 160 pb of the first peripheral circuit region PR_U in the cross-sectional structure shown.

[0237] refer to Figure 9A ,refer to Figure 1A and Figure 1B The upper peripheral wirings 160pa and 160pb described above may be replaced by a peripheral pad pattern 160p disposed at the same level as the cell pad pattern 160m1. Figure 1A and Figure 1BUpper peripheral wirings 169pa and 169pb having substantially the same shape as the upper peripheral wirings 160pa and 160pb described above may be provided on the peripheral pad pattern 160p. A portion of the lower region of the second electrode 169 may be provided at the same level as the upper peripheral wirings 169pa and 169pb. For example, the lower surfaces of the upper peripheral wirings 169pa and 169pb may be provided at a level lower than the level of the second electrode 169, and the upper surfaces of the upper peripheral wirings 169pa and 169pb may be provided at a level higher than the lower surface of the second electrode 169 and lower than the upper surface of the second electrode 169. The upper peripheral wirings 169pa and 169pb may be provided at the same level as a portion of the second electrode 169. The upper peripheral wirings 169pa and 169pb may be formed of the same conductive material as the conductive material of the second electrode 169.

[0238] In the following description, reference will be made to Figure 9B Examples of semiconductor devices according to example embodiments are described. Figure 9B is a cross-sectional view illustrating an example of a semiconductor device according to example embodiments.

[0239] refer to Figure 9B , you can Figure 1A The structure including the first structure CH1 and the second structure CH2 is arranged upside down. For example, the second structure CH2 can be arranged on the first structure CH1.

[0240] The first structure CH1 may further include a routing structure 179m electrically connecting the on-cell wiring 184m to the first bonding pad 35 and the second bonding pad 196 between the on-cell wiring 184m and the second structure CH2. In the first structure CH1, the bit lines 190m1 and 190m2 may be closer to the second structure CH2 than the data storage structures DS1 and DS2.

[0241] The second structure CH2 may further include a back-side insulating layer 50 on the substrate 5, a through-electrode 60 penetrating the back-side insulating layer 50 and the substrate 5 and electrically connected to the second routing wiring structure 30, an insulating spacer 55 on a side surface of the through-electrode 60, and a conductive pad 70 on the back-side insulating layer 50 connected to the through-electrode 60.

[0242] In the following description, reference will be made to Figure 10 Examples of semiconductor devices according to example embodiments are described. Figure 10 is a cross-sectional view illustrating an example of a semiconductor device according to example embodiments.

[0243] refer to Figure 10 ,refer to Figure 1A and Figure 1BThe first structure CH1 described as having the first and second memory regions MR1 ​​and MR2 and the first peripheral circuit region PR_U may be modified as follows. Figure 10 The first structure CH1a shown has a first memory region MR1, a second memory region MR2, and a first peripheral circuit region PR_U. Figure 1A and Figure 1B The second structure CH2 having the first and second core circuit regions CR1 and CR2 and the second peripheral circuit region PR_L described in the preceding text may be modified as follows: Figure 10 The second structure CH2a shown has a first core circuit region CR1, a second core circuit region CR2 and a second peripheral circuit region PR_L. The second structure CH2a can be provided on the first structure CH1a. Figure 10 shown.

[0244] The first structure CH1a can be Figure 1A The first structure in Figure 1A The CH1 in FIG is substantially the same, wherein the first bonding pad ( Figure 1A 196 of ). Accordingly, Figure 1A The first insulating structure 198 in FIG. 1 may be bonded to the second structure CH2 a .

[0245] The second structure CH2a may include a substrate 205 and a device isolation region 210 defining an active region 210a on the substrate 205. The substrate 205 may be configured as a semiconductor substrate.

[0246] The first structure CH1 may further include a routing structure 179m electrically connecting the upper cell wiring 184m to a second routing wiring structure 192 between the upper cell wiring 184m and the second structure CH2. In the first structure CH1, the bit lines 190m1 and 190m2 may be closer to the second structure CH2 than the data storage structures DS1 and DS2.

[0247] The second structure CH2a may include lower peripheral circuit transistors 225a, 225b, 225c arranged on the substrate 205, a second routing wiring structure 230 electrically connected to the lower peripheral circuit transistors 225a, 225b, 225c on the lower peripheral circuit transistors 225a, 225b, 225c, and a lower insulating structure 240 on the substrate 205 covering the lower peripheral circuit transistors 225a, 225b, 225c and the second routing wiring structure 230.

[0248] The lower peripheral circuit transistors 225a, 225b, 225c may include peripheral gate structures 215a, 215b and peripheral source / drain regions 220sd, respectively. The peripheral gate structures 215a and 215b may include a peripheral gate dielectric layer 215a and a peripheral gate electrode 215b.

[0249] The lower peripheral circuit transistors 225a, 225b, and 225c may include a first core circuit transistor 225a in the first core circuit region CR1, a second core circuit transistor 225b in the second core circuit region CR2, and a second peripheral circuit transistor 225c in the second peripheral circuit region PR_L.

[0250] The first core circuit region CR1 may include a first core circuit transistor 225a. The second core circuit region CR2 may include a second core circuit transistor 225b. The first core circuit transistor 225a may vertically overlap the first data storage structure DS1, and the second core circuit transistor 225b may vertically overlap the second data storage structure DS2.

[0251] The second structure CH2a may be disposed under the substrate 205 and may further include a back insulating layer 250 bonded to the first insulating structure 198. A lower surface of the back insulating layer 250 and an upper surface of the first insulating structure 198 may be bonded to form a bonding surface JSa between the first and second structures CH1a and CH2a.

[0252] The second structure CH2a may include through-electrodes 260a, 260b, 260c, and insulating spacers 265 surrounding side surfaces of each of the through-electrodes 260a, 260b, and 260c. The through-electrodes 260a, 260b, 260c may penetrate the substrate 5, extend upward, and be connected to the second routing wiring structure 230, and may penetrate the substrate 5 and the insulating layer 250, extend downward, and be connected to the first routing wiring structure 192 in the first structure CH1a.

[0253] Upper surfaces of the through-electrodes 260 a , 260 b , and 260 c may be connected to the second routing wiring structure 230 , and lower surfaces of the through-electrodes 260 a , 260 b , and 260 c may be connected to the first routing wiring structure 192 .

[0254] The through-electrodes 260a, 260b and 260c may include a first through-electrode 260a electrically connecting the first core circuit transistor 225a to the first bit line 190m1, a second through-electrode 260b electrically connecting the second core circuit transistor 225b to the second bit line 190m2, and a third through-electrode 260c disposed in the first peripheral circuit region PR_L and the second peripheral circuit region PR_U.

[0255] The second structure CH2 a may further include a conductive pad 285 disposed on the lower insulating structure 240 and electrically connected to the second routing wiring structure 230 .

[0256] In the following description, reference will be made to Figure 11 Examples of semiconductor devices according to example embodiments are described. Figure 11 is a cross-sectional view illustrating an example of a semiconductor device according to example embodiments.

[0257] refer to Figure 11 ,refer to Figure 1A and Figure 1B The first structure CH1 described as having the first and second memory regions MR1 ​​and MR2 and the first peripheral circuit region PR_U may be modified as follows. Figure 11 The first structure CH1b shown in FIG. 1 has a first storage region MR1, a second storage region MR2, and a first peripheral circuit region PR_U. Figure 1A and Figure 1B The second structure CH2 having the first and second core circuit regions CR1 and CR2 and the second peripheral circuit region PR_L described in the preceding text may be modified as follows: Figure 11 The second structure CH2b shown in FIG. 1 has the first and second core circuit regions CR1 and CR2 and the second peripheral circuit region PR_L.

[0258] Compared with the first structure ( Figure 1A Unlike CH1 in FIG, the first structure CH1b may not be provided with a first bonding pad ( Figure 1A 196 in), a first routing wiring structure 192, a connecting contact plug 194, a cell upper wiring 184m and a third peripheral upper wiring 184p, and with the first structure ( Figure 1A Different from CH1 in FIG, it may further include an upper routing wiring structure 384 disposed in the upper insulating structure 181, and a first bonding pad 335 having an upper surface coplanar with an upper surface of the upper insulating structure 181 and electrically connected to the upper routing wiring structure 384.

[0259] and Figure 1A The first structure in Figure 1A Unlike CH1 in FIG. 1 , the first structure CH1 b may further include a connecting routing structure 394 connecting the first bit line 190 m 1 and the second bit line 190 m 2 to the upper routing wiring structure 384 .

[0260] Each connection routing structure 394 may include an upper plug 394c disposed at the same level as the peripheral contact plug 178p and connected to the upper routing wiring structure 384, an intermediate pad pattern 394b disposed at the same level as the cell pad pattern 160m, and a lower plug 394a disposed between the first and second bit lines 190m1 and 190m2 and the intermediate pad pattern 394b.

[0261] The second structure CH2b may be disposed on the first structure CH1b.

[0262] The second structure CH2b may include a substrate 405 and a device isolation region 410 defining an active region 410a under the substrate 405. The substrate 405 may be configured as a semiconductor substrate.

[0263] The second structure CH2b may include lower peripheral circuit transistors 425a, 425b, 425c arranged below the substrate 405, a second routing wiring structure 430 electrically connected to the lower peripheral circuit transistors 425a, 425b, 425c below the lower peripheral circuit transistors 425a, 425b, 425c, a lower insulating structure 440 covering the lower peripheral circuit transistors 425a, 425b, 425c, the second routing wiring structure 430 below the substrate 405, and a first bonding pad 435 having a lower surface coplanar with the lower surface of the lower insulating structure 440.

[0264] Each of the lower peripheral circuit transistors 425a, 425b, and 425c may include a peripheral gate structure 415a and 415b and a peripheral source / drain region 420sd. The peripheral gate structures 415a and 415b may include a peripheral gate dielectric layer 415a and a peripheral gate electrode 415b.

[0265] The lower peripheral circuit transistors 425a, 425b, and 425c may include a first core circuit transistor 425a in the first core circuit region CR1, a second core circuit transistor 425b in the second core circuit region CR2, and a second peripheral circuit transistor 425c in the second peripheral circuit region PR_L.

[0266] The first core circuit region CR1 may include a first core circuit transistor 425a. The second core circuit region CR2 may include a second core circuit transistor 425b. The first core circuit transistor 425a may vertically overlap the first data storage structure DS1, and the second core circuit transistor 425b may vertically overlap the second data storage structure DS2.

[0267] The lower surface of the lower insulating structure 440 of the second structure CH2b may be bonded to the upper surface of the upper insulating structure 181 of the first structure CH1b, and the lower surface of the second bonding pad 435 of the second structure CH2b may be bonded to the upper surface of the upper insulating structure 181 of the first structure CH1b. The second structure CH2b may be bonded to the upper surface of the first bonding pad 335 of the first structure CH1b, and the lower surface of the second bonding pad 435 may be bonded to the upper surface of the first bonding pad 335. Accordingly, a bonding surface JSc formed by bonding the upper surface of the first structure CH1b to the lower surface of the second structure CH2b may be formed.

[0268] The second structure CH2b may further include a back-side insulating layer 450 on the substrate 405, a through-electrode 460 penetrating the back-side insulating layer 450 and the substrate 405 and electrically connected to the second routing wiring structure 430, an insulating spacer 455 on a side surface of the through-electrode 460, and a conductive pad 470 on the back-side insulating layer 450 connected to the through-electrode 460.

[0269] In the following description, reference will be made to Figure 12 Examples of semiconductor devices according to example embodiments are described. Figure 12 is a cross-sectional view illustrating an example of a semiconductor device according to example embodiments.

[0270] refer to Figure 12 ,refer to Figure 11 The described first structure CH1b having the first and second memory regions MR1 ​​and MR2 and the first peripheral circuit region PR_U may be modified as follows. Figure 12 The first structure CH1c shown in FIG. 1 has the first and second memory regions MR1 ​​and MR2 and the first peripheral circuit region PR_U. Figure 11 The second structure CH2b having the first and second core circuit regions CR1 and CR2 and the second peripheral circuit region PR_L described in the above may be modified as follows. Figure 12 The second structure CH2c shown in FIG. 1 has the first and second core circuit regions CR1 and CR2 and the second peripheral circuit region PR_L.

[0271] The first structure CH1c can be Figure 11 The first structure in Figure 11 The CH1b in FIG is substantially the same, except that the first bonding pad ( Figure 11 335 in ). Accordingly, Figure 12 As shown, an upper surface of the upper insulating structure 181 may be bonded to a lower surface of the second structure CH2c.

[0272] The second structure CH2c may include a substrate 505 and a device isolation region 510 defining an active region 510a on the substrate 505. The substrate 505 may be configured as a semiconductor substrate.

[0273] The second structure CH2c may include lower peripheral circuit transistors 525a, 525b, 525c set on the substrate 505, a second routing wiring structure 530 electrically connected to the lower peripheral circuit transistors 525a, 525b, 525c on the lower peripheral circuit transistors 525a, 525b, 525c, a lower insulating structure 540 on the substrate 505 covering the lower peripheral circuit transistors 525a, 525b, 525c and the second routing wiring structure 530, and an insulating layer 550 set under the substrate 505.

[0274] A lower surface of the insulating layer 550 and an upper surface of the upper insulating structure 181 may be bonded to form a bonding surface JSd between the first structure CH1 c and the second structure CH2 c.

[0275] The lower peripheral circuit transistors 525a, 525b, and 525c may include peripheral gate structures 515a, 515b, and peripheral source / drain regions 520sd, respectively. The peripheral gate structures 515a and 515b may include a peripheral gate dielectric layer 515a and a peripheral gate electrode 515b.

[0276] The lower peripheral circuit transistors 525a, 525b, and 525c may include a first core circuit transistor 525a in the first core circuit region CR1, a second core circuit transistor 525b in the second core circuit region CR2, and a second peripheral circuit transistor 525c in the second peripheral circuit region PR_L.

[0277] The first core circuit region CR1 may include a first core circuit transistor 525a. The second core circuit region CR2 may include a second core circuit transistor 525b. The first core circuit transistor 525a may vertically overlap the first data storage structure DS1, and the second core circuit transistor 525b may vertically overlap the second data storage structure DS2.

[0278] The second structure CH2c may include through-electrodes 560a, 560b and 560c, and an insulating spacer 565 surrounding the side surface of each of the through-electrodes 560a, 560b and 560c. The through-electrodes 560a, 560b and 560c may penetrate the substrate 505, extend upward and be connected to the second routing wiring structure 530, and may penetrate the substrate 505 and the insulating layer 550, extend downward and be connected to the first routing wiring structure 384a in the first structure CH1c.

[0279] Upper surfaces of the through-electrodes 560 a , 560 b , and 560 c may be connected to the second routing wiring structure 530 , and lower surfaces of the through-electrodes 560 a , 560 b , and 560 c may be connected to the first routing wiring structure 384 a .

[0280] The through-electrodes 560a, 560b and 560c may include a first through-electrode 560a electrically connecting the first core circuit transistor 525a to the first bit line 190m1, a second through-electrode 560b electrically connecting the second core circuit transistor 525b to the second bit line 190m2, and a third through-electrode 560c disposed in the first peripheral circuit region PR_L and the second peripheral circuit region PR_U.

[0281] The second structure CH2 c may further include a conductive pad 585 disposed on the lower insulating structure 540 and electrically connected to the second routing wiring structure 530 .

[0282] In the following description, reference will be made to Figure 13 Examples of semiconductor devices according to example embodiments are described. Figure 13 is a cross-sectional view illustrating an example of a semiconductor device according to example embodiments.

[0283] refer to Figure 13 , Figures 1A to 12 The example embodiment in may further include a power capacitor CAP_P disposed in the first peripheral circuit region PR_U and having a structure similar to that of the data storage structures DS1 and DS2, and an electrode connection pattern 660p connected to the power capacitor CAP_P. Figure 1A The first structure CH1 in FIG. 6 may further include a power capacitor CAP_P and an electrode connection pattern 660 p .

[0284] The power capacitor CAP_P may include a first power electrode 663 disposed at the same level as the first electrode 163 , a second power electrode 669 disposed at the same level as the second electrode 169 , and a dielectric layer 666 between the first and second power electrodes 663 and 669 .

[0285] The electrode connection pattern 660 p may be disposed at the same level as the cell pad patterns 161 m 1 and 160 m 2 and may be connected to a lower surface of the first power electrode 663 .

[0286] In the following description, reference will be made to Figure 14 Example embodiments of semiconductor devices according to example embodiments are described. Figure 14 is a perspective view illustrating a semiconductor device according to example embodiments.

[0287] refer to Figure 14 , in the example, Figures 1A to 13 One of the exemplary embodiments may further include a third structure CH3 to increase the integration density. Figure 1A and Figure 1B The semiconductor device 1 described above may further include a third structure CH3 disposed on the first structure CH1. Figure 13 As shown, the third structure CH3 can be provided in a manner including a power capacitor ( Figure 13 The first structure of CAP_P) is on CH1. Figure 14 Shown Figure 1A The semiconductor device 1 in FIG. 1 further includes an example of a third structure CH3, but example embodiments thereof are not limited thereto. For example, in Figure 11 and Figure 12 In example embodiments, the third structure CH3 may be disposed under the first structures CH1b and CH1c.

[0288] exist Figures 1A to 13 In one of the example embodiments, a plurality of first storage regions MR1 ​​may be arranged in a first horizontal direction X, a plurality of second storage regions MR2 may be arranged in the first horizontal direction X, a plurality of first core circuit regions CR1 may be arranged in the first horizontal direction X, and a plurality of second core circuit regions CR2 may be arranged in the first horizontal direction X. The plurality of first storage regions MR1 ​​and the plurality of first core circuit regions CR1 may overlap in a vertical direction Z, and the plurality of second storage regions MR2 and the plurality of second core circuit regions CR2 may overlap in the vertical direction Z.

[0289] The first peripheral circuit region PR_U may be disposed between the plurality of first memory regions MR1 ​​and the plurality of second memory regions MR2 , and the second peripheral circuit region PR_L may be disposed between the plurality of first core circuit regions CR1 and the plurality of second core circuit regions CR2 .

[0290] The third structure CH3 may include a plurality of third memory regions MR3 vertically overlapping the plurality of first memory regions MR1 ​​, and a fourth memory region MR4 vertically overlapping the plurality of second memory regions MR2 .

[0291] The third and fourth storage regions MR3 and MR4 may include substantially the same cell transistors as those of the first and second storage regions MR1 ​​and MR2. Figure 1A and Figure 1B c_TRa and c_TRb) and data storage structure ( Figure 1A DS1, DS2 in the .

[0292] The third structure CH3 may include a third peripheral circuit region PR_Ua vertically overlapping the first peripheral circuit region PR_U, but in example embodiments, the third peripheral circuit region PR_Ua may not be provided.

[0293] In another example embodiment, the third storage region MR3 and the fourth storage region MR4 may be formed on the first storage region MR1 and the second storage region MR2 in the first structure CH1 without separately forming the third structure CH3. For example, the first structure CH1 may further include the third storage region MR3 and the fourth storage region MR4 disposed on and vertically overlapping the first storage region MR1 and the second storage region MR2.

[0294] In the following description, reference will be made to Figure 15 A method of manufacturing a semiconductor device according to example embodiments is described. Figure 15 is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0295] refer to Figure 15 , a first structure including a first peripheral circuit region and a storage region may be formed (S10). The first structure may be Figures 1A to 14 The first structure of one of the example embodiments in FIG. For example, the first structure may be Figure 1A or Figure 13 In the first structure CH1, the first peripheral circuit area can be Figure 1A or Figure 13 The first peripheral circuit region PR_U in the embodiment, and the storage region may be Figure 1A or Figure 13 The first storage region MR1 and the second storage region MR2.

[0296] A second structure including a second peripheral circuit region and a core circuit region may be formed (S20). The second structure may be Figures 1A to 14 For example, the second structure may be Figure 1A or Figure 13 In the second structure CH2, the second peripheral circuit area can be Figure 1A or Figure 13 The second peripheral circuit region PR_L in the core circuit region may be Figure 1A or Figure 13 The first core circuit region CR1 and the second core circuit region CR2.

[0297] The first structure and the second structure may be bonded to each other (S30). Accordingly, the first structure and the second structure bonded to each other may be formed. For example, Figure 1AAs shown in FIG, a first structure CH1 and a second structure CH2 coupled to each other may be formed.

[0298] In the following description, reference will be made to 16A to 16H and Figure 17 A method of manufacturing a semiconductor device according to example embodiments is described. Figure 15 is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments, and 16A to 16H as well as Figure 17 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0299] refer to Figure 16A , a sacrificial substrate 103, a buffer insulating layer 106, a semiconductor layer 109, and an insulating layer 112 may be stacked in sequence. The semiconductor layer 109 may be formed of a semiconductor material such as single crystal silicon.

[0300] Trenches 115 may be formed penetrating the insulating layer 112, the semiconductor layer 109, and the buffer insulating layer 106. The trenches 115 may be formed in the first memory region MR1, the first peripheral circuit region PR_U, and the second memory region MR2 and sequentially arranged in the second horizontal direction Y.

[0301] Each of the trenches 115 may have a linear shape extending in the first horizontal direction X. The semiconductor layers 109 may be spaced apart from each other in the second horizontal direction Y by the trenches 115 .

[0302] A back gate dielectric layer 118 may be formed to conformally cover the inner wall of the trench 115. A back gate conductive layer may be formed on the back gate dielectric layer 118. The back gate conductive layer may be partially etched back using an etch-back process to form a preliminary back gate electrode 121 partially filling the trench 115. A back gate capping insulating layer 124 may be formed on the preliminary back gate electrode 121 to fill the remaining portion of the trench 115. The back gate capping insulating layer 124 may be formed of an insulating material.

[0303] refer to Figure 16B , a mask pattern 127 may be formed, and the semiconductor layer may be patterned ( Figure 16A 109) forms vertical active patterns 109m1, 109p1, 109p2 and 109m2. Figure 16B In the cross-sectional structure shown in , a pair of vertical active patterns adjacent to each other among the vertical active patterns 109 m 1 , 109 p 1 , 109 p 2 , and 109 m 2 may be formed on both sides of one of the preliminary back gate electrodes 121 .

[0304] The vertical active patterns 109m1, 109p1, 109p2, and 109m2 may include a first unit vertical active pattern 109m1 in the first memory region MR1, a second unit vertical active pattern 109m2 in the second memory region MR2, and NMOS and PMOS vertical active patterns 109p1 and 109p2 in the first peripheral circuit region PR_U.

[0305] Insulation layer ( Figure 16A The insulating pattern 112a may include an insulating pattern 112a remaining on the vertical active patterns 109m1, 109p1, 109p2, and 109m2. The insulating pattern 112a may be formed on the patterned semiconductor layer ( Figure 16A During the etching process, the upper surfaces of the vertical active patterns 109m1, 109p1, 109p2 and 109m2 are protected. Figure 16A An opening 130 is formed by forming the buffer insulating layer 106 through the opening 130 . The opening 130 may expose the buffer insulating layer 106 .

[0306] refer to Figure 16C Buffer insulating layer 133 may be disposed on buffer insulating layer 106, and then a gate dielectric layer 136 may be formed to conformally cover the inner wall of opening 130. A preliminary gate conductive layer may be formed to conformally cover gate dielectric layer 136. A gate conductive layer 138 may be formed by anisotropically etching the preliminary gate conductive layer. A gap-fill insulating layer 142 may be formed on gate conductive layer 138 to fill opening 130. Mask pattern 127 may be removed.

[0307] refer to Figure 16D , gate electrodes 139m1, 139p1, 139p2, and 139m2 may be formed by partially etching the gate conductive layer 138. The gate electrodes 139m1, 139p1, 139p2, and 139m2 may include a first word line 139m1 in the first memory region MR1, a second word line 139m2 in the second memory region MR2, and a peripheral NMOS gate electrode 139p1 and a peripheral PMOS gate electrode 139p2 in the first peripheral circuit region PR_U. An upper gate capping insulating layer 145 may be formed on the gate electrodes 139m1, 139p1, 139p2, and 139m2.

[0308] refer to Figure 16E A planarization process may be performed until upper surfaces of the vertical active patterns 109m1, 109p1, 109p2, and 109m2 are exposed. Accordingly, the insulating pattern 112a may be removed.

[0309] By performing the first ion implantation process, upper cell source / drain regions 187m may be formed in upper regions of the first and second cell vertical active patterns 109m1 and 109m2. The upper cell source / drain regions 187m may have N-type conductivity.

[0310] By performing the second ion implantation process, an upper NMOS source / drain region 187p1 may be formed in an upper region of the NMOS vertical active pattern 109p1. The upper NMOS source / drain region 187p1 may have N-type conductivity.

[0311] In an example, the upper NMOS source / drain region 187 p 1 may have a doping concentration different from that of the upper cell source / drain region 187 m .

[0312] In another example, when the upper NMOS source / drain region 187 p 1 has the same doping concentration as that of the upper cell source / drain region 187 m , the first and second ion implantation processes may be performed as an integrated process.

[0313] By performing the third ion implantation process, an upper PMOS source / drain region 187p2 may be formed in an upper region of the PMOS vertical active pattern 109p2. The upper PMOS source / drain region 187p2 may have P-type conductivity.

[0314] refer to Figure 16F , an insulating structure 151 may be formed on the elements formed as above, and plugs 154m1, 154p1, 154p2, and 154m2 penetrating the insulating structure 151 may be formed.

[0315] The plugs 154m1, 154p1, 154p2 and 154m2 may include cell plug patterns 154m1, 154m2 connected to the first and second cell upper source / drain regions 187m, and peripheral contact structures 154p1 and 154p2 connected to the upper NMOS source / drain regions 187p1 and the upper PMOS source / drain regions 187p2.

[0316] An insulating structure 157 and conductive patterns 160m1, 160pa, 160pb, and 160m2 may be formed on the insulating structure 151 and the plugs 154m1, 154p1, 154p2, and 154m2. The insulating structure 157 may be formed on side surfaces of the conductive patterns 160m1, 160pa, 160pb, and 160m2.

[0317] The conductive patterns 160m1, 160pa, 160pb, and 160m2 may include cell pad patterns 160m1, 160m2 connected to the cell plug patterns 154m1, 154m2, and upper peripheral wirings 160pa and 160pb connected to the peripheral contact structures 154p1 and 154p2.

[0318] Data storage structures DS1 and DS2 may be formed on the cell plug patterns 154m1 and 154m2. The data storage structures DS1 and DS2 may have first electrodes 163 extending in the vertical direction Z, second electrodes 169 on side surfaces and an upper surface of each first electrode 163, and a dielectric layer between the first and second electrodes 163 and 169.

[0319] An insulating structure 175 covering the data storage structures DS1 and DS2 may be formed, and contact plugs 178 m and 178 p penetrating the insulating structure 175 may be formed.

[0320] The contact plugs 178m, 178p may include a cell contact plug 178m connected to the second electrode 169 of the data storage structures DS1 and DS2, and a peripheral contact plug 178p connected to an upper peripheral wiring 160pb of one of the upper peripheral wirings 160pa and 160pb.

[0321] Upper wirings 184 m and 184 p connected to the contact plugs 178 m and 178 p may be formed on the insulation structure 175 , and an upper insulation structure 181 covering the upper wirings 184 m and 184 p may be formed.

[0322] refer to Figure 16G By removing the sacrificial substrate 103 , the buffer insulating layer 133 , the vertical active patterns 109 m 1 , 109 p 1 , 109 p 2 , and 109 m 2 , and the preliminary back gate electrode 121 may be exposed.

[0323] By etching back the preliminary back-gate electrode 121 , back-gate electrodes 121 m 1 , 121 m 2 , 121 p 1 , and 121 p 2 may be formed.

[0324] The back gate electrodes 121m1, 121m2, 121p1, and 121p2 may include cell back gate electrodes 121m1 and 121m2 in the first and second memory regions MR1 ​​and MR2, and third peripheral gate electrodes 121p1 and 121p2 in the first peripheral circuit region PR_U.

[0325] An upper back gate capping insulating layer 189 may be formed on the back gate electrodes 121m1, 121m2, 121p1, and 121p2.

[0326] By performing the fourth ion implantation process, lower cell source / drain regions 148m may be formed in lower regions of the first and second cell vertical active patterns 109m1 and 109m2. The lower cell source / drain regions 148m may have N-type conductivity.

[0327] A lower NMOS source / drain region 148p1 may be formed in a lower region of the NMOS vertical active pattern 109p1 by performing a fifth ion implantation process. The lower NMOS source / drain region 148p1 may have N-type conductivity.

[0328] In an example, the lower NMOS source / drain region 148 p 1 may have a doping concentration different from that of the lower cell source / drain region 148 m .

[0329] In another example, when the lower NMOS source / drain region 148 p 1 has the same doping concentration as the lower cell source / drain region 148 m , the first ion implantation process and the second ion implantation process may be performed as an integrated process.

[0330] By performing the sixth ion implantation process, a lower PMOS source / drain region 148p2 may be formed in a lower region of the PMOS vertical active pattern 109p2. The lower PMOS source / drain region 148p2 may have P-type conductivity.

[0331] Each cell vertical active pattern 109m1 may include a lower cell source / drain region 148m, an upper cell source / drain region 187m, and a cell channel region CHm between the lower cell source / drain region 148m and the upper cell source / drain region 187m.

[0332] Each NMOS vertical active pattern 109 p 1 may include a lower NMOS source / drain region 148 p 1 , an upper NMOS source / drain region 187 p 1 , and an NMOS channel region CHp 1 between the lower NMOS source / drain region 148 p 1 and the upper NMOS source / drain region 187 p 1 .

[0333] Each PMOS vertical active pattern 109p2 may include a lower PMOS source / drain region 148p2, an upper PMOS source / drain region 187p2, and a PMOS channel region CHp2 between the lower PMOS source / drain region 148p2 and the upper PMOS source / drain region 187p2.

[0334] refer to Figure 16H , bit lines 190m1 and 190m2 and lower peripheral wirings 190p1 and 190p2 may be formed. Each of the bit lines 190m1 and 190m2 and the lower peripheral wirings 190p1 and 190p2 may include a first conductive layer 190a and a second conductive layer 190b on the first conductive layer 190a.

[0335] The bit lines 190m1 and 190m2 may be connected to the cell vertical active pattern 109m1. The lower peripheral wirings 190p1 and 190p2 may be connected to the peripheral vertical active patterns 109p1 and 109p2.

[0336] An insulating structure 198, a first routing wiring structure 192, a connecting contact plug 194, and a first bonding pad 196 may be formed. The first bonding pad 196 may have an upper surface coplanar with an upper surface of the insulating structure 198.

[0337] First routing wiring structure 192 may include a plurality of wirings arranged at different levels, and a plurality of vias connected to the upper and lower surfaces of each of the plurality of wirings. The lower surface of connection contact plug 194 may be connected to first upper peripheral wiring 160pa among upper peripheral wirings 160pa and 160pb. One of the plurality of wirings arranged at different levels of first routing wiring structure 192 may be connected to the upper surface of connection contact plug 194.

[0338] Accordingly, the following can be formed: Figure 1A and Figure 7 The first structure CH1 in.

[0339] In the following description, reference is made to Figure 17 , a device isolation region 10s defining the active region 10a may be formed on the substrate 5. The substrate 5 may be configured as a semiconductor substrate. Lower peripheral circuit transistors 25a, 25b, and 25c may be formed on the substrate 5. Each of the lower peripheral circuit transistors 25a, 25b, and 25c may include peripheral gate structures 15a and 15b disposed on the active region 10a, and peripheral source / drain regions 20sd disposed on both sides of the peripheral gate structures 15a and 15b and disposed in the active region 10a. The peripheral gate structures 15a and 15b may include a peripheral gate dielectric layer 15a and a peripheral gate electrode 15b stacked in sequence.

[0340] A second routing wiring structure 30 electrically connected to the lower peripheral circuit transistors 25a, 25b, and 25c, a second bonding pad 35 electrically connected to the second routing wiring structure 30 on the second routing wiring structure 30, and a lower insulating structure 40 may be formed on the lower peripheral circuit transistors 25a, 25b, and 25c. The lower insulating structure 40 may have an upper surface coplanar with an upper surface of the second bonding pad 35. The lower peripheral circuit transistors 25a, 25b, and 25c may include a first core circuit transistor 25a in the first core circuit region CR1, a second core circuit transistor 25b in the second core circuit region CR2, and a second peripheral circuit transistor 25c in the second peripheral circuit region PR_L. Accordingly, a structure such as Figure 1A The second structure CH2 in.

[0341] refer to Figure 1A as well as Figure 16H and Figure 17 The first structure CH1 and the second structure CH2 may be bonded to each other by performing a wafer bonding process. The upper surface of the second bonding pad 35 may be bonded to the lower surface of the first bonding pad 196, and the upper surface of the lower insulating structure 40 may be bonded to the lower surface of the first insulating structure 198. Accordingly, a bonding surface JSa may be formed between the first structure CH1 and the second structure CH2.

[0342] According to the aforementioned example embodiments, a transistor including a vertical active pattern extending in a vertical direction and a gate electrode facing a side surface of the vertical active pattern can be provided. Accordingly, the integration density of a semiconductor device can be increased.

[0343] Furthermore, in order to increase the integration density of the semiconductor device, a first peripheral circuit region may be provided outside the memory region, and a core circuit region may be provided in a region vertically overlapping with the memory region.

[0344] Furthermore, in order to increase the integration density of the semiconductor device, a second peripheral circuit region vertically overlapping the first peripheral circuit region may be provided.

[0345] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the example embodiments as defined by the appended claims.

Claims

1. A semiconductor device comprising: A first structure including a storage area and a first peripheral circuit area; as well as a second structure vertically overlapping the first structure and comprising a core circuit region and a second peripheral circuit region, The storage area includes: A first unit vertical active pattern; a first word line having a side surface facing the first side surface of the first cell vertical active pattern; and a first cell gate dielectric layer between the first cell vertical active pattern and the first word line, Wherein, the first peripheral circuit area includes: a first peripheral vertical active pattern disposed at substantially the same level as the first unit vertical active pattern; a first peripheral gate electrode having a side surface facing the first side surface of the first peripheral vertical active pattern; and A first peripheral gate dielectric layer is between the first peripheral vertical active pattern and the first peripheral gate electrode.

2. The semiconductor device according to claim 1, in, The storage area also includes a data storage structure, wherein the core circuit region includes core circuit transistors vertically overlapping the storage region, and The second peripheral circuit region includes peripheral circuit transistors that do not vertically overlap with the storage region.

3. The semiconductor device according to claim 2, wherein The first peripheral circuit region also includes a power capacitor disposed at substantially the same level as the data storage structure.

4. The semiconductor device according to claim 1, wherein The first unit vertical active pattern includes: Lower unit source / drain region; an upper unit source / drain region, on the lower unit source / drain region; and a cell channel region, between the lower cell source / drain region and the upper cell source / drain region, Wherein, the first peripheral vertical active pattern includes: lower peripheral source / drain region; an upper peripheral source / drain region on the lower peripheral source / drain region; and a peripheral channel region, between the lower peripheral source / drain region and the upper peripheral source / drain region, wherein the side surface of the first word line faces the cell channel region of the first cell vertical active pattern, and Wherein, the side surface of the first peripheral gate electrode faces the peripheral channel region of the first peripheral vertical active pattern.

5. The semiconductor device according to claim 1, in, The storage area also includes: a bit line below the first cell vertical active pattern; a cell contact structure on the first cell vertical active pattern; and A data storage structure, on the cell contact structure, Wherein, the first peripheral circuit area also includes: a first peripheral wiring below the first peripheral vertical active pattern; a peripheral contact structure on the first peripheral vertical active pattern; and a second peripheral wiring on the peripheral contact structure, and The first peripheral wiring is provided at substantially the same level as the bit line.

6. The semiconductor device according to claim 5, in, The unit contact structure includes: a cell plug pattern on the first cell vertical active pattern; and a cell pad pattern on the cell plug pattern, wherein the peripheral contact structure is disposed at substantially the same level as the cell plug pattern, and The second peripheral wiring is disposed at substantially the same level as the cell pad pattern.

7. The semiconductor device according to claim 5, in, The data storage structure includes: a first electrode extending in a vertical direction and on the cell contact structure; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode, and At least a portion of the second peripheral wiring is provided at the same level as a portion of the second electrode.

8. The semiconductor device according to claim 1, wherein A vertical length of the first peripheral gate electrode is substantially the same as a vertical length of the first word line.

9. The semiconductor device according to claim 1, in, The first peripheral circuit area further includes: a second peripheral vertical active pattern disposed at substantially the same level as the first unit vertical active pattern; a second peripheral gate electrode having a side surface facing the first side surface of the second peripheral vertical active pattern; and a second peripheral gate dielectric layer between the second peripheral vertical active pattern and the second peripheral gate electrode, and The vertical length of the second peripheral gate electrode is different from the vertical length of the first word line.

10. The semiconductor device according to claim 1, wherein The thickness of the first peripheral gate dielectric layer is different from the thickness of the first cell gate dielectric layer.

11. The semiconductor device according to claim 1, in, The storage area also includes: a second unit vertical active pattern adjacent to the first unit vertical active pattern and spaced apart from each other; a second word line having a side surface facing the second side surface of the second unit vertical active pattern; a second cell gate dielectric layer between the second cell vertical active pattern and the second word line; and a cell back gate electrode disposed between the first cell vertical active pattern and the second cell vertical active pattern, and The first unit vertical active pattern and the second unit vertical active pattern are disposed between the first word line and the second word line.

12. The semiconductor device according to claim 1, in, The first peripheral circuit area further includes: a second peripheral vertical active pattern adjacent to and spaced apart from the first peripheral vertical active pattern; a second peripheral gate electrode having a side surface facing the second side surface of the second peripheral vertical active pattern; a second peripheral gate dielectric layer between the second peripheral vertical active pattern and the second peripheral gate electrode; and a peripheral back gate electrode disposed between the first peripheral vertical active pattern and the second peripheral vertical active pattern, and The first peripheral vertical active pattern and the second peripheral vertical active pattern are disposed between the first peripheral gate electrode and the second peripheral gate electrode.

13. A semiconductor device comprising: a first structure including a first storage area and a second storage area spaced apart from each other, and a first peripheral circuit area between the first storage area and the second storage area; as well as a second structure vertically overlapping the first structure and joined to the first structure, Wherein, the second structure includes: a first core circuit region vertically overlapping the first storage region; a second core circuit region vertically overlapping the second storage region; and a second peripheral circuit region vertically overlapping the first peripheral circuit region, wherein each of the first storage area and the second storage area includes a cell transistor and a data storage structure electrically connected to the cell transistor, Wherein, the unit transistor includes: Unit vertical active pattern; a word line having a side surface facing at least a portion of a side surface of the cell vertical active pattern; and A cell gate dielectric layer is between the cell vertical active pattern and the word line.

14. The semiconductor device according to claim 13, in, The first peripheral circuit area includes: a peripheral vertical active pattern disposed at substantially the same level as the unit vertical active pattern; a peripheral gate electrode having a side surface facing at least a portion of a side surface of the peripheral vertical active pattern; and A peripheral gate dielectric layer is between the peripheral vertical active pattern and the peripheral gate electrode.

15. The semiconductor device according to claim 13, wherein The first peripheral circuit region also includes a power capacitor disposed at substantially the same level as the data storage structure.

16. The semiconductor device according to claim 13, in, The first core circuit region includes a first core circuit transistor vertically overlapping the data storage structure of the first storage region, wherein the second core circuit region includes second core circuit transistors vertically overlapping the data storage structure of the second storage region, and The second peripheral circuit region includes peripheral circuit transistors that do not vertically overlap with the data storage structures of the first storage region and the second storage region.

17. A semiconductor device comprising: a storage region including cell transistors and a data storage structure; a first peripheral circuit region disposed outside the storage region and comprising a first peripheral circuit transistor; a core circuit region vertically overlapping the memory region and including core circuit transistors; as well as The second peripheral circuit region is disposed outside the core circuit region, vertically overlaps the first peripheral circuit region, and includes a second peripheral circuit transistor.

18. The semiconductor device according to claim 17, in, The unit transistor includes: a unit vertical active pattern; and a word line having a side surface facing the first side surface of the cell vertical active pattern, and Wherein, the first peripheral circuit transistor includes: a peripheral vertical active pattern disposed at substantially the same level as the unit vertical active pattern; and A peripheral gate electrode has a side surface facing the first side surface of the peripheral vertical active pattern.

19. The semiconductor device according to claim 18, in, The storage region further includes a bit line disposed below the cell vertical active pattern, and The first peripheral circuit region further includes a peripheral wiring disposed below the peripheral vertical active pattern and at substantially the same level as the bit line.

20. The semiconductor device according to claim 17, wherein The first peripheral circuit region also includes a power capacitor disposed at substantially the same level as the data storage structure.

Images