Double-junction enhanced GaN-based current aperture vertical electron transistor and preparation method thereof
By introducing the p-GaN cap layer and AlGaN-pGaN heterojunction into the CAVET device, the problem of low threshold voltage was solved, and the preparation of a double-junction enhancement-mode GaN-based current aperture vertical electron transistor with high threshold voltage and high breakdown voltage was achieved, thereby improving the gate control capability and safety of the device.
Patent Information
- Application Number
- CN202510777158.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-11
- Publication Date
- 2025-09-09
AI Technical Summary
The threshold voltage of existing CAVET devices is relatively low, making it difficult to achieve both high threshold voltage and high breakdown voltage. Traditional adjustment methods have failed to significantly improve gate control capabilities.
A p-GaN cap layer is introduced below the gate and between the barrier layer to deplete the two-dimensional electron gas in the channel layer through band modulation and polarization, and an AlGaN-pGaN heterojunction is introduced above the barrier layer to regulate the channel electric field, forming a double junction structure.
It realizes the transformation of normally-off devices, improves the threshold voltage and breakdown voltage, enhances the gate control capability and safety of the device, and prevents current surges and false triggering.
Smart Images
Figure CN120614844A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of transistors, in particular to a double-junction enhanced GaN-based current aperture vertical electronic transistor and a preparation method thereof. Background Art
[0002] The current aperture vertical electron transistor (CAVET) is a new type of high electron mobility transistor (HEMT) device. Its development stems from the urgent demand for high-voltage, high-current and high-reliability power devices. Although traditional HEMT devices perform well in the high-frequency and high-speed fields, their lateral conductive channel is close to the surface and is easily affected by surface / interface trap states, resulting in a significant increase in dynamic on-resistance and current collapse effect, which limits their application in high-voltage fields. In addition, the electric field of the lateral structure is concentrated at the edge of the gate, which easily causes local breakdown, and the voltage withstand capability is difficult to exceed the theoretical limit of the material. As power electronic systems develop towards high power density and high frequency, vertical structure devices with high breakdown voltage show significant advantages due to their unique longitudinal current transmission mode.
[0003] However, the development of CAVET devices faces several challenges, one of which is their low threshold voltage. In traditional lateral HEMT devices, the gate directly modulates the concentration of the two-dimensional electron gas (2DEG) by controlling the lateral electric field. However, the gate-drain electric field in CAVET devices is typically a vertical structure, requiring penetration through a thicker drift layer or barrier layer. This results in a decrease in electric field strength, weakening the gate's ability to control channel carriers. Consequently, the threshold voltage of CAVET devices is relatively low.
[0004] In existing research, a gradual gradient doping structure is usually used to increase the breakdown voltage of CAVET devices. However, the polarization strength is usually not changed. Instead, the electric field is adjusted through local doping, which has little effect on the threshold voltage, resulting in no significant improvement in its gate control capability. That is, although the breakdown voltage of existing CAVET devices is large, the threshold voltage is relatively small. Therefore, there is an urgent need for a current aperture vertical electron transistor that takes into account both high threshold voltage and high breakdown voltage. Summary of the Invention
[0005] In view of the shortcomings of the existing technology, the present invention provides a double-junction enhanced GaN-based current aperture vertical electron transistor and a preparation method thereof. The present invention can greatly improve the threshold voltage and breakdown voltage of the device while realizing an enhanced CAVET device.
[0006] The technical solution of the present invention is: a double-junction enhancement-mode GaN-based current aperture vertical electron transistor, comprising a substrate layer, an n-column GaN layer, a p-column GaN layer, a p-GaN cap layer, a barrier layer, a junction layer, and a passivation layer; a drain is provided on the lower surface of the substrate layer, and an n-column GaN layer and a p-column GaN layer are provided on the upper surface of the substrate layer;
[0007] A current blocking layer is further provided on the upper surface of the p-column GaN layer; a channel layer is provided on the upper surface of the n-column GaN layer and part of the current blocking layer; a source electrode is further provided on the upper surface of part of the current blocking layer;
[0008] A barrier layer is provided on the upper surface of the channel layer; two p-GaN cap layers are provided on the upper surface of the barrier layer; a passivation layer is provided on the upper surfaces of the barrier layers on the left and right sides of the two p-GaN cap layers; a gate and a junction layer are also provided on the upper surfaces of the two p-GaN cap layers, respectively; a field plate layer is also provided on the upper surface of the passivation layer on one side of the gate, and the field plate layer extends to the junction layer and the upper surface of the passivation layer on one side of the junction layer. By introducing a p-GaN cap layer below the gate, the two-dimensional electron gas in the underlying channel layer is depleted through energy band modulation and polarization between the p-GaN cap layer and the barrier layer, achieving the transition to a normally-off device. Furthermore, an AlGaN-pGaN heterojunction is introduced in the region above the barrier layer not covered by the gate to regulate the channel electric field.
[0009] Preferably, the substrate layer and the channel layer are n-type GaN.
[0010] Preferably, the n-column GaN layer and the p-column GaN layer are n-type and p-type respectively.
[0011] Preferably, the current blocking layer is p-type heavily doped GaN.
[0012] Preferably, the drain and source are made of any one or more materials selected from Ti, Al, Ni, and Au, and the gate is made of any one or more materials selected from Ni and Au.
[0013] Preferably, the barrier layer is n-type AlGaN with an Al composition of 0.23; and the bonding layer is n-type AlGaN with an Al composition of 0.2.
[0014] Preferably, the passivation layer is Si3N4.
[0015] Preferably, the material of the field plate layer is Au.
[0016] Preferably, the contact interface between the source electrode and the current blocking layer, the contact interface between the drain electrode and the substrate layer, and the contact interface between the gate electrode and the cap layer include at least ohmic contacts.
[0017] Preferably, the present invention also provides a method for preparing a double-junction enhancement-mode GaN-based current aperture vertical electron transistor, comprising the following steps:
[0018] S1), sequentially growing an n-column GaN layer and a p-column GaN layer on the substrate layer using a selective area epitaxial growth process; and growing a current blocking layer on the p-column GaN layer; then growing a channel layer on the current blocking layer and the n-column GaN layer, and growing a barrier layer on the channel layer;
[0019] S2), using an inductively coupled plasma device to etch two grooves on the barrier layer, and then using a selective area epitaxial growth process (SAG) to grow a p-GaN cap layer in the two grooves, and then growing a junction layer on the right cap layer;
[0020] S3), using plasma enhanced chemical vapor deposition (PECVD) process to deposit Si3N4 passivation layer on the barrier layer regions on the left and right sides of the two p-GaN cap layers;
[0021] S4), using an electron beam evaporation device to evaporate any one or more materials of Ti, Al, Ni, and Au on the ohmic contact area of the ohmic contact layer, and then placing the sample in a rapid annealing furnace, passing nitrogen gas, and annealing at a temperature of 750° C. for 30 seconds to obtain a source electrode and a drain electrode;
[0022] S5), evaporating any one or more materials of Ni and Au on the ohmic contact region of the doped layer, and then placing the sample in a rapid annealing furnace, passing air, and annealing at a temperature of 550° C. for 5 minutes to obtain a gate;
[0023] S6), then evaporating Au on the upper surface of the passivation layer on the gate side, and on the junction layer and the upper surface of the passivation layer on the junction layer side to obtain a field plate layer.
[0024] Preferably, the substrate layer and the channel layer are n-type GaN, and the thickness of the substrate layer is 1 μm.
[0025] Preferably, the n-column GaN layer and the p-column GaN layer are n-type and p-type respectively, the thickness of the n-column GaN layer is 10.3 μm, and the thickness of the p-column GaN layer is 10 μm.
[0026] Preferably, the current blocking layer is p-type heavily doped GaN, and the thickness of the current blocking layer is 0.3 μm.
[0027] Preferably, the barrier layer is n-type AlGaN with an Al component of 0.23, the barrier layer thickness is 17nm, and the etching depth is 6nm; the bonding layer is n-type AlGaN with an Al component of 0.2, and the bonding layer thickness is 49nm.
[0028] The beneficial effects of the present invention are:
[0029] 1. The present invention introduces a p-type GaN cap layer below the gate and etches the AlGaN barrier layer below. This allows the two-dimensional electron gas in the channel layer below to be depleted through band modulation and polarization between the cap layer and the barrier layer. This converts the normally-on device into a normally-off device without the need for additional negative voltage to maintain the cutoff state. This effectively prevents current surges and false triggering, thereby improving device safety.
[0030] 2. The present invention forms an inverse pn junction on the right side of the gate by growing an AlGaN junction layer and a p-type GaN cap layer to regulate the distribution of the channel electric field, thereby increasing the device threshold voltage and breakdown voltage;
[0031] 3. While realizing an enhanced CAVET device, the present invention also greatly improves the threshold voltage and breakdown voltage of the device, solving the technical problem of low threshold voltage of traditional CAVET. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 Schematic diagram of the structure of the transistor of the present invention;
[0033] Figure 2 is a transfer curve diagram of the transistor of the present invention;
[0034] Figure 3 This is a breakdown curve diagram of the transistor of the present invention.
[0035] In the figure, 1-drain layer; 2-substrate layer; 3-n-pillar GaN layer; 4-p-pillar GaN layer; 5-current blocking layer; 6-channel layer; 7-source; 8-barrier layer; 9-p-GaN cap layer; 10-junction layer; 11-passivation layer; 12-gate 13-field plate layer. DETAILED DESCRIPTION
[0036] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings:
[0037] Example 1
[0038] like Figure 1 As shown, this embodiment provides a double-junction enhancement-mode GaN-based current aperture vertical electron transistor, comprising a substrate layer 2, an n-column GaN layer 3, a p-column GaN layer 4, a p-GaN cap layer 9, a barrier layer 8, a junction layer 10, and a passivation layer 11; a drain electrode 1 is provided on the lower surface of the substrate layer 2, and an n-column GaN layer 3 and a p-column GaN layer 4 are provided on the upper surface of the substrate layer 2;
[0039] A current blocking layer 5 is further provided on the upper surface of the p-column GaN layer 4; a channel layer 6 is provided on the upper surface of the n-column GaN layer 3 and part of the current blocking layer 5; a source electrode 7 is further provided on the upper surface of part of the current blocking layer 5;
[0040] A barrier layer 8 is provided on the upper surface of the channel layer 6; two p-GaN cap layers 9 are provided on the upper surface of the barrier layer 8; corresponding passivation layers 11 are provided on the upper surfaces of the barrier layer 8 on the left and right sides of the two p-GaN cap layers 9; a gate 12 and a junction layer 10 are also provided on the upper surfaces of the two p-GaN cap layers 9, respectively; a field plate layer 13 is also provided on the upper surface of the passivation layer 11 on one side of the gate 12, and the field plate layer 13 extends to the junction layer 10 and the upper surface of the passivation layer 11 on one side of the junction layer 10.
[0041] In this embodiment, a p-GaN cap layer 9 is introduced below the gate 12 so that the two-dimensional electron gas in the underlying channel layer 6 is depleted through energy band adjustment and polarization between the p-GaN cap layer 9 and the barrier layer 8 .
[0042] As preferred in this embodiment, the substrate layer 2 and the channel layer 6 are both made of n-type GaN, the thickness of the substrate layer 2 is 1 μm, and the thickness of the channel layer 6 is 0.15 μm.
[0043] As preferred in this embodiment, the n-column GaN layer 3 and the p-column GaN layer 4 are n-type and p-type respectively, the thickness of the n-column GaN layer 3 is 10.3 μm, and the thickness of the p-column GaN layer 4 is 10 μm.
[0044] As preferred in this embodiment, the current blocking layer 5 is made of p-type heavily doped GaN, and the thickness of the current blocking layer 5 is 0.3 μm.
[0045] As a preferred embodiment of the present invention, the drain 1 and the source 7 are made of any one or several materials selected from Ti, Al, Ni, and Au, and the gate 12 is made of any one or several materials selected from Ni and Au. The thickness of the drain 1 and the source 7 is 270 nm, and the thickness of the gate 12 is 150 nm.
[0046] As preferred in this embodiment, the barrier layer 8 is n-type AlGaN with an Al component of 0.23, and the thickness of the barrier layer 8 is 17nm. The bonding layer 10 is n-type AlGaN with an Al component of 0.2, and the thickness of the bonding layer 10 is 49nm.
[0047] As a preferred embodiment of this invention, the passivation layer 11 is Si3N4.
[0048] As preferred in this embodiment, the thickness of the p-GaN cap layer 9 is 152 nm.
[0049] As preferred in this embodiment, the field plate layer 13 is made of Au and has a thickness of 50 nm.
[0050] As preferred in this embodiment, the contact interface between the source electrode 7 and the current blocking layer 5 , the contact interface between the drain electrode 1 and the substrate layer 2 , and the contact interface between the gate electrode 12 and the cap layer at least include ohmic contacts.
[0051] from Figure 2 It can be seen that the transistor of this embodiment can achieve a threshold voltage of 3.3V, which is significantly higher than the threshold voltage of the vertical device proposed in the prior art.
[0052] from Figure 3 It can be seen that when the drain voltage reaches 2395V, the drain current jumps from the mA level to the A level, and the curve also shows obvious breakdown characteristics. Therefore, it can be confirmed that the breakdown voltage of the transistor in this embodiment reaches 2395V, which is higher than the breakdown voltage value of the device in the prior art.
[0053] Example 2
[0054] This embodiment provides a method for preparing a double-junction enhancement-mode GaN-based current aperture vertical electron transistor, comprising the following steps:
[0055] S1), using a metal organic chemical vapor deposition system to sequentially grow an n-pillar GaN layer 3 and a p-pillar GaN layer 4 on an N-type GaN substrate layer 2 having a thickness of 1 μm using a selective area epitaxial growth process; and growing a current blocking layer 5 on the p-pillar GaN layer 4; then growing a channel layer 6 on the current blocking layer 5 and the n-pillar GaN layer 3, and growing a barrier layer 8 on the channel layer 6;
[0056] The n-column GaN layer 3 and the p-column GaN layer 4 are n-type and p-type, respectively. The thickness of the n-column GaN layer 3 is 10.3 μm, and the thickness of the p-column GaN layer 4 is 10 μm. The current blocking layer 5 is p-type heavily doped GaN and has a thickness of 0.3 μm.
[0057] The channel layer 6 is made of n-type GaN, and the thickness of the channel layer 6 is 0.15 μm.
[0058] The barrier layer 8 is n-type AlGaN with an Al composition of 0.23, and the thickness of the barrier layer 8 is 17 nm.
[0059] S2) using an inductively coupled plasma device to etch two grooves on the barrier layer with an etching depth of 6 nm; then using a selective area epitaxial growth process (SAG) to grow a p-GaN cap layer 9 in the two grooves, and then growing a junction layer 10 on the right cap layer 9;
[0060] The bonding layer 10 is n-type AlGaN with an Al content of 0.2, and the thickness of the bonding layer 10 is 49 nm. The thickness of the p-GaN cap layer 9 is 152 nm.
[0061] S3) Depositing Si 3 N 4 passivation layers 11 on the barrier layer 8 regions on the left and right sides of the two p-GaN cap layers 9 using a plasma enhanced chemical vapor deposition (PECVD) process.
[0062] S4) Using an electron beam evaporation device, evaporate any one or more materials among Ti, Al, Ni, and Au on the ohmic contact area of the ohmic contact layer, and then place the sample in a rapid annealing furnace, introduce nitrogen, and anneal at 750°C for 30s to obtain a source electrode 7 and a drain electrode 1; the thickness of the drain electrode 1 and the source electrode 7 is 270nm.
[0063] S5) Vapor-depositing any one or more materials of Ni and Au on the ohmic contact region of the doped layer, then placing the sample in a rapid annealing furnace, introducing air, and annealing at 550° C. for 5 minutes to obtain a gate 12 having a thickness of 150 nm.
[0064] S6), then evaporate Au on the upper surface of the passivation layer 11 on the side of the gate 12, and on the junction layer 10 and the upper surface of the passivation layer 11 on the side of the junction layer 10 to obtain a field plate layer 13, wherein the thickness of the field plate layer 13 is 50 nm.
[0065] The above embodiments and descriptions are only for explaining the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, which shall fall within the scope of the invention to be protected.
Claims
1. Double-junction enhancement mode GaN-based current aperture vertical electron transistor, characterized in that The invention comprises a substrate layer (2), an n-column GaN layer (3), a p-column GaN layer (4), a p-GaN cap layer (9), a barrier layer (8), a junction layer (10), and a passivation layer (11); a drain electrode (1) is provided on the lower surface of the substrate layer (2), and an n-column GaN layer (3) and a p-column GaN layer (4) are provided on the upper surface of the substrate layer (2); A current blocking layer (5) is also provided on the upper surface of the p-column GaN layer (4); a channel layer (6) is provided on the upper surfaces of the n-column GaN layer (3) and part of the current blocking layer (5); and a source electrode (7) is also provided on the upper surface of part of the current blocking layer (5); A barrier layer (8) is provided on the upper surface of the channel layer (6); two p-GaN cap layers (9) are provided on the upper surface of the barrier layer (8); corresponding passivation layers (11) are provided on the upper surfaces of the barrier layers (8) on the left and right sides of the two p-GaN cap layers (9); a gate (12) and a junction layer (10) are also provided on the upper surfaces of the two p-GaN cap layers (9); a field plate layer (13) is also provided on the upper surface of the passivation layer (11) on one side of the gate (12), and the field plate layer (13) extends to the junction layer (10) and the upper surface of the passivation layer (11) on one side of the junction layer (10).
2. The double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 1, characterized in that: The substrate layer (2) and the channel layer (6) are both n-type GaN.
3. The double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 1, characterized in that: The current blocking layer (5) is p-type heavily doped GaN.
4. The double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 1, characterized in that: The drain (1) and source (7) are made of any one or more materials selected from Ti, Al, Ni, and Au, and the gate (12) is made of any one or more materials selected from Ni and Au.
5. The double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 1, characterized in that: The barrier layer (8) is n-type AlGaN with an Al component of 0.23; the junction layer (10) is n-type AlGaN with an Al component of 0.
2.
6. The double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 1, characterized in that: The passivation layer (11) is Si3N4.
7. The double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 1, characterized in that: The contact interface between the source electrode (7) and the current blocking layer (5), the contact interface between the drain electrode (1) and the substrate layer (2), and the contact interface between the gate electrode (12) and the cap layer at least include ohmic contacts.
8. A method for preparing a double-junction enhancement mode GaN-based current aperture vertical electronic transistor, characterized in that: The steps include: S1), sequentially growing an n-column GaN layer (3) and a p-column GaN layer (4) on a substrate layer (2) using a selective area epitaxial growth process; growing a current blocking layer (5) on the p-column GaN layer (4); then growing a channel layer (6) on the current blocking layer (5) and the n-column GaN layer (3); and growing a barrier layer (8) on the channel layer (6); S2), using an inductively coupled plasma device to etch two grooves on the barrier layer (8), then using a selective area epitaxial growth process (SAG) to grow a p-GaN cap layer (9) at the two grooves, and then growing a junction layer (10) on the right cap layer (9); S3), depositing a Si3N4 passivation layer (11) on the barrier layer (8) regions on the left and right sides of the two p-GaN cap layers (9) using a plasma enhanced chemical vapor deposition (PECVD) process; S4), using electron beam evaporation equipment to evaporate any one or more materials among Ti, Al, Ni, and Au on the ohmic contact area of the ohmic contact layer, and then placing the sample in a rapid annealing furnace, passing nitrogen gas, and annealing at a temperature of 750° C. for 30 seconds to obtain a source electrode (7) and a drain electrode (1); S5), evaporating any one or more materials of Ni and Au on the ohmic contact region of the doped layer, and then placing the sample in a rapid annealing furnace, passing air, and annealing at a temperature of 550° C. for 5 minutes to obtain a gate (12); S6), then evaporating Au on the upper surface of the passivation layer (11) on one side of the gate (12), and on the junction layer (10) and the upper surface of the passivation layer (11) on one side of the junction layer (10) to obtain a field plate layer (13).
9. The method for preparing a double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 8, characterized in that: The n-column GaN layer (3) and the p-column GaN layer (4) are n-type and p-type respectively; the thickness of the n-column GaN layer (3) is 10.3 μm, and the thickness of the p-column GaN layer (4) is 10 μm.
10. The method for preparing a double-junction enhancement mode GaN-based current aperture vertical electron transistor according to claim 8, characterized in that: The barrier layer (8) is n-type AlGaN with an Al component of 0.23, the barrier layer (8) has a thickness of 17nm, and the etching depth is 6nm; the bonding layer (10) is n-type AlGaN with an Al component of 0.2, and the bonding layer (10) has a thickness of 49nm.