Metal oxide semiconductor (MOS) tube based on gallium nitride and preparation method thereof

Abstract

The invention belongs to the technical field of MOS transistors, and particularly relates to a gallium nitride-based MOS transistor and a preparation method thereof. The MOS tube based on gallium nitride comprises a substrate; the buffer layer is positioned on the substrate and is made of aluminum nitride or gallium nitride; the gallium nitride drift layer is located on the buffer layer, the groove structure penetrates through the gallium nitride drift layer and extends to the buffer layer, and the groove is filled with a gate dielectric layer; the source electrode and the drain electrode are respectively positioned on the surface of the gallium nitride drift layer on two sides of the groove and are connected through an ohmic contact metal layer; and the isolation structure is arranged between the adjacent power units, comprises a P-type nitride layer and a gate layer, and is used for exhausting the two-dimensional electron gas to block a current path.

Description

Technical Field

[0001] The present invention belongs to the technical field of MOS tubes, and in particular relates to a gallium nitride-based MOS tube and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN), a third-generation wide-bandgap semiconductor material, boasts high electron mobility, high breakdown field strength, and a wide bandgap, significantly outperforming traditional silicon-based devices in power density, switching speed, and high-temperature stability. With the surging demand for high-performance, miniaturized devices in 5G communications, new energy vehicles, fast-charging technologies, and renewable energy, GaN MOSFETs have become a key technology for breaking through the performance bottleneck of silicon-based devices. However, the contradiction between on-resistance and switching losses in traditional silicon-based MOSFETs in high-voltage and high-frequency scenarios has become increasingly prominent, limiting improvements in system efficiency. The high critical breakdown electric field characteristics of GaN make it more suitable for medium-voltage, high-voltage, and ultra-high-frequency applications.

[0003] Despite the significant advantages of GaN MOSFETs, their practical application still faces the following technical challenges: 1. Uneven on-resistance and current distribution: Traditional trench MOSFETs (T-MOSFETs) have poor current scalability in the drift region, resulting in increased on-resistance. 2. Inadequate reverse recovery performance: When conventional devices are freewheeling in the reverse direction, the body diode turns on, leading to bipolar currents. This increases the reverse recovery time and peak current, increasing switching losses. 3. Thermal management and reliability issues: Under high-frequency operation, electric field concentration within the device (such as at the bottom of the trench) can easily cause localized overheating, reducing long-term reliability. Furthermore, the lattice mismatch between the GaN epitaxial layer and the substrate (such as silicon or sapphire) leads to interface defects, which affect device life.

[0004] Optimizing the existing manufacturing process is the core of improving GaN MOSFET performance. Current mainstream technologies include: 1. Epitaxial growth technology: Metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) is used to grow high-quality GaN epitaxial layers on pre-treated substrates. 2. Etching and passivation process: Cl2 / BCl3 / Ar plasma etching (ICP) is used to form a precise trench structure, and atomic layer deposition (ALD) is used to grow a hafnium oxide (HfO2) gate dielectric layer to reduce gate leakage current. 3. Laser annealing and interface treatment: Combined with a laser annealing process in a nitrogen atmosphere, lattice defects are reduced and interface quality is improved. However, existing technologies still face challenges such as high cost and insufficient process maturity.

[0005] Therefore, there is an urgent need for a GaN-based MOS tube and a preparation method thereof. Summary of the Invention

[0006] The object of the present invention is to provide a gallium nitride-based MOS tube and a preparation method thereof.

[0007] In order to achieve the above object, the present invention provides the following technical solutions: GaN-based MOS tubes, including: substrate (silicon); a buffer layer, located on the substrate and composed of aluminum nitride or gallium nitride; a gallium nitride drift layer, located on the buffer layer, A trench structure, penetrating the gallium nitride drift layer and extending to the buffer layer, wherein the trench is filled with a gate dielectric layer (hafnium oxide HfO2); The source and drain are respectively located on the surface of the gallium nitride drift layer on both sides of the trench and are connected through an ohmic contact metal layer (Ti / Al / Ni / Au multilayer structure); The isolation structure, which is provided between adjacent power units, includes a P-type nitride layer (p-GaN) and a gate layer, which is used to deplete the two-dimensional electron gas (2DEG) to block the current path.

[0008] Furthermore, the isolation structure includes: P-type nitride layer, thickness 50-200nm; The gate layer is made of polysilicon and covers the P-type nitride layer.

[0009] Furthermore, the sidewalls of the trench structure are covered with a composite polarization layer, including an AlGaN / InAlN stack.

[0010] Furthermore, it also includes a heat dissipation structure: limiting grooves are provided on both sides and the bottom surface of the MOS tube body, and the fastening part of the heat dissipation block is embedded in the limiting grooves; a ceramic sheet (aluminum nitride ceramic) is provided on the contact surface between the heat dissipation block and the MOS tube to improve heat dissipation efficiency.

[0011] Furthermore, a plurality of vertical shallow super junction structures are embedded in the gallium nitride drift layer, including alternatingly arranged N-type doping regions and P-type doping regions.

[0012] Furthermore, the P-type nitride layer has a doping concentration of 1×1017cm-3~1×1019cm-3.

[0013] The present invention provides a method for preparing a gallium nitride-based MOS transistor, comprising the following steps: (1) A buffer layer, a gallium nitride drift layer, and a barrier layer (AlGaN) are sequentially grown on the substrate by metal organic chemical vapor deposition (MOCVD); (2) The trench structure is formed by inductively coupled plasma (ICP) etching process with an etching depth of 1-10 μm and a sidewall tilt angle of 30°~60°; (3) Forming a gate dielectric layer in the trench by atomic layer deposition (ALD) process with a thickness of 10-100 nm; (4) Depositing source and drain metal layers on the surface of the GaN drift layer on both sides of the trench and performing rapid annealing in a nitrogen atmosphere (temperature 400-800°C, time 30-120 seconds); (5) A P-type nitride layer is epitaxially grown between adjacent power units, and the surface is flattened by a chemical mechanical polishing process. A heat dissipation structure is set up to obtain a gallium nitride-based MOS tube.

[0014] Furthermore, the MOCVD process parameters include: The reaction chamber pressure is 10-100 Torr; The Ga source flow rate was 10-100 μmol / min; Ammonia flow rate is 800-6000sccm; The hydrogen flow rate is 1000-2000 sccm.

[0015] Furthermore, the step of forming the source and drain metal layers includes: The Ti / Al / Ni / Au multilayer metal combination was deposited using magnetron sputtering technology; The electrode pattern is defined by photolithography and dry etching processes, and the etching is terminated on the surface of the gallium nitride drift layer.

[0016] Compared with the prior art, the advantages and beneficial effects of the present invention are: 1. This invention significantly optimizes device electrical performance through a multi-dimensional trench array and composite polarization layer structure. The tilted trench design, combined with the AlGaN / InAlN stacked polarization layer, effectively expands the parallel current path, reducing the on-resistance (Rds_on) to less than 60% of that of traditional devices, while also increasing the two-dimensional electron gas (2DEG) density and enhancing current uniformity. Furthermore, the introduction of a P-type nitride layer in the isolation structure completely depletes the 2DEG channel between adjacent cells, blocking current crosstalk and shortening the reverse recovery time (trr), making it suitable for high-frequency switching scenarios.

[0017] 2. The fabrication process of this invention utilizes a substrate pretreatment followed by laser annealing, combined with high-precision ICP etching and ALD gate dielectric deposition, reducing gate leakage current to less than one-fifth that of conventional devices. Optimized MOCVD process parameters ensure uniform drift layer doping, and a vertical shallow superjunction structure (N / P alternating regions) achieves uniform electric field distribution, boosting the breakdown voltage to over 1200V. Chemical mechanical polishing (CMP) and the integration of an aluminum nitride ceramic heat sink further reduce the device's temperature rise by over 30% under high-temperature conditions, extending its service life.

[0018] 3. This invention significantly reduces manufacturing costs through silicon-based substrate compatibility design and intelligent process parameter optimization. Compared with traditional SiC-based GaN devices, this solution improves yield on silicon substrates and eliminates the need for complex epitaxial buffer layers (AlN thickness <100nm). Furthermore, the magnetron sputtering Ti / Al / Ni / Au electrode process is compatible with existing semiconductor production lines, reducing equipment modification costs and making it feasible for large-scale commercial applications. DETAILED DESCRIPTION

[0019] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0020] Example 1 This embodiment provides a gallium nitride-based MOS transistor, including: substrate (silicon); a buffer layer, located on the substrate and composed of aluminum nitride or gallium nitride; a gallium nitride drift layer, located on the buffer layer, A trench structure, penetrating the gallium nitride drift layer and extending to the buffer layer, wherein the trench is filled with a gate dielectric layer (hafnium oxide HfO2); The source and drain are respectively located on the surface of the gallium nitride drift layer on both sides of the trench and are connected through an ohmic contact metal layer (Ti / Al / Ni / Au multilayer structure); The isolation structure, which is provided between adjacent power units, includes a P-type nitride layer (p-GaN) and a gate layer, which is used to deplete the two-dimensional electron gas (2DEG) to block the current path.

[0021] Heat dissipation structure: Limiting grooves are provided on both sides and the bottom of the MOS tube body, and the fastening part of the heat dissipation block is embedded in the limiting grooves; a ceramic sheet (aluminum nitride ceramic) is provided on the contact surface between the heat dissipation block and the MOS tube to improve heat dissipation efficiency.

[0022] The isolation structure includes: P-type nitride layer, 100 nm thick; The gate layer is made of polysilicon and covers the P-type nitride layer.

[0023] The sidewall of the trench structure is covered with a composite polarization layer including an AlGaN / InAlN stacked layer.

[0024] A plurality of vertical shallow superjunction structures are embedded in the gallium nitride drift layer, including N-type doping regions and P-type doping regions that are alternately arranged.

[0025] P-type nitride layer with a doping concentration of 1×10 17 cm -3 .

[0026] The method for preparing a gallium nitride-based MOS transistor is characterized by comprising the following steps: (1) A buffer layer, a gallium nitride drift layer, and a barrier layer (AlGaN) are sequentially grown on the substrate by metal organic chemical vapor deposition (MOCVD); (2) The trench structure was formed by inductively coupled plasma (ICP) etching process with an etching depth of 3 μm and a sidewall tilt angle of 40°; (3) forming a gate dielectric layer with a thickness of 60 nm in the trench by atomic layer deposition (ALD) process; (4) Depositing source and drain metal layers on the surface of the GaN drift layer on both sides of the trench and performing rapid annealing in a nitrogen atmosphere (temperature 600°C, time 90 seconds); (5) A P-type nitride layer is epitaxially grown between adjacent power units, and the surface is flattened by a chemical mechanical polishing process. A heat dissipation structure is set up to obtain a gallium nitride-based MOS tube.

[0027] The MOCVD process parameters include: The reaction chamber pressure is 60 Torr; The Ga source flow rate was 80 μmol / min; The ammonia flow rate is 1000 sccm; The hydrogen flow rate was 1500 sccm.

[0028] The steps of forming the source and drain metal layers include: The Ti / Al / Ni / Au multilayer metal combination was deposited using magnetron sputtering technology; The electrode pattern is defined by photolithography and dry etching processes, and the etching is terminated on the surface of the gallium nitride drift layer.

[0029] Example 2 This embodiment provides a gallium nitride-based MOS transistor, including: substrate (silicon); a buffer layer, located on the substrate and composed of aluminum nitride or gallium nitride; a gallium nitride drift layer, located on the buffer layer, A trench structure, penetrating the gallium nitride drift layer and extending to the buffer layer, wherein the trench is filled with a gate dielectric layer (hafnium oxide HfO2); The source and drain are respectively located on the surface of the gallium nitride drift layer on both sides of the trench and are connected through an ohmic contact metal layer (Ti / Al / Ni / Au multilayer structure); The isolation structure, which is provided between adjacent power units, includes a P-type nitride layer (p-GaN) and a gate layer, which is used to deplete the two-dimensional electron gas (2DEG) to block the current path.

[0030] Heat dissipation structure: Limiting grooves are provided on both sides and the bottom of the MOS tube body, and the fastening part of the heat dissipation block is embedded in the limiting grooves; a ceramic sheet (aluminum nitride ceramic) is provided on the contact surface between the heat dissipation block and the MOS tube to improve heat dissipation efficiency.

[0031] The isolation structure includes: P-type nitride layer, 50nm thick; The gate layer is made of polysilicon and covers the P-type nitride layer.

[0032] The sidewall of the trench structure is covered with a composite polarization layer including an AlGaN / InAlN stacked layer.

[0033] A plurality of vertical shallow superjunction structures are embedded in the gallium nitride drift layer, including N-type doping regions and P-type doping regions that are alternately arranged.

[0034] P-type nitride layer with a doping concentration of 1×10 19 cm -3 .

[0035] The method for preparing a gallium nitride-based MOS transistor is characterized by comprising the following steps: (1) A buffer layer, a gallium nitride drift layer, and a barrier layer (AlGaN) are sequentially grown on the substrate by metal organic chemical vapor deposition (MOCVD); (2) The trench structure was formed by inductively coupled plasma (ICP) etching process with an etching depth of 10 μm and a sidewall tilt angle of 30°; (3) forming a gate dielectric layer with a thickness of 100 nm in the trench by atomic layer deposition (ALD) process; (4) Depositing source and drain metal layers on the surface of the GaN drift layer on both sides of the trench and performing rapid annealing in a nitrogen atmosphere (temperature 400°C, time 120 seconds); (5) A P-type nitride layer is epitaxially grown between adjacent power units, and the surface is flattened by a chemical mechanical polishing process. A heat dissipation structure is set up to obtain a gallium nitride-based MOS tube.

[0036] The MOCVD process parameters include: The reaction chamber pressure is 10 Torr; The Ga source flow rate was 100 μmol / min; The ammonia flow rate is 800 sccm; The hydrogen flow rate was 2000 sccm.

[0037] The steps of forming the source and drain metal layers include: The Ti / Al / Ni / Au multilayer metal combination was deposited using magnetron sputtering technology; The electrode pattern is defined by photolithography and dry etching processes, and the etching is terminated on the surface of the gallium nitride drift layer.

[0038] Example 3 This embodiment provides a gallium nitride-based MOS transistor, including: substrate (silicon); a buffer layer, located on the substrate and composed of aluminum nitride or gallium nitride; a gallium nitride drift layer, located on the buffer layer, A trench structure, penetrating the gallium nitride drift layer and extending to the buffer layer, wherein the trench is filled with a gate dielectric layer (hafnium oxide HfO2); The source and drain are respectively located on the surface of the gallium nitride drift layer on both sides of the trench and are connected through an ohmic contact metal layer (Ti / Al / Ni / Au multilayer structure); The isolation structure, which is provided between adjacent power units, includes a P-type nitride layer (p-GaN) and a gate layer, which is used to deplete the two-dimensional electron gas (2DEG) to block the current path.

[0039] Heat dissipation structure: Limiting grooves are provided on both sides and the bottom of the MOS tube body, and the fastening part of the heat dissipation block is embedded in the limiting grooves; a ceramic sheet (aluminum nitride ceramic) is provided on the contact surface between the heat dissipation block and the MOS tube to improve heat dissipation efficiency.

[0040] The isolation structure includes: P-type nitride layer, 50nm thick; The gate layer is made of polysilicon and covers the P-type nitride layer.

[0041] The sidewall of the trench structure is covered with a composite polarization layer including an AlGaN / InAlN stacked layer.

[0042] A plurality of vertical shallow superjunction structures are embedded in the gallium nitride drift layer, including N-type doping regions and P-type doping regions that are alternately arranged.

[0043] P-type nitride layer with a doping concentration of 1×10 19 cm -3 .

[0044] The method for preparing a gallium nitride-based MOS transistor is characterized by comprising the following steps: (1) A buffer layer, a gallium nitride drift layer, and a barrier layer (AlGaN) are sequentially grown on the substrate by metal organic chemical vapor deposition (MOCVD); (2) The trench structure was formed by inductively coupled plasma (ICP) etching process with an etching depth of 9 μm and a sidewall tilt angle of 60°; (3) forming a gate dielectric layer with a thickness of 60 nm in the trench by atomic layer deposition (ALD) process; (4) Depositing source and drain metal layers on the surface of the GaN drift layer on both sides of the trench and performing rapid annealing in a nitrogen atmosphere (temperature 700°C, time 120 seconds); (5) A P-type nitride layer is epitaxially grown between adjacent power units, and the surface is flattened by a chemical mechanical polishing process. A heat dissipation structure is set up to obtain a gallium nitride-based MOS tube.

[0045] The MOCVD process parameters include: The reaction chamber pressure is 100 Torr; The Ga source flow rate was 100 μmol / min; The ammonia flow rate is 6000 sccm; The hydrogen flow rate was 2000 sccm.

[0046] The steps of forming the source and drain metal layers include: The Ti / Al / Ni / Au multilayer metal combination was deposited using magnetron sputtering technology; The electrode pattern is defined by photolithography and dry etching processes, and the etching is terminated on the surface of the gallium nitride drift layer.

[0047] Performance Testing Performance test of the MOS tubes prepared in Examples 1-3 1. Electrical performance test and results (1) On-resistance (Rds_on) and switching speed The on-resistance of the gallium nitride MOS transistor of this invention is significantly lower than that of traditional silicon-based devices. By optimizing the trench structure and the composite polarization layer (AlGaN / InAlN stack), the on-resistance is reduced to less than 65% of that of traditional devices, and the current distribution is more uniform.

[0048] (2) Breakdown voltage and reverse recovery performance The GaN MOS transistor of this invention has a higher breakdown voltage design margin. Through a vertical shallow superjunction structure (N / P alternating doped regions), the breakdown voltage can be increased to over 1200V. The reverse recovery time (trr) is shortened by 40%, and the reverse recovery peak current is reduced to one-sixth of that of traditional devices.

[0049] 2. Thermal performance test and results (1) Thermal resistance and heat dissipation capacity The thermal resistance parameters of the GaN MOS tube of the present invention were evaluated using standardized testing methods. By optimizing the heat dissipation structure, the temperature rise was reduced by more than 33% under high-temperature conditions.

[0050] Performance tests of the GaN MOS transistors of this invention demonstrate significant advantages over traditional silicon-based devices in terms of on-resistance, high-frequency switching, thermal stability, and reliability. Through structural optimization (e.g., trench arrays and vertical superjunctions) and process innovations (e.g., ALD gate dielectrics and laser annealing), the devices demonstrate high power density, low loss, and long life in scenarios such as fast charging and industrial power supplies, providing technical support for large-scale commercial applications.

[0051] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. MOS tube based on gallium nitride, characterized in that: include: substrate; a buffer layer, located on the substrate and composed of aluminum nitride or gallium nitride; a gallium nitride drift layer, located on the buffer layer, a trench structure, penetrating the gallium nitride drift layer and extending to the buffer layer, wherein the trench is filled with a gate dielectric layer; The source and drain are respectively located on the surface of the gallium nitride drift layer on both sides of the trench and are connected through an ohmic contact metal layer; The isolation structure is arranged between adjacent power units and includes a P-type nitride layer and a gate layer.

2. The gallium nitride-based MOS transistor according to claim 1, characterized in that: The isolation structure includes: P-type nitride layer, thickness 50-200nm; The gate layer is made of polysilicon and covers the P-type nitride layer.

3. The gallium nitride-based MOS transistor according to claim 1, characterized in that: The sidewall of the trench structure is covered with a composite polarization layer including an AlGaN / InAlN stacked layer.

4. The gallium nitride-based MOS transistor according to claim 1, characterized in that: It also includes a heat dissipation structure: the MOS tube body is provided with limiting grooves on both sides and the bottom surface, and the fastening part of the heat dissipation block is embedded in the limiting grooves; the contact surface between the heat dissipation block and the MOS tube is provided with a ceramic sheet.

5. The gallium nitride-based MOS transistor according to claim 1, characterized in that: A plurality of vertical shallow superjunction structures are embedded in the gallium nitride drift layer, including N-type doping regions and P-type doping regions that are alternately arranged.

6. The gallium nitride-based MOS transistor according to claim 1, characterized in that: P-type nitride layer with a doping concentration of 1×10 17 cm -3 ~1×10 19 cm -3 .

7. A method for preparing a gallium nitride-based MOS transistor according to any one of claims 1 to 6, characterized in that: The following steps are involved: (1) A buffer layer, a GaN drift layer, and a barrier layer are sequentially grown on a substrate by metal organic chemical vapor deposition; (2) The trench structure is formed by inductively coupled plasma etching process with an etching depth of 1-10 μm and a sidewall tilt angle of 30°~60°; (3) Forming a gate dielectric layer in the trench by atomic layer deposition process with a thickness of 10-100 nm; (4) Depositing source and drain metal layers on the surface of the GaN drift layer on both sides of the trench and performing rapid annealing in a nitrogen atmosphere; (5) A P-type nitride layer is epitaxially grown between adjacent power units, and the surface is flattened by a chemical mechanical polishing process. A heat dissipation structure is set up to obtain a gallium nitride-based MOS tube.

8. The method for preparing a gallium nitride-based MOS transistor according to claim 8, characterized in that: The MOCVD process parameters include: The reaction chamber pressure is 10-100 Torr; The Ga source flow rate was 10-100 μmol / min; Ammonia flow rate is 800-6000sccm; The hydrogen flow rate is 1000-2000 sccm.

9. The method for preparing a gallium nitride-based MOS transistor according to claim 9, characterized in that: The steps of forming the source and drain metal layers include: The Ti / Al / Ni / Au multilayer metal combination was deposited using magnetron sputtering technology; The electrode pattern is defined by photolithography and dry etching processes, and the etching is terminated on the surface of the gallium nitride drift layer.