Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a separation gate structure, and a source contact. The silicon carbide substrate has first, second and third regions, and has a first conductivity type. The epitaxial layer is disposed on the top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The first electrode is arranged in the epitaxial layer of the first region and extends along a first direction. The separation gate structure is disposed in the epitaxial layer of the first region. The separation gate structure includes a first gate and a second gate separated from each other on opposite sidewalls of the first electrode. A top portion of the first electrode is exposed from the separation gate structure. The source contact is arranged on the epitaxial layer of the first region. The source contact covers and is electrically connected with the top of the first electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a power transistor device with a self-aligned contact feature and a method for forming the same. Background Art

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated into a given area. For example, the trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET), widely used in power switch devices, utilizes a vertical structure design to reduce the cell pitch to increase functional density. It uses the backside of the chip as the drain, while the source and gate of multiple transistors are fabricated on the front side of the chip. As a result, the driving current flows in a vertical direction instead of in-plane, which enables the semiconductor device to achieve high reverse voltage resistance and low on-resistance.

[0003] However, as the functional density requirements for semiconductor devices continue to increase, the complexity of the components integrated into semiconductor devices and their formation methods has also increased, and there are certain electronic characteristics that require trade-offs in performance that need to be considered. Therefore, although existing semiconductor devices are generally suitable and sufficient for their intended purposes, they are not completely satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a separation gate structure, and a source contact. The silicon carbide substrate has a first region, a second region, and a third region, and has a first conductivity type. The epitaxial layer is arranged on the top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The first electrode is arranged in the epitaxial layer of the first region and extends along a first direction. The separation gate structure is arranged in the epitaxial layer of the first region. The separation gate structure includes a first gate and a second gate separated from each other, located on opposite side walls of the first electrode, and extending along the first direction. The top of the first electrode is exposed from the separation gate structure. The source contact is arranged on the epitaxial layer of the first region. The source contact covers and is electrically connected to the top of the first electrode.

[0005] Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes providing a silicon carbide substrate having a first region, a second region, and a third region, and having a first conductivity type; growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming a first trench in the epitaxial layer in the first region along a first direction; forming a first electrode in the first trench, wherein the first electrode extends along the first direction; forming a first gate and a second gate separated from each other along a second direction on opposite sidewalls of the first electrode; forming an interlayer dielectric layer throughout the entirety; completely removing the interlayer dielectric layer on the top surface of the epitaxial layer in the first region to expose the top of the first electrode; and forming a source contact on the epitaxial layer in the first region, wherein the source contact covers and electrically connects to the top of the first electrode.

[0006] The present invention can improve the electrical uniformity and reliability of semiconductor devices and save the cost of high-resolution masks and photolithography processes when the component density is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description will provide a better understanding of the present invention when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are provided for illustrative purposes only. Indeed, the dimensions of the elements may be arbitrarily increased or decreased to clearly illustrate the features of the present invention.

[0008] Figure 1 Schematic cross-sectional views of semiconductor devices according to some embodiments of the present invention.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 To form Figure 1 FIG2 is a schematic cross-sectional view of a semiconductor device at an intermediate stage according to some embodiments of the present invention.

[0010] Figure 20 To form Figure 1 A schematic top view of an intermediate stage of a semiconductor device according to some embodiments of the present invention is shown, showing the configuration of a source region and a wiring doping region above a well region.

[0011] Figure Number:

[0012] 100:Silicon carbide substrate

[0013] 100T,200T,216T,216ART,216BRT,220AT,220BT,220CT,220ART,220BRT,220CRT,241T,230AG1T,230AG2T,220F2T,230BGT: Top

[0014] 100B,212A-B,212B-B,212C-B,234B: bottom

[0015] 200: epitaxial layer

[0016] 210: mask layer

[0017] 210P: Mask pattern

[0018] 212A, 212B, 212C: Grooves

[0019] 212A-S,212B-S,212C-S,220F1S,220F2S,250S1,250S2,250S3,250S4: Sidewall

[0020] 216, 216AR, 216BR, 216CR: shielding dielectric layer

[0021] 220A, 220B, 220C, 220AR, 220BR, 220CR: Conductive materials

[0022] 220AR-1, 220BR-1: upper part

[0023] 220F1: First electrode

[0024] 220F1-1,220AR-1,220BR-1: Top

[0025] 220F2: Second electrode

[0026] 220F3: Third electrode

[0027] 222,222CR: oxide layer

[0028] 222T1,222T2: Upper surface

[0029] 224A, 224B, 224A-1, 224A-2, 224B-1, 224B-2, 241: Gate dielectric layer

[0030] 224AR-1: Part 1

[0031] 230:Electrode material

[0032] 230AG: Split gate structure

[0033] 230AG1, 230AG2, 230BG: Gate

[0034] 234: Well region

[0035] 236: Source region

[0036] 238: Wiring doping area

[0037] 240, 240BR, 240CR: interlayer dielectric layer

[0038] 240AR: Part 2

[0039] 242A, 242B, 244A, 244B: Open

[0040] 246S, 246G: Metal silicide

[0041] 248S, 248G: Contact conductive layer

[0042] 250S: Source contact

[0043] 250BS1, 250BS2, 250BS3: bottom surface

[0044] 250G: Gate contact

[0045] 300,310,320: direction

[0046] 400: District 1

[0047] 400M: table area

[0048] 410: District 2

[0049] 420: District 3

[0050] 500:Semiconductor devices

[0051] PR1, PR2, PR3, PR4, PR5: photoresist pattern

[0052] T1, T2: thickness

[0053] W1,W2,W3,W4,W5: Width DETAILED DESCRIPTION

[0054] The present disclosure is more fully described below with reference to the accompanying drawings of exemplary embodiments of the present invention. However, the present disclosure may be implemented in a variety of different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements. It will be understood that additional steps may be provided before, during, or after the method, and that some described steps may be replaced or deleted for other embodiments of the method.

[0055] Various embodiments or examples are provided below for implementing various components of the provided semiconductor structure. Reference to a first component being formed above a second component may include embodiments in which the first and second components are in direct contact, as well as embodiments in which an additional component is formed between the first and second components, preventing direct contact. Furthermore, embodiments of the present invention may use repeated reference numerals across multiple examples. This repetition is for simplicity and clarity purposes only and does not represent a specific relationship between the various embodiments and / or configurations discussed.

[0056] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms may be used in the following description to simplify the description of the relationship of one element or component to other elements or components as shown in the figures. Such spatially relative terms encompass not only the orientation depicted in the figures, but also different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0057] In a high-density shielded gate trench MOSFET (SGT MOSFET) cell array, expensive high-resolution masks (such as deep ultraviolet (DUV) masks) and photolithography processes are required to form source contacts between adjacent transistor cells. However, during the existing source contact process, photoresist rework problems often occur due to errors in contact to trench overlay, which increases process costs and production cycles. In addition, the above-mentioned contact-trench coverage errors will cause uneven electrical parameters of adjacent transistor cells, thereby failing to pass component reliability tests (such as UIS (Unclamped Inductive Switching) electrical tests) and may even cause component burnout. Therefore, it is necessary to seek a semiconductor device of an isolated gate trench MOSFET and a method for forming the same that can solve or improve the above-mentioned problems.

[0058] Figure 1 Schematic cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. In some embodiments, the semiconductor device 500 includes a power metal oxide semiconductor field effect transistor (power MOSFET), such as an isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) having a split-gate structure. Figure 1 As shown, the semiconductor device 500 includes a silicon carbide (SiC) substrate 100, an epitaxial layer 200, a split gate structure 230AG, and a source contact 250S. Figure 1 In the following figures, directions 300 and 310 are substantially parallel to the top surface 100T of the silicon carbide substrate 100 and can also be considered as lateral directions. Direction 320 is substantially perpendicular to the top surface 100T of the silicon carbide substrate 100 and can also be considered as a longitudinal direction (or can be considered as a channel length direction). Furthermore, direction 300 is perpendicular to directions 310 and 320, direction 310 is perpendicular to directions 300 and 320, and direction 320 (can also be considered as a channel width direction) is perpendicular to directions 300 and 310.

[0059] like Figure 1 As shown, the silicon carbide substrate 100 has a top surface 100T and a bottom surface 100B. Furthermore, the silicon carbide substrate 100 has a first region 400, a second region 410, and a third region 420. In some embodiments, the first region 400 may be a cell region in which a power metal oxide semiconductor field effect transistor array is formed. The second region 410 may be a gate pickup region in which a gate contact is formed. Furthermore, the third region 420 may be a termination region, which surrounds the cell region and serves as a buffer for the doped regions in the cell region to prevent a rapid drop in the device breakdown voltage at the cell region boundary. In the following embodiments, the cell region (first region 400) is described as having two isolated gate trench metal oxide semiconductor field effect transistor units. Furthermore, the gate pickup region (second region 410) and the termination region (third region 420) are described as having a trench electrode (e.g., a source electrode). However, any number of isolated gate trench MOSFET units and trench electrodes may be provided in the cell region, the gate connection region, and the terminal region, and are not limited to the embodiments described herein.

[0060] In some embodiments, the conductivity type of the silicon carbide substrate 100 can be P-type or N-type depending on design requirements. In this embodiment, the silicon carbide substrate 100 can be doped with dopants to have a first conductivity type, such as N-type. In applications involving vertical trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), the silicon carbide substrate 100 having the first conductivity type can serve as the drain region of the final semiconductor device 500.

[0061] The epitaxial layer 200 is disposed on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial layer 200 may be doped with dopants to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the epitaxial layer 200 is an N-type epitaxial layer 200. Furthermore, the doping concentration of the epitaxial layer 200 (e.g., about 10 15 -10 16 atoms / cm 3 ) is less than the doping concentration of the silicon carbide substrate 100 (10 19 -10 21 atoms / cm 3 For example, when the silicon carbide substrate 100 is an N-type heavily doped (N+) silicon carbide substrate 100, the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200. In applications of vertical trench-gate metal oxide semiconductor field effect transistors (vertical trench-gate MOSFETs), the epitaxial layer 200 having the first conductivity type can serve as a drift region of the final semiconductor device 500. In some embodiments, the epitaxial layer 200 comprises silicon carbide.

[0062] The well region 234 of the semiconductor device 500 is located in the epitaxial layer 200 in the first region 400, the second region 410, and the third region 420, and is close to the top surface 200T of the epitaxial layer 200. In some embodiments, the well region 234 may be doped with dopants to have a second conductivity type opposite to the first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the well region 234 is a P-type well region 234. In addition, the above-mentioned dopants with the second conductivity type may include aluminum (Al), boron (B), or other suitable dopants. In some embodiments, the doping concentration of the well region 234 (e.g., about 10 17 -10 18 atoms / cm 3) is greater than the doping concentration of the epitaxial layer 200. In some embodiments, the well region 234 may be formed using an ion implantation process. In applications of vertical trench-gate metal-oxide-semiconductor field-effect transistors, the well region 234 having the second conductivity type may serve as a channel region of the final semiconductor device 500.

[0063] The source region 236 of the semiconductor device 500 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. In addition, the second region 410 and the third region 420 may not have the source region 236. Figure 1 As shown, the source region 236 is surrounded by the well region 234. In some embodiments, the source region 236 may be doped with a dopant to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the source region 236 is an N-type source region 236. Furthermore, the doping concentration of the source region 236 is greater than the doping concentration of the epitaxial layer 200. For example, when the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200, the source region 236 is an N-type heavily doped (N+) source region 236.

[0064] The semiconductor device 500 further includes a wiring doping region 238 ( Figure 16 、 Figure 20 ). The wiring doping region 238 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. In addition, the second region 410 and the third region 420 may not have the wiring doping region 238. Figure 16 As shown, the wiring doping region 238 is surrounded by the well region 234. The source region 236 and the wiring doping region 238 are adjacent to each other along direction 310. In addition, in some embodiments, multiple source regions 236 and multiple wiring doping regions 238 are staggered along direction 310. The source region 236 and the wiring doping region 238 may have opposite conductivity types. For example, when the source region 236 has a first conductivity type, the wiring doping region 238 has a second conductivity type. The wiring doping region 238 has the same conductivity type as the well region 234, for example, a P-type wiring doping region 238. Furthermore, the doping concentration of the wiring doping region 238 is greater than the doping concentration of the well region 234. For example, when the well region 234 is a P-type well region 234, the wiring doping region 238 is a P-type heavily doped (P+) wiring doping region 238, serving as the wiring doping region of the well region 234.

[0065] The semiconductor device 500 further includes shielding dielectric layers 216AR, 216BR, 216CR and a first electrode 220F1, a second electrode 220F2, and a third electrode 220F3. Figure 1As shown, the shielding dielectric layer 216AR and the first electrode 220F1 are disposed in the epitaxial layer 200 in the first region 400. The shielding dielectric layer 216AR is located below the top surface 200T of the epitaxial layer 200. The first electrode 220F1 is on the shielding dielectric layer 216AR, and the shielding dielectric layer 216AR covers the bottom surface and opposite sidewalls of the first electrode 220F1. Figure 1 As shown, the first electrode 220F1 extends along a direction 320 toward the top surface 200T of the epitaxial layer 200 and the silicon carbide substrate 100. Furthermore, a top portion 220F1-1 of the first electrode 220F1 is exposed from the split gate structure 230AG. In some embodiments, in the direction 300, a width W1 of an upper portion of the first electrode 220F1 (including the top portion 220F1-1) is less than a width W2 of a lower portion of the first electrode 220F1.

[0066] like Figure 1 As shown, a shielding dielectric layer 216BR and a second electrode 220F2 are disposed in the epitaxial layer 200 of the second region 410. The second electrode 220F2 extends from a position near the top surface 200T of the epitaxial layer 200 along a direction 320 toward the silicon carbide substrate 100. The second electrode 220F2 is located on the shielding dielectric layer 216BR, and the shielding dielectric layer 216BR covers the bottom surface and opposite sidewalls of the second electrode 220F2. In some embodiments, in the direction 300, the width W3 of the upper portion of the second electrode 220F2 is less than the width W4 of the lower portion of the second electrode 220F2. In some embodiments, the width W1 may be equal to the width W3, and the width W2 may be equal to the width W4.

[0067] like Figure 1 As shown, a shielding dielectric layer 216CR and a third electrode 220F3 are disposed in the epitaxial layer 200 in the third region 420. The third electrode 220F3 extends from a position near the top surface 200T of the epitaxial layer 200 along a direction 320 toward the silicon carbide substrate 100. The third electrode 220F3 is located on the shielding dielectric layer 216CR, and the shielding dielectric layer 216CR covers the bottom surface and opposite sidewalls of the third electrode 220F3. In some embodiments, in the direction 300, the third electrode 220F3 has a uniform width W5. In some embodiments, the width W5 can be equal to the widths W1 and W3.

[0068] In some embodiments, the shielding dielectric layers 216AR, 216BR, and 216CR may comprise the same material. For example, the shielding dielectric layers 216AR, 216BR, and 216CR may comprise silicon oxide, other suitable semiconductor oxide materials, or combinations thereof. In some embodiments, the shielding dielectric layers 216AR, 216BR, and 216CR may be formed using a conformable deposition process, an oxidation process, or other suitable formation process. In some embodiments, the oxidation process may be thermal oxidation or other suitable process. In some embodiments, the deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), other suitable processes, or combinations thereof.

[0069] In some embodiments, the first electrode 220F1, the second electrode 220F2, and the third electrode 220F3 may optionally include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the first electrode 220F1, the second electrode 220F2, and the third electrode 220F3 are respectively a P-type first electrode 220F1, a P-type second electrode 220F2, and a P-type third electrode 220F3. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopants. In some embodiments, the first electrode 220F1, the second electrode 220F2, and the third electrode 220F3 are electrically connected to the source contact 250S.

[0070] In some embodiments, the first electrode 220F1 can reduce the gate-to-drain capacitance (C gd ) to improve the switching characteristics of the semiconductor device 500, and it has a field plate function, so that the gate dielectric layer (eg Figure 1 The electric field distribution of the gate dielectric layer 241 shown is more uniform and the breakdown voltage is increased, thereby improving the reliability of the gate dielectric layer. In addition, by setting the first electrode 220F1, the doping concentration of the epitaxial layer 200 can be further increased to reduce the on-resistance (R onsp ).

[0071] exist Figure 1In the embodiment shown, two separate gate structures 230AG are disposed in the epitaxial layer 200 of the first region 400 and are located above the lower portion of the first electrode 220F1. The two separate gate structures 230AG are separated from each other by the epitaxial layer 200 along the direction 300. Furthermore, the region of the epitaxial layer 200 between the two separate gate structures 230AG can be considered as a mesa region 400M of the semiconductor device 500. Figure 1 As shown, the split gate structure 230AG extends along direction 320. In some embodiments, the split gate structure 230AG includes a gate dielectric layer 241 and gates 230AG1 and 230AG2 separated from each other along direction 300. In some embodiments, the split gate structure 230AG can further reduce the overall gate-to-drain capacitance (C gd ) and feedback capacitor (C rss =C gd ) to improve the overall power conversion efficiency of the semiconductor device 500.

[0072] like Figure 1As shown, a gate dielectric layer 241 is disposed in the epitaxial layer 200 in the first region 400. The gate dielectric layer 241 extends from near the top surface 200T of the epitaxial layer 200 into the epitaxial layer 200 along a direction 320. A top portion 220F1-1 of the first electrode 220F1 is exposed from the gate dielectric layer 241 of the split gate structure 230AG. Specifically, the top portion 220F1-1 of the first electrode 220F1 protrudes from the top surface 241T of the gate dielectric layer 241 along the direction 320. In some embodiments, the gate dielectric layer 241 may be a composite structure. For example, the gate dielectric layer 241 may include a first portion 224AR-1 and a second portion 240AR. The first portion 224AR-1 is located between the gate 230AG1 (or gate 230AG2) and the first electrode 220F1. The second portion 240AR is located between the top surface 230AG1T (or top surface 230AG2T) of the gate 230AG1 (or gate 230AG2) and the top surface 241T of the gate dielectric layer 241. In some embodiments, the first portion 224AR-1 has a thickness T1 along direction 300, and the second portion 240AR has a thickness T2 along direction 320. In some embodiments, the thickness T2 of the second portion 240AR is greater than the thickness T1 of the first portion 224AR-1. Furthermore, the ratio of thickness T2 to thickness T1 may be between 2 and 3. If the ratio of thickness T2 to thickness T1 is less than 2, the thickness of the second portion 240AR may be too thin, failing to provide adequate electrical isolation between the gates 230AG1 and 230AG2 and the source contact 250S subsequently formed thereon. If the ratio of the thickness T2 to the thickness T1 is greater than 3, the height of the top portion 220F1 - 1 of the first electrode 220F1 protruding from the gate dielectric layer 241 is too small, which is not conducive to electrical connection between the first electrode 220F1 and the source contact 250S subsequently formed thereon.

[0073] In some embodiments, the first portion 224AR-1 and the second portion 240AR of the gate dielectric layer 241 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), a low-k dielectric material, and / or other suitable dielectric materials, or combinations thereof. In this embodiment, the first portion 224AR-1 and the second portion 240AR of the gate dielectric layer 241 may include silicon oxide. In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR and the gate dielectric layer 241 may be made of the same or different materials depending on actual needs. In some embodiments, the first portion 224AR-1 of the gate dielectric layer 241 can be formed using an oxidation process. In some embodiments, the oxidation process can include thermal oxidation or other suitable processes. In some embodiments, the second portion 240AR of the gate dielectric layer 241 can be formed using a conformable deposition process, other suitable formation processes, and a subsequent etch-back process. In some embodiments, the deposition process can include spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), other suitable processes, or combinations thereof.

[0074] Gates 230AG1 and 230AG2 are located on opposite sidewalls 220F1S of first electrode 220F1 and extend along direction 320. Top surfaces 230AG1T and 230AG2T of gates 230AG1 and 230AG2 may be lower than top surface 200T of epitaxial layer 200 and top portion 220F1-1 of first electrode 220F1. Furthermore, gate dielectric layer 241 surrounds gates 230AG1 and 230AG2. Furthermore, first electrode 220F1 may extend from below gates 230AG1 and 230AG2 to above gates 230AG1 and 230AG2 along direction 320. Furthermore, first electrode 220F1 may be interposed between gates 230AG1 and 230AG2 along direction 300. Opposite sidewalls 220F1S of the first electrode 220F1 proximate to the gates 230AG1 and 230AG2 are separated from the gates 230AG1 and 230AG2 by a first portion 224AR- 1 of the gate dielectric layer 241 .

[0075] In some embodiments, the gates 230AG1 and 230AG2 may be a single-layer or multi-layer structure formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), and platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide (WSi x In some embodiments, the gates 230AG1 and 230AG2 may optionally include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the gates 230AG1 and 230AG2 are P-type gates 230AG1 and 230AG2. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF2), or other suitable dopant. In some embodiments, the first electrode 220F1, the second electrode 220F2, and the third electrode 220F3 may include the same or different materials as the gates 230AG1 and 230AG2.

[0076] The semiconductor device 500 further includes a gate dielectric layer 224B and a gate 230BG disposed in the epitaxial layer 200 in the second region 410. The gate dielectric layer 224B extends from near the top surface 200T of the epitaxial layer 200 into the epitaxial layer 200 along the direction 320. Furthermore, the gate dielectric layer 224B covers the top of the second electrode 220F2. The gate 230BG is located on the gate dielectric layer 224B and is connected to the separation gate structure 230AG. In some embodiments, the gate 230BG extends from opposite sidewalls 220F2S of the second electrode 220F2 to cover the top surface 220F2T of the second electrode 220F2 and the top surface 200T of the epitaxial layer 200. Portions of the gate 230BG located on the opposite sidewalls 220F2S of the second electrode 220F2 may extend along the direction 320. Furthermore, a portion of the gate 230BG located above the top surface 220F2T of the second electrode 220F2 and the top surface 200T of the epitaxial layer 200 may extend along a direction 300 .

[0077] The semiconductor device 500 further includes interlayer dielectric layers 240BR and 240CR. The interlayer dielectric layers 240BR and 240CR are disposed on the epitaxial layer 200 in the second region 410 and the third region 420, exposing the top portion 220F1-1 of the first electrode 220F1, the source region 236, the wiring doped region 238, and the top surface 230BGT of the gate 230BG. This means that no interlayer dielectric layer may be present above the top surface 200T of the epitaxial layer 200 in the first region 400. In some embodiments, the interlayer dielectric layers 240BR and 240CR may include silicon oxide, silicon nitride, silicon oxynitride, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or a combination thereof. In some embodiments, the interlayer dielectric layers 240BR and 240CR may be formed using a conformable deposition process, an oxidation process, or other suitable formation process, followed by a subsequent patterning process. In some embodiments, the oxidation process may be thermal oxidation or other suitable processes. In some embodiments, the deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), other suitable processes, or combinations thereof.

[0078] A source contact 250S is disposed on the epitaxial layer 200 in the first region 400. The source contact 250S covers and electrically connects the top portion 220F1-1 of the first electrode 220F1, the source region 236, and the wiring doped region 238. The source contact 250S may be electrically connected to the second electrode 220F2 and the third electrode 220F3 via other interconnects (not shown). Furthermore, the gates 230AG1 and 230AG2 may be separated from the source contact 250S by a gate dielectric layer 241. The source contact has opposing sidewalls 250S1 and 250S2 and opposing sidewalls 250S3 and 250S4. In some embodiments, the sidewalls 250S1 and 250S3 are adjacent to the first electrode 220F1, and the sidewalls 250S2 and 250S4 are adjacent to the source region 236 and the wiring doped region 238.

[0079] In some embodiments, source contact 250S has multiple discontinuous lower surfaces 250BS1, 250BS2, and 250BS3. Lower surface 250BS1 connects to 220F1-1 of first electrode 220F1, lower surface 250BS2 connects to gate dielectric layer 241, and lower surface 250BS3 connects to source region 236 and wiring doped region 238. In some embodiments, lower surfaces 250BS1 and 250BS2 are not coplanar (i.e., not aligned with each other along direction 300). In some embodiments, lower surfaces 250BS2 and 250BS3 are not coplanar (i.e., not aligned with each other along direction 300). In some embodiments, lower surfaces 250BS1 and 250BS3 may be coplanar (i.e., aligned with each other along direction 300).

[0080] In some embodiments, the source contact 250S may include a metal silicide 246S, a contact barrier layer (not shown), and a contact conductive layer 248S. Figure 1 As shown, the lower surfaces 250BS1 and 250BS3 of the source contact 250S may be formed of metal silicide 246S, while the lower surface 250BS2 of the source contact 250S is not formed of metal silicide 246S. Therefore, the metal silicide 246S may be a discontinuous layer, formed only on a portion of the lower surface of the source contact 250S. The metal silicide 246S covers the top portion 220F1-1 of the first electrode 220F1 exposed from the interlayer dielectric layer 240BR, the source region 236, and the wiring doped region 238. The contact barrier layer and the contact conductive layer 248S thereon cover the metal silicide 246S and the gate dielectric layer 241.

[0081] In some embodiments, the metal silicide 246S includes, for example, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, other suitable metal silicides, or combinations thereof. In some embodiments, the metal layer can be deposited globally using chemical vapor deposition (CVD) (e.g., low-pressure vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD)), physical vapor deposition (PVD) (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), electroplating, atomic layer deposition (ALD), other suitable processes, or combinations thereof. An annealing process is then performed to react the metal layer on the top portion 220F1-1 of the first electrode 220F1, the source region 236, and the wiring doped region 238 in the first region 400 that is not covered by the gate dielectric layer 241 with the semiconductor material, forming a discontinuously distributed metal silicide 246S. The unreacted metal layer is then removed.

[0082] In some embodiments, the contact barrier layer may be used to prevent the subsequently formed contact conductive layer 248S from diffusing into the gates 230AG1 and 230AG2. The contact barrier layer may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or combinations thereof.

[0083] In some embodiments, the contact conductive layer 248S of the source contact 250S may have a single-layer or multi-layer structure. The material of the contact conductive layer 248S may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), other suitable metals, or combinations thereof. In some embodiments, the contact conductive layer 248S may be formed using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or combinations thereof.

[0084] The semiconductor device 500 further includes a gate contact 250G. The gate contact 250G is disposed on the epitaxial layer 200 in the second region 410. The gate contact 250G extends from above the interlayer dielectric layer 240BR along the direction 320 through the interlayer dielectric layer 240BR to cover and electrically connect the gate 230BG. Similar to the source contact 250S, the gate contact 250G may include a metal silicide 246G, a contact barrier layer (not shown), and a contact conductive layer 248G. The metal silicide 246G covers the gate 230BG. The contact barrier layer and the contact conductive layer 248G thereon cover the metal silicide 246G and the interlayer dielectric layer 240BR. In some embodiments, the contact barrier layer includes the same or similar materials and processes and may be formed simultaneously. The contact conductive layers 248S and 248G may include the same or similar materials and processes and may be formed simultaneously.

[0085] Next, Figures 2 to 19 Methods for forming a semiconductor device 500 according to some embodiments of the present invention are described. Figures 2 to 19 To form Figure 1 The cross-sectional view of the semiconductor device 500 in the intermediate stage of some embodiments of the present invention is shown. Figure 1 The same or similar reference numerals represent the same or similar elements.

[0086] like Figure 2 As shown, a silicon carbide substrate 100 having a first conductivity type is provided, for example, an N-type heavily doped (N+) silicon carbide substrate 100 .

[0087] Next, an epitaxial growth process is performed to grow an epitaxial layer 200 having a first conductivity type, such as an N-type lightly doped (N-) silicon carbide epitaxial layer 200, on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial growth process includes metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable epitaxial growth processes, or combinations thereof.

[0088] Then, if Figure 3As shown, an ion implantation process may be performed to form a well region 234 of the second conductivity type, such as a P-type well region 234 , in the epitaxial layer 200 . The well region 234 extends from the top surface 200T of the epitaxial layer 200 to a portion of the epitaxial layer 200 .

[0089] Then, if Figure 4 As shown, a deposition process may be performed to form a mask layer 210 on the epitaxial layer 200. In some embodiments, the mask layer 210 may be a single layer or a multi-layer structure. In some embodiments, the mask layer 210 may include an insulating material such as silicon oxide.

[0090] Then, if Figure 5 As shown, a photolithography process and a subsequent patterning process are performed. A portion of the mask layer 210 is removed to form mask patterns 210P on the top surface 200T of the epitaxial layer 200 to define the formation position of the trench. Afterwards, the epitaxial layer 200 is etched using the mask pattern 210P as an etching mask. The above etching process removes the epitaxial layer 200 not covered by the mask pattern 210P to form trenches 212A, 212B, and 212C in the epitaxial layer 200 in the first area 400, the second area 410, and the third area 420 along the direction 320. Figure 5 In the illustrated embodiment, the etching process forms two trenches 212A in the epitaxial layer 200 in the first region 400, one trench 212B in the epitaxial layer 200 in the second region 410, and one trench 212C in the epitaxial layer 200 in the third region 420. Two adjacent trenches 212A are spaced apart from each other along a direction 300 and define a mesa region 400M of the epitaxial layer 200. In some embodiments, the etching process includes dry etching. The dry etching process may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma etching, or other suitable processes.

[0091] Then, if Figure 6As shown, a selective etching process may be performed to remove the mask pattern 210P. Subsequently, an oxidation process and subsequent etching processes may be performed to form a sacrificial oxide layer (SAC oxide layer) (not shown) on the sidewalls 212A-S, 212B-S, 212C-S and bottom surfaces 212A-B, 212B-B, 212C-B of the trenches 212A, 212B, 212C. An etching process may then be performed to remove the sacrificial oxide layer, exposing the sidewalls 212A-S, 212B-S, 212C-S and bottom surfaces 212A-B, 212B-B, 212C-B of the trenches 212A, 212B, 212C. Figure 6 The oxidation process and etching process shown can remove the etching process ( Figure 5 ) surface damage caused by.

[0092] Then, if Figure 7 As shown, an oxidation process and a subsequent deposition process may be performed to fully form a shielding dielectric layer 216. The shielding dielectric layer 216 covers the top surface 200T of the epitaxial layer 200 and extends into the trenches 212A, 212B, and 212C, conformally covering the sidewalls 212A-S, 212B-S, and 212C-S and bottom surfaces 212A-B, 212B-B, and 212C-B of the trenches 212A, 212B, and 212C. Figure 6 ).

[0093] In some embodiments, a thermal process may be optionally performed on the shielding dielectric layer 216 to increase the density of the shielding dielectric layer 216 and improve the interface properties between the shielding dielectric layer 216 and the epitaxial layer 200. In some embodiments, the thermal process may be a rapid thermal annealing (RTA) process.

[0094] Then, if Figure 8 As shown, a deposition process and a subsequent planarization process may be performed on the trenches 212A, 212B, and 212C ( Figure 7) to form conductive materials 220A, 220B, and 220C. In some embodiments, conductive materials 220A, 220B, and 220C are formed simultaneously. A top surface 220AT of conductive material 220A, a top surface 220BT of conductive material 220B, and a top surface 220CT of conductive material 220C are all higher than a top surface 200T of epitaxial layer 200 and are aligned with one another. For example, top surface 220AT of conductive material 220A, a top surface 220BT of conductive material 220B, and a top surface 220CT of conductive material 220C are all aligned with a top surface 216T of shielding dielectric layer 216. Furthermore, conductive materials 220A, 220B, and 220C comprise the same material. In some embodiments, conductive materials 220A, 220B, and 220C may be formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide (WSi x In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0095] Then, if Figure 9 As shown, an etch-back process may be performed to remove portions of the conductive materials 220A, 220B, and 220C from the top surfaces 220AT, 220BT, and 220CT of the conductive materials 220A, 220B, and 220C. After the etch-back process, the remaining conductive materials 220A, 220B, and 220C are labeled as conductive materials 220AR, 220BR, and 220CR. The top surfaces 220ART, 220BRT, and 220CRT of the conductive materials 220AR, 220BR, and 220CR may be above the top surface 200T of the epitaxial layer 200. For example, the top surfaces 220ART, 220BRT, and 220CRT of the conductive materials 220AR, 220BR, and 220CR may be higher than the top surface 200T of the epitaxial layer 200 and lower than the top surface 216T of the shielding dielectric layer 216. In some embodiments, the etch-back process may be a selective etching process, such as dry etching.

[0096] Then, if Figure 10As shown, a deposition process can be performed to fully form an oxide layer 222. The oxide layer 222 covers the shielding dielectric layer 216 and the conductive materials 220A, 220B, and 220C. When both the oxide layer 222 and the shielding dielectric layer 216 comprise silicon oxide, the interface between the oxide layer 222 and the shielding dielectric layer 216 is not distinct. In some embodiments, the oxide layer 222 comprises tetraethyl orthosilicate (TEOS) oxide formed using low-pressure chemical vapor deposition (LPCVD). Because the top surfaces 220ART, 220BRT, and 220CRT of the conductive materials 220AR, 220BR, and 220CR are lower than the top surface 216T of the shielding dielectric layer 216, the upper surface 222T1 of the portion of the oxide layer 222 directly above the conductive materials 220AR, 220BR, and 220CR is lower than the upper surface 222T2 of the portion of the oxide layer 222 directly above the shielding dielectric layer 216.

[0097] Then, if Figure 11 As shown, a photolithography process can be performed to form a photoresist pattern PR1 on the epitaxial layer 200 in the third region 420. The photoresist pattern PR1 covers the conductive material 220CR and a portion of the shielding dielectric layer 216 and the oxide layer 222 in the third region 420, and makes the first region 400 and the second region 410 partially oxide layer 222 ( Figure 10 ) is exposed from the photoresist pattern PR1. Then, a selective etching process may be performed to remove the oxide layer 222 and a portion of the shielding dielectric layer 216 ( ) from the top surface 200T of the epitaxial layer 200 and the upper portion of the trenches 212A and 212B close to the top surface 200T of the epitaxial layer 200. Figure 10 ), exposing the upper portions 220AR-1 and 220BR-1 of the conductive materials 220AR and 220BR. After the selective etching process, the shielding dielectric layer 216 remaining in the trenches 212A and 212B in the first and second regions 400 and 410 is labeled as shielding dielectric layers 216AR and 216BR. The shielding dielectric layers 216AR and 216BR surround the lower portions of the conductive materials 220AR and 220BR and expose the sidewalls 212A-S and 212B-S of the upper portion of the trench 212A. The top surfaces 216ART and 216BRT of the shielding dielectric layers 216AR and 216BR may be below the bottom surface 234B of the well region 234. In some embodiments, the selective etching process includes wet etching. After forming the shielding dielectric layers 216AR and 216BR, the photoresist pattern PR1 is removed.

[0098] Then, if Figure 12As shown, an oxidation process may be performed to form a gate dielectric layer 224A in the trench 212A and a gate dielectric layer 224B in the trench 212B. The oxidation process includes oxidizing the sidewalls 212A-S of the upper portion of the trench 212A and the upper portion 220AR-1 ( Figure 11 ) to form a gate dielectric layer 224A and a first electrode 220F1 in the trench 212A. The oxidation process further includes oxidizing the sidewall 212B-S of the upper portion of the trench 212B and the upper portion 220BR-1 ( Figure 11 ) to form a gate dielectric layer 224B and a second electrode 220F2 in the trench 212B. The shielding dielectric layers 216AR and 216BR surround the lower portion of the conductive materials 220AR and 220BR, so that the lower portion of the conductive materials 220AR and 220BR will not be oxidized. When the gate dielectric layers 224A and 224B and the shielding dielectric layers 216AR and 216BR all include silicon oxide, the interface between the gate dielectric layer 224A and the shielding dielectric layer 216AR (or the gate dielectric layer 224B and the shielding dielectric layer 216BR) is not obvious. In addition, the gate dielectric layers 224A and 224B extend to cover the top surface 200T of the epitaxial layer 200 in the first region 400 and the second region 410. The above-mentioned oxidation process also includes forming an oxide layer (not shown) on the oxide layer 222CR in the third region 420.

[0099] In some embodiments of the present invention, the gate dielectric layer 224A does not completely fill the trench 212A. In addition, the gate dielectric layer 224A includes sidewalls 212A-S ( Figure 11 ) and a gate dielectric layer 224A-1 on the upper portion of the first electrode 220F1, and a gate dielectric layer 224A-2 surrounding the upper portion of the first electrode 220F1. Similarly, the gate dielectric layer 224B does not fill the trench 212B. In addition, the gate dielectric layer 224B includes a sidewall 212B-S ( Figure 11 ) and a gate dielectric layer 224B-1 on the upper portion of the second electrode 220F2, and a gate dielectric layer 224B-2 surrounding the upper portion of the second electrode 220F2. In some embodiments, the thickness of the gate dielectric layers 224A-1 and 224A-2 is less than the thickness of the shielding dielectric layers 216AR and 216BR. Compared to the gate dielectric layers 224A-1 and 224B-1 formed by oxidation of the epitaxial layer 200 of silicon carbide, for example, the gate dielectric layers 224A-2 and 224B-2 are made of a conductive material 220AR and 220BR (for example, polysilicon) Figure 11 ) is oxidized, so it has a thicker thickness.

[0100] After the oxidation process, the unoxidized conductive material 220AR in the trench 212A forms a first electrode 220F1, the unoxidized conductive material 220BR in the trench 212B forms a second electrode 220F2, and the unoxidized conductive material 220CR in the trench 212C forms a third electrode 220F3. In some embodiments of the present invention, the first electrode 220F1, the second electrode 220F2, and the third electrode 220F3 extend along a direction 320. In the direction 300, because the gate dielectric layers 224A-2 and 224B-2 are thicker than the gate dielectric layers 224A-1 and 224A-2, the width W1 of the upper portion of the first electrode 220F1 (the upper portion 220AR-1 of the unoxidized conductive material 220A) can be smaller than the width W2 of the lower portion of the first electrode 220F1 (the portion surrounded by the shielding dielectric layer 216AR). Similarly, in direction 300, the width W3 of the upper portion of the second electrode 220F2 (the upper portion 220BR-1 of the unoxidized conductive material 220B) may be smaller than the width W4 of the lower portion of the second electrode 220F2 (the portion surrounded by the shielding dielectric layer 216BR). In some embodiments, width W1 may be equal to width W3, and width W2 may be equal to width W4. Furthermore, in direction 300, the third electrode 220F3 has a uniform width W5. In some embodiments, width W5 may be equal to widths W1 and W3.

[0101] In some embodiments, the oxidation process may be thermal oxidation or other suitable processes. In some embodiments, the gate dielectric layers 224A and 224B may be formed using an oxidation process followed by a deposition process. In some embodiments, the deposition process may be low-pressure chemical vapor deposition (LPCVD) or other suitable processes.

[0102] Then, if Figure 13 As shown, a deposition process and a subsequent planarization process may be performed to form an electrode material 230 on the entire epitaxial layer 200. The electrode material 230 covers the gate dielectric layers 224A and 224B in the first region 400 and the second region 410, and the oxide layer 222CR in the third region 420. Furthermore, the electrode material 230 fills the trenches 212A and 212B ( Figure 12In some embodiments, the electrode material 230 and the first, second, and third electrodes 220F1, 220F2, and 220F3 may comprise the same material, such as polysilicon. In some embodiments, the deposition process may include metalorganic chemical vapor deposition (MOCVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

[0103] Then, if Figure 14 As shown, a patterning process may be performed to remove a portion of the electrode material 230 ( Figure 13 ). The above-mentioned patterning process includes a photolithography process and a subsequent selective etching process. The above-mentioned photolithography process can form a photoresist pattern PR2 above the epitaxial layer 200 in the second area 410. The photoresist pattern PR2 covers the electrode material 230 in the second area 410 and exposes the electrode material 230 in the first area 400 and the third area 420. Afterwards, a selective etching process can be performed to remove the electrode material 230 located on the top surface 200T of the epitaxial layer 200 in the first area 400 and the upper portion of the trench 212A close to the top surface 200T of the epitaxial layer 200, so as to form gates 230AG1 and 230AG2 separated from each other along the direction 300 and extending along the direction 320 on the opposite sidewalls 220F1S of the first electrode 220F1 in the trench 212A. The gates 230AG1 and 230AG2 can extend along the direction 320 to below the bottom surface 234B of the well region 234. In some embodiments, the gates 230AG1 and 230AG2 do not completely fill the trench 212A. In some embodiments, a top portion 220F1 - 1 of the first electrode 220F1 is located above a top surface 230AG2T of the gate 230AG1 and a top surface 230AG2T of the gate 230AG2 .

[0104] like Figure 14 As shown, the selective etching process can also remove the electrode material 230 on the oxide layer 222CR of the third region 420. After the selective etching process, the electrode material 230 can be removed from the epitaxial layer 200 of the second region 410 and the trench 212B ( Figure 12) is formed in the trench 212B. In some embodiments, the gate 230BG fills the remaining space in the trench 212B and extends to cover the second electrode 220F2 and the epitaxial layer 200 outside the trench 212B. Because the electrode material 230, the gate dielectric layer 224A, and the oxide layer 222CR are made of different materials, the selective etching process described above does not remove the gate dielectric layers 224A, 224B, and the oxide layer 222CR. In some embodiments, the selective etching process includes dry etching. After forming the gates 230AG1, 230AG2, and 230BG, the photoresist pattern PR2 is removed.

[0105] Then, Figure 15 、 Figure 16 The formation methods of the source region 236 and the wiring doping region 238 are described separately. Figure 20 The formation positions of the source region 236 and the wiring doping region 238 in the first region 400 are described. In order to describe the configuration of the source region 236 and the wiring doping region 238, Figure 20 The gate dielectric layer 224A- 1 covering the top surface 200T of the epitaxial layer 200 is not shown. Figure 15 、 Figure 16 Cross-sectional views of intermediate structures of a semiconductor device 500 at different positions along direction 310 are shown according to some embodiments of the present invention. Figure 20 To form Figure 1 The diagram is a top view of a semiconductor device 500 at an intermediate stage according to some embodiments of the present invention, showing the arrangement of the source region 236 and the interconnect doping region 238 above the well region 234 . Figure 15 、 Figure 16 The first area 400 shown may correspond to Figure 20 The cross-sectional positions of the AA′ and BB′ lines are used to illustrate the formation of the source regions 236 and the wiring doping regions 238 that are staggered along the direction 310 in the epitaxial layer 200 of the first region 400 .

[0106] like Figure 15 As shown, a photolithography process can be performed to form a photoresist pattern PR3 on the epitaxial layer 200 in the second region 410 and the third region 420, exposing a predetermined formation area of ​​the source region 236 in the first region 400 (corresponding to Figure 20 Then, an ion implantation process is performed to form a source region 236 of the first conductivity type (eg, an N-type source region 236) on the well region 234 of the first region 400. After forming the source region 236, the photoresist pattern PR3 is removed.

[0107] like Figure 16As shown, a photolithography process can be performed to form a photoresist pattern PR4 on the epitaxial layer 200 in the second region 410 and the third region 420, exposing a predetermined formation area of ​​the wiring doping region 238 in the first region 400 (corresponding to Figure 20 It is worth noting that the predetermined formation regions of the source region 236 and the wiring doping region 238 are respectively located in different regions of the epitaxial layer 200 that are staggered along the direction 310 ( Figure 20 ). Then, an ion implantation process is performed to form a wiring doping region 238 having a second conductivity type (eg, a P-type wiring doping region 238) on the well region 234 of the first region 400. After forming the wiring doping region 238, the photoresist pattern PR4 is removed.

[0108] In some embodiments, each source region 236 and each wiring doped region 238 is disposed in the epitaxial layer 200 between two adjacent pairs of gates 230AG1 and 230AG2 along direction 300. In direction 300, no other doped regions exist between opposing sidewalls of each source region 236 and wiring doped region 238 and two adjacent gates 230AG1 and 230AG2 in the two adjacent pairs of gates 230AG1 and 230AG2.

[0109] In some embodiments, Figure 15 、 Figure 16 The process sequence shown can be interchanged, that is, the wiring doping region 238 can be formed first and then the source region 236 can be formed.

[0110] Then, if Figure 17 As shown, a deposition process and a subsequent planarization process may be performed to form an interlayer dielectric layer 240 on the epitaxial layer 200. The interlayer dielectric layer 240 covers the gates 230AG1, 230AG2, 230BG, the gate dielectric layers 224A, 224B and the oxide layer 222CR, and fills the trench 212A ( Figure 16 When the gate dielectric layers 224A, 224B, the oxide layer 222CR, and the interlayer dielectric layer 240 all comprise silicon oxide, the interfaces between the gate dielectric layers 224A, 224B, the oxide layer 222CR, and the interlayer dielectric layer 240 are not obvious. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

[0111] Then, if Figure 18As shown, a photolithography process can be performed to form a photoresist pattern PR5 on the epitaxial layer 200. The photoresist pattern PR5 has an opening 242A that completely exposes the first region 400, and an opening 242B located directly above the gate 230BG in the second region 410. Furthermore, the photoresist pattern PR5 completely covers the epitaxial layer 200 and the interlayer dielectric layer 240 in the third region 420. The opening 242A has a size large enough to completely expose the first region 400, and the opening 242B only needs to be located directly above the gate 230BG. Therefore, a high-resolution mask such as a deep ultraviolet (DUV) mask is not required (for example, a lower-resolution I-line mask is used), which can save photolithography process costs.

[0112] Then, if Figure 19 As shown, an etching process may be performed to remove the opening 242A ( Figure 18 ) The top surface 200T of the epitaxial layer 200 of the first region 400 exposed, as well as the interlayer dielectric layer 240 and the gate dielectric layer 224A on the upper portion of the first trench 212A, are formed in the interlayer dielectric layer 240 to completely expose the first region 400, thereby exposing the top 220F1-1 of the first electrode 220F1, the source region 236, and the wiring doping region 238. The above-mentioned etching process simultaneously forms an opening (contact hole) 244B in a portion of the interlayer dielectric layer 240 directly above the gate 230BG of the second region 410, thereby exposing the gate 230BG. In some embodiments, the above-mentioned etching process includes dry etching and subsequent wet etching. Dry etching can be used to first remove most of the interlayer dielectric layer 240 ( Figure 18), and the remaining interlayer dielectric layer 240 covers the source region 236 and the wiring doping region 238 to prevent the source region 236 and the wiring doping region 238 from being damaged during the dry etching. Thereafter, a portion of the interlayer dielectric layer 240 is removed by wet etching until the top 220F1-1 of the first electrode 220F1, the source region 236, the wiring doping region 238 and the gate 230BG are exposed. After the above etching process, the remaining interlayer dielectric layer 240 in the first region 400 and the remaining gate dielectric layer 224A can together form a gate dielectric layer 241 to form a separate gate structure 230AG together with the gates 230AG1 and 230AG2. The remaining gate dielectric layer 224A can be regarded as (labeled as) the first portion 224AR-1 of the gate dielectric layer 241, and the remaining interlayer dielectric layer 240 can be regarded as (labeled as) the second portion 240AR of the gate dielectric layer 241. Furthermore, the remaining interlayer dielectric layer 240 in the second region 410 and the third region 420 are respectively labeled as interlayer dielectric layers 240BR and 240CR. After forming the gate dielectric layer 241 and the interlayer dielectric layers 240BR and 240CR, the photoresist pattern PR5 is removed.

[0113] Then, if Figure 1 As shown, a deposition process and subsequent annealing process and removal process can be performed to self-align to form a discontinuously distributed metal silicide 246S on the top 220F1-1 of the first electrode 220F1, the source region 236, and the wiring doping region 238 in the opening (contact hole) 244A of the first region 400, and to self-align to form a continuously distributed metal silicide 246G on the gate 230BG in the opening (contact hole) 244B of the second region 410.

[0114] Then, if Figure 1 As shown, a deposition process and a subsequent patterning process may be performed to form an opening (contact hole) 244A ( Figure 19 ) is formed on the top 220F1-1 of the first electrode 220F1, the source region 236, and the wiring doping region 238, and a contact barrier layer (not shown) and a contact conductive layer 248S are formed in the opening (contact hole) 244B ( Figure 19) is formed on the gate 230BG in the first region 400. The contact barrier layer is conformably deposited on the epitaxial layer 200 and the gate dielectric layer 241 in the opening (contact hole) 244S in the first region 400, and in the opening (contact hole) 244B in the second region 410. The contact conductive layer 248S fills the opening (contact hole) 244A and covers the first electrode 220F1, the source region 236, and the wiring doped region 238. Furthermore, the contact conductive layer 248G covers the interlayer dielectric layer 240BR in the second region 410 and fills the remaining space in the opening (contact hole) 244B. The interlayer dielectric layer 240CR in the third region 420 is not covered by the contact barrier layer and the contact conductive layer. After the above process, a source contact 250S (including a metal silicide 246S, a contact barrier layer (not shown) and a contact conductive layer 248S) is formed on the epitaxial layer 200 in the first region 400, and a gate contact 250G (including a metal silicide 246G, a contact barrier layer (not shown) and a contact conductive layer 248G) is formed on the epitaxial layer 200 in the second region 410.

[0115] Subsequent processes may be further performed to form a drain contact (not shown) on the bottom surface 100B of the silicon carbide substrate 100. The drain contact may be electrically connected to the silicon carbide substrate 100. After the above processes, the semiconductor device 500 is formed.

[0116] Some embodiments of the present invention provide semiconductor devices and methods for forming the same. The semiconductor device includes an isolation gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit formed in a cell region (e.g., the first region 400) of an epitaxial layer. The isolation gate trench metal oxide semiconductor field effect transistor unit has a split gate structure. The two gates of the split gate structure (e.g., gates 230AG1 and 230AG2) are formed on opposite side walls of an electrode having a field plate function (also referred to as a source electrode, such as the first electrode 220F1). The split gate structure can further reduce the overall gate-to-drain capacitance (C gd ) and feedback capacitor (C rss =C gd ) to improve the overall power conversion efficiency of the isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit. In addition to reducing the gate-to-drain capacitance (C gd ) to improve the switching characteristics of semiconductor devices, and can make the electric field distribution of the gate dielectric layer near the bottom of the separated gate structure more uniform and increase the breakdown voltage to improve the reliability of the gate dielectric layer. It can also further increase the doping concentration of the epitaxial layer to reduce the on-resistance (R) of the isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit. onsp ).

[0117] In some embodiments, the top surfaces of the two separated gates are lower than the top surface of the epitaxial layer and the top of the source electrode, and are surrounded and covered by the gate dielectric layer. Furthermore, the top of the source electrode is exposed from the separated gate structure. Therefore, without the need for a high-resolution mask lithography process, a metal silicide (e.g., metal silicide 246S) of a source contact (e.g., source contact 250S) can be precisely and self-alignedly formed on the top of the source electrode, the source region, and the top surface of the wiring doped region (i.e., the top surface of the epitaxial layer), thereby further forming a source contact (e.g., source contact 250S) that is precisely connected to the source electrode, the source region, and the wiring doped region. This can avoid contact-trench coverage errors and subsequent photoresist rework issues caused by existing lithography processes, improve the electrical uniformity and reliability of semiconductor devices, and save high-resolution mask and lithography process costs when device density is increased.

[0118] In some embodiments, the ratio of the longitudinal thickness of the gate dielectric layer between the gate and source electrodes (e.g., thickness T1 along direction 320) to the lateral thickness of the gate dielectric layer between the gate and source contact (e.g., thickness T2 along direction 300) can be between 2 and 3. This ensures good electrical isolation between the source contact and the gate and facilitates electrical connection between the source electrode and the source contact. In some embodiments, the source region and the wiring doping region of the isolated gate trench MOSFET cell are staggered along the channel width (e.g., direction 310), further reducing the lateral dimensions of the source contact, thereby increasing device density and reducing device on-resistance.

[0119] Although the present invention is disclosed above with reference to the aforementioned embodiments, they are not intended to limit the present invention. Those skilled in the art may make modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that: include: A silicon carbide substrate having a first region, a second region, and a third region, and having a first conductivity type; an epitaxial layer disposed on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; a first electrode disposed in the epitaxial layer of the first region and extending along a first direction; a split gate structure disposed in the epitaxial layer of the first region, wherein the split gate structure comprises: A first gate and a second gate separated from each other are located on opposite sidewalls of the first electrode, wherein a top of the first electrode is exposed from the separated gate structure; as well as A source contact is disposed on the epitaxial layer in the first region, wherein the source contact covers and is electrically connected to the top of the first electrode.

2. The semiconductor device according to claim 1, wherein The split-gate structure further includes: A gate dielectric layer is disposed in the epitaxial layer in the first region and surrounds the first gate and the second gate, wherein the top of the first electrode protrudes from a top surface of the gate dielectric layer.

3. The semiconductor device according to claim 2, wherein The gate dielectric layer has a first portion located between the first gate and the first electrode, and a second portion located between a first gate top surface of the first gate and the top surface of the gate dielectric layer, wherein the first portion has a first thickness along a second direction, the second portion has a second thickness along the first direction, and the ratio of the second thickness to the first thickness is between 2 and 3.

4. The semiconductor device according to claim 2, wherein Also includes: a well region located in the epitaxial layer, and the well region has a second conductivity type; and A plurality of source regions and a plurality of wiring doping regions are located on the well region in the first region and close to a top surface of the epitaxial layer, wherein the plurality of source regions and the plurality of wiring doping regions are staggered along a third direction and have opposite conductivity types. The source contact covers and electrically connects the plurality of source regions and the plurality of wiring doping regions.

5. The semiconductor device according to claim 4, wherein The source contact has a first sidewall and a second sidewall opposite to each other, the first sidewall is adjacent to the first electrode, and the second sidewall is adjacent to the plurality of source regions and the plurality of wiring doping regions.

6. The semiconductor device according to claim 4, wherein The source contact has a first lower surface, a second lower surface and a third lower surface, the first lower surface is connected to the top of the first electrode, the second lower surface is connected to the gate dielectric layer, and the third lower surface is connected to the multiple source regions and the multiple wiring doping regions.

7. The semiconductor device according to claim 6, wherein The first lower surface and the second lower surface are not coplanar.

8. The semiconductor device according to claim 6, wherein The first lower surface and the third lower surface of the source contact are formed by a first metal silicide.

9. The semiconductor device according to claim 1, wherein The first electrode extends from below the first gate and the second gate to above the first gate and the second gate along the first direction, and is inserted between the first gate and the second gate along a second direction.

10. The semiconductor device according to claim 4, wherein Also includes: a second electrode disposed in the epitaxial layer of the second region and extending along the first direction, wherein the second electrode is electrically connected to the source contact; a third gate disposed in the epitaxial layer of the second region and connected to the split-gate structure, wherein the third gate extends from opposite sidewalls of the second electrode to cover a second electrode top surface of the second electrode and the top surface of the epitaxial layer; a gate contact disposed on the epitaxial layer in the second region, wherein the gate contact covers and is electrically connected to the third gate; and A third electrode is disposed in the epitaxial layer in the third region and extends along the first direction, wherein the third electrode is electrically connected to the source contact.

11. The semiconductor device according to claim 10, wherein Also includes: An interlayer dielectric layer is disposed on the epitaxial layer in the second region and the third region, and exposes the top of the first electrode, the plurality of source regions, the plurality of wiring doping regions and a top surface of the third gate.

12. A method for forming a semiconductor device, characterized in that: include: Providing a silicon carbide substrate having a first region, a second region, and a third region, and having a first conductivity type; growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; forming a first trench in the epitaxial layer of the first region along a first direction; forming a first electrode in the first trench, wherein the first electrode extends along the first direction; forming a first gate and a second gate separated from each other on opposite sidewalls of the first electrode; Fully forming an interlayer dielectric layer; completely removing the interlayer dielectric layer on a top surface of the epitaxial layer in the first region, so that a top portion of the first electrode is exposed from the remaining interlayer dielectric layer; and A source contact is formed on the epitaxial layer in the first region, wherein the source contact covers and is electrically connected to the top of the first electrode.

13. The method for forming a semiconductor device according to claim 12, wherein: Also includes: Before forming the first trench, forming a well region in the epitaxial layer, wherein the well region has a second conductivity type; and After forming the first gate and the second gate, a plurality of source regions and a plurality of wiring doping regions are formed on the well region of the first region, wherein the plurality of source regions and the plurality of wiring doping regions are staggered along a third direction and have opposite conductivity types.

14. The method for forming a semiconductor device according to claim 13, wherein: Before forming the source contact, the plurality of source regions and the plurality of wiring doping regions are exposed from the remaining interlayer dielectric layer.

15. The method for forming a semiconductor device according to claim 14, wherein: Forming the source contact includes: A first metal silicide is formed on the top of the first electrode, the plurality of source regions, and the plurality of wiring doping regions.

16. The method for forming a semiconductor device according to claim 12, wherein: Also includes: During the formation of the first trench, a second trench and a third trench are formed in the epitaxial layer in the second region and the third region respectively along the first direction; forming a first conductive material, a second conductive material, and a third conductive material in the first trench, the second trench, and the third trench, wherein the first conductive material, the second conductive material, and the third conductive material comprise the same material; forming an oxide layer on the third conductive material; and An oxidation process is performed to form a gate dielectric layer in the first trench and the second trench, wherein forming the gate dielectric layer includes partially oxidizing a first upper portion of the first conductive material and a second upper portion of the second conductive material, and the unoxidized first conductive material, the second conductive material, and the third conductive material form the first electrode, a second electrode, and a third electrode, respectively.

17. The method for forming a semiconductor device according to claim 16, wherein: Top surfaces of the first conductive material, the second conductive material, and the third conductive material are located above the top surface of the epitaxial layer.

18. The method for forming a semiconductor device according to claim 16, wherein: Also includes: After forming the first electrode, the second electrode, and the third electrode, an electrode material is formed entirely on the epitaxial layer, wherein the electrode material fills the first trench and the second trench; and A patterning process is performed to remove a portion of the electrode material above the epitaxial layer in the first region and the third region to form the first gate and the second gate in the first trench and to form a third gate in the second trench.

19. The method for forming a semiconductor device according to claim 18, wherein: The top of the first electrode is located above a first gate top surface of the first gate and a second gate top surface of the second gate.

20. The method for forming a semiconductor device according to claim 18, wherein: Also includes: During the complete removal of the interlayer dielectric layer on the top surface of the epitaxial layer in the first region, a portion of the interlayer dielectric layer on the third gate is removed; and During the formation of the source contact, a gate contact is formed on the third gate.

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