Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate, a first middle-high voltage element region and a low-voltage element region are defined on the substrate, the first middle-high voltage element region comprises a first gate contact and a first source / drain contact, and the low-voltage element region comprises a second gate contact and a second source / drain contact. The low-voltage element region comprises two second source / drain contacts and a second gate contact, the second gate contact is located between the two second source / drain contacts and directly touches the two second source / drain contacts, the first lead layer is located in the first middle-high voltage element region, the first lead layer does not extend into the low-voltage element region, and the second lead layer does not extend into the second middle-high voltage element region. And the second lead layer is positioned above the first lead layer and spans the first middle-high voltage element region and the low-voltage element region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a structure generated at the junction of a medium- and high-voltage component area and a low-voltage component area in the semiconductor manufacturing technology. Background Art

[0002] In semiconductor manufacturing, nanometers are often used to describe the precision of a nanofabrication process. For example, a 14nm process represents a minimum line width of 14nm. As manufacturing technology advances, the line width of nanofabrication processes also decreases.

[0003] However, even with the gradual advancement of nanofabrication technology, not all components are suitable for high-precision nanofabrication. For example, if the size of a component does not match the precision of the nanofabrication process, not only will the yield of the component decrease, but it will also increase costs. Therefore, to accommodate components of different sizes or precision, different nanofabrication processes with different precision are used to form different components.

[0004] On a single chip, components of varying precision may coexist in different regions, each fabricated using nanofabrication processes with varying degrees of precision. Therefore, structural issues may arise more easily at the interface between these regions. Summary of the Invention

[0005] The present invention provides a semiconductor structure, comprising a substrate, on which a first medium- and high-voltage component region and a low-voltage component region are defined, adjacent to each other, the first medium- and high-voltage component region comprising a first gate contact and a first source / drain contact, the low-voltage component region comprising two second source / drain contacts and a second gate contact, wherein the second gate contact is located between the two second source / drain contacts and directly touches the two second source / drain contacts, a first conductor layer, located in the first medium- and high-voltage component region and electrically connected to the first gate contact or the first source / drain contact, wherein the first conductor layer does not extend into the low-voltage component region, and a second conductor layer, located above the first conductor layer and spanning the first medium- and high-voltage component region and the low-voltage component region, wherein the second conductor layer is electrically connected to the first conductor layer.

[0006] The present invention also provides a method for manufacturing a semiconductor structure, including providing a substrate, on which a first medium- and high-voltage component region and a low-voltage component region are defined, adjacent to each other, the first medium- and high-voltage component region including a first gate contact and a first source / drain contact, and the low-voltage component region including two second source / drain contacts and a second gate contact, wherein the second gate contact is located between the two second source / drain contacts and directly touches the two second source / drain contacts to form a first conductor layer located in the first medium- and high-voltage component region and electrically connected to the first gate contact or the first source / drain contact, wherein the first conductor layer does not extend into the low-voltage component region, and a second conductor layer is formed, located above the first conductor layer and spans the first medium- and high-voltage component region and the low-voltage component region, wherein the second conductor layer is electrically connected to the first conductor layer.

[0007] The applicant has found that with the advancement of technology, the size of semiconductor components is getting smaller and smaller, especially at the junction of the medium and high voltage component area and the low voltage component area, various structural problems are prone to occur. For example, in the existing 22 nanometer or 28 nanometer manufacturing process, the junction of the medium and high voltage component area and the low voltage component area does not cause dielectric layer breakdown problems, but as the manufacturing process advances to below 17 nanometers, the conductor layer located in the medium and high voltage component area is too close to the components in the low voltage component area, which may affect the quality of other components due to the dielectric layer breakdown problem. Therefore, the present invention solves this problem. Specifically, the semiconductor structure is designed so that the first conductor layer in the medium and high voltage component area does not extend above the low voltage component area, and the second conductor layer in the medium and high voltage component area extends above the low voltage component area. In this way, without changing the manufacturing process conditions and subject to the limitations of the manufacturing process, the dielectric layer breakdown problem caused by the conductor layer in the medium and high voltage component area being too close to the components in the low voltage component area can be avoided, thereby improving the quality of the components. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To facilitate understanding, the present disclosure is accompanied by reference to the accompanying drawings and detailed descriptions. The present disclosure is described in detail using the specific embodiments described herein and the accompanying drawings, thereby illustrating the principles of operation of the present disclosure. Furthermore, for clarity, the features in the drawings may not be drawn to scale, and the dimensions of some features in certain drawings may be intentionally exaggerated or reduced.

[0009] Figure 1 A schematic top view of a junction between a high-voltage component area and a low-voltage component area in the first embodiment of the present invention;

[0010] Figure 2 This is a cross-sectional view of a junction between a medium- and high-voltage component area and a low-voltage component area according to the first embodiment of the present invention, especially along Figure 1 The cross-sectional structure obtained by the section line AA';

[0011] Figure 3 A schematic top view of a junction between a high-voltage component area and a low-voltage component area in a second embodiment of the present invention;

[0012] Figure 4 This is a cross-sectional view of a junction between a middle and high voltage component area and a low voltage component area according to the second embodiment of the present invention, especially along Figure 3 The cross-sectional structure obtained by the section line BB'.

[0013] Explanation of symbols

[0014] 1: Base

[0015] 10: Medium and high voltage component area (first medium and high voltage component area)

[0016] 12: Interlayer dielectric layer

[0017] 14: Dielectric layer

[0018] 20: Low voltage component area

[0019] 30: Medium and high voltage component area (second medium and high voltage component area)

[0020] B1: Boundary Line

[0021] B2: Boundary Line

[0022] BS1: bottom surface

[0023] BS2: Bottom

[0024] D: Diffusion zone

[0025] F: Fin structure

[0026] G1: Gate structure (first gate structure)

[0027] G2: Gate structure (second gate structure)

[0028] M1: First conductor layer

[0029] M2: Second conductor layer

[0030] MD1: First source / drain contact

[0031] MD2: Second source / drain contact

[0032] MP1: First gate contact

[0033] MP2: Second gate contact

[0034] P: Path

[0035] TS1: Top surface

[0036] V0: contact structure

[0037] V1: Contact structure DETAILED DESCRIPTION

[0038] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.

[0039] For ease of explanation, the drawings of this invention are merely illustrative to facilitate understanding of the present invention. The detailed scales may be adjusted based on design requirements. The vertical relationships of relative components depicted in the drawings herein are understood by those skilled in the art to refer to the relative positions of the objects. Therefore, the same components can be reversed to present the same components, and this is fully understood within the scope of this specification. This is further clarified.

[0040] Although the present invention uses terms such as first, second, and third to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not imply or represent any preceding ordinal number of the elements, nor do they represent the order in which one element is arranged relative to another element, or the order in which they are manufactured. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

[0041] The terms "about" or "substantially" mentioned herein generally mean within 20% of a given value or range, such as within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even if "about" or "substantially" is not specifically stated, the meaning of "about" or "substantially" may still be implied.

[0042] The terms "couple," "coupled," and "electrically connected" as used herein include any direct and indirect electrical connection means. For example, if a first component is described as being coupled to a second component, this means that the first component may be directly electrically connected to the second component or indirectly electrically connected to the second component through other devices or connection means.

[0043] Although the invention is described below by way of specific embodiments, the principles of the invention may also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details may be omitted, and the omitted details are within the knowledge of a person of ordinary skill in the art.

[0044] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic top view of a junction between a high-voltage device region and a low-voltage device region in the first embodiment of the present invention is shown. Figure 2 A cross-sectional view of a junction between a medium- and high-voltage component region and a low-voltage component region according to a first embodiment of the present invention is shown, particularly along the Figure 1 The cross-sectional structure obtained by the section line A-A' in FIG. Figure 1 and Figure 2 As shown, the semiconductor structure 10 of the present invention includes a medium- and high-voltage component region 10, a low-voltage component region 20, and another medium- and high-voltage component region 30. The low-voltage component region 20 is located between the medium- and high-voltage component regions 10 and 30. A boundary B1 is defined between the medium- and high-voltage component regions 10 and 20, while a boundary B2 is defined between the medium- and high-voltage component regions 30 and 20. The medium- and high-voltage component regions 10, 30, and 20 differ in the operating voltages of the components contained therein. Generally speaking, taking a display chip as an example, the low-voltage component region 20 includes logic circuits, for example, whose operating voltage is below 5 volts, and preferably within 1.5 volts. Conversely, the electronic components contained within the medium- and high-voltage component regions 10 and 30 have operating voltages greater than 5 volts, typically above 10 volts. For example, the driver components in a display chip require a higher voltage to drive their components; these components are considered medium- and high-voltage components of the present invention.

[0045] In this embodiment, the medium and high voltage component area 10 and the medium and high voltage component area 30 may have the same or similar structure. Figure 1 For example, the medium-high voltage component area 10 and the medium-high voltage component area 30 have mutually symmetrical structures, but the components therein have the same material and manufacturing method. Therefore, the medium-high voltage component area 10 and the low voltage component area 20 are mainly described in the following paragraphs, and the medium-high voltage component area 30 is not described repeatedly because it has the same characteristics as the medium-high voltage component area 10.

[0046] As described in the prior art, different components on the same chip may be formed using nanofabrication processes with different precisions due to their different sizes or applications. In this embodiment, the medium- and high-voltage components or other related electronic components (such as conductive lines or trenches) within the medium- and high-voltage component region 10 are formed using, for example, a 17-nanometer fabrication process, while the various low-voltage components (such as logic circuits) within the low-voltage component region 20 require higher nanometer precision and are formed using, for example, a 14-nanometer fabrication process. However, it should be noted that the aforementioned 17-nanometer or 14-nanometer fabrication processes are merely examples of the present invention and are not limited thereto.

[0047] As the nanometer precision of semiconductor manufacturing processes increases, the size of components becomes smaller and smaller, and components can also develop towards three-dimensional structures to increase the density per unit area. In this embodiment, the low-voltage component area 20 includes multiple fin-shaped structures F to form a three-dimensional structure to reduce the size of the components. The medium and high voltage component area 10 needs to withstand higher operating voltages, and three-dimensional structures such as fin-shaped structures are easily penetrated under high operating voltages. Therefore, the medium and high voltage component area 10 mainly forms a planar structure. In other words, Figure 1 The top view of the semiconductor structure can be viewed as the boundary between two regions including planar electronic components and a region including three-dimensional electronic components, wherein the two regions are formed by different nanometer precision manufacturing processes.

[0048] Please continue to refer to Figure 1 and Figure 2 The medium and high voltage device area 10 includes medium and high voltage devices, such as a substrate 1, on which there are an interlayer dielectric layer 12, a diffusion region D, a gate structure G1, a gate contact MP1, and a source / drain contact MD1. The low voltage device area 20 also includes various devices, such as a substrate 1, an interlayer dielectric layer 12, a fin structure F, a gate structure G2, a gate contact MP2, and a source / drain contact MD2. Figure 2 As can be seen, the gate structure G1, gate structure G2, gate contact MP1, gate contact MP2, source / drain contact MD1, and source / drain contact MD2 are all located within an interlayer dielectric layer 12. The material of the interlayer dielectric layer 12 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. Furthermore, in this embodiment, the top surfaces of the gate contact MP1 and source / drain contact MD1 in the mid- and high-voltage device region 10 are aligned with the top surfaces of the gate contact MP2 and source / drain contact MD2 in the low-voltage device region 20, but the present invention is not limited thereto.

[0049] In more detail, the formation of a high voltage transistor is described as an example. Figure 1 and Figure 2As shown, high-voltage transistors are formed in the medium- and high-voltage component regions 10 and 30. These two high-voltage transistors can be treated as two independent components. The low-voltage component region 20 between the medium- and high-voltage component regions 10 and 30 can serve as a peripheral region for the medium- and high-voltage component regions to accommodate some dummy patterns and mitigate exposure issues caused by pattern density differences. Alternatively, low-voltage electronic components can be formed in the low-voltage component region 20. All of these fall within the scope of the present invention.

[0050] In this embodiment, the substrate 1 is, for example, a silicon substrate. The diffusion region D in the mid- and high-voltage component region 10 and the fin structure F in the low-voltage component region 20 are made of, for example, silicon and are part of the substrate 1. The diffusion region D is a planar structure, while the fin structure F is a three-dimensional structure. The gate structure G1 and the gate structure G2, for example, polysilicon gates or metal gates, span the diffusion region D and the fin structure F, forming various semiconductor devices. In this embodiment, the gate structure G1 spans the diffusion region D in the mid- and high-voltage component region 10 to form a high-voltage transistor structure. Furthermore, in this embodiment, the gate pattern G2 also spans the fin structure F in the low-voltage component region 20. As described above, the gate pattern G2 formed in the low-voltage component region 20 can serve as a dummy pattern for the gate structure G1 in the mid- and high-voltage component region 10, thereby reducing the difference in pattern density between different regions. Alternatively, in other embodiments, the gate structure G2 in the low-voltage component region 20 can be used to form other electronic devices, rather than serving as a dummy pattern for the gate structure G1. This also falls within the scope of the present invention.

[0051] The material of the gate contact MP1, gate contact MP2, source / drain contact MD1, and source / drain contact MD2 is, for example, a metal. In this embodiment, the metals include, but are not limited to, tungsten, cobalt, copper, aluminum, gold, silver, and the like. The gate contact MP1 is located in the medium- and high-voltage component region 10, and the gate contact MP2 is located in the low-voltage component region 20. They are respectively used to electrically connect the gate structures G1 and G2 and other subsequent circuits. Therefore, the gate contacts MP1 and MP2 are respectively located above the gate structures G1 and G2. The source / drain contact MD1 is located on the diffusion region D and is used to connect to the source / drain region of the high-voltage transistor. The source / drain contact MD2 is located on the fin structure F. The gate contacts MP1 and MP2 and the source / drain contacts MD1 and MD2 are all used to connect to other circuit layers that are subsequently formed.

[0052] It is worth noting that as the size of semiconductor devices continues to shrink, the sizes of the aforementioned components, including the gate structures G1, G2, gate contacts MP1, MP2, and source / drain contacts MD1, MD2, have also shrunk. In this case, the difficulty of the overlapping and aligning steps of the gate contact MP1 and the gate structure G1 increases. In other words, because the gate contact MP1 must precisely overlap the gate structure G1 to electrically connect them, this overlapping step becomes increasingly difficult as the sizes of the gate contact MP1 and the gate structure G1 decrease. Furthermore, the size of the gate contact MP1 (the lateral dimension in the cross-sectional view) is approaching the exposure limit of current equipment, making it difficult to achieve a sufficient height for the gate contact MP1. This would result in an excessively large aspect ratio for the gate contact MP1, leading to manufacturing defects (such as cracking of the gate contact MP1 due to difficulty in filling the gap). In this embodiment, in a 17nm process, the height of the gate contact MP1 can only be approximately 450 angstroms. If the height of the gate contact MP1 is too high, the aforementioned problem of insufficient gap filling and breakage of the gate contact MP1 due to the large aspect ratio will easily occur. To illustrate, in other larger process sizes, such as 22nm or 28nm processes, after the gate contact MP1 is formed on the gate structure G1, a first conductive layer M1 can be directly formed to connect to the gate contact MP1. However, when the process size is reduced to below 17nm, due to the height limitation of the gate contact MP1, the first conductive layer M1 cannot be directly formed on the gate contact MP1. Otherwise, the first conductive layer M1 will directly contact other adjacent contact structures, such as the source / drain contacts MD1.

[0053] In order to solve the above problems, in addition to forming the gate contact MP1, in this embodiment, a contact structure V0 is also formed on the gate contact MP1 and the source / drain contact MD1, and then a first conductive layer M1 is formed above the contact structure V0. The material of the contact structure V0 and the first conductive layer M1 described here is, for example, tungsten, cobalt, copper, aluminum, gold, silver and other metals, but not limited thereto. The function of the contact structure V0 and the first conductive layer M1 is to connect the high-voltage transistor element below to other elements formed above. In other words, in order to overcome the problem of insufficient height of the gate contact MP1, two overlapping contact structures (i.e., the gate contact MP1 and the contact structure V0) are used to replace the original single contact structure. In addition, the contact structure V0 and the first conductive layer M1 are located in a dielectric layer 14. The dielectric layer 14 is, for example, an extremely low dielectric constant (ULK) layer, and its dielectric constant is preferably lower than 2.9, but not limited thereto. Commonly used ULK materials may include Black Diamond (a carbon-doped silicon oxide low-k material launched by Applied Materials), MSQ (methylsilsesquioxane), porous SiLK (a low-k material developed by Dow Chemical), etc., but are not limited thereto.

[0054] However, the height of the contact structure V0 is also limited by the manufacturing process. For example, in the present embodiment, the height of the contact structure V0 is about 480 angstroms, and the first conductor layer M1 is formed on the contact structure V0, and a portion of the first conductor layer M1 extends laterally from the medium and high voltage component area 10 to the low voltage component area 20. Therefore, the bottom surface BS1 of the first conductor layer M1 in the low voltage component area 20 is only about 480 angstroms away from the top surface TS1 of the source / drain contact MD1 below (the same as the height of the contact structure V0). In this case, the applicant discovered another problem, that is, when the high voltage semiconductor element is operating, it may produce a dielectric breakdown (TDDB) effect, that is, the current may penetrate the dielectric layer 14 and flow to the source / drain contact MD below, causing the circuit to be unable to connect to the intended element. For example, in the present embodiment, if Figure 2 As shown, if the source / drain contact MD2 in the low-voltage component area 20 is connected to the gate contact MP2, the current may flow through the path P from the high-voltage semiconductor component in the medium- and high-voltage component area 10 to the component in the low-voltage component area 20, and then flow to another high-voltage semiconductor component in the medium- and high-voltage component area 30. Therefore, the high-voltage semiconductor components in two different areas will be affected by each other, causing electrical errors and component damage.

[0055] It is worth noting that the present invention Figure 1 The device pattern in the low voltage device area 20 may be changed according to the needs, not limited to Figure 1 The structure shown. Figure 1Although the source / drain contact MD2 is designed to be connected to the gate contact MP2, this pattern structure is merely one example of the present invention. In other embodiments of the present invention, other components, such as transistors, may be formed within the low-voltage component region 20, and the source / drain contact MD2 and the gate contact MP2 may not be in contact with each other. However, even if the source / drain contact MD2 and the gate contact MP2 are not in contact with each other, the current within the medium- and high-voltage component region 10 may still pass through the first conductive layer M1, through the dielectric layer 14, and be transferred to the components within the low-voltage component region 20, thereby affecting the quality of the components within the low-voltage component region.

[0056] The applicant discovered Figure 2 The structure has the above-mentioned probability of defects, especially at the junction of the medium and high voltage component area and the low voltage component area. Therefore, in order to improve Figure 2 The applicant proposed another structure, please refer to Figure 3 and Figure 4 , Figure 3 A schematic top view of a junction between a high-voltage device region and a low-voltage device region in a second embodiment of the present invention is shown. Figure 4 A cross-sectional view of a junction between a middle and high voltage component region and a low voltage component region according to a second embodiment of the present invention is shown, particularly along the Figure 3 The cross-sectional structure obtained by cross section BB' in FIG. In this embodiment, since it is known that the bottom surface BS1 of the first conductive layer M1 is too close to the top surface TS1 of the underlying source / drain contacts MD, which may cause dielectric breakdown (TDDB), the first conductive layer M1 is not extended into the low-voltage component area 20. Contact structure V1 and second conductive layer M2 are formed on the first conductive layer M1. If device configuration requires extension into the low-voltage component area 20, the second conductive layer M2 is extended into the low-voltage component area 20. In other words, the bottom surface BS2 of the second conductive layer M2 is sufficiently far from the top surface TS1 of the underlying source / drain contacts MD, at least 700 angstroms, to minimize the risk of dielectric breakdown, which could cause unintended current flow to devices within the low-voltage component area 20. This effectively addresses the dielectric breakdown issue at the interface between the mid- and high-voltage component areas and the low-voltage component area, improving component quality, even at a 17nm manufacturing process.

[0057] Based on the above description and drawings, the present invention provides a semiconductor structure, including a substrate 1, on which a first medium- and high-voltage device region 10 and a low-voltage device region 20 are defined, adjacent to each other, the first medium- and high-voltage device region 10 including a first gate contact MP1 and a first source / drain contact MD1, the low-voltage device region 20 including two second source / drain contacts MD2 and a second gate contact MP2, wherein the second gate contact MP2 is located between the two second source / drain contacts MD2 and directly touches the two second source / drain contacts MD2, a first wire layer M1 is located in the first medium- and high-voltage device region 10 and is electrically connected to the first gate contact MP1 or the first source / drain contact MD1, wherein the first wire layer M1 does not extend into the low-voltage device region 20, and a second wire layer M2 is located above the first wire layer M1 and spans the first medium- and high-voltage device region 10 and the low-voltage device region 20, wherein the second wire layer M2 is electrically connected to the first wire layer M1.

[0058] In some embodiments of the present invention, the first medium / high voltage device region 10 further includes a first gate structure G1 spanning a diffusion region D, wherein the first gate contact MP1 is electrically connected to the first gate structure G1 , and the first source / drain contact MD1 is electrically connected to the diffusion region D.

[0059] In some embodiments of the present invention, the low-voltage device region 20 further includes a second gate structure G2 spanning across a plurality of fin structures F, and the second source / drain contacts are electrically connected to the plurality of fin structures.

[0060] In some embodiments of the present invention, a top surface of the second gate contact MP2 is flush with top surfaces of the two second source / drain contacts MD2 .

[0061] In some embodiments of the present invention, within the low-voltage device area 20, no conductive material layer is included at the same horizontal plane as the first wire layer M1 (meaning that the first wire layer M1 will not extend to the low-voltage device area 20, and the low-voltage device area 20 will not include other wire materials located at the horizontal plane of the first wire layer M1).

[0062] In some embodiments of the present invention, the second conductive line layer M2 extends into the low-voltage device region 20 and is located directly above at least one second source / drain contact MD2 .

[0063] In some embodiments of the present invention, within the low-voltage device region 20, a distance in a vertical direction between a bottom surface BS2 of the second conductive layer M2 and a top surface TS1 of the second source / drain contact MD2 is greater than 700 angstroms (according to experiments conducted by the applicant, a distance greater than 700 angstroms can avoid dielectric layer breakdown).

[0064] In some embodiments of the present invention, a second medium- and high-voltage component area 30 is further included, wherein the low-voltage component area 20 is located between the first medium- and high-voltage component area 10 and the second medium- and high-voltage component area 30, and the low-voltage component area 20 is directly adjacent to the first medium- and high-voltage component area 10 and the second medium- and high-voltage component area 30.

[0065] In some embodiments of the present invention, the components included in the second medium- and high-voltage component area 30 and the components included in the first medium- and high-voltage component area 10 are arranged in a mirror-image manner.

[0066] In some embodiments of the present invention, from a cross-sectional view, the first source / drain contact MD1 in the first medium / high voltage component region 10 is directly adjacent to one of the second source / drain contacts MD2 in the low voltage component region 20 (that is, from a cross-sectional view, no other components are included between the first source / drain contact MD1 and the second source / drain contact MD2 on both sides of the boundary line B1).

[0067] The present invention further provides a method for manufacturing a semiconductor structure, including providing a substrate 1, on which a first medium- and high-voltage device region 10 and a low-voltage device region 20 are defined adjacent to each other, the first medium- and high-voltage device region 10 including a first gate contact MP1 and a first source / drain contact MD1, the low-voltage device region 20 including two second source / drain contacts MD2 and a second gate contact MP2, wherein the second gate contact MP2 is located between the two second source / drain contacts MD2 and directly touches the two second source / drain contacts MD2, forming a first wire layer M1, located in the first medium- and high-voltage device region 10, and electrically connected to the first gate G1 contact or the first source / drain contact MD1, wherein the first wire layer M1 does not extend into the low-voltage device region 20, and forming a second wire layer M2, located above the first wire layer M1 and spanning the first medium- and high-voltage device region 10 and the low-voltage device region 20, wherein the second wire layer M2 is electrically connected to the first wire layer M1.

[0068] In summary, the applicant has found that with the advancement of technology, the size of semiconductor components is getting smaller and smaller, especially at the junction of the medium and high voltage component area and the low voltage component area, various structural problems are prone to occur. For example, in the existing 22 nanometer or 28 nanometer manufacturing process, the junction of the medium and high voltage component area and the low voltage component area does not cause dielectric layer breakdown problems, but as the manufacturing process advances to below 17 nanometers, the wire layer located in the medium and high voltage component area is too close to the components in the low voltage component area, which may affect the quality of other components due to the dielectric layer breakdown problem. Therefore, the present invention solves this problem. Specifically, the semiconductor structure is designed so that the first wire layer in the medium and high voltage component area does not extend above the low voltage component area, and the second wire layer in the medium and high voltage component area extends above the low voltage component area. In this way, without changing the manufacturing process conditions and subject to the limitations of the manufacturing process, the dielectric layer breakdown problem caused by the wire layer in the medium and high voltage component area being too close to the components in the low voltage component area can be avoided, thereby improving the quality of the components.

[0069] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising: a substrate having a first medium- and high-voltage device region and a low-voltage device region defined thereon, the first medium- and high-voltage device region including a first gate contact and a first source / drain contact, and the low-voltage device region including two second source / drain contacts and a second gate contact, wherein the second gate contact is located between the two second source / drain contacts and directly contacts the two second source / drain contacts; a first conductive line layer located in the first medium- and high-voltage device region and electrically connected to the first gate contact or the first source / drain contact, wherein the first conductive line layer does not extend into the low-voltage device region; and The second wire layer is located above the first wire layer and spans the first medium- and high-voltage component area and the low-voltage component area, wherein the second wire layer is electrically connected to the first wire layer.

2. The semiconductor structure as claimed in claim 1, wherein the first medium- and high-voltage device region further comprises a first gate structure spanning a diffusion region, wherein the first gate contact is electrically connected to the first gate structure, and the first source / drain contact is electrically connected to the diffusion region. 3 . The semiconductor structure as claimed in claim 1 , wherein the low-voltage device region further comprises a second gate structure spanning a plurality of fin structures, and the second source / drain contact is electrically connected to the plurality of fin structures. 4 . The semiconductor structure of claim 1 , wherein a top surface of the second gate contact is flush with top surfaces of the two second source / drain contacts. 5 . The semiconductor structure as claimed in claim 1 , wherein in the low-voltage device region, no conductive material layer is included at the same level as the first conductive line layer. 6 . The semiconductor structure as claimed in claim 1 , wherein the second conductive line layer extends into the low-voltage device region and is located directly above at least one of the second source / drain contacts. 7 . The semiconductor structure of claim 6 , wherein in the low-voltage device region, a vertical distance between a bottom surface of the second conductive line layer and a top surface of the second source / drain contact is greater than 700 angstroms.

8. The semiconductor structure as described in claim 1 further includes a second medium-high voltage component area, wherein the low voltage component area is located between the first medium-high voltage component area and the second medium-high voltage component area, and the low voltage component area is directly adjacent to the first medium-high voltage component area and the second medium-high voltage component area. 9 . The semiconductor structure of claim 8 , wherein the devices included in the second medium- and high-voltage device region and the devices included in the first medium- and high-voltage device region are arranged in a mirror-image arrangement. 10 . The semiconductor structure of claim 1 , wherein from a cross-sectional view, the first source / drain contact in the first medium- and high-voltage device region is directly adjacent to one of the second source / drain contacts in the low-voltage device region.

11. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein a first medium- and high-voltage device region and a low-voltage device region are defined on the substrate, the first medium- and high-voltage device region including a first gate contact and a first source / drain contact, and the low-voltage device region including two second source / drain contacts and a second gate contact, wherein the second gate contact is located between the two second source / drain contacts and directly contacts the two second source / drain contacts; forming a first conductive line layer located in the first medium- and high-voltage device region and electrically connected to the first gate contact or the first source / drain contact, wherein the first conductive line layer does not extend into the low-voltage device region; as well as A second wire layer is formed, located above the first wire layer and spanning the first medium- and high-voltage component area and the low-voltage component area, wherein the second wire layer is electrically connected to the first wire layer.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein the first medium- and high-voltage device region further comprises a first gate structure crossing a diffusion region, wherein the first gate contact is electrically connected to the first gate structure, and the first source / drain contact is electrically connected to the diffusion region. 13 . The method for fabricating a semiconductor structure according to claim 11 , wherein the low-voltage device region further comprises a second gate structure spanning a plurality of fin structures, and the second source / drain contact is electrically connected to the plurality of fin structures. 14 . The method for fabricating a semiconductor structure according to claim 11 , wherein a top surface of the second gate contact is flush with top surfaces of the two second source / drain contacts. 15 . The method for manufacturing a semiconductor structure according to claim 11 , wherein in the low-voltage device region, no conductive material layer is included at the same level as the first conductive line layer. 16 . The method for fabricating a semiconductor structure according to claim 11 , wherein the second conductive line layer extends into the low-voltage device region and is located directly above at least one of the second source / drain contacts. 17 . The method for fabricating a semiconductor structure according to claim 16 , wherein in the low-voltage device region, a vertical distance between a bottom surface of the second conductive line layer and a top surface of the second source / drain contact is greater than 700 angstroms.

18. The method for manufacturing a semiconductor structure as described in claim 11 further includes defining a second medium- and high-voltage device region, wherein the low-voltage device region is located between the first medium- and high-voltage device region and the second medium- and high-voltage device region, and the low-voltage device region is directly adjacent to the first medium- and high-voltage device region and the second medium- and high-voltage device region. 19 . The method for fabricating a semiconductor structure according to claim 18 , wherein the devices included in the second medium- and high-voltage device region and the devices included in the first medium- and high-voltage device region are arranged in a mirror-image arrangement. 20 . The method for fabricating a semiconductor structure according to claim 11 , wherein from a cross-sectional view, the first source / drain contact in the first medium- and high-voltage device region is directly adjacent to one of the second source / drain contacts in the low-voltage device region.

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