Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a base, an insulating layer located on the surface of the base and a semiconductor layer located on the surface of the insulating layer, and the semiconductor layer comprises a gate region and a plurality of channel regions surrounding the gate region; forming a first opening exposing the surface of the insulating layer and the surface of the side wall of each channel region in the gate region; forming a gate structure in the first opening, wherein the gate structure is in contact with the side wall of each channel region; forming a plurality of second openings exposing the surface of the insulating layer in the semiconductor layer; and forming a source-drain doping layer in each second opening, wherein each source-drain doping layer is located between two adjacent channel regions. On one hand, the grid structure, the source-drain doping layer and the well doping region are led out through the conductive plug, part of the insulating layer does not need to be removed, and the large height difference between different circuit modules is avoided; and on the other hand, the conductive plug is located on the gate structure, the source-drain doped layer and the well doped region, so that the area occupied by the conductive plug is reduced, and the design flexibility of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As advanced semiconductor manufacturing processes have fully transitioned to sub-28nm processes, traditional process devices are facing issues such as small feature sizes, thin gate oxide layers, and susceptibility to short channel effects and gate leakage. Modern semiconductor manufacturing processes have developed two major routes: Fin Field-Effect Transistor (FINFET) and Fully Depleted Silicon-On-Insulator (FDSOI) technology.

[0003] Compared to bulk silicon-based metal-oxide semiconductor field-effect transistors or fin field-effect transistors, fully depleted silicon-on-insulator transistors can save up to 35% of power consumption and improve peak performance by 50% while maintaining the same performance. Their low drain / source parasitic capacitance, lower device delay and dynamic power consumption, and independent threshold voltage dependence on gate bias make them more suitable for low-power applications. Furthermore, fully depleted silicon-on-insulator transistors have a flexible and adjustable back bias voltage, which can significantly improve chip performance.

[0004] However, there are still many problems with the current fully depleted silicon-on-insulator transistor technology. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which increases the flexibility of device design, reduces the device area, and reduces the preparation cost.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, wherein the substrate comprises: a base, an insulating layer located on the surface of the base, and a semiconductor layer located on the surface of the insulating layer, wherein the semiconductor layer comprises a gate region and a plurality of channel regions surrounding the gate region; a gate structure located in the gate region and on the surface of the insulating layer, wherein the gate structure is in contact with the sidewalls of each of the channel regions; and a plurality of source-drain doped layers located in the semiconductor layer and on the surface of the insulating layer, wherein each of the source-drain doped layers is located between two adjacent channel regions.

[0007] Optionally, the number of the source-drain doping layers is 4; the number of the channel regions is 4.

[0008] Optionally, the projection pattern of the gate structure on the substrate surface includes a quadrilateral.

[0009] Optionally, the gate structure, the source-drain doped layer and the channel region are arranged in an array.

[0010] Optionally, the gate structure includes: a gate oxide layer in contact with the side wall surface of the channel region, a gate dielectric layer located on the surface of the gate oxide layer, and a gate layer located on the surface of the gate dielectric layer; the gate dielectric layer material includes: a high dielectric material with N-type doped ions or a high dielectric material with P-type doped ions; the gate layer material includes polysilicon with N-type doped ions or with P-type doped ions.

[0011] Optionally, the material of the source / drain doping layer includes polysilicon, and the doping ions of the source / drain doping layer include N-type doping ions or P-type doping ions.

[0012] Optionally, it also includes: a well-doped region located in the semiconductor layer, the well-doped region surrounding each of the source-drain doped layers and each of the channel regions; a first isolation layer located between the well-doped region and the channel region, and between the well-doped region and the source-drain doped layers; and a third conductive plug located on the well-doped region.

[0013] Optionally, the method further includes: a second isolation layer located in the semiconductor layer, wherein the second isolation layer surrounds the well doping region.

[0014] Optionally, the method further includes: a first conductive plug located on the surface of each of the source and drain doped layers; and a second conductive plug located on the surface of the gate structure.

[0015] Correspondingly, the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base, an insulating layer located on the surface of the base, and a semiconductor layer located on the surface of the insulating layer, the semiconductor layer including a gate region and a plurality of channel regions surrounding the gate region; forming a first opening in the gate region to expose the surface of the insulating layer and the sidewall surfaces of each of the channel regions; forming a gate structure in the first opening, the gate structure contacting the sidewalls of each of the channel regions; forming a plurality of second openings in the semiconductor layer to expose the surface of the insulating layer; forming a source-drain doping layer in each of the second openings, each of the source-drain doping layers being located between two adjacent channel regions.

[0016] Optionally, the number of the source-drain doping layers is 4; the number of the channel regions is 4.

[0017] Optionally, the projection pattern of the gate structure on the substrate surface includes a quadrilateral.

[0018] Optionally, the gate structure, the source-drain doped layer and the channel region are arranged in an array.

[0019] Optionally, the method for forming the gate structure includes: forming a gate oxide layer at the bottom of the first opening and the sidewalls of the first opening, and forming a gate dielectric layer on the surface of the gate oxide layer; forming an initial gate layer on the surface of the gate dielectric layer; and flattening the initial gate layer to form a gate layer and the gate structure.

[0020] Optionally, the semiconductor layer further includes a well doping region, and the well doping region surrounds each of the source and drain doping layers and each of the channel regions.

[0021] Optionally, the method further includes: forming a third opening exposing the insulating layer between the well doping region and the channel region, and between the well doping region and the source / drain doping layer; and forming a first isolation layer in the third opening.

[0022] Optionally, the method further includes: performing P-type doping or N-type doping on the well-doped region; and forming a third conductive plug on the well-doped region.

[0023] Optionally, the method for forming the source-drain doped layer includes: forming an initial source-drain doped layer on the bottom and sidewalls of the second opening; and performing a planarization process on the initial source-drain doped layer to form the source-drain doped layer.

[0024] Optionally, the method further includes: forming a first conductive plug on the surface of each of the source and drain doped layers; and forming a second conductive plug on the surface of the gate structure.

[0025] Optionally, the method further includes: forming a second isolation layer in the semiconductor layer, wherein the second isolation layer surrounds the well doping region.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the semiconductor structure of the technical solution of the present invention, each channel region surrounds the gate structure, and each source / drain doped layer is located between two adjacent channel regions. On the one hand, when the conductive plugs subsequently formed on each source / drain doped layer, on the gate structure, and on the well-doped region lead out the gate structure, source / drain doped layer, and well-doped region, there is no need to remove portions of the insulating layer, thereby avoiding large height differences between different circuit modules and simplifying the process flow. On the other hand, the conductive plugs located on each source / drain doped layer, on the gate structure, and on the well-doped region reduce the area occupied by the conductive plugs along a direction parallel to the substrate surface, reducing manufacturing costs and enhancing device design flexibility.

[0028] In the method for forming a semiconductor structure according to the technical solution of the present invention, each channel region surrounds the gate structure, and each source / drain doped layer is located between two adjacent channel regions. When subsequently forming conductive plugs on each source / drain doped layer, on the gate structure, and on the well-doped region, on the one hand, the conductive plugs lead out the gate structure, source / drain doped layer, and well-doped region without removing portions of the insulating layer, thereby avoiding large height differences between different circuit modules and simplifying the process flow. On the other hand, the conductive plugs located on the gate structure, source / drain doped layer, and well-doped region reduce the area occupied by the conductive plugs in a direction parallel to the substrate surface, thereby reducing manufacturing costs and enhancing device design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 13 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the existing fully depleted silicon-on-insulator transistor technology still has many problems.

[0031] In a fully depleted silicon-on-insulator embodiment, the back bias control terminal is drawn out from the wafer and is in the same plane as the gate, source, and drain, thereby increasing the area of ​​the chip in the horizontal direction.

[0032] To address the above-mentioned technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein each channel region surrounds the gate structure, and each source / drain doped layer is located between two adjacent channel regions. When subsequently forming plugs located on each source / drain doped layer, the gate structure, and the well-doped region, on the one hand, the plugs lead out the gate structure, source / drain doped layer, and well-doped region without removing part of the insulating layer, thereby avoiding large height differences between different circuit modules and simplifying the process flow. On the other hand, the location of the plugs on the gate structure, source / drain doped layer, and well-doped region reduces the area occupied by the plugs in a direction parallel to the substrate surface, thereby reducing manufacturing costs and enhancing device design flexibility.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 13 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 A top view of Figure 2 yes Figure 1A cross-sectional view at position A1A2 provides a substrate.

[0036] The substrate includes a base 101 , an insulating layer 102 located on a surface of the base 101 , and a semiconductor layer located on a surface of the insulating layer 102 . The semiconductor layer includes a gate region 103 and a plurality of channel regions 104 surrounding the gate region 103 .

[0037] The substrate 101 is made of silicon and silicon germanium.

[0038] The insulating layer 102 is made of silicon oxide and silicon oxycarbide.

[0039] Materials of the semiconductor layer include silicon and silicon germanium.

[0040] The semiconductor layer provides a structural basis for the subsequent formation of the source-drain doped layer 112 and the gate structure.

[0041] The substrate may also be a silicon-on-insulator (SOI) substrate.

[0042] The semiconductor layer further includes a well doping region 105 , and the well doping region 105 surrounds each of the channel regions 104 and a source / drain doping layer 112 to be formed subsequently.

[0043] Specifically, in this embodiment, the number of the channel regions 104 is four.

[0044] In other embodiments, the number of the channel regions 104 is other values.

[0045] The aspect ratio of the channel region 104 ranges from 5 to 20.

[0046] Specifically, in this embodiment, the method further includes forming a second isolation layer 106 in the semiconductor layer, wherein the second isolation layer 106 surrounds the well doping region 105 .

[0047] The second isolation layer 106 is made of silicon oxide.

[0048] The second isolation layer 106 is used to isolate adjacent devices.

[0049] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 A top view of Figure 4 yes Figure 3 In the cross-sectional view at position A1A2 , a first opening 107 is formed in the gate region 103 to expose the surface of the insulating layer 102 and the sidewall surfaces of each of the channel regions 104 .

[0050] The method for forming the first opening 107 includes: forming a first mask layer (not shown) on the surface of the semiconductor layer, the first mask layer exposing a portion of the surface of the semiconductor layer; using the first mask layer as a mask, etching the semiconductor layer until a portion of the surface of the insulating layer 102 and the sidewall surfaces of each of the channel regions 104 are exposed, thereby forming a first opening 107 located in the gate region 103.

[0051] The etching method includes dry etching.

[0052] The first opening 107 provides a structural basis for forming a gate structure.

[0053] The depth of the first opening 107 ranges from 200 nm to 2000 nm.

[0054] A gate structure is formed in the first opening 107, and the gate structure contacts the sidewalls of each of the channel regions 104. The method for forming the gate structure includes: forming a gate oxide layer 108 at the bottom of the first opening 107 and the sidewalls of the first opening 107, forming a gate dielectric layer 109 on the surface of the gate oxide layer 108; forming an initial gate layer 110 on the surface of the gate dielectric layer 109; and performing a planarization process on the initial gate layer 110 to form a gate layer 111 and the gate structure. For details, please refer to Figures 5 to 8 .

[0055] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 A top view of Figure 6 yes Figure 5 In the cross-sectional view at position A1A2, a gate oxide layer 108 is formed at the bottom of the first opening 107 and the sidewalls of the first opening 107, a gate dielectric layer 109 is formed on the surface of the gate oxide layer 108, and an initial gate layer 110 is formed on the surface of the gate dielectric layer 109.

[0056] The gate oxide layer 108 is made of silicon oxide.

[0057] The gate dielectric layer 109 may be made of a material comprising a high dielectric material with N-type dopant ions or a high dielectric material with P-type dopant ions.

[0058] The material of the initial gate layer 110 includes polysilicon with N-type dopant ions or polysilicon with P-type dopant ions.

[0059] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 A top view of Figure 8 yes Figure 7In the cross-sectional view at position A1A2, the initial gate layer 110 is planarized to form a gate layer 111 and the gate structure.

[0060] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical-mechanical polishing. Specifically, in this embodiment, the planarization method is chemical-mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical-mechanical polishing, through the combined action of chemical and mechanical forces, avoids the surface damage caused by mechanical polishing alone and the shortcomings of chemical polishing alone, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical-mechanical polishing is widely used for high-planarization of various materials at the nanoscale.

[0061] The projection pattern of the gate structure on the substrate surface includes a quadrilateral. Specifically, in this embodiment, the quadrilateral is a square.

[0062] In other embodiments, the projection pattern of the gate structure on the substrate surface is other shapes.

[0063] Specifically, in this embodiment, the gate structure, the subsequently formed source / drain doped layers 112, and the channel region 104 are arranged in an array. Specifically, in a plane parallel to the substrate surface, the subsequently formed source / drain doped layers 112 are arranged in an array along intersecting first and second directions X and Y. The channel region 104 is located between two adjacent source / drain doped layers 112 along either the first or second direction. The gate structure is located at a position surrounded by multiple channel regions 104. The first and second directions may be perpendicular to each other.

[0064] For example, the projection pattern of the gate structure on the substrate surface includes a quadrilateral, the subsequently formed source and drain doped layers 112 are located at the top corners of the quadrilateral gate structure, and the channel region 104 is located at the sides of the quadrilateral gate structure.

[0065] Please refer to Figure 9 and Figure 10 , Figure 9 yes Figure 10 A top view of Figure 10 yes Figure 9 In the cross-sectional view at positions B1B2, several second openings (not shown) are formed in the semiconductor layer, exposing the surface of the insulating layer 102. A source-drain doped layer 112 is formed in each of the second openings, with each source-drain doped layer 112 located between two adjacent channel regions 104. The method for forming the source-drain doped layer 112 includes: forming an initial source-drain doped layer (not shown) at the bottom and sidewalls of the second opening; and planarizing the initial source-drain doped layer to form the source-drain doped layer 112.

[0066] The method for forming the second openings includes: forming a second mask layer (not shown) on the surface of the semiconductor layer, the second mask layer exposing a portion of the surface of the semiconductor layer; etching the semiconductor layer using the second mask layer as a mask until a portion of the surface of the insulating layer 102 is exposed, thereby forming a plurality of second openings. Specifically, in this embodiment, the method further includes: forming third openings (not shown) between the well doped region 105 and the channel region 104, and between the well doped region 105 and the source / drain doped layer 112, exposing the insulating layer 102; and forming a first isolation layer 113 within the third openings.

[0067] The first isolation layer 113 is made of silicon oxide.

[0068] The first isolation layer 113 functions to isolate the well doping region 105 from the channel region 104 , and to isolate the well doping region 105 from the source / drain doping layer 112 .

[0069] For example, in a plane parallel to the substrate surface, the first isolation layer 113 is in a square shape, the semiconductor layer surrounded by the first isolation layer 113 is in a square shape, and the source / drain doped layer 112 is located at the top corners of the square semiconductor layer.

[0070] The material of the initial source / drain doping layer includes polysilicon. The doping ions of the initial source / drain doping layer include N-type doping ions or P-type doping ions. The doping method of the initial source / drain doping layer includes ion implantation or in-situ doping.

[0071] Specifically, in this embodiment, the number of the source-drain doped layers 112 is four.

[0072] In other embodiments, the number of the source-drain doping layers is other values.

[0073] The material of the source / drain doping layer 112 includes polysilicon. The doping ions of the source / drain doping layer 112 include N-type doping ions or P-type doping ions. The doping method of the source / drain doping layer 112 includes ion implantation or in-situ doping.

[0074] The gate structure, the source / drain doped layers 112, and the channel region 104 are arranged in an array. Specifically, in a plane parallel to the substrate surface, the source / drain doped layers 112 are arranged in an array along intersecting first and second directions X and Y. The channel region 104 is located between two adjacent source / drain doped layers 112 along either the first or second direction. The gate structure is located at a position surrounded by multiple channel regions 104. The first and second directions may be perpendicular to each other.

[0075] For example, the projection pattern of the gate structure on the substrate surface includes a quadrilateral, the source-drain doped layer 112 is located at the top corner of the quadrilateral gate structure, and the channel region 104 is located at the edge of the quadrilateral gate structure. Figures 11 to 13 , Figure 11 yes Figure 12 and Figure 13 A top view of Figure 12 yes Figure 11 Cross-sectional view at position A1A2, Figure 13 yes Figure 11 In the cross-sectional view at positions B1B2, a first conductive plug 114 is formed on the surface of each source / drain doped layer 112; a second conductive plug 115 is formed on the surface of the gate structure. The well doped region 105 is subjected to P-type or N-type doping; and a third conductive plug 116 is formed on the well doped region 105.

[0076] When forming the first conductive plug 114 located on each of the source-drain doped layers 112, the second conductive plug 115 located on the gate structure, and the third conductive plug 116 located on the well-doped region 105, on the one hand, the first conductive plug 114 leads out the source-drain doped layer 112, the second conductive plug 115 leads out the gate structure, and the third conductive plug 116 leads out the well-doped region 105, without the need to remove part of the insulating layer 102, thereby avoiding a large height difference between different circuit modules and simplifying the process flow; on the other hand, the first conductive plug 114 is located on the source-drain doped layer 112, the second conductive plug 115 is located on the gate structure, and the third conductive plug 116 is located on the well-doped region 105, which reduces the area occupied by each conductive plug along the direction parallel to the substrate surface, reduces the preparation cost, and improves the flexibility of device design.

[0077] Specifically, in this embodiment, the connection line between each of the third conductive plugs 116 and the second conductive plug 115 is perpendicular to or parallel to the direction A1A2.

[0078] Specifically, in this embodiment, the first conductive plugs 114 are arranged in an array along the intersecting first direction X and second direction Y. Each third conductive plug 116 is located on the central axis of a line connecting two adjacent first conductive plugs 114 along either the first direction or the second direction.

[0079] The materials of the first conductive plug 114 , the second conductive plug 115 , and the third conductive plug 116 include: one or more of copper, tungsten, aluminum, or titanium nitride.

[0080] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figures 11 to 13 , Figure 11 yes Figure 12 and Figure 13 A top view of Figure 12 yes Figure 11 Cross-sectional view at position A1A2, Figure 13 yes Figure 11 The cross-sectional view at position B1B2 includes: a substrate, the substrate including: a base 101, an insulating layer 102 located on the surface of the base 101, and a semiconductor layer located on the surface of the insulating layer 102, the semiconductor layer including a gate region 103 and a plurality of channel regions 104 surrounding the gate region 103; a gate structure located in the gate region 103 and on the surface of the insulating layer 102, the gate structure contacting the side walls of each of the channel regions 104; a plurality of source-drain doped layers 112 located in the semiconductor layer and on the surface of the insulating layer 102, each of the source-drain doped layers 112 being located between two adjacent channel regions 104.

[0081] The semiconductor structure includes a substrate, the substrate including a base 101, an insulating layer 102 located on the surface of the base 101, and a semiconductor layer located on the surface of the insulating layer 102, the semiconductor layer including a gate region 103 (such as Figure 1 ) and a plurality of channel regions 104 (as shown) surrounding the gate region 103 Figure 1 shown).

[0082] The substrate 101 is made of silicon and silicon germanium.

[0083] The insulating layer 102 is made of silicon oxide and silicon oxycarbide.

[0084] Materials of the semiconductor layer include silicon and silicon germanium.

[0085] The substrate may also be a silicon-on-insulator (SOI) substrate.

[0086] The semiconductor layer further includes a well doping region 105 , and the well doping region 105 surrounds each of the channel regions 104 and a source / drain doping layer 112 to be formed subsequently.

[0087] The type of the well doping region 105 includes: N-type or P-type.

[0088] Specifically, in this embodiment, the number of the channel regions 104 is four.

[0089] In other embodiments, the number of the channel regions 104 is other values.

[0090] The aspect ratio of the channel region 104 ranges from 5 to 20.

[0091] The semiconductor structure further includes a second isolation layer 106 located in the semiconductor layer, and the second isolation layer 106 surrounds the well doping region 105 .

[0092] The second isolation layer 106 is made of silicon oxide.

[0093] The semiconductor structure further includes a first isolation layer 113 located between the well doping region 105 and the channel region 104 , and between the well doping region 105 and the source / drain doping layer 112 .

[0094] The first isolation layer 113 is made of silicon oxide.

[0095] The semiconductor structure includes a well region located in the substrate.

[0096] The well region may be of an N-type or a P-type.

[0097] The semiconductor structure includes a gate structure located in the gate region 103 and on the surface of the insulating layer 102 , and the gate structure is in contact with sidewalls of each of the channel regions 104 .

[0098] The projection pattern of the gate structure on the substrate surface includes a quadrilateral. Specifically, in this embodiment, the projection pattern of the gate structure on the substrate surface is a square.

[0099] In other embodiments, the projection pattern of the gate structure on the substrate surface is other shapes.

[0100] The gate structure includes: a gate oxide layer 108 contacting the sidewall surface of the channel region 104 , a gate dielectric layer 109 located on the surface of the gate oxide layer 108 , and a gate layer 111 located on the surface of the gate dielectric layer 109 .

[0101] The gate oxide layer 108 is made of silicon oxide.

[0102] The gate dielectric layer 109 may be made of a material comprising a high dielectric material with N-type dopant ions or a high dielectric material with P-type dopant ions.

[0103] The material of the gate layer 111 includes polysilicon with N-type dopant ions or polysilicon with P-type dopant ions.

[0104] The semiconductor structure includes: a plurality of source-drain doped layers 112 located within the semiconductor layer and on the surface of the insulating layer 102 , and each of the source-drain doped layers 112 is located between two adjacent channel regions 104 .

[0105] The source / drain doping layer 112 is made of polysilicon.

[0106] The doping ions of the source / drain doping layer 112 include N-type doping ions or P-type doping ions.

[0107] Specifically, in this embodiment, the number of the source-drain doped layers 112 is 4. In other embodiments, the number of the source-drain doped layers is other values.

[0108] Specifically, in this embodiment, the gate structure, the source-drain doped layer 112 and the channel region 104 are arranged in an array.

[0109] Specifically, in a plane parallel to the substrate surface, the source / drain doped layers 112 are arranged in an array along intersecting first and second directions X and Y. The channel region 104 is located between two adjacent source / drain doped layers 112 along either the first or second direction. The gate structure is located at a position surrounded by the plurality of channel regions 104. The first and second directions may be perpendicular to each other.

[0110] For example, the projection pattern of the gate structure on the substrate surface includes a quadrilateral, the source-drain doped layer 112 is located at the top corners of the quadrilateral gate structure, and the channel region 104 is located at the sides of the quadrilateral gate structure.

[0111] The semiconductor structure further includes a first conductive plug 114 located on the surface of each of the source-drain doped layers 112 .

[0112] The semiconductor structure further includes a second conductive plug 115 located on the surface of the gate structure.

[0113] The semiconductor structure further includes a third conductive plug 116 located on the well doped region 105 .

[0114] On the one hand, the first conductive plug 114 leads out the source-drain doped layer 112, the second conductive plug 115 leads out the gate structure, and the third conductive plug 116 leads out the well-doped region 105, without removing part of the insulating layer 102, thereby avoiding a large height difference between different circuit modules and simplifying the process flow; on the other hand, the first conductive plug 114 is located on the source-drain doped layer 112, the second conductive plug 115 is located on the gate structure, and the third conductive plug 116 is located on the well-doped region 105, which reduces the area occupied by each conductive plug along the direction parallel to the substrate surface, reduces the preparation cost, and improves the flexibility of device design.

[0115] Specifically, in this embodiment, the connection line between each of the third conductive plugs 116 and the second conductive plug 115 is perpendicular to or parallel to the direction A1A2.

[0116] Specifically, in this embodiment, the first conductive plugs 114 are arranged in an array along the intersecting first direction X and second direction Y. Each third conductive plug 116 is located on the central axis of a line connecting two adjacent first conductive plugs 114 along either the first direction or the second direction.

[0117] The materials of the first conductive plug 114 , the second conductive plug 115 , and the third conductive plug 116 include: one or more of copper, tungsten, aluminum, or titanium nitride.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate, comprising: a base, an insulating layer located on a surface of the base, and a semiconductor layer located on a surface of the insulating layer, wherein the semiconductor layer comprises a gate region and a plurality of channel regions surrounding the gate region; a gate structure located in the gate region and on the surface of the insulating layer, wherein the gate structure contacts the sidewalls of each of the channel regions; A plurality of source-drain doped layers are located in the semiconductor layer and on the surface of the insulating layer, and each of the source-drain doped layers is located between two adjacent channel regions.

2. The semiconductor structure according to claim 1, wherein The number of the source-drain doping layers is four; the number of the channel regions is four.

3. The semiconductor structure according to claim 1, wherein: The projection pattern of the gate structure on the substrate surface includes a quadrilateral.

4. The semiconductor structure according to claim 1, wherein The gate structure, the source-drain doped layer and the channel region are arranged in an array.

5. The semiconductor structure according to claim 1, wherein The gate structure includes: a gate oxide layer in contact with the sidewall surface of the channel region, a gate dielectric layer located on the surface of the gate oxide layer, and a gate layer located on the surface of the gate dielectric layer; the gate dielectric layer material includes: a high dielectric material with N-type doped ions or a high dielectric material with P-type doped ions; the gate layer material includes polysilicon with N-type doped ions or with P-type doped ions.

6. The semiconductor structure according to claim 1, wherein The material of the source / drain doping layer includes polysilicon, and the doping ions of the source / drain doping layer include N-type doping ions or P-type doping ions.

7. The semiconductor structure according to claim 1, wherein: Also includes: a well-doped region located in the semiconductor layer, the well-doped region surrounding each of the source-drain doped layers and each of the channel regions; a first isolation layer located between the well-doped region and the channel region, and between the well-doped region and the source-drain doped layers; A third conductive plug is located on the well doped region.

8. The semiconductor structure according to claim 7, wherein: Also includes: A second isolation layer is located in the semiconductor layer, and the second isolation layer surrounds the well doping region.

9. The semiconductor structure according to claim 1, wherein: Also includes: a first conductive plug located on the surface of each of the source-drain doped layers; A second conductive plug is located on the surface of the gate structure.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base, an insulating layer located on a surface of the base, and a semiconductor layer located on a surface of the insulating layer, the semiconductor layer comprising a gate region and a plurality of channel regions surrounding the gate region; forming a first opening in the gate region to expose the surface of the insulating layer and the sidewall surfaces of each of the channel regions; forming a gate structure in the first opening, wherein the gate structure contacts the sidewalls of each of the channel regions; forming a plurality of second openings in the semiconductor layer to expose the surface of the insulating layer; A source-drain doped layer is formed in each of the second openings, and each of the source-drain doped layers is located between two adjacent channel regions.

11. The method for forming a semiconductor structure according to claim 10, wherein: The number of the source-drain doping layers is four; the number of the channel regions is four.

12. The method for forming a semiconductor structure according to claim 10, wherein: The projection pattern of the gate structure on the substrate surface includes a quadrilateral.

13. The method for forming a semiconductor structure according to claim 10, wherein: The gate structure, the source-drain doped layer and the channel region are arranged in an array.

14. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the gate structure includes: forming a gate oxide layer at the bottom of the first opening and the sidewalls of the first opening, and forming a gate dielectric layer on the surface of the gate oxide layer; forming an initial gate layer on the surface of the gate dielectric layer; and flattening the initial gate layer to form a gate layer and the gate structure.

15. The method for forming a semiconductor structure according to claim 10, wherein: The semiconductor layer further includes a well doping region, and the well doping region surrounds each of the source and drain doping layers and each of the channel regions.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: forming a third opening between the well doping region and the channel region, and between the well doping region and the source / drain doping layer to expose the insulating layer; A first isolation layer is formed in the third opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: Performing P-type doping or N-type doping on the well doping region; A third conductive plug is formed on the well doped region.

18. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the source-drain doped layer includes: forming an initial source-drain doped layer on the bottom and sidewalls of the second opening; The initial source-drain doped layer is planarized to form the source-drain doped layer.

19. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: forming a first conductive plug on the surface of each of the source and drain doped layers; A second conductive plug is formed on the surface of the gate structure.

20. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: A second isolation layer is formed in the semiconductor layer, wherein the second isolation layer surrounds the well doping region.

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