Semiconductor structure unit, forming method thereof and semiconductor structure

Abstract

The invention discloses a semiconductor structure unit and a forming method thereof, and a semiconductor structure, and the semiconductor structure unit comprises a substrate which comprises a first region and a second region; the first gate structures and the second gate structures are located on the substrate, and the first gate structures are located between the adjacent second gate structures; the plurality of first metal layers are positioned on the first gate structure and the second gate structure in the first region, and the first metal layers are parallel to the first direction; the plurality of second metal layers are located on the first gate structure and the second gate structure in the second region, and the second metal layers are parallel to the first direction; the plurality of first plugs are positioned on the plurality of first metal layers; a plurality of second plugs located on the second metal layer; the first conductive layer is positioned on the first metal layer in the first region and is parallel to the second direction; and the second conductive layer is positioned on the second metal layer in the second region and is parallel to the second direction. The area of the semiconductor structure unit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structural unit and a forming method thereof, and a semiconductor structure. Background Art

[0002] Most Application Specific Integrated Circuits (ASIC) designs must undergo engineering change orders (ECOs) to minimize defects and meet the ever-changing needs of customers. These change requirements not only require design resources and time, but also require multiple masks to implement the desired changes. Multiple factors affect the number of layers to be changed and the cost involved in the change. In addition, in some cases, due to insufficient chip resources and budget constraints, the change may not be possible. This situation may lead to one of two results: either change the original mask layer to achieve it, which will require a comprehensive redesign of all masks, or abandon the change request because if the mask is fully redesigned, the product cost will increase significantly.

[0003] These changes are accomplished by manipulating standard digital engineering modification cells on the silicon wafer through a photomask. These cells are "spare" cells in the original silicon wafer, and modifications can be implemented by changing their connections, using the fewest possible layers and minimizing costs and resources. These spare cells make it easier to modify the digital logic on the chip. Their placement is determined by numerous heuristic algorithms designed by engineers to maximize gains in the logic most prone to errors.

[0004] However, in the process of using the standard digital engineering modification unit, it is still impossible to ensure that, after the silicon wafer is manufactured, the necessary changes can be implemented according to the standard digital engineering modification unit to maintain customer benefits in the product. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structural unit and a forming method thereof, and a semiconductor structure to optimize a standard digital engineering modification unit and its application.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure unit, comprising: a substrate, the substrate comprising a first region and a second region arranged along a first direction, the first direction being parallel to the substrate surface; a plurality of first gate structures and a plurality of second gate structures located on the substrate, the first gate structures being located between adjacent second gate structures, the first gate structures and the second gate structures being parallel to a second direction, the first gate structures and the second gate structures spanning the first region and the second region, the second direction being parallel to the substrate surface and perpendicular to the first direction; a plurality of first metal layers located on the first gate structures and the second gate structures in the first region, the first metal layers being parallel to the first direction ; Several second metal layers located on the first gate structure and the second gate structure in the second area, the second metal layers are parallel to the first direction; Several first plugs located on the several first metal layers, one first plug is located on one first metal layer; Several second plugs located on the second metal layer, one second plug is located on one second metal layer; A first conductive layer located on the first metal layer in the first area, the first conductive layer is parallel to the second direction, and the first conductive layer is located on a side of the first area away from the second area; A second conductive layer located on the second metal layer in the second area, the second conductive layer is parallel to the second direction, and the second conductive layer is located on a side of the second area away from the first area.

[0007] Optionally, a projection of the first metal layer on the substrate is located between adjacent first gate structures and second gate structures; a projection of the second metal layer on the substrate is located between adjacent first gate structures and second gate structures.

[0008] Optionally, the substrate further includes an isolation region located between the first region and the second region; and further includes: a first isolation layer located in the isolation region, the first isolation layer electrically isolating the first metal layer from the second metal layer.

[0009] Optionally, the first isolation layer further isolates the second gate structure on the first region and the second region.

[0010] Optionally, it also includes: a second isolation layer located in the first area, the second isolation layer is parallel to the second direction, and the first conductive layer is located on the second isolation layer; a third isolation layer located in the second area, the third isolation layer is parallel to the second direction, and the second conductive layer is located on the third isolation layer.

[0011] Optionally, the first plugs on two adjacent first metal layers are staggered in the second direction; and the second plugs on two adjacent second metal layers are staggered in the second direction.

[0012] Optionally, the method further includes: a gate plug located on the first gate structure on the isolation region.

[0013] Optionally, the number of the first gate structures includes 2, the number of the second gate structures includes 3, and the first gate structures and the second gate structures are alternately arranged in parallel along the second direction.

[0014] Optionally, the substrate further includes: a first active area located in the first region, wherein the projection of the first metal layer on the substrate is located in the first active area; and a second active area located in the second region, wherein the projection of the second metal layer on the substrate is located in the second active area.

[0015] Optionally, the number of the first gate structures includes 2, and the number of the second gate structures includes 4.

[0016] Optionally, the substrate further includes: a first active region and a second active region located in the first region, the first active region and the second active region are distributed along the second direction, the first active region and the second active region are separated from each other, a projection of the first metal layer between the first gate structure and the second gate structure on the substrate is located in the first active region, and a projection of the first metal layer between another first gate structure and the second gate structure on the substrate is located in the second active region; a third active region and a fourth active region located in the second region, the third active region and the fourth active region are distributed along the second direction, the third active region and the fourth active region are separated from each other, a projection of the second metal layer between the first gate structure and the second gate structure on the substrate is located in the third active region, and a projection of the second metal layer between another first gate structure and the second gate structure on the substrate is located in the fourth active region.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure unit, comprising: providing a substrate, the substrate comprising a first region and a second region arranged along a first direction, the first direction being parallel to the substrate surface; forming a plurality of first gate structures and a plurality of second gate structures on the substrate, the first gate structure being located between adjacent second gate structures, the first gate structure and the second gate structure being parallel to a second direction, the first gate structure and the second gate structure spanning the first region and the second region, the second direction being parallel to the substrate surface and perpendicular to the first direction; forming a plurality of first metal layers on the first region, the first metal layers being parallel to the first direction, the first metal layers being located on the first gate structure and the second gate structure; A plurality of second metal layers are formed on the second region, the second metal layers are parallel to the first direction, and the second metal layers are located on the first gate structure and the second gate structure; a plurality of first plugs are formed on the plurality of first metal layers, and one first plug is located on one first metal layer; a plurality of second plugs are formed on the second metal layer, and one second plug is located on one second metal layer; a first conductive layer is formed on the first metal layer in the first region, the first conductive layer is parallel to the second direction, and the first conductive layer is located on a side of the first region away from the second region; a second conductive layer is formed on the second metal layer in the second region, the second conductive layer is parallel to the second direction, and the second conductive layer is located on a side of the second region away from the first region.

[0018] Optionally, a projection of the first metal layer on the substrate is located between adjacent first gate structures and second gate structures; a projection of the second metal layer on the substrate is located between adjacent first gate structures and second gate structures.

[0019] Optionally, the substrate further includes an isolation region located between the first region and the second region; and further includes: forming a first isolation layer located in the isolation region, the first isolation layer electrically isolating the first metal layer and the second metal layer.

[0020] Optionally, the first isolation layer further isolates the second gate structure on the first region and the second region.

[0021] Optionally, it also includes: forming a second isolation layer located in the first area, the second isolation layer is parallel to the second direction, and the first conductive layer is located on the second isolation layer; forming a third isolation layer located in the second area, the third isolation layer is parallel to the second direction, and the second conductive layer is located on the third isolation layer.

[0022] Optionally, the first plugs on two adjacent first metal layers are staggered in the second direction; and the second plugs on two adjacent second metal layers are staggered in the second direction.

[0023] Optionally, the number of the first gate structures includes 2, and the number of the second gate structures includes 3; the first gate structures and the second gate structures are arranged alternately in parallel along the second direction; or, the number of the first gate structures includes 2, and the number of the second gate structures includes 4.

[0024] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a semiconductor structure unit; several conductive layers located on the first metal layer and the second metal layer, several of the conductive layers are parallel to the second direction, and the conductive layers are electrically connected to the first plug; a connecting layer located on the several conductive layers, the connecting layer is parallel to the first direction, and the connecting layer is selectively electrically connected to the conductive layer.

[0025] Optionally, the substrate includes a first side and a second side opposite to each other along a second direction; the first metal layer includes a first layer and a second layer arranged from the first side to the second side, and includes a third layer and a fourth layer arranged from the second side to the first side; the second metal layer includes a fifth layer and a sixth layer arranged from the first side to the second side, and includes a seventh layer and an eighth layer arranged from the second side to the first side.

[0026] Optionally, the conductive layer includes: a third conductive layer, the third conductive layer is electrically connected to the second layer and the third layer through a first plug; a fourth conductive layer, the fourth conductive layer is electrically connected to the first layer and the fourth layer through a first plug; a fifth conductive layer, the fifth conductive layer is electrically connected to the sixth layer and the seventh layer through a second plug; a sixth conductive layer, the sixth conductive layer is electrically connected to the fifth layer through a second plug; and a seventh conductive layer, the seventh conductive layer is electrically connected to the eighth layer through a second plug.

[0027] Optionally, the connecting layer includes: a first connecting layer, which is electrically connected to the first conductive layer and the fourth conductive layer; a second connecting layer, which is electrically connected to the third conductive layer and the seventh conductive layer; and a third connecting layer, which is electrically connected to the second conductive layer and the sixth conductive layer.

[0028] Optionally, the conductive layer further includes: an eighth conductive layer located on the gate plug in the isolation region.

[0029] Optionally, it further includes: a plurality of third plugs and a fourth plug located on the plurality of conductive layers, the connection layer is electrically connected to the conductive layer on the first region through the third plugs, and the connection layer is electrically connected to the conductive layer on the second region through the second plugs.

[0030] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, comprising: a plurality of semiconductor structure units, wherein the plurality of semiconductor structure units are regularly spliced ​​and arranged.

[0031] Optionally, the plurality of semiconductor structures are arranged along the second direction, and in two adjacent semiconductor structure units, the first side of the substrate in one semiconductor structure unit is connected to the second side of the substrate in the other semiconductor structure unit.

[0032] Optionally, a plurality of the semiconductor structure units are arranged along a first direction and a second direction, and in two adjacent semiconductor structure units along the second direction, the first side of the substrate in one semiconductor structure unit is connected to the second side of the substrate in the other semiconductor structure unit, and in two adjacent semiconductor structure units along the first direction, the second region in one semiconductor structure unit is connected to the first region in the other semiconductor structure unit.

[0033] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0034] In the semiconductor structure unit of the present invention, the first conductive layer is located on the second isolation layer, electrically isolated from the first metal layer by the second isolation layer; the second conductive layer is located on the third isolation layer, electrically isolated from the second metal layer by the third isolation layer. This eliminates the need for a first metal layer and a second metal layer. Because the projections of the first and second metal layers on the substrate are located between adjacent first and second gate structures, the area of ​​two contacted poly pitches (CPPs) is saved, reducing the area of ​​the semiconductor structure unit and saving space in circuit design.

[0035] The semiconductor structure of the present invention is formed by forming a conductive layer and a connecting layer on a semiconductor structural unit. In the semiconductor structural unit, the first metal layer, the second metal layer, the first plug, the second plug, the first conductive layer, and the second conductive layer are all fixed, and the number of masks used to form the first metal layer, the second metal layer, the first plug, the second plug, the first conductive layer, and the second conductive layer is also fixed. The design requirements can be met by simply adjusting the positions of the conductive layer, the connecting layer, the third plug, and the fourth plug according to the design requirements. That is, the number of fixed masks is increased, thereby saving the number of masks and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figures 1 to 3 This is a structural schematic diagram of a semiconductor structure unit forming process according to an embodiment;

[0037] Figures 4 to 6 is a schematic diagram of a formation process of a semiconductor structure unit in one embodiment of the present invention;

[0038] Figure 7 is a schematic structural diagram of a semiconductor structure unit in another embodiment of the present invention;

[0039] Figure 8 and Figure 9 is a structural schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention;

[0040] Figure 10 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention;

[0041] Figure 11 FIG. 1 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0042] As described in the background art, the application of the standard digital engineering modification unit still has some uncertainties.

[0043] Figures 1 to 3 It is a structural schematic diagram of a semiconductor structure unit forming process according to an embodiment.

[0044] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 Schematic diagram of the structure along the section line AA1, Figure 1 for Figure 2A top view of the substrate 100 is provided, wherein the substrate 100 includes a first region I, an isolation region III, and a second region II arranged along a first direction X, wherein the first direction X is parallel to the surface of the substrate 100; a plurality of first gate structures 101 and a plurality of second gate structures 102 are formed on the substrate 100, wherein the first gate structures 101 are located between adjacent second gate structures 102, and the first gate structures 101 and the second gate structures 102 are parallel to a second direction Y, and the first gate structures 101 and the second gate structures 102 span the first region I and the second region II, wherein the second direction Y is parallel to the surface of the substrate 100 and perpendicular to the first direction X; a plurality of first metal layers 103 are formed on the first region I, and the first metal layers 103 are parallel to the first direction X; a plurality of second metal layers 103 are formed on the second region II A second metal layer 104 is formed, and the second metal layer 104 is parallel to the first direction X; a first isolation layer 105 is formed in the isolation region III, and the first isolation layer 105 electrically isolates the first metal layer 103 and the second metal layer 104; a second isolation layer 106 is formed in the first region I, and the second isolation layer 106 is parallel to the second direction Y, and the second isolation layer 106 is located on the side of the first region I away from the second region II; a third isolation layer 107 is formed in the second region II, and the third isolation layer 107 is parallel to the second direction Y, and the third isolation layer 107 is located on the side of the second region II away from the first region I, and the third isolation layer 107 exposes the second metal layer 104 that needs to be electrically connected later, and the second isolation layer 106 exposes the first metal layer 103 that needs to be electrically connected later.

[0045] In this embodiment, the substrate 100 further includes: a first active region 131 and a second active region 132 located in the first region I, the first active region 131 and the second active region 132 are distributed along the second direction Y, and the first active region 131 and the second active region 132 are separate from each other; a third active region 133 and a fourth active region 134 located in the second region II, the third active region 133 and the fourth active region 134 are distributed along the second direction Y, and the third active region 133 and the fourth active region 134 are separate from each other.

[0046] In this embodiment, the projection of the first metal layer 103 between a first gate structure 101 and a second gate structure 102 on the substrate 100 is located in the first active area 131, and the projection of the first metal layer 103 between another first gate structure 101 and the second gate structure 102 on the substrate 100 is located in the second active area 132; the projection of the second metal layer 104 between a first gate structure 101 and the second gate structure 102 on the substrate 100 is located in the third active area 133, and the projection of the second metal layer 104 between another first gate structure 101 and the second gate structure 102 on the substrate 100 is located in the fourth active area 134.

[0047] In this embodiment, the second gate structure 102 is a dummy gate structure.

[0048] In this embodiment, the present invention further includes: forming a first dielectric layer 120 located on the substrate 100, wherein the first gate structure 101 and the second gate structure 102 are located in the first dielectric layer 120; forming a second dielectric layer 121 located on the first dielectric layer 120, wherein the first metal layer 103 and the second metal layer 104 are located in the second dielectric layer 121.

[0049] Please refer to Figure 3 , Figure 3 For Figure 1 Based on the schematic diagram, a first conductive layer 108 is formed on the second isolation layer 106, and the first conductive layer 108 is electrically connected to the first metal layer 103 exposed by the second isolation layer 106, and the first conductive layer 108 is used to provide a power supply voltage VDD to the first area I; a second conductive layer 109 is formed on the third isolation layer 107, and the second conductive layer 109 is electrically connected to the second metal layer 104 exposed by the third isolation layer 107, and the second conductive layer 109 is used to provide a ground voltage VSS to the second area II.

[0050] In the semiconductor structure unit, the first conductive layer 108 provides a power supply voltage VDD to the first region I through the first metal layer 103, and the second conductive layer 109 provides a ground voltage VSS to the second region II through the second metal layer 104. Therefore, specific first metal layers 103 and second metal layers 104 are required to achieve this function. In this embodiment, there are two first gate structures 101 and four second gate structures 102. The projections of the first metal layer 103, which is required to be electrically connected to the first conductive layer 108, and the second metal layer 104, which is required to be electrically connected to the second conductive layer 109, are located between adjacent second gate structures 102. The projection of the first metal layer 103, which is required to be electrically connected to the first conductive layer 108, on the substrate 100 is located between the first active region 131 and the second active region 132, and the projection of the second metal layer 104, which is required to be electrically connected to the second conductive layer 109, on the substrate is located between the third active region 133 and the fourth active region 134. This results in a larger area for the semiconductor structure unit.

[0051] Furthermore, in this embodiment, the number of first metal layers 103 is five, and the number of second metal layers 104 is five. This requires the use of more V0s between the first metal layer 103 and the substrate, and between the second metal layer 104 and the substrate, thus reducing the space between the V0s. Consequently, more masks must be used to remove the V0s. However, the additional masks and variable layers increase the cost of engineering modifications to standard digital cells.

[0052] In addition, the semiconductor structure unit can only support a mixed metal back-end process with a double diffusion break (DDB) structure. The double diffusion break requires two second gate structures 202, and thus has a narrow application range. In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure unit and a method for forming the same, as well as a semiconductor structure. In the semiconductor structure unit, the first conductive layer is located on the second isolation layer, and the first conductive layer is electrically isolated from the first metal layer by the second isolation layer; the second conductive layer is located on the third isolation layer, and the second conductive layer is electrically isolated from the second metal layer by the third isolation layer. In this way, a first metal layer and a second metal layer can be omitted. Since the projections of the first metal layer and the second metal layer on the substrate are located between the adjacent first gate structures and the second gate structures, the area of ​​two contacted poly pitches (CPPs) can be saved, thereby reducing the area of ​​the semiconductor structure unit and saving area in circuit design.

[0053] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Figures 4 to 6 FIG. 1 is a schematic diagram of a formation process of a semiconductor structure unit in one embodiment of the present invention.

[0055] Please refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 Schematic diagram of the structure along the section line AA1, Figure 4 for Figure 5 A substrate 200 is provided, wherein the substrate 200 includes a first region I and a second region II arranged along a first direction X, and the first direction X is parallel to the surface of the substrate 200.

[0056] In this embodiment, the substrate 200 further includes an isolation region III, and the isolation region III is located between the first region I and the second region II.

[0057] In this embodiment, the substrate 200 further includes: a first active region 310 located in the first region I, the first active region 310 spanning the first region I; and a second active region 311 located in the second region II, the second active region 311 spanning the second region II.

[0058] Please continue to refer to Figure 4 and Figure 5 , a plurality of first gate structures 201 and a plurality of second gate structures 202 are formed on a substrate 200, wherein the first gate structures 201 are located between adjacent second gate structures 202, the first gate structures 201 and the second gate structures 202 are parallel to a second direction Y, and the first gate structures 201 and the second gate structures 202 span the first region I and the second region II, and the second direction Y is parallel to the surface of the substrate 200 and perpendicular to the first direction X.

[0059] In this embodiment, the number of the first gate structures 201 includes two, the number of the second gate structures 202 includes three, the first gate structures 201 are located between adjacent second gate structures 202, and the first gate structures 201 and the second gate structures 202 are alternately arranged in parallel along the second direction Y.

[0060] In this embodiment, the substrate 200 includes a first side and a second side along a second direction Y. Two second gate structures 202 are located at the edges of the first side and the second side, respectively. Of the second gate structures 202 located on the first side, half are located on the first side of the substrate 200; and of the second gate structures 202 located on the second side, half are located on the second side of the substrate 200. Because the first active region 310 spans the first region I and the second active region 311 spans the second region II, only half of the second gate structures 202 on the first and second sides of the substrate 200 are located on the substrate 200, respectively. This reduces the area of ​​the semiconductor structure unit.

[0061] In this embodiment, the second gate structure 202 is a dummy gate structure.

[0062] In this embodiment, the first source-drain doping regions are formed in the first active region 310 on both sides of the first gate structure 201 and the second gate structure 202 (see FIG. Figure 5 , not marked); forming a second source-drain doped region in the second active region 311 located on both sides of the first gate structure 201 and the second gate structure 202 (reference Figure 5 , not indicated).

[0063] In this embodiment, the conductivity type of the first source / drain doping region is opposite to the conductivity type of the second source / drain doping region.

[0064] The conductivity types of the first source-drain doping region and the second source-drain doping region include N-type or P-type.

[0065] A first dielectric layer 260 is formed on the substrate 200 , and the first gate structure 201 and the second gate structure 202 are located in the first dielectric layer 260 .

[0066] Please continue to refer to Figure 4 and Figure 5 , a plurality of first metal layers 203 are formed on the first dielectric layer 260 in the first region I, the first metal layers 203 are parallel to the first direction X, and the first metal layers 203 are located on the first gate structure 201 and the second gate structure 202; a plurality of second metal layers 204 are formed on the first dielectric layer 260 in the second region II, the second metal layers 204 are parallel to the first direction X, and the second metal layers 204 are located on the first gate structure 201 and the second gate structure 202.

[0067] In this embodiment, the projection of the first metal layer 203 on the substrate 200 is located in the first active area 310 between the adjacent first gate structure 201 and the second gate structure 202, and the first metal layer 203 is electrically connected to the first source-drain doped area; the projection of the second metal layer 204 on the substrate 200 is located in the second active area 311 between the adjacent first gate structure 201 and the second gate structure 202, and the second metal layer 204 is electrically connected to the second source-drain doped area.

[0068] In this embodiment, the fifth plug 262 is formed in the first dielectric layer 260 (see FIG. Figure 5 ) and a sixth plug (not shown), the first metal layer 203 is electrically connected to the first source-drain doped region through the fifth plug 262, and the second metal layer 204 is electrically connected to the second source-drain doped region through the sixth plug.

[0069] In this embodiment, the first metal layer 203 and the second metal layer 204 are formed simultaneously.

[0070] In this embodiment, the further embodiment includes: forming a second dielectric layer 261 on the first dielectric layer 260 , and the first metal layer 203 and the second metal layer 204 are located in the second dielectric layer 261 .

[0071] In this embodiment, the further embodiment includes: forming a first isolation layer 207 in the isolation region III, wherein the first isolation layer 207 electrically isolates the first metal layer 203 from the second metal layer 204 .

[0072] In this embodiment, the first isolation layer 207 further isolates the second gate structure 202 on the first region I and the second region II.

[0073] In this embodiment, while forming the first isolation layer 207, the following also includes forming a second isolation layer 208 in the first region I, the second isolation layer 208 being parallel to the second direction Y and located on a side of the first region I away from the second region II; and forming a third isolation layer 209 in the second region II, the third isolation layer 209 being parallel to the second direction Y and located on a side of the second region II away from the first region I. The top surfaces of the first isolation layer 207, the second isolation layer 208, and the third isolation layer 209 are flush with the top surface of the second dielectric layer 261.

[0074] In this embodiment, the first barrier layer 207 , the second barrier layer 208 , and the third barrier layer 209 are formed simultaneously.

[0075] Please continue to refer to Figure 4 and Figure 5, a plurality of first plugs 205 are formed on a plurality of first metal layers 203 , with one first plug 205 being located on one first metal layer 203 ; a plurality of second plugs 206 are formed on a plurality of second metal layers 204 , with one second plug 206 being located on one second metal layer 204 .

[0076] In this embodiment, the first plug 205 and the second plug 206 are formed simultaneously.

[0077] In this embodiment, the process further includes forming a gate plug 210 on the first gate structure 201 in the isolation region III.

[0078] In other embodiments, the gate plug may not be formed on the first gate structure in the isolation region.

[0079] Please refer to Figure 6 , Figure 6 For Figure 4 Based on the schematic diagram, a first conductive layer 211 is formed on the second isolation layer 208 in the first area I, and the first conductive layer 211 is parallel to the second direction Y; a second conductive layer 212 is formed on the third isolation layer 209 in the second area II, and the second conductive layer 212 is parallel to the second direction Y.

[0080] In this embodiment, the first conductive layer 211 and the second conductive layer 212 are formed simultaneously.

[0081] Accordingly, the embodiment of the present invention further provides a semiconductor structure unit, please continue to refer to Figure 6 ,include:

[0082] A substrate 200 comprising a first region I and a second region II arranged along a first direction X, wherein the first direction X is parallel to a surface of the substrate 200;

[0083] A plurality of first gate structures 201 and a plurality of second gate structures 202 are located on a substrate 200, wherein the first gate structures 201 are located between adjacent second gate structures 202, the first gate structures 201 and the second gate structures 202 are parallel to a second direction Y, and the first gate structures 201 and the second gate structures 202 span the first region I and the second region II, and the second direction Y is parallel to the surface of the substrate 200 and perpendicular to the first direction X;

[0084] A plurality of first metal layers 203 located on the first gate structure 201 and the second gate structure 202 in the first region I, wherein the first metal layers 203 are parallel to the first direction X;

[0085] A plurality of second metal layers 204 located on the first gate structure 201 and the second gate structure 202 in the second region II, wherein the second metal layers 204 are parallel to the first direction X;

[0086] a plurality of first plugs 205 located on the plurality of first metal layers 203 , wherein one first plug 205 is located on one first metal layer 203 ;

[0087] a plurality of second plugs 206 located on the second metal layer 204 , wherein one second plug 206 is located on one second metal layer 204 ;

[0088] a first conductive layer 211 located on the first metal layer 203 in the first region I, wherein the first conductive layer 211 is parallel to the second direction Y and is located on a side of the first region I away from the second region II;

[0089] The second conductive layer 212 is located on the second metal layer 204 in the second region II. The second conductive layer 212 is parallel to the second direction Y. The second conductive layer 212 is located on a side of the second region II away from the first region I.

[0090] In this embodiment, the projection of the first metal layer 203 on the substrate 200 is located between the adjacent first gate structures 201 and the second gate structures 202 ; the projection of the second metal layer 204 on the substrate 200 is located between the adjacent first gate structures 201 and the second gate structures 202 .

[0091] In this embodiment, the substrate 200 further includes an isolation region III, and the isolation region III is located between the first region I and the second region II.

[0092] In this embodiment, the invention further includes: a first isolation layer 207 located in the isolation region III, and the first isolation layer 207 electrically isolates the first metal layer 203 and the second metal layer 204 .

[0093] In this embodiment, the first isolation layer 207 further isolates the second gate structure 202 on the first region I and the second region II.

[0094] In this embodiment, the device further includes a second isolation layer 208 located in the first region I, the second isolation layer 208 being parallel to the second direction Y, and the first conductive layer 211 being located on the second isolation layer 208. The first conductive layer 211 is electrically isolated from the first metal layer 203 by the second isolation layer 208.

[0095] In this embodiment, the present invention further includes a third isolation layer 209 located in the second region II, the third isolation layer 209 being parallel to the second direction Y, and the second conductive layer 212 being located on the third isolation layer 209. The second conductive layer 212 is electrically isolated from the second metal layer 204 by the third isolation layer 209.

[0096] In this embodiment, the first plugs 205 on two adjacent first metal layers 203 are staggered in the second direction Y; and the second plugs 206 on two adjacent second metal layers 204 are staggered in the second direction Y.

[0097] In this embodiment, the present invention further includes: a gate plug 210 located on the first gate structure 201 on the isolation region III.

[0098] In other embodiments, the gate plug may not be included.

[0099] In this embodiment, the number of the first gate structures 201 includes two, the number of the second gate structures includes three, and the first gate structures 201 and the second gate structures 202 are alternately arranged in parallel along the second direction Y.

[0100] In this embodiment, the substrate 200 further includes: a first active area 310 located in the first region I, and a projection of the first metal layer 203 on the substrate 200 is located in the first active area 310; a second active area 311 located in the second region II, and a projection of the second metal layer 204 on the substrate 200 is located in the second active area 311.

[0101] In the semiconductor structure unit, the first conductive layer 211 is located on the second isolation layer 208, and is electrically isolated from the first metal layer 203 by the second isolation layer 208. The second conductive layer 212 is located on the third isolation layer 209, and is electrically isolated from the second metal layer 204 by the third isolation layer 209. This eliminates the need for a first metal layer and a second metal layer. Because the projections of the first and second metal layers on the substrate are located between the adjacent first and second gate structures 201 and 202, the area of ​​two contacted poly pitches (CPPs) can be saved, thereby reducing the area of ​​the semiconductor structure unit and saving area in circuit design.

[0102] Furthermore, since the number of first and second metal layers is reduced, the number of fifth and sixth plugs 262 that need to be formed is also reduced, thereby widening the process window for forming fifth and sixth plugs 262 and 266, eliminating the need for multiple photomasks, and thus reducing the number of photomasks. In this embodiment, only one semiconductor structure unit is required to implement logic functions such as an invertor (INV), a two-input NAND gate (NAND2), and a two-input NOR gate (NOR2).

[0103] In this embodiment, the semiconductor structure unit can support a hybrid metal back-end process with a double diffusion break (DDB) structure, which requires two second gate structures 202; it can also support a hybrid metal back-end process with a single diffusion break (SDB) structure, thus having a wider range of applications.

[0104] Figure 7 FIG. 1 is a schematic structural diagram of a semiconductor structure unit in another embodiment of the present invention.

[0105] Please refer to Figure 7 , Figure 7 The semiconductor structure unit in Figure 6 The difference between the semiconductor structure units is that: in this embodiment, the number of the first gate structures 201 includes two, the number of the second gate structures 202 includes four, and the first gate structures 201 are located between adjacent second gate structures 202.

[0106] In this embodiment, the substrate 200 further includes: a first active region 301 and a second active region 302 located in the first region I, the first active region 301 and the second active region 302 are distributed along the second direction Y, and the first active region 301 and the second active region 302 are separated from each other; a third active region 303 and a fourth active region 304 located in the second region II, the third active region 303 and the fourth active region 304 are distributed along the second direction Y, and the third active region 303 and the fourth active region 304 are separated from each other.

[0107] In this embodiment, the projection of the first metal layer 203 between one first gate structure 201 and the second gate structure 202 on the substrate 200 is located in the first active area 301, and the projection of the first metal layer 203 between another first gate structure 201 and the second gate structure 202 on the substrate 200 is located in the second active area 302; the projection of the second metal layer 204 between one first gate structure 201 and the second gate structure 202 on the substrate 200 is located in the third active area 303, and the projection of the second metal layer 204 between another first gate structure 201 and the second gate structure 202 on the substrate 200 is located in the fourth active area 304; the projection of the first metal layer 203 between adjacent second gate structures 202 on the substrate 200 is located between the first active area 301 and the second active area 302, and the projection of the second metal layer 204 between adjacent second gate structures 202 on the substrate 200 is located between the third active area 303 and the fourth active area 304.

[0108] The semiconductor structure is subsequently applied to a hybrid metal back-end process with a double diffusion break (DDB) structure, which requires two second gate structures 202; it can also be applied to a hybrid metal back-end process with a single diffusion break (SDB) structure, thus having a wider range of applications.

[0109] Figure 8 and Figure 9 It is a structural schematic diagram of a semiconductor structure forming process in one embodiment of the present invention.

[0110] Please refer to Figure 8 , Figure 8 For Figure 6 Based on the schematic diagram, several conductive layers are formed on the first metal layer 203 and the second metal layer 204 . The several conductive layers are parallel to the second direction Y, and the conductive layers are electrically connected to the first plug 205 .

[0111] In this embodiment, the substrate 200 includes a first side and a second side opposite to each other along the second direction Y; the first metal layer includes a first layer 221 and a second layer 222 arranged from the first side to the second side, and includes a third layer 223 and a fourth layer 224 arranged from the second side to the first side; the second metal layer includes a fifth layer 225 and a sixth layer 226 arranged from the first side to the second side, and includes a seventh layer 227 and an eighth layer 228 arranged from the second side to the first side.

[0112] In this embodiment, the conductive layer includes: a third conductive layer 230, wherein the third conductive layer 230 is electrically connected to the second layer 222 and the third layer 223 through a first plug; a fourth conductive layer 231, wherein the fourth conductive layer 231 is electrically connected to the first layer 221 and the fourth layer 224 through a first plug; a fifth conductive layer 233, wherein the fifth conductive layer 233 is electrically connected to the sixth layer 226 and the seventh layer 227 through a second plug; a sixth conductive layer 234, wherein the sixth conductive layer 234 is electrically connected to the fifth layer 225 through a second plug; and a seventh conductive layer 235, wherein the seventh conductive layer 235 is electrically connected to the eighth layer 228 through a second plug.

[0113] The conductive layer further includes an eighth conductive layer 232 located on the gate plug 210 in the isolation region III.

[0114] In another embodiment, Figure 8 For Figure 7 Schematic diagram based on the foundation.

[0115] Please refer to Figure 9 , a plurality of connection layers are formed on the conductive layer, wherein the connection layers are parallel to the first direction X and are selectively electrically connected to the conductive layer.

[0116] In this embodiment, the connecting layer includes: a first connecting layer 241, the first connecting layer 241 is electrically connected to the first conductive layer 211 and the fourth conductive layer 231; a second connecting layer 242, the second connecting layer 242 is electrically connected to the third conductive layer 230 and the seventh conductive layer 235; and a third connecting layer 243, the third connecting layer 243 is electrically connected to the second conductive layer 212 and the sixth conductive layer 234.

[0117] In this embodiment, several third plugs 251 and fourth plugs 252 are also formed on the several conductive layers. The connection layer is electrically connected to the conductive layer on the first region I through the third plugs 251, and the connection layer is electrically connected to the conductive layer on the second region II through the second plugs 252.

[0118] In this embodiment, the first conductive layer 211 serves as a power supply line VDD. The first conductive layer 211 is electrically connected to the first layer 221 and the fourth layer 224 via the first connecting layer 241 and the fourth conductive layer 231. The first layer 221 and the fourth layer 224 are electrically connected to the first source and drain doped regions on both sides of the bottom gate structure. The power supply line VDD is connected to the corresponding first active area 310 via the first connecting layer 241 and the fourth conductive layer 231.

[0119] In this embodiment, the second conductive layer 212 is a ground line VSS. The second conductive layer 212 is electrically connected to the fifth layer 225 via the third connecting layer 243 and the sixth conductive layer 234. The fifth layer 225 is electrically connected to the second source and drain doped regions on both sides of the bottom gate structure. The ground line VSS is connected to the corresponding second active area 311 via the third connecting layer 243 and the sixth conductive layer 234.

[0120] The semiconductor structure is formed by Figure 6 or Figure 7 A conductive layer and a connecting layer are formed on the semiconductor structure unit. Figure 6 or Figure 7 In the semiconductor structure unit, the first metal layer 203, the second metal layer 204, the first plug 205, the second plug 206, the first conductive layer 211 and the second conductive layer 212 are all fixed, and the number of masks used to form the first metal layer 203, the second metal layer 204, the first plug 205, the second plug 206, the first conductive layer 211 and the second conductive layer 212 is also fixed. It is only necessary to adjust the positions of the conductive layer, the connecting layer, the third plug 251 and the fourth plug 252 according to the design requirements to meet the design requirements, that is, the number of fixed masks is increased, thereby saving the number of masks and reducing costs.

[0121] Figure 9 The semiconductor structure described in this embodiment realizes the logic function of a 2-input NAND gate (NAND2). The first metal layer 203, the second metal layer 204, the first plug 205, the second plug 206, the first conductive layer 211 and the second conductive layer 212 in the bottom semiconductor structure unit are fixed. The logical connection function of the circuit is realized through the conductive layer and the upper connection layer. The design is simple, saving masks and area.

[0122] In another embodiment, the gate plug may not be formed on the first gate structure in the isolation region, and the connection function of the gate plug may be achieved through the upper conductive layer and the connection layer.

[0123] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 9 ,include:

[0124] like Figure 6 The semiconductor structure unit; several conductive layers located on the first metal layer, several of the conductive layers are parallel to the second direction Y, and the conductive layers are electrically connected to the first plug; a connecting layer located on the several conductive layers, the connecting layer is parallel to the first direction X, and the connecting layer is selectively electrically connected to the conductive layer.

[0125] In this embodiment, the substrate 200 includes a first side and a second side opposite to each other along the second direction Y; the first metal layer includes a first layer 221 and a second layer 222 arranged from the first side to the second side, and includes a third layer 223 and a fourth layer 224 arranged from the second side to the first side; the second metal layer includes a fifth layer 225 and a sixth layer 226 arranged from the first side to the second side, and includes a seventh layer 227 and an eighth layer 228 arranged from the second side to the first side.

[0126] In this embodiment, the conductive layer includes: a third conductive layer 230, wherein the third conductive layer 230 is electrically connected to the second layer 222 and the third layer 223 through a first plug; a fourth conductive layer 231, wherein the fourth conductive layer 231 is electrically connected to the first layer 221 and the fourth layer 224 through a first plug; a fifth conductive layer 233, wherein the fifth conductive layer 233 is electrically connected to the sixth layer 226 and the seventh layer 227 through a second plug; a sixth conductive layer 234, wherein the sixth conductive layer 234 is electrically connected to the fifth layer 225 through a second plug; and a seventh conductive layer 235, wherein the seventh conductive layer 235 is electrically connected to the eighth layer 228 through a second plug.

[0127] In this embodiment, the conductive layer further includes an eighth conductive layer 232 located on the gate plug 210 in the isolation region III.

[0128] In this embodiment, the connecting layer includes: a first connecting layer 241, the first connecting layer 241 is electrically connected to the first conductive layer 211 and the fourth conductive layer 231; a second connecting layer 242, the second connecting layer 242 is electrically connected to the third conductive layer 230 and the seventh conductive layer 235; and a third connecting layer 243, the third connecting layer 243 is electrically connected to the second conductive layer 212 and the sixth conductive layer 234.

[0129] In this embodiment, it also includes: a plurality of third plugs 251 and a fourth plug 252 located on the plurality of conductive layers, the connection layer is electrically connected to the conductive layer on the first region I through the third plug 251, and the connection layer is electrically connected to the conductive layer on the second region II through the second plug 252.

[0130] Figure 10 FIG. 1 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

[0131] Please refer to Figure 10 , the semiconductor structure includes: a plurality of Figure 6 The semiconductor structure units are arranged in a regular pattern.

[0132] In this embodiment, the plurality of semiconductor structures are arranged along the second direction Y. In two adjacent semiconductor structure units, the first side of the substrate in one semiconductor structure unit is connected to the second side of the substrate in the other semiconductor structure unit.

[0133] The figure schematically shows a situation where three semiconductor structure units are arranged along the second direction Y. In other embodiments, there may be other numbers of semiconductor structure units, such as 2, 4, 5 or more than 5.

[0134] In this embodiment, in two adjacent semiconductor structure units, half of the second dummy gate structure 202 on the first side of the substrate 200 of one semiconductor structure unit and half of the second dummy gate structure 202 on the second side of the substrate 200 of the other semiconductor structure unit are merged into one second dummy gate structure 202.

[0135] In other embodiments, the semiconductor structure includes: a plurality of Figure 7 The semiconductor structure unit includes a plurality of semiconductor structures arranged along the second direction Y.

[0136] The semiconductor structure can be used to design complex logic circuits, such as multiplexer circuits (MUX), latch circuits (LATCH), bistable trigger circuits (Flip-Flop), etc. The semiconductor structure adopts Figure 6 or Figure 7 The semiconductor structural unit structure saves area.

[0137] Figure 11 FIG. 1 is a schematic structural diagram of a semiconductor structure in another embodiment of the present invention.

[0138] Please refer to Figure 11 , the semiconductor structure includes: a plurality of Figure 6 or Figure 7 The semiconductor structure units are arranged in a regular pattern.

[0139] In this embodiment, the plurality of semiconductor structure units are arranged along a first direction X and a second direction Y. In two adjacent semiconductor structure units along the second direction Y, the first side of the substrate in one semiconductor structure unit is connected to the second side of the substrate in the other semiconductor structure unit. In two adjacent semiconductor structure units along the first direction X, the second region II in one semiconductor structure unit is connected to the second region II in the other semiconductor structure unit, and the first region I in one semiconductor structure unit is connected to the first region I in the other semiconductor structure unit.

[0140] The figure schematically shows the arrangement of four semiconductor structure units in a first direction X and a second direction Y. The number of semiconductor structure units arranged in the first direction X is two, and the number of semiconductor structure units arranged in the second direction Y is two.

[0141] In other embodiments, the number of semiconductor structure units arranged in the first direction X and the second direction Y may be other numbers, such as 1, 3, 4, 5, or more than 5. The number of semiconductor structure units arranged in the first direction X and the second direction Y may be equal or unequal.

[0142] In this embodiment, in two adjacent semiconductor structure units along the first direction X, half of the second dummy gate structure 202 on the first side of the substrate 200 of one semiconductor structure unit and half of the second dummy gate structure 202 on the second side of the substrate 200 of the other semiconductor structure unit are merged into one second dummy gate structure 202.

[0143] In other embodiments, the semiconductor structure includes: a plurality of Figure 7 In the semiconductor structure unit, a plurality of semiconductor structures are arranged along a first direction X and a second direction Y.

[0144] The semiconductor structure can be used to design complex logic circuits, such as multiplexer circuits (MUX), latch circuits (LATCH), bistable trigger circuits (Flip-Flop), etc. The semiconductor structure adopts Figure 6 or Figure 7 The semiconductor structural unit structure saves area.

[0145] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure unit, characterized in that: include: a substrate comprising a first region and a second region arranged along a first direction, wherein the first direction is parallel to a surface of the substrate; a plurality of first gate structures and a plurality of second gate structures located on the substrate, wherein the first gate structures are located between adjacent second gate structures, the first gate structures and the second gate structures are parallel to a second direction, the first gate structures and the second gate structures span the first region and the second region, and the second direction is parallel to the substrate surface and perpendicular to the first direction; a plurality of first metal layers located on the first gate structure and the second gate structure in the first region, wherein the first metal layers are parallel to the first direction; a plurality of second metal layers located on the first gate structure and the second gate structure in the second region, wherein the second metal layers are parallel to the first direction; a plurality of first plugs located on the plurality of first metal layers, wherein one first plug is located on one first metal layer; a plurality of second plugs located on the second metal layer, wherein one second plug is located on one second metal layer; a first conductive layer located on the first metal layer in the first region, the first conductive layer being parallel to the second direction and located on a side of the first region away from the second region; A second conductive layer is located on the second metal layer in the second region, the second conductive layer is parallel to the second direction, and the second conductive layer is located on a side of the second region away from the first region.

2. The semiconductor structure unit according to claim 1, wherein: The projection of the first metal layer on the substrate is located between the adjacent first gate structure and the second gate structure; the projection of the second metal layer on the substrate is located between the adjacent first gate structure and the second gate structure.

3. The semiconductor structure unit according to claim 1, wherein: The substrate further includes an isolation region located between the first region and the second region; and a first isolation layer located in the isolation region, the first isolation layer electrically isolating the first metal layer from the second metal layer.

4. The semiconductor structure unit according to claim 3, wherein: The first isolation layer further isolates the second gate structure on the first region and the second region.

5. The semiconductor structure unit according to claim 1, wherein: Also includes: a second isolation layer located in the first region, the second isolation layer being parallel to the second direction, and the first conductive layer being located on the second isolation layer; A third isolation layer is located in the second region, the third isolation layer is parallel to the second direction, and the second conductive layer is located on the third isolation layer.

6. The semiconductor structure unit according to claim 1, wherein: The first plugs on two adjacent first metal layers are staggered in the second direction; and the second plugs on two adjacent second metal layers are staggered in the second direction.

7. The semiconductor structure unit according to claim 1, wherein: Also includes: A gate plug is located on the first gate structure on the isolation region.

8. The semiconductor structure unit according to claim 2, wherein: The number of the first gate structures includes 2, the number of the second gate structures includes 3, and the first gate structures and the second gate structures are alternately arranged in parallel along the second direction.

9. The semiconductor structure unit according to claim 8, wherein: The substrate further includes: a first active area located in the first region, wherein a projection of the first metal layer on the substrate is located in the first active area; and a second active area located in the second region, wherein a projection of the second metal layer on the substrate is located in the second active area.

10. The semiconductor structure unit according to claim 2, wherein: The number of the first gate structures includes 2, and the number of the second gate structures includes 4.

11. The semiconductor structure unit according to claim 10, wherein: The substrate also includes: a first active area and a second active area located in the first area, the first active area and the second active area are distributed along the second direction, the first active area and the second active area are separated from each other, a projection of the first metal layer between the first gate structure and the second gate structure on the substrate is located in the first active area, and a projection of the first metal layer between another first gate structure and the second gate structure on the substrate is located in the second active area; a third active area and a fourth active area located in the second area, the third active area and the fourth active area are distributed along the second direction, the third active area and the fourth active area are separated from each other, a projection of the second metal layer between the first gate structure and the second gate structure on the substrate is located in the third active area, and a projection of the second metal layer between another first gate structure and the second gate structure on the substrate is located in the fourth active area.

12. A method for forming a semiconductor structure unit, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region arranged along a first direction, the first direction being parallel to a surface of the substrate; forming a plurality of first gate structures and a plurality of second gate structures on a substrate, wherein the first gate structures are located between adjacent second gate structures, the first gate structures and the second gate structures are parallel to a second direction, the first gate structures and the second gate structures span the first region and the second region, and the second direction is parallel to the substrate surface and perpendicular to the first direction; forming a plurality of first metal layers on the first region, wherein the first metal layers are parallel to a first direction and are located on the first gate structure and the second gate structure; forming a plurality of second metal layers on the second region, wherein the second metal layers are parallel to the first direction and are located on the first gate structure and the second gate structure; forming a plurality of first plugs on the plurality of first metal layers, wherein one first plug is located on one first metal layer; forming a plurality of second plugs on the second metal layer, wherein one second plug is located on one second metal layer; forming a first conductive layer on the first metal layer in the first region, wherein the first conductive layer is parallel to the second direction and is located on a side of the first region away from the second region; A second conductive layer is formed on the second metal layer in the second region, wherein the second conductive layer is parallel to the second direction and is located on a side of the second region away from the first region.

13. The method for forming a semiconductor structure unit according to claim 12, wherein: The projection of the first metal layer on the substrate is located between the adjacent first gate structure and the second gate structure; the projection of the second metal layer on the substrate is located between the adjacent first gate structure and the second gate structure.

14. The method for forming a semiconductor structure unit according to claim 12, wherein: The substrate further includes an isolation region located between the first region and the second region; and further includes: forming a first isolation layer located in the isolation region, the first isolation layer electrically isolating the first metal layer from the second metal layer.

15. The method for forming a semiconductor structure unit according to claim 14, wherein: The first isolation layer further isolates the second gate structure on the first region and the second region.

16. The method for forming a semiconductor structure unit according to claim 12, wherein: Also includes: A second isolation layer is formed in the first area, the second isolation layer is parallel to the second direction, and the first conductive layer is located on the second isolation layer; a third isolation layer is formed in the second area, the third isolation layer is parallel to the second direction, and the second conductive layer is located on the third isolation layer.

17. The method for forming a semiconductor structure unit according to claim 12, wherein: The first plugs on two adjacent first metal layers are staggered in the second direction; and the second plugs on two adjacent second metal layers are staggered in the second direction.

18. The method for forming a semiconductor structure unit according to claim 12, wherein: The number of the first gate structures includes 2, the number of the second gate structures includes 3, and the first gate structures and the second gate structures are alternately arranged in parallel along the second direction; or, the number of the first gate structures includes 2, and the number of the second gate structures includes 4.

19. A semiconductor structure, characterized in that include: The semiconductor structure unit as described in any one of Figures 1 to 11; a plurality of conductive layers located on the first metal layer and the second metal layer, wherein the plurality of conductive layers are parallel to the second direction and are electrically connected to the first plug; A connection layer is located on the plurality of conductive layers, the connection layer is parallel to the first direction, and the connection layer is selectively electrically connected to the conductive layers.

20. The semiconductor structure according to claim 19, wherein The substrate includes a first side and a second side opposite to each other along a second direction; the first metal layer includes a first layer and a second layer arranged from the first side to the second side, and includes a third layer and a fourth layer arranged from the second side to the first side; the second metal layer includes a fifth layer and a sixth layer arranged from the first side to the second side, and includes a seventh layer and an eighth layer arranged from the second side to the first side.

21. The semiconductor structure according to claim 20, wherein The conductive layer includes: a third conductive layer, the third conductive layer is electrically connected to the second layer and the third layer through a first plug; a fourth conductive layer, the fourth conductive layer is electrically connected to the first layer and the fourth layer through a first plug; a fifth conductive layer, the fifth conductive layer is electrically connected to the sixth layer and the seventh layer through a second plug; a sixth conductive layer, the sixth conductive layer is electrically connected to the fifth layer through a second plug; and a seventh conductive layer, the seventh conductive layer is electrically connected to the eighth layer through a second plug.

22. The semiconductor structure according to claim 21, wherein The connecting layer includes: a first connecting layer, which is electrically connected to the first conductive layer and the fourth conductive layer; a second connecting layer, which is electrically connected to the third conductive layer and the seventh conductive layer; and a third connecting layer, which is electrically connected to the second conductive layer and the sixth conductive layer.

23. The semiconductor structure according to claim 20, wherein: The conductive layer further includes an eighth conductive layer located on the gate plug in the isolation region.

24. The semiconductor structure according to claim 19, wherein Also includes: A plurality of third plugs and a fourth plug are located on the plurality of conductive layers. The connection layer is electrically connected to the conductive layer on the first region through the third plugs. The connection layer is electrically connected to the conductive layer on the second region through the second plugs.

25. A semiconductor structure, characterized in that include: A plurality of semiconductor structure units as described in any one of Figures 1 to 11 are arranged in a regular splicing pattern.

26. The semiconductor structure according to claim 25, wherein: The plurality of semiconductor structures are arranged along the second direction. In two adjacent semiconductor structure units, the first side of the substrate in one semiconductor structure unit is connected to the second side of the substrate in the other semiconductor structure unit.

27. The semiconductor structure according to claim 25, wherein Multiple semiconductor structure units are arranged along a first direction and a second direction. Among two adjacent semiconductor structure units along the second direction, the first side of the substrate in one semiconductor structure unit is connected to the second side of the substrate in the other semiconductor structure unit. Among two adjacent semiconductor structure units along the first direction, the second region in one semiconductor structure unit is connected to the first region in the other semiconductor structure unit.

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