Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a preparation method thereof, and a photovoltaic module. The solar cell comprises a silicon substrate; the first passivation contact structures are located on the back face of the silicon substrate, and each first passivation contact structure comprises a first tunneling layer and a first doped crystalline silicon layer; the interval grooves are located between the adjacent first passivation contact structures, and passivation insulating layers are arranged on the side walls of the interval grooves; the second passivation contact structure is located in the interval groove, the second passivation contact structure comprises a second tunneling layer and a second doped crystalline silicon layer, and the doping type of the second doped crystalline silicon layer is opposite to that of the first doped crystalline silicon layer; the first electrode is in contact with the first doped crystalline silicon layer; and the second electrode is in contact with the second doped crystalline silicon layer. According to the solar cell, the passivation insulating layers are arranged on the side walls of the interval grooves, so that the electric leakage risk between the N region and the P region can be effectively reduced, and the overall efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaics, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] With the iterative development of photovoltaic technology, various new technologies and new battery structures are constantly being developed and improved, and the efficiency of solar cells is also continuously updated. Among them, TOPCon (Tunnel Oxide Passivated Contact) and BC (Back Contact) batteries are generally considered by the industry to be the future development direction of solar cells.

[0003] The new battery structure formed by combining Topcon battery technology and BC battery technology is called TBC battery; related TBC batteries generally have the problem of contact leakage and short circuit between the N region and the P region, which seriously limits the development of TBC batteries.

[0004] In view of this, it is necessary to provide an improved solar cell and a preparation method thereof, and a photovoltaic module to solve the above technical problems. Summary of the Invention

[0005] The present invention provides a solar cell and a preparation method thereof, and a photovoltaic module, which are helpful to improve the contact leakage problem between the P region and the N region on the back of the cell, thereby improving the cell efficiency.

[0006] In order to achieve one of the above-mentioned objects, the present invention adopts the following technical solution:

[0007] A solar cell comprising:

[0008] Silicon substrate;

[0009] a plurality of first passivation contact structures located on the back side of the silicon substrate, wherein the first passivation contact structures include a first tunneling layer and a first doped crystalline silicon layer;

[0010] a spacing groove located between adjacent first passivation contact structures, wherein a passivation insulating layer is formed on a sidewall of the spacing groove;

[0011] a second passivation contact structure located in the spacing trench, the second passivation contact structure comprising a second tunneling layer and a second doped crystalline silicon layer, the second doped crystalline silicon layer and the first doped crystalline silicon layer having opposite doping types;

[0012] a first electrode, contacting the first doped crystalline silicon layer;

[0013] The second electrode contacts the second doped crystalline silicon layer.

[0014] Furthermore, the passivation insulating layer is an aluminum oxide layer, and the thickness of the passivation insulating layer is 0.2 nm to 1.2 nm.

[0015] Furthermore, along the thickness direction of the silicon substrate, the second passivation contact structure does not exceed the spacing groove.

[0016] Furthermore, the first tunneling layer is an aluminum oxide layer, and the thickness of the first tunneling layer is 0.5 nm to 2.5 nm; and / or the second tunneling layer is an aluminum oxide layer, and the thickness of the second tunneling layer is 0.5 nm to 2.5 nm.

[0017] Furthermore, the silicon substrate is an N-type silicon wafer, and the first doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20cm -3 ~3E21cm -3 , the thickness of the second doped crystalline silicon layer is 60nm to 120nm;

[0018] Alternatively, the silicon substrate is a P-type silicon wafer, and the first doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20 cm -3 ~3E21cm -3 The thickness of the second doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm.

[0019] Furthermore, the first electrode and the second electrode each include a plurality of connecting portions distributed along a first direction, and connecting gate lines connecting the connecting portions, wherein the connecting portions include closed gate lines, internal gate lines extending inward from the closed gate lines, and external gate lines extending outward from the closed gate lines.

[0020] Furthermore, the connecting portion of the first electrode and the connecting portion of the second electrode are staggered along a first direction.

[0021] Furthermore, the outer gate line extends outward from the intersection of the closed gate line and the inner gate line.

[0022] Furthermore, all the internal grid lines are compared at at least one intersection.

[0023] Furthermore, the closed grid lines are in a square shape, and the inner grid lines and the closed grid lines are in a grid shape.

[0024] Furthermore, the solar cell further comprises:

[0025] a back passivation layer and a back anti-reflection layer located on the back sides of the first passivation contact structure and the second passivation contact structure, wherein the first electrode passes through the back anti-reflection layer and the back passivation layer to contact the first doped crystalline silicon layer, and the second electrode passes through the back anti-reflection layer and the back passivation layer to contact the second doped crystalline silicon layer;

[0026] A front passivation layer and a front anti-reflection layer are sequentially arranged on the front surface of the silicon substrate.

[0027] A method for preparing a solar cell comprises the following steps:

[0028] forming a plurality of first passivation contact structures spaced apart from each other on the back side of the silicon substrate, wherein the first passivation contact structures include a first tunneling layer and a first doped crystalline silicon layer;

[0029] forming a passivation insulating layer on sidewalls of the spacing grooves between adjacent first passivation contact structures;

[0030] forming a second passivation contact structure in the spacing groove, wherein the second passivation contact structure includes a second tunneling layer and a second doped crystalline silicon layer, wherein the second doped crystalline silicon layer and the first doped crystalline silicon layer have opposite doping types;

[0031] A first electrode and a second electrode are formed on the back surface, respectively contacting the first doped crystalline silicon layer and the second doped crystalline silicon layer.

[0032] Furthermore, the “several first passivation contact structures” include the following steps:

[0033] forming a first tunneling layer and a first doped crystalline silicon layer on the entire back side of the silicon substrate;

[0034] A mask layer is formed on the back side of the first doped polysilicon layer, and then a portion of the first tunneling layer and the first doped crystalline silicon layer is removed by trenching to form a plurality of the spacing trenches.

[0035] Furthermore, the mask layer is an oxide layer formed by oxidation on the surface of the first doped crystalline silicon layer, and the spacer groove is formed by a laser grooving process, and the laser parameters are: power 20W~35W, frequency 250kHz~1500kHz, and pulse width 3-50ns; or, a layer of photoresist is printed on the surface of the first doped crystalline silicon layer, and then the spacer groove is formed by a wet grooving process; wherein, the wet etching solution is a mixture of hydrofluoric acid, nitric acid and acetic acid, an aqueous solution with a molar ratio of 3:50:20, a total molar concentration of 2%~8%, an etching time of 90s~200s, and a reaction temperature of 40℃~80℃.

[0036] Furthermore, “forming a passivation insulating layer on the sidewall of the spacing groove” includes the following steps:

[0037] forming a passivation insulating layer in the spacing groove;

[0038] The passivation insulating layer in the middle area and the bottom of the spacing groove is removed, and the passivation insulating layer on the side wall of the spacing groove is retained.

[0039] Furthermore, “forming a passivation insulating layer on the sidewall of the spacing groove” includes the following steps:

[0040] forming a passivation insulating layer on the entire back surface;

[0041] Removing the passivation insulating layer in the middle area and the bottom of the spacing groove, and retaining the passivation insulating layer on the sidewall of the spacing groove;

[0042] Clean the passivation insulation layer outside the spacing groove.

[0043] Furthermore, the passivation insulating layer is an aluminum oxide layer, and the thickness of the aluminum oxide layer retained on the side wall of the spacing groove is 0.2nm~1.2nm; preferably, a laser process is used to remove the aluminum oxide layer in the middle area and bottom of the spacing groove, and the laser parameters are: power 20W~35W, frequency 250kHz~1500kHz, and pulse width 3ns~50ns.

[0044] Furthermore, along the thickness direction of the silicon substrate, the second passivation contact structure does not exceed the spacing groove.

[0045] Furthermore, the first tunneling layer is an aluminum oxide layer, and the thickness of the first tunneling layer is 0.5 nm to 2.5 nm; and / or the second tunneling layer is an aluminum oxide layer, and the thickness of the second tunneling layer is 0.5 nm to 2.5 nm.

[0046] Furthermore, the silicon substrate is an N-type silicon wafer, and the first doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20cm -3 ~3E21cm -3 , the thickness of the second doped crystalline silicon layer is 60nm to 120nm;

[0047] Alternatively, the silicon substrate is a P-type silicon wafer, and the first doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20 cm -3 ~3E21cm -3The thickness of the second doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60 nm to 120 nm.

[0048] Furthermore, the first electrode and the second electrode each include a plurality of connecting portions distributed along a first direction, and connecting gate lines connecting the connecting portions, wherein the connecting portions include closed gate lines, internal gate lines extending inward from the closed gate lines, and external gate lines extending outward from the closed gate lines.

[0049] Preferably, the connecting portion of the first electrode and the connecting portion of the second electrode are staggered along a first direction.

[0050] Preferably, the outer gate line extends outward from an intersection of the closed gate line and the inner gate line.

[0051] Preferably, all internal grid lines cross at least one point.

[0052] Preferably, the closed grid lines are square, the inner grid lines and the closed grid lines are in a grid pattern, and the outer grid lines extend outward from the closed grid lines along a second direction, which is perpendicular to the first direction.

[0053] Furthermore, before forming the first electrode and the second electrode, the method for preparing a solar cell further includes:

[0054] forming a front passivation layer and a front anti-reflection layer on the front surface;

[0055] forming a back passivation layer and a back anti-reflection layer on the back surface;

[0056] The first electrode sequentially passes through the back anti-reflection layer and the back passivation layer to contact the first doped crystalline silicon layer, and the second electrode sequentially passes through the back anti-reflection layer and the back passivation layer to contact the second doped crystalline silicon layer.

[0057] A photovoltaic module, comprising:

[0058] A solar cell as described above;

[0059] an insulating strip located between the first electrode and the second electrode;

[0060] The back plate comprises an insulating base plate, an adhesive film layer located on the insulating base plate and a current collector. The first electrode and the second electrode are respectively connected to the current collector through conductive paste or conductive glue.

[0061] Furthermore, the first electrode and the second electrode each include a plurality of connecting portions distributed along a first direction and connecting grid lines connecting the connecting portions, wherein the connecting portions include closed grid lines, internal grid lines extending inward from the closed grid lines, and external grid lines extending outward from the closed grid lines; the conductive adhesive or conductive paste is located within the closed grid lines and contacts all the internal grid lines. The beneficial effects of the present invention are as follows: the solar cell of the present invention, by providing a passivation insulating layer on the sidewalls of the spacing groove, can, on the one hand, effectively reduce the risk of leakage between the N region and the P region, thereby improving the overall efficiency of the solar cell; on the other hand, the first passivation contact structure, the second passivation contact structure, and the passivation insulating layer completely passivate the back side of the entire silicon substrate, thereby reducing interface recombination and improving cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a schematic diagram after forming a first tunneling layer and a first doped crystalline silicon layer on a silicon substrate;

[0063] Figure 2 For Figure 1 Schematic diagram after forming a plurality of first passivation contact structures and spacing grooves on the basis;

[0064] Figure 3 For Figure 2 Schematic diagram of forming a full-surface passivation insulating layer on the base;

[0065] Figure 4 For Figure 3 Schematic diagram of removing the passivation insulating layer in the middle area of ​​the spacing groove;

[0066] Figure 5 For Figure 4 A schematic diagram of a second passivation contact structure formed in the spacing groove based on the present invention;

[0067] Figure 6 For Figure 5 Schematic diagram of removing the passivation insulating layer outside the spacing groove;

[0068] Figure 7 For Figure 6 Schematic diagram after forming a front passivation layer and a front anti-reflection layer on the front surface;

[0069] Figure 8 For Figure 7 Schematic diagram of a back surface anti-reflection layer formed on the back surface of the base;

[0070] Figure 9 is a schematic diagram after forming a first electrode and a second electrode on the basis of FIG;

[0071] Figure 10 Schematic diagram of the first electrode and the second electrode on the back side of a solar cell;

[0072] Figure 11 is a schematic diagram of the connecting portion of the first electrode and the second electrode;

[0073] Figure 12 For Figure 10 Schematic diagram of the base after coating with insulating glue and conductive glue;

[0074] Figure 13 for Figure 12 Schematic side view of

[0075] Figure 14 is a schematic diagram of a backplane in one embodiment of the present invention;

[0076] Figure 15 Schematic diagram of a current collector in one embodiment of the present invention.

[0077] Among them, 100-solar cell, 1-silicon substrate, 2-first passivation contact structure, 21-first tunneling layer, 22-first doped crystalline silicon layer, 3-spacer groove, 31-passivation insulating layer, 4-second passivation contact structure, 41-second tunneling layer, 42-second doped crystalline silicon layer, 5-first electrode, 51-connecting portion, 52-connecting gate line, 521-enclosed gate line, 522-inner gate line, 523-external gate line, 6-second electrode, 7-back anti-reflection layer, 8-front passivation layer, 9-front anti-reflection layer, 10-insulating glue, 11-conductive paste or conductive glue, 12-back plate, 121-insulating bottom plate, 122-adhesive film layer, 123-current collector. DETAILED DESCRIPTION

[0078] The present invention will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0079] In the various drawings of the present invention, for the sake of convenience, some sizes of structures or parts are exaggerated relative to other structures or parts, and thus, are only used to illustrate the basic structure of the subject matter of the present invention.

[0080] The inventors have discovered that during the TBC cell fabrication process, a natural oxide layer forms at the interface between the N- and P-regions after laser or wet chemical etching, reducing leakage. However, the growth of this natural oxide layer is uncertain and uncontrollable, posing significant challenges to mass production and process control. The present invention aims to optimize cell structural design and fabrication processes. A solar cell 100 and its fabrication method are proposed, in which a passivation insulating layer 31 is grown at the interface between the N- and P-regions, completely resolving the leakage issue at this interface.

[0081] Please refer to Figures 1 to 9 , illustrating a method for preparing a solar cell in one embodiment of the present invention; please refer to Figure 9 , illustrating a solar cell 100 according to a preferred embodiment.

[0082] Please refer to Figure 9 As shown, the solar cell 100 includes a silicon substrate 1, a plurality of first passivation contact structures 2 located on the back side of the silicon substrate 1, a spacing groove 3 located between adjacent first passivation contact structures 2, a second passivation contact structure 4 located in the spacing groove 3, a first electrode 5 located on the back side of the first passivation contact structure 2, and a second electrode 6 located on the back side of the second passivation contact structure 4.

[0083] The silicon substrate 1 can be an N-type silicon wafer or a P-type silicon wafer as the base of the solar cell 100 .

[0084] The first passivation contact structure 2 includes a first tunneling layer 21 and a first doped crystalline silicon layer 22 , and the second passivation contact structure 4 includes a second tunneling layer 41 and a second doped crystalline silicon layer 42 , which prevent the first electrode 5 and the second electrode 6 from directly contacting the silicon substrate 1 and reduce electron recombination.

[0085] The first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42 may be doped polycrystalline silicon layers or doped microcrystalline silicon layers. The first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42 have opposite doping types, that is, the first passivation contact structure 2 and the second passivation contact structure 4 have opposite doping types. One of the first passivation contact structures 2 and the second passivation contact structure 4 constitute the P region of the solar cell 100, and the other constitutes the N region. Thus, alternating P regions and N regions are formed on the back side of the silicon substrate 1.

[0086] Preferably, the first tunneling layer 21 and / or the second tunneling layer 41 is an aluminum oxide layer. On the one hand, the aluminum oxide layer can be formed using an ALD process, and its thickness can be precisely controlled, specifically by controlling the number of ALD process cycles. On the other hand, compared to traditional silicon oxide and silicon oxynitride tunneling layers, the aluminum oxide layer has a better passivation effect on the surface of the silicon substrate 1. Furthermore, Al can also be doped into the silicon substrate 1, further increasing the open circuit voltage (Voc) of the battery.

[0087] In one embodiment, the thickness of the first tunneling layer 21 and the second tunneling layer 41 is 0.5 nm to 2.5 nm, corresponding to 3 to 20 ALD turns, which meets the requirements of passivation and electron transition and can also provide excellent passivation effect, thereby improving the efficiency of the solar cell 100.

[0088] The doping types of the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42 are adaptively adjusted according to the silicon substrate 1 .

[0089] When the silicon substrate 1 is an N-type silicon wafer, the first doped crystalline silicon layer 22 is boron-doped with a doping concentration of 1E20 cm^-3 to 9E20 cm^-3; the thickness of the first doped crystalline silicon layer 22 is 60 nm to 120 nm. The second doped crystalline silicon layer 42 is phosphorus-doped with a doping concentration of 2E20 cm^-3 to 3E21 cm^-3; the thickness of the second doped crystalline silicon layer 42 is 60 nm to 120 nm. By selecting appropriate doping concentrations and thickness ranges, the conductivity and stability of the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42 can be optimized, thereby ensuring the performance and stability of the solar cell 100.

[0090] On the contrary, when the silicon substrate 1 is a P-type silicon wafer, the first doped crystalline silicon layer 22 is phosphorus-doped, and the second doped layer is boron-doped. The doping concentration and thickness are set as above and will not be repeated here.

[0091] The sidewalls of the spacing groove 3 are provided with a passivation insulating layer 31, which, on the one hand, can effectively reduce the risk of leakage between the N region and the P region and improve the overall efficiency of the solar cell 100; on the other hand, the first passivation contact structure 2, the second passivation contact structure 4 and the passivation insulating layer 31 completely passivate the back side of the entire silicon substrate 1, reducing interface recombination and improving battery efficiency.

[0092] Preferably, the passivation insulating layer 31 is an aluminum oxide layer, which ensures insulation and reduces the possibility of leakage. It also passivates the sides of the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42. The thickness of the aluminum oxide layer on the sidewalls is set to 0.2nm to 1.2nm, which reduces the distance between the first passivation contact structure 2 and the second passivation contact structure 4, improves the effective area utilization, and improves the battery efficiency.

[0093] Along the thickness direction of the silicon substrate 1, the second passivation contact structure 4 does not exceed the spacing groove 3. On the one hand, all side surfaces of the second passivation contact structure 4 are surrounded by the aluminum oxide layer, which improves the passivation effect of the side surfaces of the second doped crystalline silicon layer 42; on the other hand, the thickness of the second tunneling layer 41 and the second doped crystalline silicon layer 42 is moderate, which helps to improve the structural stability of the solar cell 100 and avoid structural damage or electrical performance problems caused by exceeding the spacing groove 3.

[0094] In one embodiment, the second passivation contact structure 4 is lower than the first passivation contact structure 2 , that is, the second passivation contact structure 4 is completely located in the spacing groove 3 , and a portion of the second electrode 6 is also located in the spacing groove 3 , which can prevent the gate line from tilting or deflecting.

[0095] In another embodiment, the second passivation contact structure 4 is at the same height as the first passivation contact structure 2 , and the two are substantially in the same plane, which facilitates the formation of the first electrode 5 and the second electrode 6 by screen printing.

[0096] In addition, the first passivation contact structure 2 and the second passivation contact structure 4 are generally in the shape of an elongated strip. For ease of description, the first passivation contact structure 2 and the second passivation contact structure 4 are defined as extending along a first direction, and a direction perpendicular to the first direction is defined as a second direction. The first passivation contact structure 2 and the second passivation contact structure 4 are spaced apart along the second direction, and the first electrode 5 and the second electrode 6 are also spaced apart along the second direction.

[0097] In the present invention, the first electrode 5 and the second electrode 6 are both main-gate-free electrodes, and the first electrode 5 and the second electrode 6 both include a plurality of connecting portions 51 distributed along a first direction and connecting gate lines 52 connecting the connecting portions 51. This can reduce the amount of slurry while ensuring effective contact between the first electrode 5 and the first doped crystalline silicon layer 22, and between the second electrode 6 and the second doped crystalline silicon layer 42, thereby improving the performance of the solar cell 100.

[0098] The connecting portion 51 is used to electrically connect to the soldering ribbon and includes a closed grid line 521, a plurality of internal grid lines 522 extending inward from the closed grid line 521, and a plurality of external grid lines 523 extending outward from the closed grid line 521. The internal grid lines 522 and external grid lines 523 increase the coverage area of ​​the electrode on the polysilicon layer, thereby increasing the contact area between the electrode and the polysilicon layer, effectively preventing grid breakage, and further improving the connection stability between the solar cell 100 and the soldering ribbon.

[0099] Preferably, the connecting portion 51 of the first electrode 5 and the connecting portion 51 of the second electrode 6 are staggered along the first direction, which helps to evenly distribute current, reduce resistance loss, and improve the conductivity and overall efficiency of the solar cell 100.

[0100] Preferably, the external gate line 523 extends outward from the intersection of the closed gate line 521 and the internal gate line 522, that is, the internal gate line 522 and the external gate line 523 are at the same position on the closed gate line 521. Even if the closed gate line 521 is broken, the current collected by the external gate line 523 can also be converged to the internal gate line 522.

[0101] Furthermore, all the internal gate lines 522 form a connected conductive network inside the closed gate line 521 at at least one intersection.

[0102] In a specific embodiment, the closed grid lines 521 are square, the inner grid lines 522 and the closed grid lines 521 are in a grid pattern, and the outer grid lines 523 extend outward from the closed grid lines 521 along the second direction, so that the graphic screen design is simple.

[0103] The staggered connection portions 51 of the first electrode 5 and the second electrode 6 , as well as the design of the closed grid lines 521 and the grid-like internal grid lines 522 , help to evenly distribute current, reduce resistance loss, and improve the conductivity and overall efficiency of the solar cell 100 .

[0104] In addition, the first electrode 5 and the second electrode 6 are made of different materials, have different wet weights for printing, and have different drying temperatures, so they are separated. In a preferred embodiment, the first electrode 5 uses silver-aluminum paste, has a wet weight of 60g to 80g, and is sintered at a temperature of 500°C to 650°C; the second electrode 6 uses silver paste, has a wet weight of 30g to 60g, and is sintered at a temperature of 650°C to 800°C.

[0105] Furthermore, the solar cell 100 further includes a backside anti-reflection layer 7 located on the backside of the first passivation contact structure 2 and the second passivation contact structure 4. The first electrode 5 contacts the first doped crystalline silicon layer 22 through the backside anti-reflection layer 7, and the second electrode 6 contacts the second doped crystalline silicon layer 42 through the backside anti-reflection layer 7.

[0106] The back anti-reflection layer 7 is used to reduce light reflection on the back side and improve the efficiency of the battery. In the present invention, the back anti-reflection layer 7 is a laminated film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm to 130nm.

[0107] Furthermore, the solar cell 100 further includes a back passivation layer and a back anti-reflection layer 7 located on the back sides of the first passivation contact structure 2 and the second passivation contact structure 4. The first electrode 5 sequentially passes through the back anti-reflection layer 7 and the back passivation layer to contact the first doped crystalline silicon layer 22, and the second electrode 6 sequentially passes through the back anti-reflection layer 7 and the back passivation layer to contact the second doped crystalline silicon layer 42.

[0108] The back passivation layer passivates the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42 to further improve the cell efficiency. In the present invention, an aluminum oxide layer is preferably used as the back passivation layer.

[0109] The back anti-reflection layer 7 is configured as described above and will not be described in detail here.

[0110] Furthermore, the solar cell 100 further includes a front passivation layer 8 and a front anti-reflection layer 9 sequentially disposed on the front surface of the silicon substrate 1 to reduce light reflection loss, improve light absorption efficiency, and reduce interface recombination.

[0111] The front passivation layer 8 can be made of hydrogenated aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, etc., which can reduce surface recombination and improve battery efficiency.

[0112] The front anti-reflection layer can be made of silicon nitride, silicon oxynitride, silicon oxide, etc., which can reduce light reflection and improve light absorption efficiency, thereby improving the photoelectric conversion efficiency of the battery.

[0113] See also Figures 1 to 9 As shown, the present invention also provides a method for preparing a solar cell, comprising the following steps: forming a plurality of first passivation contact structures 2 spaced apart on the back side of a silicon substrate 1, the first passivation contact structure 2 comprising a first tunneling layer 21 and a first doped crystalline silicon layer 22; forming an aluminum oxide layer on the sidewalls of a spacing groove 3 between adjacent first passivation contact structures 2; forming a second passivation contact structure 4 in the spacing groove 3, the second passivation contact structure 4 comprising a second tunneling layer 41 and a second doped crystalline silicon layer 42, the doping type of the second doped crystalline silicon layer 42 being opposite to that of the first doped crystalline silicon layer 22; and forming a first electrode 5 and a second electrode 6 on the back side, the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42 being in contact with the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42, respectively.

[0114] The first passivation contact structure 2 and the second passivation contact structure 4 are isolated by the passivation insulating layer 31 on the sidewall of the spacing groove 3, effectively reducing the risk of leakage and improving the overall efficiency of the solar cell 100; at the same time, the passivation insulating layer 31 can passivate the side surfaces of the first doped crystalline silicon layer 22 and the second doped crystalline silicon layer 42, further improving the cell efficiency.

[0115] The silicon substrate 1 is an N-type silicon wafer or a P-type silicon wafer, and is preferably textured on the front side to improve light absorption.

[0116] Specifically, the silicon wafer is first cleaned to remove surface impurities and pollutants; then, an alkali liquid texturing treatment is used to form a pyramid structure on the surface of the silicon substrate 1 to increase the surface light confinement and improve efficiency.

[0117] Please refer to Figure 1 and Figure 2As shown, forming several of the first passivation contact structures 2 includes the following steps: forming the first tunneling layer 21 and the first doped crystalline silicon layer 22 on the entire back side of the silicon substrate 1; then forming a mask layer on the back side of the first doped crystalline silicon layer 22, and then grooved to remove the first tunneling layer 21 and the first doped crystalline silicon layer 22 corresponding to the spacing grooves 3 to form several of the spacing grooves 3.

[0118] Specifically, an aluminum oxide layer is formed as the first tunneling layer 21 through the ALD process, the number of ALD turns is 3 to 20 turns, and the thickness of the formed first tunneling layer 21 is 0.5 nm to 2.5 nm, which meets the performance of passivation and electron transition, and can also provide an excellent passivation effect, thereby improving the efficiency of the solar cell 100.

[0119] A boron-doped amorphous silicon layer is grown by in-situ doping using PECVD, and annealed at 850° C. to 980° C. to form a first doped crystalline silicon layer 22 with a doping concentration of 1E20 cm^-3 to 9E20 cm^-3. The thickness of the first doped crystalline silicon layer 22 is 60 nm to 120 nm.

[0120] In the present invention, the spacing grooves 3 are formed by trenching under the cover of a mask layer, and the position and size of the first passivation contact structure 2 or the spacing grooves 3 can be precisely controlled, thereby ensuring the consistency of the first passivation contact structure 2 .

[0121] In one embodiment, the mask layer is an oxide layer formed by oxidizing the surface of the first doped crystalline silicon layer 22 , and the spacer grooves 3 are formed on this basis by using a laser grooving process.

[0122] Specifically, the oxide layer formation process involves in-situ doping and growing a boron-doped amorphous silicon layer using PECVD, followed by the introduction of nitrous oxide and silane to grow an oxide layer on the surface. Laser grooving is then performed at locations corresponding to the spacer grooves 3. First, a hole is created in the oxide layer, followed by the removal of the first doped crystalline silicon layer 22 and the first tunneling layer 21 to form the spacer grooves 3. Laser parameters for the laser grooving process are: power 20W-35W, frequency 250kHz-1500kHz, and pulse width 3-50ns.

[0123] In another embodiment, a layer of photoresist is printed on the surface of the first doped crystalline silicon layer 22 , and then the spacer grooves 3 are formed by a wet grooving process.

[0124] Specifically, after coating the photoresist, the pattern on the mask is transferred to the photoresist on the surface of the first doped polysilicon to form a patterned photoresist, exposing the position corresponding to the spacer groove 3, and protecting the underlying material in the subsequent wet etching process.

[0125] The wet etching solution is a mixture of hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH) in a molar ratio of 3:50:20, with a total molar concentration of 2% to 8%. The etching time is 90 seconds to 200 seconds, and the reaction temperature is 40°C to 80°C. The wet etching solution selectively etches the non-photoresist area to form the spacer groove 3.

[0126] The spacer groove 3 is formed by laser grooving or wet grooving process, which can accurately control the position and shape of the spacer groove 3, ensure the integrity of the first tunneling layer 21 and the first doped crystalline silicon layer 22, and improve the passivation effect and electrical performance of the solar cell 100.

[0127] Please refer to Figure 3 and Figure 4 As shown, "forming an aluminum oxide layer on the side wall of the spacing groove 3" includes the following steps: forming the aluminum oxide layer in the spacing groove 3; removing the aluminum oxide layer in the middle area and bottom of the spacing groove 3, and retaining the aluminum oxide layer on the side wall of the spacing groove 3.

[0128] Or "forming an aluminum oxide layer on the side wall of the spacing groove 3" includes the following steps: forming the aluminum oxide layer on the entire back side, removing the aluminum oxide layer in the middle area and bottom of the spacing groove 3, retaining only the aluminum oxide layer on the side wall of the spacing groove 3, and cleaning the aluminum oxide layer outside the spacing groove 3 in a subsequent step.

[0129] Both of the above methods first fill the spacing groove 3 with a slow aluminum oxide layer to ensure that the side wall is completely covered by the aluminum oxide layer, and then remove the aluminum oxide layer in the middle area and the bottom, leaving only the aluminum oxide layer on the side wall, which can ensure the insulation effect of the side wall.

[0130] Preferably, a laser process is used to remove the aluminum oxide layer in the middle area and bottom of the spacing groove 3, and the thickness of the aluminum oxide layer remaining on the sidewall of the spacing groove 3 is 0.2nm to 1.2nm. The laser parameters are: power 20W to 35W, frequency 250kHz to 1500kHz, and pulse width 3ns to 50ns.

[0131] Please refer to Figure 5 and Figure 6 As shown, forming the second passivation contact structure 4 in the spacing groove 3 includes the following steps: first forming an aluminum oxide layer as the second tunneling layer 41 by ALD process, then growing a phosphorus-doped amorphous silicon layer by PECVD in-situ doping, and annealing at 850℃~980℃ to form a first doped crystalline silicon layer 22 with a doping concentration of 2E20cm -3 ~3E21cm -3The thickness of the second doped crystalline silicon layer 42 is 60 nm to 120 nm; the thickness of the first doped crystalline silicon layer 22 is 60 nm to 120 nm.

[0132] As described above, along the thickness direction of the silicon substrate 1, the second passivation contact structure 4 does not exceed the spacing groove 3. On the one hand, all side surfaces of the second passivation contact structure 4 are surrounded by the aluminum oxide layer, which improves the passivation effect of the side surfaces of the second doped crystalline silicon layer 42. On the other hand, the thickness of the second tunneling layer 41 and the second doped crystalline silicon layer 42 is moderate, which helps to improve the structural stability of the solar cell 100 and avoid structural damage or electrical performance problems caused by exceeding the spacing groove 3.

[0133] For further information, please refer to Figure 7 As shown, the method for preparing the solar cell further includes: sequentially forming a front passivation layer 8 and a front anti-reflection layer 9 on the front surface.

[0134] The front passivation layer 8 is a stack of one or more selected from hydrogenated aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride, which can reduce surface recombination and improve battery efficiency.

[0135] The front anti-reflection layer is selected from silicon nitride, silicon oxynitride, silicon oxide, etc., which can reduce light reflection and improve light absorption efficiency, thereby improving the photoelectric conversion efficiency of the battery.

[0136] For further information, please refer to Figure 8 As shown, the preparation method of the solar cell also includes: forming a back anti-reflection layer 7 on the back side, or forming a back passivation layer and a back anti-reflection layer 7 in sequence on the back side; then forming a first electrode 5 and a second electrode 6 on the back side, the first electrode 5 passes through the back anti-reflection layer 7 or passes through the back anti-reflection layer 7 and the back passivation layer in sequence to contact the first doped crystalline silicon layer 22, and the second electrode 6 passes through the back anti-reflection layer 7 or passes through the back anti-reflection layer 7 and the back passivation layer in sequence to contact the second doped crystalline silicon layer 42.

[0137] Among them, the back passivation layer is preferably an aluminum oxide layer, which has good passivation effect and high process controllability.

[0138] The back anti-reflection layer 7 is a laminated film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60 nm to 130 nm, and reduces reflectivity.

[0139] Preferably, the front anti-reflection layer 9 and the back anti-reflection layer 7 are deposited simultaneously, and the process steps are simple.

[0140] Please refer to Figure 9 As shown, the present invention adopts screen printing and sintering processes to form the first electrode 5 and the second electrode 6. The structural shapes of the two electrodes are set as above and will not be repeated here.

[0141] It should be noted that the back passivation layer, the back anti-reflection layer 7, the front passivation layer 8, and the front anti-reflection layer 9 are all non-essential film layers. One or more of these three film layers may not exist in individual batteries, and accordingly, the preparation method does not include corresponding process steps.

[0142] Hereinafter, the present invention will describe in detail the method for preparing the solar cell of the present invention with reference to a specific embodiment.

[0143] S1 selects an N-type silicon wafer as the silicon substrate 1, cleans the stains on the surface, forms a pyramid structure through alkaline texturing, cleans, and polishes the back.

[0144] S2: On the back of the silicon substrate 1, an aluminum oxide layer with a thickness of 1 nm is formed by the ALD process as the first tunneling layer 21, and a P-type poly layer is prepared as the first doped crystalline silicon layer 22; BSG is removed by cleaning, and the structure formed is as follows Figure 1 shown.

[0145] S3 forms a silicon oxide layer as a mask layer on the surface of the first doped crystalline silicon layer 22, uses laser to open holes to form the spacing groove 3, and then cleans the silicon oxide mask layer. Alternatively, print photoresist on the surface of the first doped crystalline silicon layer 22, provide patterned light to make the photoresist form a mask layer, and then open holes by wet etching to form the spacing groove 3, and then clean the photoresist. The structure formed is as shown Figure 2 shown.

[0146] S4 deposits an aluminum oxide film layer on the surface of the patterned P-type poly layer, and laser etches the aluminum oxide film in the spacing groove 3 to form a well-shaped structure, exposing the N-type silicon substrate 1 at the bottom of the spacing groove 3. A 0.2nm to 1.2nm thick aluminum oxide layer remains on the sidewall of the spacing groove 3. The structure formed is as follows Figure 4 shown.

[0147] S5 forms an aluminum oxide layer with a thickness of 0.8 nm as the second tunneling layer 41 at the bottom of the well structure by ALD process, and then grows a phosphorus-doped amorphous silicon layer in situ, and anneals at 850℃~980℃ to form an N-type poly layer as the second doped crystalline silicon layer 42. The structure formed is as follows Figure 5 shown.

[0148] S6 wet cleaning, removes PSG and the aluminum oxide film layer outside the spacing groove 3, and the resulting structure is as follows Figure 6 shown.

[0149] S7 deposits a front passivation layer 8 , the passivation material of which is hydrogenated aluminum oxide, gallium oxide, silicon oxide, silicon nitride or silicon oxynitride.

[0150] S8 deposits the front anti-reflection layer 9, which is made of silicon nitride, silicon oxynitride or silicon oxide. Figure 7 shown.

[0151] S9 deposits silicon nitride or silicon oxynitride on the back side as a back side anti-reflection layer 7, and the resulting structure is as follows: Figure 8 shown.

[0152] S10 screen printing back gate line electrode. Print silver aluminum paste on the back of the first passivation contact structure 2, with a wet weight of 60g to 80g, and sintering temperature of 500℃ to 650℃ to form the first electrode 5. Print silver paste on the back of the second passivation contact structure 4, with a wet weight of 30g to 60g, and sintering temperature of 650℃ to 800℃ to form the second electrode 6. Figure 9 shown.

[0153] The present invention further provides a photovoltaic module, which includes the solar cell 100 and the back sheet 12 as described above.

[0154] Please refer to Figure 14 and Figure 15 As shown, the back plate 12 includes an insulating base plate 121 , an adhesive film layer 122 located on the insulating base plate 121 , and a current collector 123 , which are integrated into one body, thereby simplifying the assembly process.

[0155] The insulating bottom plate 121 can isolate moisture, and in particular prevent the outer adhesive film from being corroded by acetic acid.

[0156] The adhesive film layer 122 is an insulating adhesive film layer, which is bonded to the battery cell.

[0157] Please refer to Figure 15 As shown, the current collector 123 is a conductive pattern, which is a finger-shaped structure in the present invention, corresponding to the arrangement direction of the first electrode 5 and the second electrode 6. Figure 15 The circle in the figure indicates the position or area that matches the conductive paste or conductive glue 11.

[0158] The current collector 123 is located on the side of the adhesive film layer 122 away from the insulating base plate 121 and is formed by spraying or printing a conductive material. This can effectively avoid the problem of difficult waste removal of the existing metal current collector 123, and is low-cost and easy to process.

[0159] The conductive material includes but is not limited to copper, aluminum, silver, graphite and other conductive materials, and may also be conductive ink, paste or other conductors.

[0160] Please refer to Figure 12 、 13As shown, before assembly, an insulating glue 10 is provided between the first electrode 5 and the second electrode 6 to prevent electrical connection between the two. Preferably, the width of the insulating glue 10 is smaller than the spacing between the first electrode 5 and the second electrode 6 to prevent the first electrode 5 and the second electrode 6 from penetrating and connecting at the insulating glue 10.

[0161] Please refer to Figure 12 、 13 As shown, in the present invention, the first electrode 5 and the second electrode 6 are respectively connected to the current collector 123 through a conductive paste or conductive glue 11.

[0162] Preferably, the conductive paste or conductive adhesive 11 is applied within the closed grid lines 521, contacting all of the internal grid lines 522. This increases the contact area between the conductive paste or conductive adhesive 11 and the first electrode 5 and the second electrode 6, and also avoids poor electrical conduction caused by broken grids. Furthermore, the height of the conductive paste or conductive adhesive 11 is greater than that of the insulating adhesive 10, facilitating interconnection with the backplane 12.

[0163] The present invention also provides a method for preparing a photovoltaic module, comprising the following steps:

[0164] An insulating glue 10 is coated between the first electrode 5 and the second electrode 6 , and the width of the insulating glue 10 is smaller than the distance between the first electrode 5 and the second electrode 6 .

[0165] Conductive paste or conductive glue 11 is coated on the first electrode 5 and the second electrode 6 .

[0166] Drying, preferably using infrared lamps, allows for highly controllable heating, so that the conductive paste or adhesive 11 is semi-cured, forming alloy interconnects with the grid lines, which can then be directly interconnected with the backplane 12. The semi-cured state facilitates the positioning of the solar cells 100 and the backplane 12.

[0167] The adhesive film and glass are stacked in sequence, and the stacked parts are turned over and laminated.

[0168] Cut edges, frame, and cure.

[0169] Through the above steps, the present invention provides a novel busbar-less TBC cell structure and its assembly preparation method that are efficient, stable, and easy to mass-produce. This effectively reduces the risk of leakage, improves the efficiency of the solar cell 100, simplifies the production process, and reduces production costs. Furthermore, half-cell technology can be used at the cell end to maximize silicon material utilization, eliminating the need for laser cutting at the assembly end, reducing laser damage, and increasing assembly power.

[0170] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0171] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; a plurality of first passivation contact structures located on the back side of the silicon substrate, wherein the first passivation contact structures include a first tunneling layer and a first doped crystalline silicon layer; a spacing groove located between adjacent first passivation contact structures, wherein a passivation insulating layer is formed on a sidewall of the spacing groove; a second passivation contact structure located in the spacing trench, the second passivation contact structure comprising a second tunneling layer and a second doped crystalline silicon layer, the second doped crystalline silicon layer and the first doped crystalline silicon layer having opposite doping types; a first electrode, contacting the first doped crystalline silicon layer; The second electrode contacts the second doped crystalline silicon layer.

2. The solar cell according to claim 1, wherein: The passivation insulating layer is an aluminum oxide layer, and the thickness of the passivation insulating layer is 0.2 nm to 1.2 nm.

3. The solar cell according to claim 1, wherein: Along the thickness direction of the silicon substrate, the second passivation contact structure does not exceed the spacing groove.

4. The solar cell according to claim 1, wherein: The first tunneling layer is an aluminum oxide layer, and the thickness of the first tunneling layer is 0.5 nm to 2.5 nm; And / or, the second tunneling layer is an aluminum oxide layer, and the thickness of the second tunneling layer is 0.5 nm to 2.5 nm.

5. The solar cell according to claim 1, wherein: The silicon substrate is an N-type silicon wafer, and the first doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20 cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20cm -3 ~3E21cm -3 , the thickness of the second doped crystalline silicon layer is 60nm to 120nm; Alternatively, the silicon substrate is a P-type silicon wafer, and the first doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20 cm -3 ~3E21cm -3 The thickness of the second doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm.

6. The solar cell according to claim 1, wherein: The first electrode and the second electrode each include a plurality of connection portions distributed along a first direction and connection gate lines connecting the connection portions. The connection portions include closed gate lines, inner gate lines extending inward from the closed gate lines, and outer gate lines extending outward from the closed gate lines.

7. The solar cell according to claim 6, wherein: The connecting portion of the first electrode and the connecting portion of the second electrode are staggered along a first direction; and / or, the outer grid lines extend outward from the intersection of the closed grid lines and the inner grid lines; and / or, all internal grid lines are compared to at least one intersection; And / or, the closed grid lines are in a square shape, and the internal grid lines and the closed grid lines are in a grid shape.

8. The solar cell according to claim 1, wherein: The solar cell further comprises: a back passivation layer and a back anti-reflection layer located on the back sides of the first passivation contact structure and the second passivation contact structure, wherein the first electrode passes through the back anti-reflection layer and the back passivation layer to contact the first doped crystalline silicon layer, and the second electrode passes through the back anti-reflection layer and the back passivation layer to contact the second doped crystalline silicon layer; A front passivation layer and a front anti-reflection layer are sequentially arranged on the front surface of the silicon substrate.

9. A method for preparing a solar cell, characterized in that: The steps include: forming a plurality of first passivation contact structures spaced apart from each other on the back side of the silicon substrate, wherein the first passivation contact structures include a first tunneling layer and a first doped crystalline silicon layer; forming a passivation insulating layer on sidewalls of the spacing grooves between adjacent first passivation contact structures; forming a second passivation contact structure in the spacing groove, wherein the second passivation contact structure includes a second tunneling layer and a second doped crystalline silicon layer, wherein the second doped crystalline silicon layer and the first doped crystalline silicon layer have opposite doping types; A first electrode and a second electrode are formed on the back surface, respectively contacting the first doped crystalline silicon layer and the second doped crystalline silicon layer.

10. The method for preparing a solar cell according to claim 9, wherein: The “several first passivation contact structures” include the following steps: forming a first tunneling layer and a first doped crystalline silicon layer on the entire back side of the silicon substrate; A mask layer is formed on the back side of the first doped polysilicon layer, and then a portion of the first tunneling layer and the first doped crystalline silicon layer is removed by trenching to form a plurality of the spacing trenches.

11. The method for preparing a solar cell according to claim 10, wherein: The mask layer is an oxide layer formed by oxidation on the surface of the first doped crystalline silicon layer. The spacing grooves are formed by a laser grooving process. The laser parameters are: power 20W-35W, frequency 250kHz-1500kHz, and pulse width 3-50ns. Alternatively, a layer of photoresist is printed on the surface of the first doped crystalline silicon layer, and then the spacer groove is formed through a wet grooving process; wherein the wet etching solution is a mixture of hydrofluoric acid, nitric acid and acetic acid, an aqueous solution with a molar ratio of 3:50:20, a total molar concentration of 2% to 8%, an etching time of 90s to 200s, and a reaction temperature of 40°C to 80°C.

12. The method for preparing a solar cell according to claim 9, wherein: “Forming a passivation insulating layer on the sidewall of the spacing groove” includes the following steps: forming a passivation insulating layer in the spacing groove; removing the passivation insulating layer in the middle area and the bottom of the spacing groove, and retaining the passivation insulating layer on the sidewall of the spacing groove; Alternatively, “forming a passivation insulating layer on the sidewall of the spacing trench” includes the following steps: forming a passivation insulating layer on the entire back surface; removing the passivation insulating layer in the middle area and the bottom of the spacing groove, and retaining the passivation insulating layer on the sidewall of the spacing groove; Clean the passivation insulation layer outside the spacing groove.

13. The method for preparing a solar cell according to claim 12, wherein: The passivation insulating layer is an aluminum oxide layer, and the thickness of the aluminum oxide layer retained on the sidewall of the spacing groove is 0.2nm to 1.2nm; Preferably, a laser process is used to remove the aluminum oxide layer in the middle area and the bottom of the spacing groove, and the laser parameters are: power 20W to 35W, frequency 250kHz to 1500kHz, and pulse width 3ns to 50ns.

14. The method for preparing a solar cell according to claim 9, wherein: Along the thickness direction of the silicon substrate, the second passivation contact structure does not exceed the spacing groove.

15. The method for preparing a solar cell according to claim 9, wherein: The first tunneling layer is an aluminum oxide layer, and the thickness of the first tunneling layer is 0.5 nm to 2.5 nm; And / or, the second tunneling layer is an aluminum oxide layer, and the thickness of the second tunneling layer is 0.5 nm to 2.5 nm.

16. The solar cell according to claim 9, wherein: The silicon substrate is an N-type silicon wafer, and the first doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20 cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20cm -3 ~3E21cm -3 , the thickness of the second doped crystalline silicon layer is 60nm to 120nm; Alternatively, the silicon substrate is a P-type silicon wafer, and the first doped crystalline silicon layer is a phosphorus-doped crystalline silicon layer with a doping concentration of 2E20 cm -3 ~3E21cm -3 The thickness of the second doped crystalline silicon layer is 60nm to 120nm; the second doped crystalline silicon layer is a boron-doped crystalline silicon layer with a doping concentration of 1E20cm -3 ~9E20cm -3 The thickness of the first doped crystalline silicon layer is 60nm to 120nm.

17. The method for preparing a solar cell according to claim 9, wherein: The first electrode and the second electrode each include a plurality of connecting portions distributed along a first direction, and connecting grid lines connecting the connecting portions, wherein the connecting portions include a closed grid line, an inner grid line extending inward from the closed grid line, and an outer grid line extending outward from the closed grid line; wherein Preferably, the connecting portion of the first electrode and the connecting portion of the second electrode are staggered along the first direction; Preferably, the outer grid lines extend outward from the intersection of the closed grid lines and the inner grid lines; Preferably, all internal grid lines cross at least one point; Preferably, the closed grid lines are square, the inner grid lines and the closed grid lines are in a grid pattern, and the outer grid lines extend outward from the closed grid lines along a second direction, which is perpendicular to the first direction.

18. The method for preparing a solar cell according to claim 9, wherein: Before forming the first electrode and the second electrode, the method for preparing a solar cell further includes: forming a front passivation layer and a front anti-reflection layer on the front surface; forming a back passivation layer and a back anti-reflection layer on the back surface; The first electrode sequentially passes through the back anti-reflection layer and the back passivation layer to contact the first doped crystalline silicon layer, and the second electrode sequentially passes through the back anti-reflection layer and the back passivation layer to contact the second doped crystalline silicon layer.

19. A photovoltaic module, characterized in that: include: A solar cell, comprising a solar cell arrangement according to any one of claims 1 to 8; an insulating strip located between the first electrode and the second electrode; The back plate comprises an insulating base plate, an adhesive film layer located on the insulating base plate and a current collector. The first electrode and the second electrode are respectively connected to the current collector through conductive paste or conductive glue.

20. The photovoltaic module according to claim 19, characterized in that: Both the first electrode and the second electrode include a plurality of connecting portions distributed along a first direction and connecting grid lines connecting the connecting portions, wherein the connecting portions include closed grid lines, internal grid lines extending inward from the closed grid lines, and external grid lines extending outward from the closed grid lines; the conductive glue or conductive paste is located within the closed grid lines and contacts all the internal grid lines.

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