Infrared transmitter and manufacturing method thereof
By applying glue protection in the MEMS structure area and combining photolithography and chemical mechanical polishing methods, the problem of copper residue in the MEMS array area was solved and effective chip packaging was achieved.
Patent Information
- Application Number
- CN202510769588.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-10
- Publication Date
- 2025-09-09
AI Technical Summary
After chemical mechanical polishing of copper in the MEMS array area, copper residue remains in the CMOS PAD area, making it impossible to effectively package the chip.
After the MEMS structure area is protected by glue, the metal residue in the CMOS PAD area is removed by photolithography, and a barrier layer and photoresist material are used for protection, and the copper residue is removed by combining chemical mechanical polishing and wet etching methods.
The copper residue in the CMOS PAD area is effectively removed, ensuring that the chip packaging can proceed normally without affecting subsequent process steps.
Smart Images
Figure CN120614920A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and in particular relates to an infrared emitter and a manufacturing method thereof. Background Art
[0002] The operating principle of an infrared emitter is generally to use certain semiconductor materials (such as infrared light-emitting diodes, or IRLEDs) to generate infrared light when current passes through them. MEMS infrared light sources (infrared emitters) manufactured using microelectromechanical systems (MEMS) technology are a new type of thermal radiation infrared light source, characterized by high electro-optical conversion efficiency, compact size, and low energy consumption. They have been widely used in the field of infrared sensing and have become a trend-setting technology for infrared light sources. The technology of monolithic integration of microelectromechanical systems (MEMS) and integrated circuits (CMOS) has been widely used. When infrared emitters are manufactured using MEMS and CMOS monolithic integration processes, copper filling and copper chemical mechanical polishing (Cu CMP) are required due to the high current flow. Before copper CMP, the height difference between the CMOS pad area and the MEMS array area is large.
[0003] Currently, due to the height difference between the PAD area and the MEMS array area, even if the copper CMP of the MEMS array area is completed, copper remains on the CMOS PAD area around each chip (DIE). This causes the entire DIE to be unable to be packaged due to CMOS PAD anomalies at the customer end. Summary of the Invention
[0004] In view of all or part of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide an infrared emitter and a manufacturing method thereof, which can effectively remove copper residues in the CMOS PAD area without affecting the MEMS structure area, thereby ensuring effective final DIE packaging.
[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:
[0006] The present invention provides a method for manufacturing an infrared emitter, comprising the following steps:
[0007] Step 1: Select a substrate, and process the integrated circuit region, MEMS structure region, and pad structure region of the infrared emitter on the substrate;
[0008] Step 2: When the integrated circuit area and the MEMS structure area are led out through metal wires, it is necessary to form holes and then fill them with metal, and grow a barrier layer before filling;
[0009] Step 3: Remove the portion of the barrier layer where the hole is to be formed by photolithography, further form the hole, fill the hole with metal, and perform chemical mechanical polishing;
[0010] Step 4: applying glue to the MEMS structure area for protection, exposing and developing the pattern of the non-MEMS structure area, i.e., the pattern of the pad structure area, through a photolithography process, and removing the metal residue in the pad structure area;
[0011] Step 5: removing the remaining barrier layer.
[0012] The infrared emitter provided by the present invention is obtained based on the monolithic integration of a micro-electromechanical system (MEMS) and an integrated circuit IC (CMOS). The large plane height difference between the MEMS structure area and the pad structure area causes chemical mechanical polishing to be unable to act on the pad structure area, i.e., the CMOS PAD area. By pre-coating the MEMS structure area with glue for protection, the metal residue in the CMOS PAD area is removed, thereby ensuring that the final DIE packaging can be carried out. Before step three of chemical mechanical polishing, a barrier layer is pre-grown to ensure the effect of chemical mechanical polishing, while having no effect on the subsequent chip processes (including photolithography alignment, etc.). Moreover, the barrier layer can also prevent metal residues in non-MEMS structure areas, especially the pad structure area, from falling directly on the surface after chemical mechanical polishing, so as to avoid affecting other layers of materials when the metal residues are removed.
[0013] In step 4, the non-MEMS structure area also includes the integrated circuit area, and the process further includes exposing and developing the pattern of the integrated circuit area through a photolithography process to remove any metal residue from the integrated circuit area. The MEMS structure area is protected by applying a photoresist coating to the integrated circuit area, the MEMS structure area, and the pad structure area on the substrate. All metal residue from the non-MEMS structure area, including the integrated circuit area and the pad structure area, is removed simultaneously.
[0014] In step 2, the barrier layer is made of one or more materials selected from silicon nitride and silicon oxide; the barrier layer has a thickness of 2K-4K angstroms. Silicon nitride is preferred, and a barrier layer of an appropriate thickness of 2K-4K angstroms is selected so that removal of the barrier layer does not affect the metal fill surface pattern.
[0015] In step 2, the metal is selected from one or more of copper, aluminum, tungsten and alloys thereof.
[0016] In step 4, the time for coating the MEMS structure area with glue for protection is within 24 hours after the chemical mechanical polishing treatment in step 3 is completed; the material of the coating is positive photoresist, and the thickness of the coating is 2um-4um. When copper (taking this as an example) is selected as the metal filling material, after the copper chemical mechanical polishing is completed, in order to avoid the surface copper oxidation affecting the subsequent removal of the copper material, preferably within 24 hours after the chemical mechanical polishing, the MEMS structure area is coated with glue for protection, that is, the integrated circuit area, the MEMS structure area and the pad structure area on the substrate are all spin-coated with a photoresist material. The coverage of the photoresist material can avoid the oxidation of the copper on the surface of the MEMS structure area and the oxidation of the copper remaining on the surface of the integrated circuit area and the pad structure area. Copper oxidation affects the subsequent removal of copper residues.
[0017] In step three, chemical mechanical polishing (CMP) is used to remove excess metal material above the MEMS structure. The CMP method includes the following steps: first, using a polishing slurry to remove most of the metal material on the surface of the barrier layer; second, using a polishing slurry to polish the metal material in contact with the barrier layer at a low speed, and using endpoint detection technology to stop the polishing on the barrier layer; third, using a polishing slurry to polish away the metal material at the top of the hole filling located in the plane of the barrier layer; and finally, cleaning the surface of the barrier layer. The metal material at the top of the hole filling is not part of the final metal via and can therefore be removed in advance.
[0018] In step 4, the metal residue is removed by wet etching. The conditions of the wet etching are as follows: the main components of the etching solution used are hydrogen peroxide, nitric acid, hydrofluoric acid, tetramethylammonium hydroxide and water; the temperature of the wet etching is 30-40°C.
[0019] In step five, the barrier layer is removed by dry etching. The dry etching conditions are as follows: the main components of the etching gas used are CF4: 40-60 sccm, CHF3: 10-30 sccm, AR: 80-110 sccm, O2: 5-20 sccm; the dry etching pressure is controlled at 40-60 mtorr.
[0020] The MEMS structure region is a MEMS array region, and a plane height difference between the deepest surface of the MEMS structure region and the deepest surface of the pad structure region is greater than or equal to 15 μm.
[0021] The present invention also provides an infrared emitter, which is manufactured using the above-mentioned method for manufacturing an infrared emitter. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 This is a schematic flow chart of a method for manufacturing an infrared emitter in Example 1.
[0024] Figure 2 It is a schematic diagram of the structure of each layer involved in the MEMS structure area in Example 1.
[0025] Figure 3 This is an image of the plane height of the pad structure area and the MEMS structure area in Example 1.
[0026] Figure 4 This is an image of the metal residue in the CMOS PAD pad structure area after chemical mechanical polishing in Example 1.
[0027] Figure 5 These are images of the MEMS structure region before and after the barrier layer is etched and removed in Example 1.
[0028] Reference numerals: 1 - substrate; 2 - MEMS structure region; 3 - dielectric layer; 4 - barrier layer; 5 - hole; 6 - metal filling region; 7 - CMOS top metal layer; 8 - photoresist protection layer. DETAILED DESCRIPTION
[0029] The following is a clear and complete description of the technical solutions in the specific embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.
[0030] It should be noted that, in order to describe the technical solution more specifically, the steps described in the following embodiments do not strictly correspond one-to-one with the steps described in the summary of the invention.
[0031] Example 1
[0032] The present invention provides a method for manufacturing an infrared emitter, referring to Figure 1 and Figure 2 , including the following steps:
[0033] Step 1: Select substrate 1 (equivalent to the CMOS structure layer) and process the infrared emitter integrated circuit region, MEMS structure region 2 and pad structure region on substrate 1; MEMS structure region 2 is the MEMS array region, and the plane height difference between the deepest surface of MEMS structure region 2 and the deepest surface of the pad structure region is greater than or equal to 15 μm. Figure 3 a and Figure 3 In figure b, a is the plane height image of the CMOS PAD (pad structure area) surface, and b is the plane height image of the MEMS structure area 2. It can be seen that the deepest surface of the pad structure area reaches 20um, while the deepest surface of the MEMS array area is only 4.6um. The plane height difference between the two exceeds 15um.
[0034] Step 2: A dielectric layer 3 is formed on the integrated circuit region and MEMS structure region 2. When the integrated circuit region and MEMS structure region 2 are led out through metal wires, holes need to be formed and then filled with metal. Before filling, a barrier layer 4 is grown on top of the dielectric layer 3. In this embodiment, the barrier layer 4 is made of silicon nitride with a thickness of 2K-4K angstroms. In other embodiments, the barrier layer 4 can also be made of silicon oxide or a combination of silicon oxide and silicon nitride. The metal filling is copper. In other embodiments, the filling metal can also be selected from one or more of aluminum, tungsten, and alloys thereof.
[0035] Step 3: Remove part of the barrier layer 4 at the location where the hole 5 is to be formed by photolithography, further form the hole 5, fill the hole 5 with metal copper, and perform chemical mechanical polishing. The chemical mechanical polishing is used to remove the excess copper material above the MEMS structure area 2. The specific method of the chemical mechanical polishing (Cu CMP polishing process) includes: the first step, using copper polishing liquid to grind away most of the copper material on the wafer surface (specifically the surface of the barrier layer 4 in this embodiment); the second step, using the same copper polishing liquid, but using a lower polishing rate to finely grind the copper material in contact with the barrier layer 4, and using the endpoint detection technology (Endpoint) to stop the grinding on the barrier layer 4; the third step, using the polishing liquid to grind away the copper material at the top of the hole 5 located on the plane where the barrier layer 4 is located (see Figure 2 The polishing pad and wafer (particularly the surface of barrier layer 4) are cleaned with a large amount of deionized water (DIW). A CMOS top metal layer 7 is formed between the metal filling area 6 and the substrate 1.
[0036] In this embodiment, the copper polishing liquid used is a cerium oxide polishing liquid, which has a high selectivity for silicon nitride and can automatically terminate polishing to a certain extent. Because in the later stages of CMP, the polishing efficiency of this stage is dominated by the cerium oxide particles and additive particles in the polishing liquid. Since the surface of silicon nitride is positively charged, a layer of negatively charged additive particles is adsorbed on its surface, forming a solid barrier layer; at the same time, since the positively charged cerium oxide particles and the positively charged silicon nitride repel each other, the polishing rate of the cerium oxide polishing liquid on silicon nitride is very low, and the polishing can automatically terminate on the barrier layer 4. After chemical mechanical polishing, copper residues can be clearly seen on the CMOS PAD (pad structure area), see Figure 4 .
[0037] Step 4: Within 24 hours after completing the chemical mechanical polishing treatment in step 3, the MEMS structure area 2 is coated with glue for protection, and a photoresist protective layer 8 is formed on the surface. That is, the integrated circuit area, MEMS structure area 2, and pad structure area on the substrate 1 are all spin-coated with photoresist material. Timely coating within 24 hours can prevent oxidation of copper on the surface of the MEMS structure area 2 and oxidation of residual copper on the surfaces of the integrated circuit area and pad structure area. Copper oxidation affects the subsequent removal of copper residues. The coating material is a high-resolution positive photoresist with a coating thickness of 2um-4um. Too thick a coating is not convenient for subsequent removal. The pattern of the non-MEMS structure area, including the pattern of the pad structure area and the integrated circuit area, is exposed and developed through a photolithography process. There are two possible scenarios for photolithography: 1. Photolithography is performed directly after coating; 2. If photolithography is performed after a period of time after coating, the protective photoresist should be removed, and then re-coated immediately, and then the photolithography process should be performed to avoid poor photoresist failure and poor photolithography results.
[0038] After the portion of the photoresist protective layer 8 above the pad structure region and the integrated circuit region is removed by photolithography, the metal residue on the barrier layer 4 is exposed. The metal residue in the pad structure region and the integrated circuit region is removed by wet etching. The wet etching conditions are as follows: the main components of the copper etching solution used are H2O2 (hydrogen peroxide), HNO3 (nitric acid), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), and water. The H2O2 oxidizes the copper metal, the HNO3 and HF etch the copper oxide, and the TMAH acts as a pH stabilizer. The wet etching temperature is 30-40°C.
[0039] Step 5: Remove the remaining barrier layer 4 by dry etching. The dry etching conditions are as follows: the main components of the etching gas used are: CF4: 40-60 sccm, CHF3: 10-30 sccm, AR: 80-110 sccm, O2: 5-20 sccm; the dry etching pressure is controlled at 40-60 mtorr. Figure 5 a and Figure 5 b in the figure, where a is the image before the barrier layer 4 is completely etched away, and b is the image after the barrier layer 4 is completely etched away. By comparison, it can be seen that after the barrier layer 4 is dry-etched away with an appropriate thickness of 2K-4K angstroms, the MEMS array area has no effect on the copper surface pattern except for a slight difference in overall color.
[0040] In CMOS manufacturing, the formation of planar height differences (i.e., differences in surface step heights between different regions) is a phased process, dependent on both the initial design of the ASIC (application-specific integrated circuit) and subsequent manufacturing steps. This planar height difference is already present in the initial substrate 1 containing the CMOS structural layer. The method provided by the present invention, such as pre-coating of the MEMS structural region 2 with a protective adhesive, can mitigate the effects of this planar height difference on the overall DIE caused by copper residue after Cu CMP.
[0041] Example 2
[0042] An infrared emitter is manufactured using the method for manufacturing an infrared emitter in Example 1.
[0043] In a manufacturing method of an infrared emitter provided by the present invention, a special treatment method is adopted for areas of the infrared emitter where copper chemical mechanical polishing (CMP) cannot be performed, such as the pad structure area, namely the CMOS PAD area. By pre-coating the MEMS structure area 2 with glue for protection and then removing the copper residue in the pad structure area and the integrated circuit area, it is ensured that the final chip DIE packaging can be effectively carried out.
[0044] The above embodiments are only intended to help understand the method and core concept of the present invention. It should be noted that, without departing from the principles of the present invention, a number of improvements and modifications may be made to the present invention by those skilled in the art, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for manufacturing an infrared emitter, characterized in that: The following steps are involved: Step 1: selecting a substrate (1), and processing the substrate (1) to obtain an integrated circuit region, a MEMS structure region (2), and a pad structure region of the infrared emitter; Step 2: When the integrated circuit region and the MEMS structure region (2) are led out through metal wires, it is necessary to form holes and then fill them with metal, and grow a barrier layer (4) before filling; Step 3: removing a portion of the barrier layer (4) at a location where a hole is to be formed by a photolithography process, further forming the hole (5), filling the hole (5) with metal, and performing a chemical mechanical polishing process; Step 4: applying glue to the MEMS structure area (2) for protection, exposing and developing the pattern of the non-MEMS structure area, i.e., the pattern of the pad structure area, through a photolithography process, and removing the metal residue in the pad structure area; Step 5: removing the remaining barrier layer (4).
2. The method for manufacturing an infrared emitter according to claim 1, wherein: In step 4, the non-MEMS structure area also includes the integrated circuit area, and the process further includes exposing and developing the pattern of the integrated circuit area through a photolithography process to remove metal residues in the integrated circuit area.
3. The method for manufacturing an infrared emitter according to claim 1, wherein: In step 2, the material of the barrier layer (4) is selected from one or more of silicon nitride and silicon oxide; the thickness of the barrier layer (4) is 2K-4K angstroms.
4. The method for manufacturing an infrared emitter according to claim 1, wherein: In step 2, the metal is selected from one or more of copper, aluminum, tungsten and alloys thereof.
5. The method for manufacturing an infrared emitter according to claim 1, wherein: In step 4, the time for coating the MEMS structure area (2) with glue for protection is within 24 hours after the chemical mechanical polishing treatment in step 3 is completed; the coating material is positive photoresist, and the thickness of the coating is 2um-4um.
6. The method for manufacturing an infrared emitter according to claim 1, wherein: In step three, the chemical mechanical polishing is used to remove excess metal material located above the MEMS structure area (2), and the chemical mechanical polishing method includes: a first step, using a polishing liquid to grind off most of the metal material on the surface of the barrier layer (4); a second step, using a polishing liquid to grind the metal material in contact with the barrier layer (4) at a low speed, and using an end point detection technology to stop the grinding on the barrier layer (4); a third step, using a polishing liquid to grind off the metal material at the top of the hole (5) located on the plane where the barrier layer (4) is located; and cleaning the surface of the barrier layer (4).
7. The method for manufacturing an infrared emitter according to claim 1, wherein: In step 4, the metal residue is removed by wet etching. The conditions of the wet etching are as follows: the main components of the etching solution used are hydrogen peroxide, nitric acid, hydrofluoric acid, tetramethylammonium hydroxide and water; the temperature of the wet etching is 30-40°C.
8. The method for manufacturing an infrared emitter according to claim 1, wherein: In step five, the barrier layer (4) is removed by dry etching, and the dry etching conditions are as follows: the main components of the etching gas used are CF4: 40-60 sccm, CHF3: 10-30 sccm, AR: 80-110 sccm, O2: 5-20 sccm; the dry etching pressure is controlled at 40-60 mtorr.
9. The method for manufacturing an infrared emitter according to claim 1, wherein: The MEMS structure region (2) is a MEMS array region, and the plane height difference between the deepest surface of the MEMS structure region (2) and the deepest surface of the pad structure region is greater than or equal to 15 μm.
10. An infrared transmitter, characterized in that: The infrared emitter is manufactured using the manufacturing method of any one of claims 1 to 9.