A crystalline silicon / perovskite tandem solar cell and its fabrication method

Abstract

This invention provides a crystalline silicon / perovskite tandem solar cell and its fabrication method. Applied to perovskite / crystalline silicon tandem solar cells, the method involves preparing a first and second edge passivation layer after the buffer layer and transparent electrode layer are fabricated. This improves the protection effect on the edge cut surfaces of the tandem cell, reducing the risk of erosion, damage, or impurity penetration of the thin film in the crystalline silicon / perovskite tandem cell. The resulting edge protection structure also improves the uniformity and continuity of the deposited transparent conductive layer and metal grid lines in the edge region, reducing the potential leakage risk of the thin film layer, lowering parallel resistance loss, and improving the device's fill factor and open-circuit voltage. By setting two edge passivation layers for protection, the negative impact of each transparent electrode deposition and metal grid line fabrication process on sensitive edge regions can be reduced, significantly improving device stability and photoelectric conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of perovskite tandem solar cell technology, specifically to a crystalline silicon / perovskite tandem solar cell and its fabrication method. Background Technology

[0002] Crystalline silicon solar cells are currently the dominant technology in the photovoltaic market, accounting for over 90% of the global market. However, the photoelectric conversion efficiency of crystalline silicon cells theoretically has a limit (the Shockley-Queisser limit), approximately 29%. Currently, the efficiency of commercially available crystalline silicon cells is typically around 20%, and even top-tier laboratory cells only achieve around 26%, relatively close to the theoretical limit. To overcome this efficiency bottleneck, researchers have begun exploring tandem cell technology. Crystalline silicon-perovskite tandem solar cells have attracted widespread attention in the photovoltaic field in recent years due to the excellent photoelectric properties of perovskite materials, such as high absorption coefficients, tunable band gaps, and simple manufacturing processes.

[0003] In the traditional production of crystalline silicon perovskite tandem solar cells, the finished tandem cells are often subjected to edge passivation treatment. Although this can reduce the carrier recombination rate in the edge region to improve the photoelectric efficiency and stability of the device, the passivation process does not take into account the physical damage to the bottom film and its edge region and the electrical protection issues caused by the preparation of transparent electrodes and metal grid lines, thus affecting the effectiveness of edge passivation.

[0004] For example, during the fabrication of transparent electrodes, the deposition of transparent electrode layers (such as ITO, AZO, etc.) will form a new, continuous conductive layer edge on the edge of the original structure (perovskite cell / buffer layer), which can easily cause serious leakage problems with subsequent metal grid lines or other parts of the cell. Moreover, the deposition process of transparent electrode layers (especially sputtering) can also easily cause serious sputtering damage or generate new defects to the bottom film layer and its edges.

[0005] Moreover, in the existing tandem battery manufacturing process, laser cutting is often used to cut the finished battery, which greatly increases the possibility of water and oxygen erosion and carrier recombination defects on the cut surface. The damage to sensitive areas such as the perovskite film layer and the edge surface of the device caused by the transparent electrode layer and metal grid line fabrication process can easily lead to an increase in carrier recombination defects at the thin film interface and edge, thereby reducing the overall lifespan and reliability of the device.

[0006] Therefore, there is an urgent need for an edge passivation process to address the thin-film interface and edge recombination defects and commercialization issues of existing tandem solar cells. Summary of the Invention

[0007] To address the challenge of applying traditional edge passivation processes to tandem solar cells, this invention provides a crystalline silicon / perovskite tandem solar cell and its fabrication method. In perovskite / crystalline silicon tandem solar cells, edge passivation is performed after the buffer layer and transparent electrode layer are fabricated. The combined effect of these two passivation layers effectively reduces carrier recombination losses at the thin film interface and device edge regions, thereby improving the conversion efficiency and stability of the solar cell module.

[0008] To achieve the above objectives, the present invention provides the following specific solution:

[0009] This application provides a crystalline silicon / perovskite tandem solar cell, comprising a crystalline silicon bottom cell, a perovskite top cell, a buffer layer, and a transparent electrode layer stacked sequentially from bottom to top. A first edge passivation layer and a second edge passivation layer are sequentially disposed on the four sides of the crystalline silicon bottom cell, the perovskite top cell, and the buffer layer. The second edge passivation layer also covers the four sides of the transparent electrode layer. Metal grid lines are also fabricated on the top and bottom surfaces of the tandem solar cell.

[0010] Furthermore, the buffer layer of the crystalline silicon / perovskite tandem solar cell can be removed, and the first edge passivation layer covers the four sides of the crystalline silicon bottom cell and the perovskite top cell.

[0011] Furthermore, the first edge passivation layer and the second edge passivation layer can be composed of thin films such as aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100 nm.

[0012] In one embodiment, the buffer layer may be composed of oxide materials such as SnO2, Yb2O3, TiO2, and Al2O3, with a thickness of 5~30nm.

[0013] In one embodiment, the transparent electrode layer may be composed of one of the following transparent materials: ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), IWO (tungsten-doped indium oxide), etc., with a thickness of 20~140nm.

[0014] In one embodiment, the metal grid line may be composed of materials such as Ag, Cu, Al, metal alloy, multilayer metal composite grid line, silver-clad metal layer, and silver-clad metal oxide grid line. The metal grid line includes a main grid line and a fine grid line. The main grid line has a thickness of 5~40um and a width of 20~1500um, and the fine grid line has a thickness of 5~30um and a width of 10~100um.

[0015] In one embodiment, the perovskite top cell includes a hole transport layer, a perovskite layer, and an electron transport layer disposed on a crystalline silicon bottom cell.

[0016] The hole transport layer is selected from poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), poly-3-hexylthiophene (P3HT), and nickel oxide (NiO). x One or more of molybdenum trioxide (MoO3), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN).

[0017] In this embodiment, the perovskite layer can be composed of an ABX3 structure, wherein,

[0018] The A site is an organic cation, including CH3NH3. + (MA + ), NH2CH=NH2 + (FA + CH3CH2NH3 + or Cs + One or more of them;

[0019] The B site is a metal cation, including Pb. 2+ Sn 2+ One or more of them;

[0020] The X-position is a halide anion, including F. - Cl - ,Br - I - One or more of them.

[0021] In this embodiment, the electron transport layer is composed of zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), and [6,6]-phenyl C. 61 Methyl butyrate (PC) 61 BM), C60 (C 60 One or more of ), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP).

[0022] In another embodiment, the perovskite top solar cell further includes a perovskite passivation layer disposed between the perovskite layer and the electron transport layer. The perovskite passivation layer is composed of at least one of two-dimensional perovskite, phenylethylamine iodide (PEAI), polymethyl methacrylate (PMMA), ammonium halide (NH4X), cesium halide (CsX), and lead halide (PbX2), and has a thickness of 5-80 nm.

[0023] Furthermore, the crystalline silicon / perovskite tandem solar cell also includes a third edge passivation layer, which is disposed on the side of the first edge passivation layer away from the second edge passivation layer; the third edge passivation layer covers the four edges of the crystalline silicon bottom cell, the hole transport layer, and the perovskite layer, or the third edge passivation layer covers the four edges of the crystalline silicon bottom cell, the hole transport layer, the perovskite layer, and the perovskite passivation layer; the third edge passivation layer can be composed of thin films such as alumina, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100 nm.

[0024] In one embodiment, the crystalline silicon base cell may be selected from one of the crystalline silicon cell structures such as PERC cell, Topcon cell, or HJT cell.

[0025] Furthermore, the PERC cell, from bottom to top, includes a passivation film, an aluminum back surface field, a P-type silicon wafer, and an N+ emitter;

[0026] Furthermore, the topcon battery comprises, from bottom to top, a p+ emitter passivation film, a p+ emitter, an N-type silicon substrate, an ultrathin tunneling oxide layer, and a phosphorus-doped polycrystalline silicon layer;

[0027] Furthermore, the HJT battery comprises, from bottom to top, a first transparent electrode layer, a P-type substrate doped layer, a substrate passivation layer, a silicon substrate, a substrate surface passivation layer, and an N-type substrate doped layer.

[0028] In one embodiment, a tunneling layer is further provided between the crystalline silicon bottom cell and the perovskite top cell. The tunneling layer is composed of oxide materials such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 1~80nm. The tunneling layer enables efficient recombination and tunneling transport of charge carriers in the series cell, while minimizing optical and electrical losses.

[0029] This application also provides a method for fabricating the above-mentioned crystalline silicon / perovskite tandem solar cell, comprising the following steps:

[0030] A stacked battery structure is provided, comprising a crystalline silicon bottom cell and a perovskite top cell thereon. A buffer layer is prepared on the surface of the perovskite top cell in the stacked battery structure. Several stacked battery structures prepared above are stacked with their faces facing the same direction and a deposition process is performed to form a first edge passivation layer on the four sides of the stacked battery structures. After deposition, the stacked battery structures are removed and separated. A transparent electrode layer is prepared on the surface of the buffer layer. Several stacked battery structures are stacked again with their faces facing the same direction and a deposition process is performed to form a second edge passivation layer on the four sides of the stacked battery structures. After deposition, the stacked battery structures are removed and separated. Metal grid lines are prepared on the top and bottom surfaces of the stacked battery structure.

[0031] In one embodiment, the buffer layer fabrication step is removed, and the first edge passivation layer is deposited on the four edges of the crystalline silicon bottom cell and the perovskite top cell thereon.

[0032] In one embodiment, the first edge passivation layer and the second edge passivation layer may be composed of thin films selected from aluminum oxide, silicon oxide, aluminum nitride, tin oxide, etc., with a thickness of 5-100 nm; and may be prepared by deposition methods such as atomic layer deposition, evaporation, chemical vapor deposition, magnetron sputtering, etc.

[0033] Optionally, when using atomic layer deposition (ALD) for deposition, the deposition temperature is controlled at 150~250℃; the deposition pressure is 0.5~3 torr; the flow rate of the passivation gas is 5000~20000 sccm, the flow rate of the water vapor is 5000~20000 sccm, and the flow rate of the nitrogen gas is 20000~40000 sccm, forming a first edge passivation layer / second edge passivation layer on the four sides of the stacked battery structure.

[0034] Optionally, when using magnetron sputtering for deposition, a passivation material target is set, the chamber pressure is controlled at 0.3~0.6pa, the deposition power is 1000~2500W, and working gases such as Ar and O2 are introduced, with the gas flow rate controlled at 500~1500sccm, to form a first edge passivation layer / second edge passivation layer on the four sides of the stacked battery structure.

[0035] In this embodiment, after the first and second edge passivation layers are deposited, an annealing process is performed. The stacked battery structure with the first and second edge passivation layers deposited is placed in an annealing equipment for annealing. The temperature is set to 80-200℃ and the annealing time is 10 min to 30 min. After annealing, subsequent preparation steps are performed.

[0036] In one embodiment, the buffer layer can be prepared by methods such as sputtering or atomic layer deposition, and has a thickness of 5~30nm.

[0037] Optionally, the buffer layer is prepared by sputtering, using a metal / metal oxide target, introducing an Ar / O2 mixed gas with an O2 partial pressure of 0.5-3%, controlling the gas flow rate at 400-1500 sccm, controlling the sputtering power at 1000-2500 W, and the vacuum degree at 0.3-0.8 Pa, thereby forming a buffer layer on the stacked battery structure.

[0038] Optionally, the buffer layer is prepared by atomic layer deposition. When depositing using atomic layer deposition, the deposition temperature is controlled at 80~200℃; the deposition pressure is controlled at 0.1~1.5 torr; the flow rate of metal / metal oxide gas is controlled at 500~1500 sccm, the flow rate of water vapor is controlled at 500~1500 sccm, and the flow rate of nitrogen is controlled at 1000~3000 sccm, thus forming a buffer layer on the stacked battery structure.

[0039] In one embodiment, the transparent electrode layer can be prepared using at least one process such as magnetron sputtering or atomic layer deposition, and has a thickness of 20~140nm.

[0040] Optionally, the transparent electrode layer is prepared by magnetron sputtering, with a metal oxide target, an Ar / O2 mixed gas introduced, an O2 partial pressure of 0.5-5%, a gas flow rate of 400-1500 sccm, a sputtering power of 1000-2500 W, and a vacuum degree of 0.3-0.8 Pa, to form a transparent electrode layer on the stacked battery structure.

[0041] In one embodiment, the metal grid lines can be prepared by at least one process such as screen printing, electroplating, inkjet printing, or nanoimprinting. The metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40µm and a width of 20~1500µm, while the fine grid lines have a thickness of 5~30µm and a width of 10~100µm.

[0042] Preferably, the metal grid lines are prepared using a screen printing process. Specifically, the stacked battery structure to be printed is placed on a printing base, a screen is placed on it, and a squeegee is used to apply printing paste to cover the screen. The screen is then removed, and the metal grid lines are obtained on the stacked battery structure. The metal grid lines are disposed on the surface of the transparent electrode layer and the bottom surface of the crystalline silicon bottom battery.

[0043] In one embodiment, the perovskite top cell includes a hole transport layer, a perovskite layer, and an electron transport layer sequentially fabricated from a crystalline silicon bottom cell; optionally, a perovskite passivation layer is further disposed between the perovskite layer and the electron transport layer.

[0044] Furthermore, the preparation method also includes a third edge passivation layer, which is prepared after the perovskite layer or perovskite passivation layer is prepared, and the preparation process is the same as that of the first and second edge passivation layers.

[0045] This application provides a crystalline silicon / perovskite tandem solar cell and its fabrication method. Applied to perovskite / crystalline silicon tandem solar cells, the method involves fabricating a first and second edge passivation layer after the buffer layer and transparent electrode layer are prepared. This improves the protection effect on the edge cut surfaces of the tandem cell, reducing the risk of erosion, damage, or impurity penetration of the thin film in the crystalline silicon / perovskite tandem cell. The resulting edge protection structure also improves the uniformity and continuity of the deposited transparent conductive layer and metal grid lines in the edge region, reducing the potential leakage risk of the thin film layer, lowering parallel resistance loss, and improving the device's fill factor and open-circuit voltage. By setting two edge passivation layers for protection, the negative impact of each transparent electrode deposition and metal grid line fabrication process on sensitive edge regions can be reduced, significantly improving device stability and photoelectric conversion efficiency. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of the crystalline silicon / perovskite tandem solar cell described in this invention;

[0047] Figure 2 This is a schematic diagram of the structure of the crystalline silicon / perovskite tandem solar cell described in this invention;

[0048] Figure 3 This is a diagram illustrating the fabrication steps of the crystalline silicon / perovskite tandem solar cell described in this invention.

[0049] Figure 4 This is a flowchart illustrating the fabrication process of the crystalline silicon / perovskite tandem solar cell described in this invention.

[0050] Figure 5 This is a schematic diagram of the crystalline silicon / perovskite tandem solar cell structure using the PERC silicon substrate in this invention;

[0051] Figure 6 This is a schematic diagram of the crystalline silicon / perovskite tandem solar cell structure using the TOPcon silicon substrate in this invention;

[0052] Figure 7 This is a schematic diagram of the crystalline silicon / perovskite tandem solar cell structure using the HJT silicon substrate in this invention;

[0053] Figure 8 This is a schematic diagram of the crystalline silicon / perovskite tandem solar cell structure using three edge passivation layers in this invention.

[0054] The labels in the diagram are named as follows:

[0055] 10. Crystalline silicon bottom cell; 20. Perovskite top cell; 30. Tunneling layer; P1. First edge passivation layer; P2. Second edge passivation layer; P3. Third edge passivation layer; 11 / 23. Metal grid lines; 21. Buffer layer; 22. Transparent electrode layer;

[0056] 101. Passivation film; 102. Aluminum back surface field; 103. P-type silicon wafer; 104. N+ emitter;

[0057] 111. P+ emitter passivation film; 112. P+ emitter; 113. N-type silicon substrate; 114. Ultrathin tunneling oxide layer; 115. Phosphorus-doped polycrystalline silicon layer;

[0058] 121. First transparent electrode; 122. P-type substrate doped layer; 123. Substrate passivation layer; 124. Silicon substrate; 125. Substrate surface passivation layer; 126. N-type substrate doped layer;

[0059] 201, Hole transport layer; 202, Perovskite layer; 2021, Perovskite passivation layer; 203, Electron transport layer. Detailed Implementation

[0060] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0061] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0062] Please see Figures 1-4This application provides a crystalline silicon / perovskite tandem solar cell, comprising a crystalline silicon bottom cell 10, a perovskite top cell 20, a buffer layer 21, and a transparent electrode layer 22 stacked sequentially from bottom to top. A first edge passivation layer P1 and a second edge passivation layer P2 are sequentially disposed on the four sides of the crystalline silicon bottom cell 10, the perovskite top cell 20, and the buffer layer 21. The second edge passivation layer P2 also covers the four sides of the transparent electrode layer 22. Metal grid lines 23 (11) are also fabricated on the top and bottom surfaces of the tandem solar cell.

[0063] This application primarily utilizes a crystalline silicon / perovskite thin-film tandem solar cell structure. In both the fabrication and fabrication of this structure, the perovskite thin film layer is a sensitive material, highly susceptible to the physical / chemical effects of water vapor, oxygen, and solvents. This is especially true at the edges of the perovskite thin-film solar cell; after laser cutting, the rough cut surface is easily eroded and penetrated by impurities such as water vapor and oxygen, thus reducing the film's stability and performance. Furthermore, if the edges of the perovskite thin film are not protected during device fabrication, subsequent processes, particularly transparent electrode deposition and metallization, can easily lead to discontinuous, lateral conductive paths formed at the rough edges of the film, causing leakage current issues. The deposition process can also easily erode and damage the underlying cell edge layer, further reducing the overall performance and long-term reliability of the device.

[0064] This embodiment employs a first edge passivation layer P1 and a second edge passivation layer P2 for passivation protection, which can improve the protection effect of the edge cut surface of the tandem cell and reduce the risk of the thin film in the crystalline silicon / perovskite tandem cell being easily eroded, damaged, or penetrated by impurities. The resulting edge protection structure can also improve the uniformity and continuity of the deposited transparent conductive layer and metal grid lines in the edge region, reduce the potential leakage risk of the thin film layer, reduce the parallel resistance loss, and improve the device's fill factor and open-circuit voltage. By setting two edge passivation layers for protection, the negative impact of each transparent electrode deposition and metal grid line fabrication process on the sensitive edge region can be reduced, significantly improving device stability and photoelectric conversion efficiency.

[0065] Furthermore, the buffer layer 21 can be removed from the crystalline silicon / perovskite tandem solar cell, and the first edge passivation layer P1 covers the four sides of the crystalline silicon bottom cell 10 and the perovskite top cell 20.

[0066] Furthermore, the first edge passivation layer P1 and the second edge passivation layer P2 can be composed of thin films such as aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100 nm.

[0067] In one embodiment, the buffer layer 21 may be composed of oxide materials such as SnO2, Yb2O3, TiO2, and Al2O3, with a thickness of 5~30nm.

[0068] In one embodiment, the transparent electrode layer 22 may be composed of one of the transparent materials such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 20~140nm.

[0069] In one embodiment, the metal grid line 23 (11) may be composed of materials such as Ag, Cu, Al, metal alloy, multilayer metal composite grid line, silver-clad metal layer, and silver-clad metal oxide grid line. The metal grid line includes a main grid line and a fine grid line. The main grid line has a thickness of 5~40um and a width of 20~1500um, and the fine grid line has a thickness of 5~30um and a width of 10~100um.

[0070] In one embodiment, the perovskite top cell 20 includes a hole transport layer 201, a perovskite layer 202, and an electron transport layer 203 disposed on a crystalline silicon bottom cell.

[0071] The hole transport layer 201 is selected from one or more of poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), poly-3-hexylthiophene (P3HT), nickel oxide (NiOx), molybdenum trioxide (MoO3), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN).

[0072] In this embodiment, the perovskite layer 202 can be composed of an ABX3 structure, wherein,

[0073] The A site is an organic cation, including CH3NH3. + (MA + ), NH2CH=NH2 + (FA + CH3CH2NH3 + or Cs + One or more of them;

[0074] The B site is a metal cation, including Pb. 2+ Sn 2+ One or more of them;

[0075] The X-position is a halide anion, including F. - Cl - ,Br - I - One or more of them.

[0076] In this embodiment, the electron transport layer 203 is composed of zinc oxide (ZnO), tin dioxide (SnO2), titanium dioxide (TiO2), and [6,6]-phenyl C. 61 Methyl butyrate (PC) 61 BM), C60 (C 60 One or more of ), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP).

[0077] Please see Figure 8 In another embodiment, the perovskite top solar cell 20 further includes a perovskite passivation layer 2021 disposed between the perovskite layer 202 and the electron transport layer 203. The perovskite passivation layer 2021 is composed of at least one of two-dimensional perovskite, phenylethylamine iodide (PEAI), polymethyl methacrylate (PMMA), ammonium halide (NH4X), cesium halide (CsX), and lead halide (PbX2), and has a thickness of 5-80 nm. The perovskite passivation layer can passivate iodine and bromide ion defects on the surface of the perovskite layer, reduce surface carrier recombination, and improve photoelectric conversion efficiency.

[0078] Furthermore, the crystalline silicon / perovskite tandem solar cell also includes a third edge passivation layer P3, which is disposed on the side of the first edge passivation layer P1 away from the second edge passivation layer P2. The third edge passivation layer P3 covers the four edges of the crystalline silicon base cell 10, the hole transport layer 201, and the perovskite layer 202; or, the third edge passivation layer P3 covers the four edges of the crystalline silicon base cell 10, the hole transport layer 201, the perovskite layer 202, and the perovskite passivation layer 2021. The third edge passivation layer P3 can be composed of thin films such as alumina, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100 nm. The inclusion of the third edge passivation layer P3 is primarily due to the easy permeation and decomposition of perovskite thin films. Forming an edge protection structure at its edge reduces water and oxygen permeation during the fabrication of the electron transport layer and inhibits interfacial migration of ions.

[0079] In one embodiment, a tunneling layer 30 is further provided between the crystalline silicon bottom cell 10 and the perovskite top cell 20. The tunneling layer 30 is composed of oxide materials such as ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 1~80nm. The tunneling layer 30 enables efficient recombination and tunneling transport of charge carriers in the series cell, while minimizing optical and electrical losses.

[0080] In one embodiment, the crystalline silicon base cell 10 may be selected from one of the crystalline silicon cell structures such as PERC cell, Topcon cell, or HJT cell.

[0081] For further details, please refer to Figure 5 The PERC cell, from bottom to top, includes a passivation film 101, an aluminum back surface field 102, a P-type silicon wafer 103, and an N+ emitter 104.

[0082] For further details, please refer to Figure 6 The topcon battery, from bottom to top, includes a p+ emitter passivation film 111, a p+ emitter 112, an N-type silicon substrate 113, an ultrathin tunneling oxide layer 114, and a phosphorus-doped polycrystalline silicon layer 115.

[0083] For further details, please refer to Figure 7 The HJT battery, from bottom to top, includes a first transparent electrode layer 121, a P-type substrate doped layer 122, a substrate passivation layer 123, a silicon substrate 124, a substrate surface passivation layer 125, and an N-type substrate doped layer 126.

[0084] The different crystalline silicon base cells 10 mentioned above are all prepared using conventional techniques or recycled from existing discarded crystalline silicon cells.

[0085] This application also provides a method for fabricating the above-mentioned crystalline silicon / perovskite tandem solar cell, comprising the following steps:

[0086] A stacked battery structure is provided, the stacked battery structure including a crystalline silicon bottom battery 10 and a perovskite top battery 20 thereon, a buffer layer 21 is prepared on the surface of the perovskite top battery 20 on the stacked battery structure, several stacked battery structures prepared above are stacked with their faces facing the same direction and placed in a carrier and sent to a deposition equipment, a first edge passivation layer P1 is formed on the four sides of the several stacked battery structures, after deposition is completed, the stacked battery structures are removed and separated, a transparent electrode layer 22 is prepared on the surface of the buffer layer 21, several stacked battery structures prepared above are stacked with their faces facing the same direction and placed in a carrier and sent to a deposition equipment, a second edge passivation layer P2 is formed on the four sides of the several stacked battery structures, after deposition is completed, the stacked battery structures are removed and separated, and metal grid lines 23 (11) are prepared on the top and bottom surfaces of the stacked battery structure.

[0087] The stacked battery structure can be prepared using conventional processes. By providing a crystalline silicon bottom cell 10, various film layers of the perovskite top cell 20 are sequentially prepared on it, which will not be elaborated here.

[0088] In one embodiment, the step of removing the buffer layer 21, i.e., the first edge passivation layer P1 is prepared on the four edges of the crystalline silicon bottom cell 10 and the perovskite top cell 20, mainly to protect the perovskite thin film layer, reduce the risk of water and oxygen erosion, and improve the uniformity and continuity of the deposited transparent conductive layer and metal grid lines in the edge region, thereby reducing the potential leakage risk of the thin film layer.

[0089] In one embodiment, the first edge passivation layer P1 and the second edge passivation layer P2 can be composed of thin films selected from aluminum oxide, silicon oxide, aluminum nitride, tin oxide, etc., with a thickness of 5-100 nm; and can be prepared by deposition methods such as atomic layer deposition, evaporation, chemical vapor deposition, magnetron sputtering, etc.

[0090] Optionally, when using atomic layer deposition (ALD) for deposition, the deposition temperature is controlled at 150~250℃; the deposition pressure is 0.5~3 torr; the flow rate of the passivation gas is 5000~20000 sccm, the flow rate of the water vapor is 5000~20000 sccm, and the flow rate of the nitrogen gas is 20000~40000 sccm, forming a first edge passivation layer P1 and a second edge passivation layer P2 on the four sides of the stacked battery structure.

[0091] Optionally, when using magnetron sputtering for deposition, a passivation material target is set, the chamber pressure is controlled at 0.3~0.6pa, the deposition power is 1000~2500W, and working gases such as Ar and O2 are introduced, with the gas flow rate controlled at 500~1500sccm, to form a first edge passivation layer P1 and a second edge passivation layer P2 on the four sides of the stacked battery structure.

[0092] In this embodiment, after the first and second edge passivation layers P1 (P2) are deposited, an annealing process is performed. The stacked battery structure with the first edge passivation layer P1 and the second edge passivation layer P2 deposited is placed in an annealing equipment for annealing. The temperature is set to 80-200℃ and the annealing time is 10min-30min. After annealing, subsequent preparation steps are performed.

[0093] In one embodiment, the buffer layer 21 can be prepared by methods such as sputtering or atomic layer deposition, and has a thickness of 5~30nm.

[0094] Optionally, the buffer layer 21 is prepared by sputtering, using a metal / metal oxide target, introducing an Ar / O2 mixed gas, controlling the O2 partial pressure to be 0.5~3%, the gas flow rate to be 400~1500 sccm, the sputtering power to be 1000~2500W, and the vacuum degree to be 0.3~0.8 Pa, thereby forming the buffer layer 21 on the stacked battery structure.

[0095] Optionally, the buffer layer 21 is prepared by atomic layer deposition. When depositing using atomic layer deposition, the deposition temperature is controlled at 80~200°C; the deposition pressure is controlled at 0.1~1.5 torr; the flow rate of metal / metal oxide gas is controlled at 500~1500 sccm, the flow rate of water vapor is controlled at 500~1500 sccm, and the flow rate of nitrogen is controlled at 1000~3000 sccm, thus forming a buffer layer on the stacked battery structure.

[0096] In one embodiment, the transparent electrode layer 22 can be prepared by at least one process such as magnetron sputtering or atomic layer deposition, and has a thickness of 20~140nm.

[0097] Optionally, the transparent electrode layer 22 is prepared by magnetron sputtering, with a metal oxide target and an Ar / O2 mixed gas introduced. The O2 partial pressure is 0.5~5%, the gas flow rate is controlled at 400~1500 sccm, the sputtering power is controlled at 1000~2500W, and the vacuum degree is 0.3~0.8Pa, thus forming the transparent electrode layer 22 on the stacked battery structure.

[0098] In one embodiment, the metal grid line 23 (11) can be prepared by at least one process such as screen printing, electroplating, inkjet printing, and nanoimprinting. The metal grid line includes a main grid line and a fine grid line. The main grid line has a thickness of 5~40um and a width of 20~1500um, and the fine grid line has a thickness of 5~30um and a width of 10~100um.

[0099] Preferably, the metal grid line 23 (11) is prepared by screen printing process. Specifically, the stacked battery structure to be printed is placed on the printing base, the screen is placed on it, the printing paste is scraped and coated to cover the screen with a squeegee, the screen is removed, and the metal grid line 23 (11) is obtained on the stacked battery structure.

[0100] The following specific embodiments and comparative examples clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0101] Example 1

[0102] Step 1: Prepare several fabricated stacked cell structures, the stacked cell including a crystalline silicon bottom cell 10 and a perovskite top cell 20 thereon, and prepare a buffer layer 21 on the surface of the perovskite top cell 20 of the stacked cell structure.

[0103] In this embodiment, a stacked battery structure with an area of ​​M6 can be selected according to production needs. The battery structure of the corresponding size is obtained by laser cutting. The crystalline silicon bottom battery 10 is a TOPcon battery structure, including SiN. x The perovskite top cell 20 comprises NIO₂ sequentially fabricated on a crystalline silicon bottom cell 10. x / CH3NH3PbI3 / C 60 composition.

[0104] In this embodiment, the buffer layer 21 is prepared by sputtering. A SnO2 target is set, an Ar / O2 mixed gas is introduced, the gas flow rate is controlled at 1000 sccm, the sputtering power is controlled at 2000 W, and the vacuum degree is 0.5 Pa, thereby forming the buffer layer 21 on the stacked battery structure.

[0105] Step 2: Stack several stacked battery structures prepared in the previous step with their faces facing the same direction and place them in a carrier. Send the carrier to a deposition equipment to form a first edge passivation layer P1 on the four sides of the stacked battery structures. After deposition, remove and separate the stacked battery structures.

[0106] In this embodiment, the first edge passivation layer P1 is deposited using atomic layer deposition, with the deposition temperature controlled at 200°C, the deposition pressure at 1 torr, the flow rate of trimethylaluminum (TMA) controlled at 15000 sccm, the flow rate of water vapor controlled at 15000 sccm, and the flow rate of nitrogen controlled at 30000 sccm, forming the first edge passivation layer P1 on the four sides of the stacked battery structure.

[0107] After the first edge passivation layer P1 is deposited, an annealing process is performed. The stacked battery structure with the first edge passivation layer P1 deposited is placed in an annealing equipment for annealing. The temperature is set to 150°C and the annealing time is 15 minutes. After annealing, subsequent preparation steps are performed.

[0108] Step 3: Prepare a transparent electrode layer 22 on the surface of the buffer layer 21.

[0109] In this embodiment, the transparent electrode layer 22 is prepared by magnetron sputtering. An ITO target is set, an Ar / O2 mixed gas is introduced, the O2 partial pressure is 1.5%, the gas flow rate is controlled at 1000 sccm, the sputtering power is controlled at 1500 W, and the vacuum degree is 0.5 Pa, thus forming the transparent electrode layer 22 on the stacked battery structure.

[0110] Step 4: Stack the several stacked cells obtained in the previous step with their faces facing the same direction and place them in a carrier. Send them to the deposition equipment to form a second edge passivation layer P2 on the four sides of the stacked cell structure. After deposition is completed, remove and separate the cells.

[0111] In this embodiment, the second edge passivation layer P2 is deposited using atomic layer deposition, with the deposition temperature controlled at 200°C, the deposition pressure at 1 torr, and the flow rates of trimethylaluminum (TMA) controlled at 15000 sccm, water vapor at 15000 sccm, and nitrogen at 30000 sccm, forming the second edge passivation layer P2 on the four sides of the stacked battery structure.

[0112] After the second edge passivation layer P2 is deposited, an annealing process is performed. The stacked battery structure with the second edge passivation layer P2 deposited is placed in an annealing equipment for annealing. The temperature is set to 150°C and the annealing time is 20 minutes. After annealing, subsequent preparation steps are performed.

[0113] Step 5: Prepare metal grid lines 23 (11) on the top and bottom surfaces of the stacked battery structure.

[0114] In this embodiment, the metal grid line 23 (11) is prepared by screen printing process. Specifically, the stacked battery structure to be printed is placed on the printing base, the screen is placed on it, the printing paste is scraped and coated to cover the screen with a squeegee, the screen is removed, and the metal grid line 23 (11) is obtained on the stacked battery structure.

[0115] Example 2

[0116] This embodiment provides a crystalline silicon / perovskite tandem solar cell prepared using this process. After preparing a buffer layer 21 on the tandem cell structure having a crystalline silicon bottom cell 10 and a perovskite top cell 20, a first edge passivation layer P1, a transparent electrode layer 22, and metal grid lines 23 (11) are sequentially deposited on the bottom and top surfaces of the tandem cell structure. The difference from Embodiment 1 is that this embodiment does not perform a second edge passivation on the tandem cell structure.

[0117] Example 3

[0118] This embodiment provides a crystalline silicon / perovskite tandem solar cell prepared using this process. After preparing a buffer layer 21 on the tandem cell structure having a crystalline silicon bottom cell 10 and a perovskite top cell 20, a transparent electrode layer 22, a second edge passivation layer P2, and metal grid lines 23 (11) are deposited on the bottom and top surfaces of the tandem cell structure in sequence. The difference from Embodiment 1 is that this embodiment does not perform a first edge passivation on the tandem cell structure.

[0119] Example 4

[0120] This embodiment provides a crystalline silicon / perovskite tandem solar cell prepared using this process. After preparing a buffer layer 21 on the tandem structure having a crystalline silicon bottom cell 10 and a perovskite top cell 20, a transparent electrode layer 22 is sequentially prepared and metal grid lines 23 (11) are deposited on the bottom and top surfaces of the tandem cell structure. The difference from Embodiment 1 is that this embodiment does not perform first and second edge passivation on the tandem cell structure.

[0121] The tandem solar cells obtained in Examples 1-4 were tested under the following conditions: a standard solar intensity calibration was performed using a solar simulator, and the solar cells with an area of ​​1.0 cm² were tested. 2 The device in this embodiment underwent a long-term IV test, with the starting voltage set to 1.95V, the cutoff voltage to 0V, and the range to 100mA. The results were rounded to one decimal place. The test results are shown in Table 1 below.

[0122] Table 1. Performance test results of the solar cells obtained in Examples 1-4

[0123] Performance indicators EFF (%) Voc(V) <![CDATA[ Isc(mA / cm 2 )]]> FF (%) Example 1 26.15 1.865 18.363 76.36 Example 2 25.83 1.827 18.331 77.13 Example 3 25.06 1.815 18.325 75.35 Example 4 23.82 1.796 18.257 72.65

[0124] In Table 1, EFF refers to the battery conversion efficiency, Voc is the cell open-circuit voltage, Isc is the cell short-circuit current, and FF refers to the fill factor.

[0125] As can be seen from the table, the perovskite-silicon tandem solar cells with edge passivation exhibit significant advantages. Examples 1-3 all employed a two-layer or one-layer edge passivation fabrication process, effectively protecting the edge film of the perovskite solar cell. This significantly improved the photoelectric conversion efficiency and open-circuit voltage, enhancing device stability and performance. In Example 4, due to the lack of at least one layer of edge passivation protection, the device was excessively affected by moisture, oxygen, and the physical / chemical effects of subsequent processes, resulting in reduced photoelectric conversion efficiency and open-circuit voltage, and poor device performance.

[0126] The stepwise edge passivation design described in this invention has significant advantages in stacked perovskite / crystalline silicon solar cells, mainly in the following aspects: 1. It can improve the protection effect of sensitive layers such as perovskite, and reduce the influence of water vapor, oxygen, solvents and the physical / chemical effects of subsequent processes; 2. It reduces the discontinuous and lateral conductive paths formed at the device edge during transparent electrode deposition and metallization processes, thus reducing the risk of leakage; 3. The two edge passivation layers can effectively passivate the device edge, reduce the recombination loss of charge carriers in the edge region, and improve the open-circuit voltage.

[0127] The above embodiments are merely preferred embodiments of the present invention. It should be noted that, for those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle of the present invention. All technical solutions after making equivalent substitutions to the claims of the present invention fall within the protection scope of the present invention, which is defined by the appended claims and their equivalents.

Claims

1. A crystalline silicon / perovskite tandem solar cell, characterized in that, Includes the following structure: The stacked solar cell consists of a crystalline silicon bottom cell, a perovskite top cell, a buffer layer, and a transparent electrode layer, stacked sequentially from bottom to top. A first edge passivation layer and a second edge passivation layer are sequentially disposed on the four sides of the crystalline silicon bottom cell, the perovskite top cell, and the buffer layer. The second edge passivation layer also covers the four sides of the transparent electrode layer. Metal grid lines are also fabricated on the top and bottom surfaces of the stacked solar cell. The first edge passivation layer and the second edge passivation layer are prepared after the buffer layer and the transparent electrode layer are prepared, respectively.

2. The crystalline silicon / perovskite tandem solar cell according to claim 1, characterized in that, The buffer layer of the crystalline silicon / perovskite tandem solar cell is removed, and the first edge passivation layer covers the four sides of the crystalline silicon bottom cell and the perovskite top cell.

3. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that, The first edge passivation layer and the second edge passivation layer are composed of a thin film selected from one of aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, with a thickness of 5-100 nm.

4. The crystalline silicon / perovskite tandem solar cell according to claim 1, characterized in that, The buffer layer is composed of one of the oxide materials SnO2, Yb2O3, TiO2, and Al2O3, with a thickness of 5~30nm.

5. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that, The transparent electrode layer is composed of one of the following transparent materials: ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 20~140nm.

6. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that, The metal grid line is composed of one of the following materials: Ag, Cu, Al, metal alloy, multilayer metal composite grid line, silver-clad metal layer, and silver-clad metal oxide grid line. The metal grid line includes a main grid line and a fine grid line. The main grid line has a thickness of 5~40um and a width of 20~1500um, and the fine grid line has a thickness of 5~30um and a width of 10~100um.

7. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that, The perovskite top cell includes a hole transport layer, a perovskite layer, and an electron transport layer disposed on a crystalline silicon bottom cell.

8. The crystalline silicon / perovskite tandem solar cell according to claim 7, characterized in that, A perovskite passivation layer is disposed between the perovskite layer and the electron transport layer. The perovskite passivation layer is composed of at least one of two-dimensional perovskite, phenylethylamine iodide (PEAI), polymethyl methacrylate (PMMA), ammonium halide (NH4X), cesium halide (CsX), and lead halide (PbX2), and has a thickness of 5~80 nm.

9. The crystalline silicon / perovskite tandem solar cell according to claim 8, characterized in that, It also includes a third edge passivation layer, which is disposed on the side of the first edge passivation layer away from the second edge passivation layer; the third edge passivation layer covers the four edges of the crystalline silicon bottom cell, the hole transport layer, and the perovskite layer, or the third edge passivation layer covers the four edges of the crystalline silicon bottom cell, the hole transport layer, the perovskite layer, and the perovskite passivation layer; the third edge passivation layer is composed of a thin film selected from aluminum oxide, silicon oxide, aluminum nitride, and tin oxide, and has a thickness of 5-100 nm.

10. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that, The crystalline silicon base cell is selected from one of the crystalline silicon cell structures: PERC cell, Topcon cell, or HJT cell.

11. The crystalline silicon / perovskite tandem solar cell according to any one of claims 1 to 2, characterized in that, A tunneling layer is also provided between the crystalline silicon bottom cell and the perovskite top cell. It is composed of one of the following oxide materials: ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped ZnO), GZO (gallium-doped ZnO), SnO2, ZnO, In2O3, ICO (cerium-doped indium oxide), and IWO (tungsten-doped indium oxide), with a thickness of 1~80nm.

12. A method for fabricating a crystalline silicon / perovskite tandem solar cell, applied to the crystalline silicon / perovskite tandem solar cell according to any one of claims 1-11, characterized in that, Including the following steps: A stacked battery structure is provided, comprising a crystalline silicon bottom cell and a perovskite top cell thereon. A buffer layer is prepared on the surface of the perovskite top cell in the stacked battery structure. Several stacked battery structures prepared above are stacked with their faces facing the same direction and deposited. A first edge passivation layer is formed on the four sides of the stacked battery structures. After deposition, the stacked battery structures are removed and separated. A transparent electrode layer is prepared on the surface of the buffer layer. Several stacked battery structures are stacked again with their faces facing the same direction and deposited. A second edge passivation layer is formed on the four sides of the stacked battery structures. After deposition, the stacked battery structures are removed and separated. Metal grid lines are prepared on the top and bottom surfaces of the stacked battery structure.

13. The method for fabricating a crystalline silicon / perovskite tandem solar cell as described in claim 12, characterized in that, The first edge passivation layer and the second edge passivation layer are composed of a thin film selected from aluminum oxide, silicon oxide, aluminum nitride and tin oxide, with a thickness of 5-100 nm; and are prepared by one of the deposition methods of atomic layer deposition, evaporation, chemical vapor deposition and magnetron sputtering.

14. The method for fabricating a crystalline silicon / perovskite tandem solar cell as described in claim 12, characterized in that, After the first and second edge passivation layers are deposited, an annealing process is performed. The stacked battery structure with the first and second edge passivation layers deposited is placed in an annealing equipment for annealing. The temperature is set to 80-200℃ and the annealing time is 10-30 minutes. After annealing, subsequent preparation steps are performed.

15. The method for fabricating a crystalline silicon / perovskite tandem solar cell as described in claim 12, characterized in that, The buffer layer is prepared by at least one method, such as sputtering or atomic layer deposition, and has a thickness of 5-30 nm.

16. The method for fabricating a crystalline silicon / perovskite tandem solar cell as described in claim 12, characterized in that, The transparent electrode layer is prepared using at least one process, such as magnetron sputtering or atomic layer deposition, and has a thickness of 20-140 nm.

17. The method for fabricating a crystalline silicon / perovskite tandem solar cell as described in claim 12, characterized in that, The metal grid lines are prepared using at least one process, including screen printing, electroplating, inkjet printing, and nanoimprinting. The metal grid lines include main grid lines and fine grid lines. The main grid lines have a thickness of 5~40µm and a width of 20~1500µm, while the fine grid lines have a thickness of 5~30µm and a width of 10~100µm.

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