Multifunctional integrated motor control system for hybrid power new energy automobile

Abstract

The invention discloses a multifunctional integrated motor control system for a hybrid new energy vehicle, which comprises a microprocessor chip, and an oil pump motor power circuit, a gear shifting motor power circuit, a power generation motor power circuit, a driving motor power circuit, an Elock circuit and a power supply circuit which are electrically connected with the microprocessor chip, the microprocessor chip controls the oil pump motor through the oil pump motor power circuit, and the microprocessor chip controls the gear shifting motor through the gear shifting motor power circuit. According to the multifunctional integrated motor control system for the hybrid power new energy automobile, a BGA292 packaging MCU main arithmetic unit chip is used, four motor control functions and a power coupling module control function are achieved, and a high-reliability hardware foundation with the cost performance advantage is provided for an electric drive controller of the hybrid power system new energy automobile.

Description

Technical Field

[0001] The present invention belongs to the technical field of motor controllers, and in particular relates to a multifunctional integrated motor control system for hybrid new energy vehicles. Background Art

[0002] All-in-one electric drive inverters for new energy vehicles can significantly reduce costs for connectors, wiring harnesses, and other applications throughout the vehicle, significantly improving product competitiveness and are increasingly being adopted by vehicle architecture designers. In typical all-in-one electric drive inverters, main arithmetic unit chips with varying pin counts are selected based on the number of integrated functions. For dual electronic control systems, pin-rich packages such as BGA516 are often used. However, larger chip size increases product price and increases the risk of BGA solder cracking during vibration.

[0003] Currently, the design of integrated electric drive controller architecture for new energy vehicles generally uses arithmetic chips with more pin resources to achieve multi-function control. The current solution has the following obvious drawbacks: 1) The main ALU chip is relatively expensive and requires multiple peripheral circuits for multi-functional integrated applications. The overall system cost is too high and lacks a competitive advantage. The larger the ALU chip package, the higher the risk of cracking at the corner BGA solder joints in hybrid vehicle applications.

[0004] 2) The functional safety goals of traditional generator motors are not clearly established, resulting in the same functional safety requirements as drive motors, which takes up more resources; miniaturized main arithmetic unit chips cannot be used.

[0005] 3) The motor of traditional new energy vehicles is directly connected to the wheels. Towing is not allowed when the vehicle breaks down, otherwise it will cause the motor to overheat and burn during the towing process.

[0006] 4) Traditional multi-function integrated controllers do not include BLDC control functions. Independent oil pump control and independent shift motor control will increase the application costs of vehicle connectors, wiring harnesses, and fixings.

[0007] 5) The multi-function integrated controller in traditional hybrid vehicles does not include a high-voltage backup power supply. In the application of the multi-function integrated controller, once the power line becomes unstable, it will affect many functional abnormalities.

[0008] Therefore, further improvements are made to the above problems. Summary of the Invention

[0009] The main purpose of this invention is to provide a multifunctional integrated motor control system for hybrid new energy vehicles. It uses a BGA292 packaged MCU main arithmetic unit chip to realize four motor control functions and power coupling module control functions, providing a high-reliability hardware foundation with cost-effective advantages for the electric drive controller of hybrid system new energy vehicles.

[0010] Another objective of this invention is to provide a multifunctional integrated motor control system for hybrid new energy vehicles. This system utilizes a main arithmetic unit (APU) chip in a BGA292 package as its foundation. The system implements ASIL-C drive motor control and ASIL-B generator, oil pump, and shift motor control. The system utilizes an SBC chip to power the system control circuits and perform functional safety verification on the MCU.

[0011] Another object of the present invention is to provide a multifunctional integrated motor control system for hybrid new energy vehicles, which is designed with a power coupling module control function. When the entire vehicle has an abnormality and needs to be towed, the motor and wheel power connection is disconnected to avoid other problems.

[0012] Another object of the present invention is to provide a multifunctional integrated motor control system for hybrid new energy vehicles, in which the SBC and power circuit adopt a 12V battery power supply and a parallel high-voltage power supply output power supply to maximize system reliability.

[0013] To achieve the above objectives, the present invention provides a multifunctional integrated motor control system for a hybrid new energy vehicle, comprising a microprocessor chip and an oil pump motor power circuit, a shift motor power circuit, a generator motor power circuit, a drive motor power circuit, an Elock circuit, and a power supply circuit, each electrically connected to the microprocessor chip. The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, the microprocessor chip controls the shift motor through the shift motor power circuit, the microprocessor chip controls the generator motor through the generator motor power circuit, the microprocessor chip controls the drive motor through the drive motor power circuit, and the microprocessor chip controls the power coupling module through the Elock circuit.

[0014] As a further preferred technical solution of the above technical solution, for the generator motor and the drive motor, the microprocessor chip collects the resolver feedback signal through the resolver circuit and controls the generator motor and the drive motor respectively in combination with the output torque target. The control of the generator motor and the drive motor by the microprocessor chip is specifically implemented as follows: The microprocessor chip sends a PWM control signal to the driver chip of the corresponding power circuit according to the expected torque and speed. The driver chip drives the IGBT after power amplification, so that the corresponding motor rotates according to the expected torque and speed. The microprocessor chip simultaneously sends out a resolver excitation signal, which is a square wave. After filtering and amplification by the resolver excitation circuit, it is output to the primary side of the resolver inside the motor; the resolver accessory feedback sine and cosine signals are filtered by the resolver sampling point and input into the microprocessor chip. Through soft decoding, it is identified whether the current speed of the motor verifies the expected instruction. If it does not meet the instruction, it enters the PI closed-loop regulation state and outputs the PWM duty cycle signal under dynamic conditions; Furthermore, the microprocessor chip includes multiple CPUs, so that different motor control codes are placed in different CPUs for operation; the hardware interface distinguishes the control signals of different motors through pin design, thereby realizing the separate control functions of different motors.

[0015] As a further preferred technical solution of the above technical solution, for the drive motor, the ASIL-C functional safety target of the drive motor is designed, and the microprocessor chip outputs the PWM control signal to the cache circuit, that is, the level conversion chip circuit. The cache circuit is used to effectively increase the driving capability and perform square wave shaping on the model to ensure the quality of the PWM signal output to the back end; at the same time, if the microprocessor chip detects a signal including overcurrent, overvoltage or other faults, the cache chip of the cache circuit is directly turned off to avoid the issuance of an erroneous signal; Design the recovery drive function of the drive motor. The microprocessor chip will use the PWM signal recovered through GPIO, parse the frequency and duty cycle values, and compare them with the frequency and duty cycle values ​​issued by the expected instruction. If they are consistent, it proves that the actual PWM signal issued is correct and the correctness of the signal is ensured. If the frequency and duty cycle values ​​of the recovered PWM signal are inconsistent with the values ​​in the expected instruction, it proves that there is a problem in the signal transmission process and it is necessary to enter the fault state and shut down, waiting for the problem to be investigated.

[0016] As a further preferred technical solution of the above technical solution, during the operation of the drive motor and the generator motor, if a fault including overcurrent or overvoltage occurs in the system, a first-level shutdown logic, a second-level shutdown logic and a third-level shutdown logic are set, wherein: The first-level shutdown logic is that the output instructions of the microprocessor chip are output according to a preset fixed level; the second-level shutdown logic is that the output instructions of the microprocessor chip directly shut down the cache chip through the logic circuit. The second-level shutdown logic requires the use of external resistors to enable the system to enter the predetermined lower bridge arm ASC functional safety state; The first level of shutdown logic is to assume that all circuit functions are normal, and the microprocessor chip will respond to normal faults. The second level of shutdown logic is to assume that if some circuit functions of the system fail and the signal cannot be effectively transmitted from the microprocessor chip to the driver chip, a separate fault channel is established, so that the microprocessor chip can directly shut down the driver chip. The third level of shutdown logic is that when the microprocessor chip does not perform WDG signal interaction with the SBC chip of the power circuit, the SBC chip believes that there is a problem with the microprocessor chip and the signal sent is unreliable, and thus directly shuts down the signal channel.

[0017] As a further preferred technical solution of the above technical solution, for the oil pump motor and the shift motor, the microprocessor chip directly communicates with the driver chip of the corresponding power circuit through SPI to configure the register to implement status and fault corresponding actions.

[0018] As a further preferred technical solution of the above technical solution, the microprocessor chip communicates with the control chip in the corresponding power circuit of the corresponding motor through SPI, thereby realizing the register configuration of the driver chip, which is specifically implemented as follows: The first step is to set the driver chip to a configurable state through the SPI communication bit, and then use SPI communication to initialize the driver chip register to achieve chip register initialization and clearing action; The second step is to configure the analog self-test and digital self-test BIST registers to enable the driver chip to perform self-status checks; The third step is to configure the driver chip output frequency and minimum dead time register, and set the frequency value and dead time limit parameters of the chip output signal; The fourth step is to configure the driver chip fault register to set the chip's response time to overcurrent and overvoltage faults. Step 5: Configure the driver chip register and set the interaction cycle value with the driver chip WDG; Step 6: Configure the driver chip fault register to set the chip's response time to over-temperature faults. Step 7: Configure the driver chip register to set whether there are any faults that need to be shielded; Step 8: Use the SPI communication bit to exit the driver chip from the configurable state.

[0019] As a further preferred technical solution of the above technical solution, the control function of the motor is also realized by a cache circuit, an emergency shutdown circuit, and a resolver circuit, wherein: The cache circuit is designed at the output end. Its digital circuit performs square wave shaping on the MCU output waveform. The cache chip's own function ensures that the output waveform is more accurately identified. The emergency shutdown circuit operates in the system's overcurrent or overvoltage fault identification state. After receiving the overvoltage or overcurrent fault, the microprocessor chip must perform at least one operation cycle before issuing a fault-related instruction. When a fault occurs, the emergency shutdown circuit uses the GTM function of the microprocessor chip to issue a fault-related instruction without going through the CPU operation cycle. Then, the signal sent at the end of the CPU operation cycle is used to check and modify the emergency fault instruction signal, achieving the goal of issuing accurate instructions quickly after signal verification. The resolver circuit includes an excitation circuit and a sampling circuit. The excitation circuit shapes the square wave emitted by the microprocessor chip into a sine wave and sends it to the circuit resolver through a power amplifier. The resolver secondary side feedback signal is input into the sampling circuit. After RC filtering, the microprocessor chip parses the motor speed and position signals through the soft decoding code to realize the normal control function of the motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a functional block diagram of the MCU chip of the present invention.

[0021] Figure 2 This is a topology diagram of the multifunctional integrated motor controller system of the present invention.

[0022] Figure 3 This is a topology diagram of a power motor drive of a multifunctional integrated motor controller of the present invention.

[0023] Figure 4 This is the functional topology diagram of the multifunctional integrated motor controller driving + generating motor of the present invention.

[0024] Figure 5 This is a BLDC drive topology diagram of the multifunctional integrated motor controller of the present invention.

[0025] Figure 6 This is a block diagram of the power coupling function principle of the multifunctional integrated motor controller of the present invention.

[0026] Figure 7 This is a functional block diagram of the power coupling control of the multifunctional integrated motor controller of the present invention. DETAILED DESCRIPTION

[0027] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art will readily appreciate other obvious variations. The basic principles of the present invention defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0028] In the preferred embodiments of the present invention, those skilled in the art should note that the motor and the like involved in the present invention may be regarded as prior art.

[0029] Preferred embodiment.

[0030] like Figure 1-7 As shown, the present invention discloses a multifunctional integrated motor control system for hybrid new energy vehicles, including a microprocessor chip (BGA292) and an oil pump motor power circuit (i.e. Figure 1 BLDC 1), shift motor power circuit (ie Figure 1 BLDC 2) Generator motor power circuit (ie Figure 1 Inverter 1 in), drive motor power circuit (i.e. Figure 1 Inverter 2), Elock circuit and power supply circuit, where: The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, the microprocessor chip controls the shift motor through the shift motor power circuit, the microprocessor chip controls the generator motor through the generator motor power circuit, the microprocessor chip controls the drive motor through the drive motor power circuit, and the microprocessor chip controls the power coupling module through the Elock circuit.

[0031] Specifically, the functional block diagram of the multi-functional integrated motor controller MCU chip is as follows: Figure 1 , for the generator motor and the drive motor, the microprocessor chip is connected to the rotary circuit (such as Figure 1 As shown, the generator motor collects the resolver feedback signal through resolver circuit 1, and the drive motor collects the resolver feedback signal through resolver circuit 2. The resolver feedback signal is combined with the output torque target to control the generator motor and the drive motor respectively. The microprocessor chip specifically implements the control of the generator motor and the drive motor as follows: The microprocessor chip sends a PWM control signal to the driver chip of the corresponding power circuit (i.e., the generator motor power circuit or the drive motor power circuit) according to the expected torque and speed. The driver chip drives the IGBT after power amplification, so that the corresponding motor rotates according to the expected torque and speed; The microprocessor chip simultaneously sends out a resolver excitation signal, which is a square wave. After filtering and amplification by the resolver excitation circuit, it is output to the primary side of the resolver inside the motor; the resolver accessory feedback sine and cosine signals are filtered by the resolver sampling point and input into the microprocessor chip. Through soft decoding, it is identified whether the current speed of the motor verifies the expected instruction. If it does not meet the instruction, it enters the PI closed-loop regulation state and outputs the PWM duty cycle signal under dynamic conditions; Furthermore, the microprocessor chip includes multiple CPUs, so that different motor control codes are placed in different CPUs for operation; the hardware interface distinguishes the control signals of different motors through pin design, thereby realizing the separate control functions of different motors.

[0032] More specifically, for the drive motor, the ASIL-C functional safety goal of the drive motor is designed. The microprocessor chip outputs a PWM control signal to a cache circuit, namely a level conversion chip circuit. The cache circuit is used to effectively increase the drive capability and perform square wave shaping on the model to ensure the quality of the PWM signal output to the back end. At the same time, if the microprocessor chip detects a signal including overcurrent, overvoltage or other fault, it directly shuts down the cache chip of the cache circuit to prevent the issuance of an erroneous signal (SBC, DSP1, and level conversion chip constitute the basic functional control part of the system; the power supply is provided by the KL30 voltage provided by the 12V battery of the power circuit). Design the recovery drive function of the drive motor. (In order to increase the system reliability, the control circuit of the drive motor is designed with a recovery drive function.) The microprocessor chip will use the PWM signal recovered through GPIO, and parse the frequency and duty cycle values, and compare them with the frequency and duty cycle values ​​issued by the expected instruction. If they are consistent, it proves that the actual PWM signal is correctly checked to ensure the correctness of the signal. If the frequency and duty cycle values ​​of the recovered PWM signal are inconsistent with the values ​​in the expected instruction, it proves that there is a problem in the signal transmission process, and it is necessary to enter the fault state and shut down, waiting for the problem to be investigated (the generator motor does not have high real-time requirements for the safety of the entire vehicle, so the ASIL-B design goal is to not recover the PWM signal input from the front end of the driver chip to reduce the demand for main arithmetic unit resources).

[0033] Furthermore, during the operation of the drive motor and the generator motor, if a fault including overcurrent or overvoltage occurs in the system, the first-level shutdown logic, the second-level shutdown logic and the third-level shutdown logic are set, wherein: The first-level shutdown logic is that the output instructions of the microprocessor chip are output according to a preset fixed level. The second-level shutdown logic is that the output instructions of the microprocessor chip directly shut down the cache chip (i.e., the level conversion chip, to achieve a faster and more stable shutdown method) through the logic circuit. The second-level shutdown logic requires the use of external resistors to enable the system to enter the predetermined lower-arm ASC functional safety state. The first level of shutdown logic is to respond to normal faults of the microprocessor chip, assuming that all circuit functions are normal. The second level of shutdown logic is to assume that if some circuit functions of the system fail and the signal cannot be effectively transmitted from the microprocessor chip to the driver chip, a separate fault channel is established, allowing the microprocessor chip to directly shut down the driver chip (this is a double insurance and will work in the event of a fault). The third-level shutdown logic is that when the microprocessor chip does not interact with the SBC chip of the power circuit through the WDG signal, the SBC chip believes that there is a problem with the microprocessor chip and the signal sent is unreliable, so it directly shuts down the signal channel (this only works when the WDG fails).

[0034] If the system encounters other abnormal and serious faults, such as high-voltage interlock problems, resolver function abnormalities, etc., the microprocessor chip can output targeted instructions according to the location of the fault. By emergency shutdown of the ASC circuit, it can directly control the IGBT isolation driver chip of the drive motor or generator motor to put the system into the predetermined functional safety state; the same design of the drive motor and generator motor power circuit sampling reduces system cost, and the topology is as follows: Figure 3 The topology of the drive motor and generator motor power section is as follows: Figure 4 .

[0035] Furthermore, for the oil pump motor and the shift motor, the microprocessor chip directly communicates with the driver chip of the corresponding power circuit via SPI to configure the register to implement the status and corresponding fault actions (after the hybrid system oil pump motor control and shift motor control functions are integrated, the system application cost can be greatly reduced. The oil pump motor control power is relatively small, and a precision sampling resistor is used to collect the output current signal for closed-loop feedback control. The oil pump motor and the shift motor power circuit use the same design to reduce system cost, and the topology is as follows Figure 5 ).

[0036] Preferably, the microprocessor chip communicates with the control chip in the corresponding power circuit of the corresponding motor via SPI, thereby realizing register configuration of the driver chip, which is specifically implemented as follows: The first step is to set the driver chip to a configurable state through the SPI communication bit, and then use SPI communication to initialize the driver chip register to achieve chip register initialization and clearing action; The second step is to configure the analog self-test and digital self-test BIST registers to enable the driver chip to perform self-status checks; The third step is to configure the driver chip output frequency and minimum dead time register, and set the frequency value and dead time limit parameters of the chip output signal; The fourth step is to configure the driver chip fault register to set the chip's response time to overcurrent and overvoltage faults. Step 5: Configure the driver chip register and set the interaction cycle value between the MCU and the driver chip WDG; Step 6: Configure the driver chip fault register to set the chip's response time to over-temperature faults. Step 7: Configure the driver chip register to set whether there are any faults that need to be shielded; Step 8: Use the SPI communication bit to exit the driver chip from the configurable state.

[0037] Preferably, the control function of the motor is also realized by a cache circuit, an emergency shutdown circuit, and a resolver circuit, wherein: (The output signal of the microprocessor chip may have an irregular waveform after a long transmission.) A cache circuit is designed at the (MCU) output end. Its digital circuit performs square wave shaping on the MCU output waveform. The cache chip's own function ensures that the output waveform is more accurately identified. The emergency shutdown circuit operates in the system's overcurrent or overvoltage fault identification state. After receiving the overvoltage or overcurrent fault, the microprocessor chip must perform at least one operation cycle before issuing a fault-related instruction. When a fault occurs, the emergency shutdown circuit uses the GTM function of the microprocessor chip to issue a fault-related instruction without going through the CPU operation cycle. Then, the signal sent at the end of the CPU operation cycle is used to check and modify the emergency fault instruction signal, achieving the goal of issuing accurate instructions quickly after signal verification. The resolver circuit includes an excitation circuit and a sampling circuit. The excitation circuit shapes the square wave emitted by the microprocessor chip into a sine wave and sends it to the circuit resolver through a power amplifier. The resolver secondary side feedback signal is input into the sampling circuit. After RC filtering, the microprocessor chip parses the motor speed and position signals through the soft decoding code to realize the normal control function of the motor.

[0038] For the drive motor and generator motor, a single BGA292 microprocessor chip (i.e., microprocessor chip) and SBC and peripheral circuits are used to implement the functional control circuit. The power supply circuit uses an SBC power supply chip with functional safety ASIL-D level as the power supply circuit for the BGA292 microprocessor chip. At the same time, the SBC and BGA292 microprocessor chip have a WDG monitoring function. If the BGA292 microprocessor chip does not feedback the WDG signal on time, the SBC considers that the main arithmetic unit chip is malfunctioning and can directly control the drive chip through the ASC circuit as in an emergency to implement fault action.

[0039] For the oil pump motor and shift motor, the control circuit design includes a main arithmetic unit chip that communicates directly with the driver chip, minimizing signal resource usage. A power module is also included to power each circuit, and a high-voltage DC-DC output circuit is designed to provide redundant power to the 12V battery.

[0040] The present invention utilizes a BGA 292 packaged microprocessor chip to realize four motor control functions and a power coupling module control function, and can achieve system solution optimization and cost optimization while ensuring system reliability to the greatest extent. The low-cost optimized architecture is conducive to increasing product competitiveness.

[0041] The main arithmetic unit chip of the present invention collects the KL30 voltage and SBC output voltage provided by the 12V battery to ensure normal power supply function.

[0042] In a hybrid power system, there are powertrain components such as engines, electric motors, and gearboxes. If the vehicle malfunctions, the motor, engine, and wheels cannot be disconnected from the power connection. Under conditions such as towing, the motor and power parts will be damaged. Therefore, in this design, a power coupling module controller is designed. Its physical structure is a solenoid valve structure. When the internal coil is conducting and working, the internal gears engage to complete the power transmission; in a fault state, the internal coil does not work, and its internal gears are disengaged, making it impossible to transmit power. This solution completes the control function of the internal coil operation. Under special circumstances, the main arithmetic unit chip can control the disconnection of the power connection, making the vehicle handling more flexible. The hybrid power connection diagram is as follows Figure 6 , the power coupling module control function topology is as follows Figure 7 .

[0043] The solution includes a high-voltage backup power supply. If the 12V battery power supply circuit of the vehicle is poorly connected or suddenly loses power during vehicle application, the high-voltage battery can continue to supply power to the low voltage, ensuring the normal function of the system and achieving the goal of high system reliability.

[0044] The advantages of the present invention are: 1) The design utilizes a BGA292 main arithmetic unit (APU) chip to control the drive motor, generator motor, oil pump motor, shift motor, power coupling module, and high-voltage backup power supply. By analyzing the impact of each function on the system and designing different functional safety targets, the system achieves all control functions while maintaining 98% APU pin utilization. This solution utilizes a relatively low-cost APU chip to achieve high reliability and diagnostic coverage for an electric drive inverter system.

[0045] 2) The solution design includes independent drive motor control circuits and generator motor control circuits. Each motor's anomaly and fault handling circuit can be independently controlled to achieve high reliability. The main arithmetic unit (CPU) directly controls the oil pump motor and shift motor, increasing the real-time performance of BLDC motor control and eliminating the need for redundant circuits to utilize the main arithmetic unit (CPU).

[0046] 3) The scheme designs the control function of the engine, motor and wheel power coupling module. If the vehicle malfunctions, the motor, engine and wheels cannot be disconnected from the power connection. In conditions such as towing, the vehicle is easier to handle and avoids damage to the motor and power components.

[0047] 4) Design a high-voltage DCDC power supply circuit, connect it in parallel with the 12V battery power supply end, and design the high-voltage power supply output voltage to be lower than the 12V battery voltage, but can ensure the normal operating voltage value of the system; when the 12V battery power supply voltage is unstable, it can directly intervene to ensure the normal power supply of the system; when the 12V battery power supply voltage is stable, it will not work as a backup power supply.

[0048] The present invention uses SBC to verify the operating status of the main arithmetic unit software. The main arithmetic unit adds sampling verification of the input signal of the drive motor power chip, which has higher safety requirements, to achieve high reliability and high functional safety level goals. The main arithmetic unit uses direct communication with the oil pump motor and shift motor driver chips to save chip resources and achieve the goal of system cost reduction. A high-voltage DC-DC power supply circuit is designed and connected in parallel with the 12V battery power supply terminal. If the 12V battery power supply voltage is unstable, it can directly intervene to ensure normal power supply of the system.

[0049] This invention utilizes a compact main arithmetic unit chip to integrate multiple motor control functions and power coupling module control at a low cost. An independent power supply solution ensures power system security. The main arithmetic unit simultaneously handles a wide range of fault conditions within the electric drive inverter assembly, effectively improving system reliability, enhancing product cost-effectiveness, and increasing the competitiveness of the vehicle.

[0050] It is worth mentioning that the technical features such as motors involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional means in the field and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0051] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multifunctional integrated motor control system for hybrid new energy vehicles, characterized in that: It includes a microprocessor chip and an oil pump motor power circuit, a shift motor power circuit, a generator motor power circuit, a drive motor power circuit, an Elock circuit and a power supply circuit electrically connected to the microprocessor chip, wherein: The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, the microprocessor chip controls the shift motor through the shift motor power circuit, the microprocessor chip controls the generator motor through the generator motor power circuit, the microprocessor chip controls the drive motor through the drive motor power circuit, and the microprocessor chip controls the power coupling module through the Elock circuit.

2. The multifunctional integrated motor control system for hybrid new energy vehicles according to claim 1, characterized in that: For the generator motor and the drive motor, the microprocessor chip collects the resolver feedback signal through the resolver circuit and controls the generator motor and the drive motor respectively in combination with the output torque target. The microprocessor chip controls the generator motor and the drive motor in the following specific implementations: The microprocessor chip sends a PWM control signal to the driver chip of the corresponding power circuit according to the expected torque and speed. The driver chip drives the IGBT after power amplification, so that the corresponding motor rotates according to the expected torque and speed. The microprocessor chip simultaneously sends out a resolver excitation signal, which is a square wave. After filtering and amplification by the resolver excitation circuit, it is output to the primary side of the resolver inside the motor; the resolver accessory feedback sine and cosine signals are filtered by the resolver sampling point and input into the microprocessor chip. Through soft decoding, it is identified whether the current speed of the motor verifies the expected instruction. If it does not meet the instruction, it enters the PI closed-loop regulation state and outputs the PWM duty cycle signal under dynamic conditions; Furthermore, the microprocessor chip includes multiple CPUs, so that different motor control codes are placed in different CPUs for operation; the hardware interface distinguishes the control signals of different motors through pin design, thereby realizing the separate control functions of different motors.

3. The multifunctional integrated motor control system for hybrid new energy vehicles according to claim 2, characterized in that: For the drive motor, the ASIL-C functional safety goal of the drive motor is designed. The microprocessor chip outputs the PWM control signal to the cache circuit, that is, the level conversion chip circuit. The cache circuit is used to effectively increase the driving capability and perform square wave shaping on the model to ensure the quality of the PWM signal output to the back end. At the same time, if the microprocessor chip detects a signal including overcurrent, overvoltage or other faults, it directly shuts down the cache chip of the cache circuit to avoid the issuance of erroneous signals. Design the recovery drive function of the drive motor. The microprocessor chip will use the PWM signal recovered through GPIO, parse the frequency and duty cycle values, and compare them with the frequency and duty cycle values ​​issued by the expected instruction. If they are consistent, it proves that the actual PWM signal issued is correct and the correctness of the signal is ensured. If the frequency and duty cycle values ​​of the recovered PWM signal are inconsistent with the values ​​in the expected instruction, it proves that there is a problem in the signal transmission process and it is necessary to enter the fault state and shut down, waiting for the problem to be investigated.

4. The multifunctional integrated motor control system for hybrid new energy vehicles according to claim 3, characterized in that: During the operation of the drive motor and generator motor, if the system encounters a fault including overcurrent and overvoltage, set the first-level shutdown logic, the second-level shutdown logic, and the third-level shutdown logic, where: The first-level shutdown logic is that the output instructions of the microprocessor chip are output according to a preset fixed level; the second-level shutdown logic is that the output instructions of the microprocessor chip directly shut down the cache chip through the logic circuit. The second-level shutdown logic requires the use of external resistors to enable the system to enter the predetermined lower bridge arm ASC functional safety state; The first level of shutdown logic is to assume that all circuit functions are normal, and the microprocessor chip will respond to normal faults. The second level of shutdown logic is to assume that if some circuit functions of the system fail and the signal cannot be effectively transmitted from the microprocessor chip to the driver chip, a separate fault channel is established, so that the microprocessor chip can directly shut down the driver chip. The third level of shutdown logic is that when the microprocessor chip does not perform WDG signal interaction with the SBC chip of the power circuit, the SBC chip believes that there is a problem with the microprocessor chip and the signal sent is unreliable, and thus directly shuts down the signal channel.

5. The multifunctional integrated motor control system for hybrid new energy vehicles according to claim 4, characterized in that: For the oil pump motor and the shift motor, the microprocessor chip directly communicates with the driver chip of the corresponding power circuit through SPI to configure the registers to implement status and fault corresponding actions.

6. The multifunctional integrated motor control system for hybrid new energy vehicles according to claim 5, characterized in that: The microprocessor chip communicates with the control chip in the corresponding power circuit of the corresponding motor via SPI, thereby realizing the register configuration of the driver chip, which is specifically implemented as follows: The first step is to set the driver chip to a configurable state through the SPI communication bit, and then use SPI communication to initialize the driver chip register to achieve chip register initialization and clearing action; The second step is to configure the analog self-test and digital self-test BIST registers to enable the driver chip to perform self-status checks; The third step is to configure the driver chip output frequency and minimum dead time register, and set the frequency value and dead time limit parameters of the chip output signal; The fourth step is to configure the driver chip fault register to set the chip's response time to overcurrent and overvoltage faults. Step 5: Configure the driver chip register and set the interaction cycle value with the driver chip WDG; Step 6: Configure the driver chip fault register to set the chip's response time to over-temperature faults. Step 7: Configure the driver chip register to set whether there are any faults that need to be shielded; Step 8: Use the SPI communication bit to exit the driver chip from the configurable state.

7. The multifunctional integrated motor control system for hybrid new energy vehicles according to claim 6, characterized in that: The motor control function is also realized through the cache circuit, emergency shutdown circuit, and resolver circuit, among which: The cache circuit is designed at the output end. Its digital circuit performs square wave shaping on the MCU output waveform. The cache chip's own function ensures that the output waveform is more accurately identified. The emergency shutdown circuit operates in the system's overcurrent or overvoltage fault identification state. After receiving the overvoltage or overcurrent fault, the microprocessor chip must perform at least one operation cycle before issuing a fault-related instruction. When a fault occurs, the emergency shutdown circuit uses the GTM function of the microprocessor chip to issue a fault-related instruction without going through the CPU operation cycle. Then, the signal sent at the end of the CPU operation cycle is used to check and modify the emergency fault instruction signal, achieving the goal of issuing accurate instructions quickly after signal verification. The resolver circuit includes an excitation circuit and a sampling circuit. The excitation circuit shapes the square wave emitted by the microprocessor chip into a sine wave and sends it to the circuit resolver through a power amplifier. The resolver secondary side feedback signal is input into the sampling circuit. After RC filtering, the microprocessor chip parses the motor speed and position signals through the soft decoding code to realize the normal control function of the motor.

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