A board card detection method, device, equipment and storage medium

Abstract

The application discloses a board card detection method and device, equipment and a storage medium, and relates to the technical field of server testing. The method comprises the following steps: detecting a board card image by using a pre-training model constructed based on a preset large-scale selective core network to obtain a first detection result; performing tomography on each to-be-detected board card to obtain a three-dimensional image to determine a second detection result; sending the first detection result and the second detection result to a host computer, obtaining a physical defect detection result returned by the host computer, and determining an initial qualified board card according to the physical defect detection result; collecting electric signal data of each initial qualified board card, and determining a target qualified board card in the initial qualified board card according to the electric signal data. The pre-training model is constructed based on the large-scale selective core network to detect the board card image, tomography is performed to obtain a three-dimensional image, an appearance detection result is obtained, and then a qualified board card is further determined according to electric signal data. Through comprehensive testing of the appearance and the signal channel, the accuracy of the board card test result is improved.

Description

Technical Field

[0001] This application relates to the field of server testing technology, and in particular to a board testing method, apparatus, device and storage medium. Background Technology

[0002] In current server design and manufacturing, some relatively independent functions are gradually being separated into individual boards to facilitate optimized server layout and differentiated configurations. However, each board in a server often involves a large number of functional interfaces, which enable signal interaction with other boards. The interaction methods are usually interface plug-in or cable connection. Before leaving the factory, the boards must be powered on and tested, and the basic functions of the board need to be verified by running FCT (Functional Circuit Test) to ensure the quality of the board leaving the factory.

[0003] Currently, the testing of circuit boards before use is still in the manual testing stage. Manual testing has disadvantages such as long testing time and lack of accuracy. In addition, when testing a small number of circuit boards, it is also inefficient and inconvenient to operate because only one item can be tested at a time. Summary of the Invention

[0004] This application provides a method, apparatus, device, and storage medium for board testing, which solves the problems of insufficient accuracy and low efficiency in current board testing. By conducting comprehensive testing from appearance to signal channels, it helps to improve the accuracy of board test results.

[0005] This application provides a board testing method, including:

[0006] The board images of each board to be detected are acquired, and the pre-trained model is used to detect the board images to obtain the first detection result of each board to be detected; the pre-trained model is a model built based on a pre-set large selective kernel network;

[0007] Each board to be tested is subjected to tomographic scanning to obtain a three-dimensional image of each board to be tested, and a second test result of each board to be tested is determined based on the three-dimensional image;

[0008] The first and second test results are sent to the preset host computer, and the physical defect test results of each board to be tested are obtained from the preset host computer. The initial qualified boards in the board to be tested are determined based on the physical defect test results.

[0009] Collect electrical signal data of each initially qualified board during operation, and determine the target qualified board among the initially qualified boards based on the electrical signal data.

[0010] This application also provides a circuit board testing device, including:

[0011] The image detection module is used to acquire the board images of each board to be detected, and to detect the board images using a pre-trained model to obtain the first detection result of each board to be detected; the pre-trained model is a model built based on a preset large selective kernel network;

[0012] The board scanning module is used to perform tomographic scanning on each board to be tested to obtain a three-dimensional image of each board to be tested, so as to determine the second detection result of each board to be tested based on the three-dimensional image;

[0013] The defect detection module is used to send the first and second detection results to the preset host computer, and obtain the physical defect detection results of each board to be tested returned by the preset host computer, and determine the initial qualified boards among the boards to be tested based on the physical defect detection results.

[0014] The signal detection module is used to collect electrical signal data during the operation of each initially qualified board and drive the target qualified board in the initially qualified board according to the electrical signal data.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described board detection methods.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described board detection methods.

[0017] This application first acquires the board images of each board to be tested, and uses a pre-trained model built based on a preset large selective kernel network to detect the board images, obtaining the first detection result of each board to be tested. Then, a tomographic scan is performed on each board to be tested to obtain the three-dimensional image of each board to be tested and determine the second detection result of each board to be tested. The first and second detection results are sent to a preset host computer to obtain the returned physical defect detection results. Based on the physical defect detection results, the initial qualified boards in the board to be tested are determined. Then, the electrical signal data of each initially qualified board during operation is collected, and the target qualified board in the initially qualified board is determined based on the electrical signal data. This application enables the construction of a pre-trained model based on a pre-defined large selective kernel network for board image detection. A tomographic scan of the board to be detected yields a 3D image, providing physical defect detection results for the board's shape. This allows for initial board screening. Then, electrical signal data from initially qualified boards is collected, and the signal channels are inspected to further identify target qualified boards among the initial qualified boards. This achieves dual automatic testing of both physical and signal channel defects, solving the problems of insufficient accuracy and low efficiency in current board testing. Comprehensive testing from shape to signal channels helps improve the accuracy of board test results. Attached Figure Description

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart of a board testing method provided in this application embodiment;

[0020] Figure 2 A circuit board testing system architecture diagram provided in this application embodiment;

[0021] Figure 3 A flowchart of board testing is provided as an embodiment of this application;

[0022] Figure 4 A flowchart illustrating a specific board testing method provided in this application embodiment;

[0023] Figure 5 This is a schematic diagram of a board testing device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0025] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0026] Currently, pre-use testing of circuit boards is still in the manual testing stage. Manual testing has disadvantages such as long testing time and insufficient accuracy. In addition, when testing a small number of circuit boards, only one item can be tested at a time, which is inefficient and inconvenient. This application can use a pre-trained model to detect circuit board images and perform tomographic scanning on the circuit board to obtain a three-dimensional image to obtain the physical defect detection results of the circuit board's shape. Then, it collects the electrical signal data of the initially qualified circuit boards, detects the signal channels of the circuit boards, and further determines the target qualified circuit board among the initially qualified circuit boards. Through comprehensive testing from shape to signal channels, it helps to improve the accuracy of circuit board test results.

[0027] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] like Figure 1 As shown, embodiments of this application provide a board detection method, which will be described in detail below with reference to the execution flow of the board detection method, including:

[0029] Step S11: Obtain the board image of each board to be detected, and use the pre-trained model to detect the board image to obtain the first detection result of each board to be detected; the pre-trained model is a model built based on a preset large selective kernel network.

[0030] In this embodiment, the images of each board to be detected are first acquired, and a pre-trained model is used to detect the board images, obtaining the first detection result for each board. The pre-trained model is a model built based on a pre-defined large selective kernel network (LSKNet). Pre-training is a deep learning model training strategy; its core is to use a large-scale dataset to initially train the model, enabling it to learn general feature representations. In this embodiment, a model training task can be designed in advance based on a library of board images, training a large-scale neural network algorithm structure to learn and implement it. The final large-scale neural network algorithm structure and parameters constitute the pre-trained model. Subsequent tasks can then be performed on this model for feature extraction or task fine-tuning to achieve specific task objectives. By pre-training on the image library, the large-scale neural network model can extract rich feature information from the board images for board qualification detection. LSKNet is a convolutional neural network architecture, and the pre-trained model in this embodiment is specifically the YOLOv10 model (You Only Look Once: Unified, Real-Time Object Detection, an object detection model).

[0031] like Figure 2 As shown, this embodiment utilizes a board interface testing fixture to test the board, including a host computer, a wireless communication module, a main control chip, a time-frequency domain collaborative testing system, a signal acquisition module, a multi-level defect intelligent identification module, a data acquisition module, and the board under test. After the main control chip issues a command, the data acquired by the data acquisition module can be imported into the multi-level defect intelligent identification module. The multi-level defect intelligent identification module detects physical defects in the board under test and inputs the results to the host computer via the wireless communication module, which then outputs the first detection result. During this process, the YOLOv10 model can be used to achieve real-time detection without NMS (Non-Maximum Suppression), and the LSKNet attention mechanism can be combined to enhance the detection of minute defects on the board.

[0032] Step S12: Perform tomographic scanning on each board to be tested to obtain a three-dimensional image of each board to be tested, and determine the second detection result of each board to be tested based on the three-dimensional image.

[0033] In this embodiment, a multi-level defect intelligent identification module detects physical defects in the test board, and the results are input to the host computer via a wireless communication module. During the process of the host computer outputting the first detection result, a tomographic scan can be performed on each test board to obtain a three-dimensional image of each board. A second detection result is then determined based on the three-dimensional image. Specifically, a tomographic scan is first performed on each test board to obtain an initial image. Then, a preset denoising algorithm is used to process the initial image, and a corresponding three-dimensional visualization model is generated based on the processed initial image to obtain the three-dimensional image. The preset denoising algorithm can be any one of spatial domain filtering, temporal domain filtering, transform domain filtering, or non-local mean filtering.

[0034] In other words, such as Figure 3 As shown, this embodiment can deploy a 3D X-ray computed tomography system to detect micro-void defects in hybrid bonding interfaces at nanometer-level resolution (<5nm). Furthermore, the 3D X-ray computed tomography system also includes the application of denoising algorithms to reduce image noise and enhance detail contrast. It generates a 3D visualization model through volume rendering or multi-planar reconstruction (MPR), supporting cross-sectional observation from any angle. Specifically, the denoising algorithm can employ any of the following: spatial domain filtering, temporal domain filtering, transform domain filtering, or non-local mean filtering.

[0035] Step S13: Send the first and second test results to the preset host computer, and obtain the physical defect test results of each board to be tested returned by the preset host computer. Determine the initial qualified board among the boards to be tested based on the physical defect test results.

[0036] In this embodiment, the first and second detection results can be sent to a preset host computer, and the physical defect detection results of each board to be tested returned by the preset host computer can be obtained. Based on the physical defect detection results, the initial qualified boards among the boards to be tested are determined. In this way, the detection of the external integrity of the boards is achieved by the combination of 3D X-ray tomography and YOLOv10 model detection, and the initial screening of the boards is realized, reducing the number of channel tests. Then, the results are input into the host computer, and the host computer outputs the initial detection results and removes the boards that fail the initial detection.

[0037] Step S14: Collect the electrical signal data of each initially qualified board during operation, and determine the target qualified board among the initially qualified boards based on the electrical signal data.

[0038] In this embodiment, after removing the boards that failed the initial test, electrical signal data of each initially qualified board during operation can be collected. Based on this data, the target qualified board among the initially qualified boards can be determined. Specifically, an oscilloscope can be used to capture the signal waveforms of each initially qualified board during operation, generating a corresponding signal eye diagram. A vector network analyzer can be used to scan the signal frequency range of each initially qualified board during operation. Based on the signal frequency range, the corresponding insertion loss and return loss are determined. The corresponding frequency domain parameters are obtained based on the insertion loss and return loss. Then, a time-domain reflectometer is used to detect impedance abrupt changes at preset connection locations in each initially qualified board. The electrical signal data of each initially qualified board during operation is obtained based on the signal eye diagram, frequency domain parameters, and impedance abrupt changes. In other words, as... Figure 2 As shown, a data acquisition command can be issued by the main control chip. At this time, the signal acquisition module acquires the electrical signal data of the board under test and tests the integrity of the electrical signals of the board under test using a time-frequency domain collaborative testing system. The test results are input to the host computer via the wireless communication module, and the host computer outputs a second detection result to determine if the target board is qualified. In this way, dual testing of the board is achieved through the board interface testing fixture, realizing comprehensive testing from its appearance to its signal channels. Furthermore, during the above signal transmission process, the signal acquisition module inputs test digital signals to the main control chip, the data acquisition module inputs test digital signals to the main control chip, and the board under test inputs analog voltage signals to the signal acquisition module.

[0039] In other words, such as Figure 3 As shown, this embodiment can construct a time-frequency domain collaborative testing system, combining a vector network analyzer (VNA) and a high-speed oscilloscope to achieve simultaneous detection of S-parameter matrix analysis and eye diagram height / jitter. This allows for secondary testing of the remaining boards, specifically through simultaneous measurement of eye diagram height / jitter to detect the board channel signals. The results of the second test are then input to the host computer via the main control chip, and the host computer outputs the second test results, removing boards that fail the second test to determine the target qualified boards.

[0040] Furthermore, after obtaining the frequency domain parameters based on insertion loss and return loss, the frequency domain parameters can be converted into the corresponding time domain impulse response through inverse fast Fourier transform. Then, the signal waveform and the time domain impulse response are compared. When the comparison result of the signal waveform and the time domain impulse response meets the preset error conditions, the electrical signal data is obtained based on the signal eye diagram, frequency domain parameters, and impedance abrupt change points. Accordingly, when determining the target qualified board among the initial qualified boards based on the electrical signal data, the signal amplitude range, signal stabilization time window, and signal jitter component corresponding to each signal eye diagram are first determined. The signal jitter component is then decomposed into random jitter and deterministic jitter. Then, the rise time or fall time of each initial qualified board during operation is determined based on the signal waveform. The signal edge rate of the signal waveform is determined based on the rise time or fall time. Finally, the target qualified board among the initial qualified boards is determined based on the signal amplitude range, signal stabilization time window, random jitter, deterministic jitter, signal edge rate, frequency domain parameters, and impedance abrupt change points. In this way, the frequency domain data measured by the VNA is converted into a time domain impulse response through inverse fast Fourier transform. Comparison with the time domain waveform measured by the oscilloscope helps verify the accuracy of the signal transmission model and ensures that the acquired electrical signals truly reflect the actual working state of the board. Through the above technical steps, comprehensive acquisition of the board's electrical signals is achieved, providing raw data for subsequent time-frequency domain collaborative analysis and obtaining accurate real-time detection results. Furthermore, through the board interface testing fixture and method of this embodiment, the collaborative cooperation of the YOLOv10 model and the time-frequency domain collaborative testing system, and the initial screening of the board using a deep learning model, along with testing through dual signal channels in both the time and frequency domains, improves testing efficiency while ensuring greater testing accuracy.

[0041] In other words, this embodiment can convert frequency domain parameters into corresponding time domain impulse responses using inverse fast Fourier transform for time-frequency domain co-testing. First, the time-frequency domain co-testing system is connected to the circuit board under test (e.g., via cable or probe contact). The main control chip issues a acquisition command, triggering a high-speed oscilloscope or other device to begin capturing the electrical signals of the circuit board during operation. Then, the oscilloscope is triggered to capture ≥10... ^6The signal waveform of each UI (Unit Interval) is used to generate an eye diagram and quantify the eye height (signal amplitude range), eye width (signal stabilization time window), and jitter component (time deviation of signal transition). The total jitter (TJ) is separated into random jitter (RJ < 0.5 ps RMS) and deterministic jitter (DJ < 9.5 ps) using the dual Dirac algorithm to verify the timing tolerance of the high-speed interface. Then, the oscilloscope captures the time for the signal to transition from low level to high level (rising edge) or from high level to low level (falling edge). The rise / fall time test is used to measure the signal edge rate to determine whether it conforms to the corresponding protocol specification of the board and to verify whether it meets the rate requirements. Simultaneously, the signal frequency range is scanned, and insertion loss and return loss are recorded. A TDR (Time Domain Reflectometry) is used to detect impedance abrupt changes at locations such as vias and connectors on the PCB (Printed Circuit Board). Then, the S-parameters measured by the VNA are converted into a time-domain impulse response using an IFFT (Inverse Fast Fourier Transform), and compared with the measured waveform on an oscilloscope to verify channel model errors and locate physical defects in signal transmission (such as via mismatch or broken traces). In this way, by combining S-parameter impedance abrupt changes with time-domain reflection events, latent defects such as PCB trace breaks and via impedance mismatches can be identified. Data is independently collected from three dimensions: time-domain waveform, frequency-domain characteristics, and physical impedance, forming a comprehensive basis for analyzing the integrity of the board's electrical signals and improving the accuracy of board testing. The total jitter formula for the above dual Dirac algorithm is:

[0042] ;

[0043] in, For Dirac The function represents the discrete distribution characteristics of deterministic jitter (DJ); μDJ is the peak-to-peak value of deterministic jitter (usually corresponding to the separation of DJ); σRJ is the standard deviation of the Gaussian distribution of random jitter (RJ); This is the convolution operator, representing the superposition effect of RJ and DJ.

[0044] This embodiment first acquires the board images of each board to be tested, and uses a pre-trained model built based on a preset large selective kernel network to detect the board images, obtaining the first detection result of each board to be tested. Then, a tomographic scan is performed on each board to be tested to obtain the three-dimensional image of each board to be tested and determine the second detection result of each board to be tested. The first and second detection results are sent to a preset host computer to obtain the returned physical defect detection results. Based on the physical defect detection results, the initial qualified boards in the board to be tested are determined. Then, the electrical signal data of each initially qualified board during operation is collected, and the target qualified board in the initially qualified board is determined based on the electrical signal data. It is understood that the above technical solution can be applied to the automatic testing of all circuit boards in computer products such as servers. Through the above technical solution, this embodiment can construct a pre-trained model based on a preset large selective core network to perform circuit board image detection, and perform tomographic scanning on the circuit board to obtain a three-dimensional image to obtain the physical defect detection results of the circuit board's appearance, perform preliminary screening of the circuit board, and then collect the electrical signal data of the initially qualified circuit boards to detect the signal channels of the circuit boards, further determining the target qualified circuit board among the initially qualified circuit boards. In this way, dual automatic testing of physical defects and signal channel defects of the circuit board is realized, solving the problems of insufficient accuracy and low efficiency in current circuit board testing. Furthermore, the frequency domain data measured by VNA is converted into time domain impulse response through inverse fast Fourier transform, and compared with the time domain waveform measured by oscilloscope, which helps to verify the accuracy of the signal transmission model and ensure that the collected electrical signals truly reflect the actual working state of the circuit board. Comprehensive acquisition of circuit board electrical signals is realized. Through comprehensive testing from appearance to signal channels, it helps to improve the accuracy of circuit board test results.

[0045] As can be seen from the previous embodiment, this application can utilize a pre-trained model to perform board image detection and generate a 3D image of the board, obtaining physical defect detection results. Then, electrical signal data is collected to further determine qualified boards. Next, this embodiment will describe in detail the process of constructing the pre-trained model. See [link to previous embodiment]. Figure 4 As shown, an embodiment of this application provides a specific board testing method, including:

[0046] Step S21: Obtain board data for qualified and unqualified boards, and construct corresponding training data based on the board data. Perform grayscale conversion, size normalization, and Gaussian filtering on the training data to obtain preprocessed data. Process the preprocessed data according to preset geometric transformation rules to obtain target data.

[0047] In this embodiment, board data of qualified and unqualified boards can be obtained, and corresponding training data can be constructed based on the board data. The training data is then subjected to grayscale conversion, size normalization, and Gaussian filtering to obtain preprocessed data. The preprocessed data is then processed based on preset geometric transformation rules to obtain target data.

[0048] Understandably, in this embodiment, YOLOv10 adopts an anchor-free design, optimizing detection performance through the following constraints: The point anchoring mechanism simplifies traditional box-based anchoring to center point prediction, reducing computational complexity and improving small object detection capabilities; decoupling the head from classification and regression tasks alleviates the problem of inconsistent objectives, but requires feature learning alignment through a loss function; dynamic label allocation dynamically assigns positive and negative samples based on the IoU (Intersection over Union) between predicted and ground truth boxes, avoiding false negatives or missed detections caused by fixed thresholds. Furthermore, YOLOv10's loss function integrates multi-task optimization objectives, specifically a classification loss (VFL, Variational Loss), using VFL instead of traditional cross-entropy to address class imbalance through dynamic weighting, focusing on high-quality predicted samples.

[0049] ;

[0050] Where qi is the IoU weighted label, pi is the predicted probability, and γ is the adjustment factor.

[0051] Step S22: Construct an initial model based on a depthwise separable convolutional model and a pre-set large selective kernel network, train the initial model using target data to obtain a pre-trained model, and use the pre-trained model to detect board images.

[0052] In this embodiment, an initial model can be constructed based on a depthwise separable convolutional model and a pre-set large selective kernel network. The initial model is then trained using target data to obtain a pre-trained model, which is used to detect circuit board images. During the initial model training process using target data, target points for circuit board defects in the circuit board data can be identified. Based on these target points, corresponding predicted bounding boxes are determined. Then, the corresponding ground truth bounding boxes are determined, and the overlap between the predicted and ground truth bounding boxes is calculated. Based on this overlap, positive and negative samples in the training data are determined, allowing the initial model to be trained using these positive and negative samples and the target data to obtain the pre-trained model.

[0053] In other words, during model training in this embodiment, multimodal data containing both normal and defective samples, such as PCB surface images and 3D CAD (Computer Aided Design) models, is first collected to generate a dataset. This dataset is then labeled and divided into a test set and a validation set. Next, grayscale conversion, size normalization, and noise reduction (Gaussian filtering) are performed on the acquired images to improve data consistency. Random geometric transformations, such as rotation ±5°, translation 10%, and color perturbation brightness adjustment ±20%, are employed to enhance data diversity and improve the model's adaptability to complex industrial scenarios. Then, the YOLOv10 model can be deployed for board defect identification. It uses depthwise separable convolution to extract multi-scale features and integrates an LSKNet module to focus on minute defect areas, such as ±0.1mm pin offsets. Spatial-channel collaborative attention enhances feature discrimination. Finally, the YOLOv10 model is trained on the test set, and the trained model is deployed on the inspection device for the initial testing of the boards to be inspected. The above technical solutions enable the construction and training of the YOLOv10 model, thereby improving the efficiency of board defect identification.

[0054] Through the above technical solution, this embodiment utilizes the YOLOv10 model to achieve real-time detection without NMS. It abandons the pre-set anchor boxes method in traditional object detection and directly predicts the center point and bounding box of the target (such as the defect location of pins, interfaces, etc. on the board) through the point anchoring mechanism. It does not require the generation of a large number of candidate anchor boxes, thereby reducing the generation of overlapping boxes from the root and reducing the dependence on NMS post-processing. At the same time, it reduces the amount of computation, improves real-time performance, and decouples the head structure, separating the model's classification task (determining whether it is a defect) and regression task (locating the bounding box of the defect) into two independent branches. Through their respective feature extraction and calculation, the conflict between the two types of task objectives is alleviated. At the same time, the feature learning of the two types of tasks is aligned through subsequent loss functions (such as Varifocal Loss), ensuring that the predicted bounding boxes are more accurate and further reducing redundant boxes. Furthermore, during training, positive and negative samples are dynamically divided based on the intersection-union ratio (IoU) between the predicted bounding box and the actual defect bounding box. This avoids false negatives (such as small defects being misclassified as negative samples due to low IoU) or false positives (such as background areas being misclassified as positive samples due to lenient thresholds) caused by fixed thresholds. This allows the model to learn more accurate target bounding box predictions during the training phase, and outputs effective results without NMS during inference. Dynamic label allocation improves sample quality and ensures the accuracy and efficiency of defect recognition.

[0055] like Figure 5 As shown, embodiments of this application also provide a board testing device, including:

[0056] Image detection module 11 is used to acquire board images of each board to be detected, and to detect the board images using a pre-trained model to obtain the first detection result of each board to be detected; the pre-trained model is a model built based on a preset large selective kernel network;

[0057] The board scanning module 12 is used to perform tomographic scanning on each board to be tested to obtain a three-dimensional image of each board to be tested, so as to determine the second detection result of each board to be tested based on the three-dimensional image.

[0058] The defect detection module 13 is used to send the first detection result and the second detection result to the preset host computer, and to obtain the physical defect detection results of each board to be tested returned by the preset host computer, and to determine the initial qualified board among the boards to be tested based on the physical defect detection results.

[0059] The signal detection module 14 is used to collect electrical signal data during the operation of each initially qualified board and drive the target qualified board in the initially qualified board according to the electrical signal data.

[0060] In this embodiment, a pre-trained model can be constructed based on a preset large selective kernel network to perform board image detection. A tomographic scan of the board to be tested is performed to obtain a three-dimensional image, thereby obtaining the physical defect detection results of the board's shape and performing preliminary screening of the board. Then, the electrical signal data of the initially qualified boards are collected, and the signal channels of the boards are detected to further determine the target qualified boards among the initially qualified boards. In this way, dual automatic testing of physical defects and signal channel defects of the board is realized, which solves the problems of insufficient accuracy and low efficiency in the current board testing. Through comprehensive testing from shape to signal channel, it helps to improve the accuracy of board test results.

[0061] In some specific embodiments, the signal detection module specifically includes:

[0062] The eye diagram generation unit is used to capture the signal waveforms of each initially qualified board during operation using an oscilloscope and generate the corresponding signal eye diagram.

[0063] The signal analysis unit is used to scan the signal frequency range of each initially qualified board during operation using a vector network analyzer, and determine the corresponding insertion loss and return loss based on the signal frequency range, and obtain the corresponding frequency domain parameters based on the insertion loss and return loss.

[0064] Impedance detection unit is used to detect impedance abrupt changes at preset connection positions in each initially qualified board using a time domain reflectometer;

[0065] The data generation unit is used to obtain the electrical signal data of each initially qualified board during operation based on the signal eye diagram, frequency domain parameters, and impedance abrupt change points.

[0066] In some specific embodiments, the signal detection module further includes:

[0067] The parameter conversion unit is used to convert frequency domain parameters into corresponding time domain impulse responses through inverse fast Fourier transform;

[0068] The signal comparison unit is used to compare the signal waveform and the time-domain impulse response so that when the comparison result of the signal waveform and the time-domain impulse response meets the preset error conditions, the electrical signal data can be obtained based on the signal eye diagram, frequency domain parameters and impedance change points.

[0069] In some specific embodiments, the signal detection module specifically includes:

[0070] The signal determination unit is used to determine the signal amplitude range, signal stabilization time window, and signal jitter component corresponding to each signal eye diagram;

[0071] The signal decomposition unit is used to decompose the signal jitter components into random jitter and deterministic jitter;

[0072] The parameter determination unit is used to determine the rise time or fall time of each initially qualified board during operation based on the signal waveform, and to determine the signal edge rate of the signal waveform based on the rise time or fall time.

[0073] The board detection unit is used to determine the target qualified board among the initial qualified boards based on the signal amplitude range, signal stability time window, random jitter, deterministic jitter, signal edge rate, frequency domain parameters, and impedance change point.

[0074] In some specific embodiments, the board scanning module specifically includes:

[0075] The board scanning unit is used to perform tomographic scanning on each board to be tested to obtain an initial image of each board to be tested.

[0076] The image processing unit is used to process the initial image using a preset denoising algorithm and generate a corresponding three-dimensional visualization model based on the processed initial image, so as to obtain a three-dimensional image based on the three-dimensional visualization model; the preset denoising algorithm is any one of spatial domain filtering, temporal domain filtering, transform domain filtering and nonlocal mean filtering.

[0077] In some specific embodiments, the board testing device further includes:

[0078] The data construction module is used to acquire board data for qualified and unqualified boards, and to construct corresponding training data based on the board data;

[0079] The data preprocessing module is used to perform grayscale conversion, size normalization, and Gaussian filtering on the training data to obtain preprocessed data, and then process the preprocessed data based on preset geometric transformation rules to obtain the target data.

[0080] The model building module is used to build an initial model based on a depthwise separable convolutional model and a pre-set large selective kernel network.

[0081] The model training module is used to train an initial model using the target data to obtain a pre-trained model.

[0082] In some specific embodiments, the model training module specifically includes:

[0083] The prediction box determination unit is used to determine the target points of board defects in the board data, and to determine the corresponding prediction boxes of the board data based on the target points of board defects.

[0084] The overlap determination unit is used to determine the ground truth bounding box corresponding to the board data and to determine the overlap between the predicted bounding box and the ground truth bounding box.

[0085] The model training unit is used to determine the positive and negative samples in the training data based on the overlap, so as to train the initial model based on the positive samples, negative samples and target data to obtain the pre-trained model.

[0086] For a description of the features in the embodiment corresponding to the board testing device, please refer to the relevant description of the embodiment corresponding to the board testing method, which will not be repeated here.

[0087] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0088] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described board detection method embodiments.

[0089] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described board detection method embodiments when running.

[0090] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0091] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described board detection method embodiments.

[0092] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described board detection method embodiments.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] The foregoing has provided a detailed description of a board testing method, apparatus, device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for testing circuit boards, characterized in that, include: The board images of each board to be detected are acquired, and the board images are detected using a pre-trained model to obtain the first detection result of each board to be detected; the pre-trained model is a model built based on a preset large selective kernel network; A tomographic scan is performed on each of the boards to be tested to obtain a three-dimensional image of each board to be tested, and a second detection result of each board to be tested is determined based on the three-dimensional image; The first detection result and the second detection result are sent to a preset host computer, and the physical defect detection results of each of the boards to be tested returned by the preset host computer are obtained. The initial qualified boards among the boards to be tested are determined according to the physical defect detection results. Collect electrical signal data of each of the initially qualified boards during operation, and determine the target qualified board among the initially qualified boards based on the electrical signal data; The electrical signal data includes the signal eye diagram, frequency domain parameters, and impedance abrupt change points during the operation of the initially qualified board. Wherein, the impedance mutation point is the impedance mutation point at the preset connection position in each of the initially qualified boards detected by a time domain reflectometer; Furthermore, the acquisition of electrical signal data during the operation of each of the initially qualified boards includes: Use an oscilloscope to capture the signal waveforms of each of the initially qualified boards during operation, and generate the corresponding signal eye diagrams; The signal frequency range of each of the initially qualified boards is scanned using a vector network analyzer, and the corresponding insertion loss and return loss are determined based on the signal frequency range. The corresponding frequency domain parameters are obtained based on the insertion loss and the return loss. The impedance abrupt change points at preset connection positions in each of the initially qualified boards are detected using a time-domain reflectometer; The electrical signal data of each of the initially qualified boards during operation are obtained based on the signal eye diagram, the frequency domain parameters, and the impedance abrupt change point. Furthermore, after obtaining the corresponding frequency domain parameters based on the insertion loss and the return loss, the method further includes: The frequency domain parameters are converted into corresponding time domain impulse responses by inverse fast Fourier transform; The signal waveform and the time-domain impulse response are compared so that when the comparison result of the signal waveform and the time-domain impulse response meets the preset error condition, the electrical signal data is obtained based on the signal eye diagram, the frequency domain parameters, and the impedance abrupt change point.

2. The board testing method according to claim 1, characterized in that, The step of determining the target qualified board in the initial qualified board based on the electrical signal data includes: Determine the signal amplitude range, signal stabilization time window, and signal jitter component corresponding to each of the aforementioned signal eye diagrams; The signal jitter components are decomposed into random jitter and deterministic jitter; Based on the signal waveform, the rise time or fall time of each of the initial qualified boards during operation is determined, and the signal edge rate of the signal waveform is determined based on the rise time or the fall time. The target qualified board in the initial qualified board is determined based on the signal amplitude range, the signal stabilization time window, the random jitter, the deterministic jitter, the signal edge rate, the frequency domain parameters, and the impedance abrupt change point.

3. The board testing method according to claim 1, characterized in that, The step of performing tomographic scanning on each of the boards to be tested to obtain a three-dimensional image of each board to be tested includes: Perform tomographic scanning on each of the boards to be tested to obtain an initial image of each board to be tested; The initial image is processed using a preset denoising algorithm, and a corresponding three-dimensional visualization model is generated based on the processed initial image, so as to obtain the three-dimensional image based on the three-dimensional visualization model; the preset denoising algorithm is any one of spatial domain filtering, temporal domain filtering, transform domain filtering and nonlocal mean filtering.

4. The board testing method according to any one of claims 1 to 3, characterized in that, Before using the pre-trained model to detect the board image, the method further includes: Obtain board data for qualified and unqualified boards, and construct corresponding training data based on the board data; The training data is subjected to grayscale conversion, size normalization, and Gaussian filtering respectively to obtain preprocessed data. The preprocessed data is then processed based on preset geometric transformation rules to obtain target data. An initial model is constructed based on a depthwise separable convolutional model and the preset large selective kernel network; The initial model is trained using the target data to obtain the pre-trained model.

5. The board testing method according to claim 4, characterized in that, The process of training the initial model using the target data to obtain the pre-trained model includes: Determine the target points of board defects in the board data, and determine the corresponding prediction boxes for the board data based on the target points of board defects; Determine the ground truth bounding box corresponding to the board data, and determine the overlap between the predicted bounding box and the ground truth bounding box; The positive and negative samples in the training data are determined based on the overlap, so that the initial model is trained based on the positive samples, the negative samples, and the target data to obtain the pre-trained model.

6. A circuit board testing device, characterized in that, include: The image detection module is used to acquire the board images of each board to be detected, and to detect the board images using a pre-trained model to obtain the first detection result of each board to be detected; the pre-trained model is a model built based on a preset large selective kernel network; The board scanning module is used to perform tomographic scanning on each of the boards to be tested to obtain a three-dimensional image of each of the boards to be tested, so as to determine a second detection result of each of the boards to be tested based on the three-dimensional image; The defect detection module is used to send the first detection result and the second detection result to a preset host computer, and to obtain the physical defect detection results of each of the boards to be tested returned by the preset host computer, and to determine the initial qualified boards among the boards to be tested based on the physical defect detection results; The signal detection module is used to collect electrical signal data during the operation of each of the initial qualified boards, and drive the target qualified board in the initial qualified boards according to the electrical signal data; The electrical signal data includes the signal eye diagram, frequency domain parameters, and impedance abrupt change points during the operation of the initially qualified board. Wherein, the impedance mutation point is the impedance mutation point at the preset connection position in each of the initially qualified boards detected by a time domain reflectometer; Furthermore, the signal detection module includes: The eye diagram generation unit is used to capture the signal waveforms of each initially qualified board during operation using an oscilloscope and generate the corresponding signal eye diagram. The signal analysis unit is used to scan the signal frequency range of each initially qualified board during operation using a vector network analyzer, and determine the corresponding insertion loss and return loss based on the signal frequency range, and obtain the corresponding frequency domain parameters based on the insertion loss and return loss. Impedance detection unit is used to detect impedance abrupt changes at preset connection positions in each initially qualified board using a time domain reflectometer; The data generation unit is used to obtain the electrical signal data of each initially qualified board during operation based on the signal eye diagram, frequency domain parameters, and impedance change points. The parameter conversion unit is used to convert frequency domain parameters into corresponding time domain impulse responses through inverse fast Fourier transform; The signal comparison unit is used to compare the signal waveform and the time-domain impulse response so that when the comparison result of the signal waveform and the time-domain impulse response meets the preset error conditions, the electrical signal data can be obtained based on the signal eye diagram, frequency domain parameters and impedance change points.

7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the board detection method as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the board detection method as described in any one of claims 1 to 5.

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