Dynamic characteristic characterization device and method for power switch device

Abstract

The invention relates to the technical field of integrated circuits, and provides a dynamic characteristic characterization device and method for a power switch device, and the device comprises a dynamic characteristic characterization circuit module and a data collection module. The dynamic characteristic characterization circuit module is connected with the data acquisition module; the dynamic characteristic characterization circuit module comprises a signal excitation and adjustment system, a stress control circuit and a measurement implementation circuit; the signal excitation and adjustment system is connected with the stress control circuit which is connected with the measurement implementation circuit. According to the invention, the dynamic characteristic characterization circuit module and the data acquisition module are configured, hard switch short-circuit stress and load short-circuit stress are applied to a to-be-tested device, and dynamic on-resistance and threshold voltage under different electric stresses and recovery conditions after short circuit are observed in the same test environment. And the physical mechanism of the dynamic stability of the power switch device under various stress conditions and the reliability of the power switch device can be deeply researched.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a device and method for characterizing the dynamic characteristics of a power switching device. Background Art

[0002] Power semiconductor devices (such as SiC MOSFETs, GaN HEMTs, and IGBTs) are core components in renewable energy power generation, electric vehicles, and industrial frequency conversion systems. Their dynamic reliability directly impacts the lifespan and safety of power electronic equipment. The drift characteristics of dynamic on-resistance and threshold voltage are key parameters for characterizing device degradation, especially under complex operating conditions (such as high-frequency switching, short-circuit events, and high-voltage bias). Their dynamic responses can reveal failure mechanisms such as material defects, interface traps, and hot carrier injection. However, existing dynamic characterization techniques face multiple bottlenecks, limiting the accuracy and efficiency of device evaluation.

[0003] Traditional testing methods typically design independent test equipment for a single stress scenario. For example, hard-switching short-circuit testing requires a high di / dt loop and fast protection circuitry, while load short-circuit testing relies on a high-current pulse generator and active thermal management modules. Off-state drain voltage stress testing requires a high-voltage DC source and a high-precision leakage current monitoring unit. This fragmented testing approach not only leads to high equipment costs, but also makes horizontal comparison of test results difficult due to differences in parasitic parameters between different platforms, failing to reflect device degradation behavior under realistic multi-stress coupling environments.

[0004] In terms of dynamic parameter measurement, existing technologies usually require interrupting the test after multiple stress applications and using static parameter measurement instruments (such as source measurement units (SMUs)) to detect the on-resistance and threshold voltage offline. However, the dynamic degradation of power devices has a memory effect. In particular, after transient stress (such as short-circuit shock), the parameter drift will partially disappear as the device temperature and carrier state recover. The offline measurement method cannot capture the real-time parameter changes at the moment of stress application, resulting in significant deviations in the assessment of the degree of dynamic degradation of the device. At the same time, the insufficient integration of the test system further exacerbates the above problems.

[0005] Therefore, it is necessary to provide a device and method for characterizing the dynamic characteristics of a power switching device. Summary of the Invention

[0006] The present invention provides a device and method for characterizing the dynamic characteristics of a power switching device. By configuring a dynamic characteristics characterization circuit module and a data acquisition module, hard switch short-circuit stress and load short-circuit stress are applied to the device under test. The dynamic on-resistance and threshold voltage under different electrical stresses, as well as the recovery after short circuit, are observed in the same test environment. This helps to conduct in-depth research on the physical mechanism of the dynamic stability of power switching devices under various stress conditions, as well as the reliability of power switching devices.

[0007] The present invention provides a device for characterizing dynamic characteristics of a power switching device, comprising:

[0008] Dynamic feature characterization circuit module and data acquisition module; the dynamic feature characterization circuit module is connected to the data acquisition module;

[0009] The dynamic characteristic characterization circuit module includes a signal excitation and regulation system, a stress control circuit, and a measurement implementation circuit; the signal excitation and regulation system is connected to the stress control circuit, and the stress control circuit is connected to the measurement implementation circuit; the signal excitation and regulation system is used to generate a drive signal for controlling the stress control circuit; the stress control circuit is used to apply two short-circuit electrical stresses to the field effect transistor under test according to the drive signal; and the measurement implementation circuit is used to measure the on-state voltage drop between the source and drain of the field effect transistor under test;

[0010] The data acquisition module is used to sample and obtain the detection current flowing between the source and drain of the field effect transistor to be tested and the gate-source voltage of the field effect transistor to be tested, and calculate based on the detection current and gate-source voltage to obtain the on-resistance and threshold voltage and characterize them.

[0011] Furthermore, the signal excitation and regulation system is a field programmable gate array chip; the signal excitation and regulation system includes an output terminal A1, an output terminal A2, an output terminal A3, an output terminal A4 and an output terminal A5.

[0012] Furthermore, the stress control circuit includes a high voltage power supply V BUS , input capacitor C BUS , load resistance RL, capacitor Cm, inductor L, freewheeling diode D1, switching transistor S1, switching transistor S2, switching transistor S3, switching transistor P and field effect transistor under test DUT; input capacitor C BUS The positive terminal of the high voltage power supply V BUS The positive terminal of the input capacitor C BUS The negative pole of the high voltage power supply V BUS The negative pole of the load resistor RL is connected to the high voltage power supply V BUS The positive pole of the load resistor RL is connected to one end of the load inductor L; the cathode of the freewheeling diode D1 is connected to the high voltage power supply V BUSThe positive electrode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, and the source of the switching transistor S1 is connected to the drain of the switching transistor P; the source of the switching transistor P is connected to the drain of the field effect transistor DUT to be tested; the switching transistor S2 is connected to the source of the field effect transistor DUT to be tested; the source of the switching transistor S2 is connected to the ground; the drain of the switching transistor S3 is connected to the source of the switching transistor P; and the source of the switching transistor S3 is connected to the ground.

[0013] Furthermore, the output terminal A1 is connected to the gate of the switching transistor S1 to control the conduction and shutoff of the switching transistor S1; the output terminal A2 is connected to the gate of the switching transistor P to control the conduction and shutoff of the switching transistor P; the output terminal A3 is connected to the gate of the field effect transistor DUT to be tested to control the conduction and shutoff of the field effect transistor DUT to be tested; the output terminal A4 is connected to the gate of the switching transistor S3 to control the conduction and shutoff of the switching transistor S3; the output terminal A5 is connected to the gate of the switching transistor S2 to control the conduction and shutoff of the switching transistor S2.

[0014] Furthermore, one end of the clamp circuit is connected to the drain of the field effect transistor DUT to be tested, and the other end of the clamp circuit is connected to the source of the switching transistor S2; when the field effect transistor DUT to be tested is in the on state, the clamp circuit samples and obtains the on-state voltage drop V1 between the drain of the field effect transistor DUT to be tested and the switching transistor S2; the capacitor Cm connected in series with the source of the field effect transistor DUT to be tested samples and obtains the source voltage V S The drain-source voltage V2 of the field effect transistor DUT to be tested is given by the formula V2=V1-V S Calculated; channel current Im is obtained according to the formula Im=Cm*dV S / dt is calculated; where dt is the time differential, dV S is the voltage V S Differential, dV S / dt is the source voltage V S The derivative of the time t, Cm is the capacitance value; the dynamic threshold voltage is obtained according to the volt-ampere characteristic curve of the field effect transistor DUT to be tested; the horizontal axis of the volt-ampere characteristic curve is V S , the vertical axis coordinate is Im.

[0015] Furthermore, the data acquisition module includes an oscilloscope, a Rogowski coil and a processing and display component; the measuring point of the Rogowski coil is connected to the source of the field effect transistor DUT to be tested, and the source-drain current I1 when the field effect transistor DUT to be tested is sampled and obtained; the dynamic on-resistance Ron of the field effect transistor DUT to be tested is calculated according to the formula Ron = V2 / I1; the oscilloscope is used to display the detection current, on-state voltage drop and source potential of the field effect transistor DUT to be tested; the processing and display component is used to calculate the on-resistance and threshold voltage based on the detection current and on-state voltage drop, and display the on-resistance and threshold voltage.

[0016] A method for characterizing the dynamic characteristics of a power switching device is implemented based on a device for characterizing the dynamic characteristics of a power switching device. The on-resistance and threshold voltage of a field effect transistor (DUT) under test are obtained and characterized by the following steps:

[0017] Step 1: The signal excitation and regulation system generates a driving signal and sends the driving signal to the stress control circuit through output terminals A1, A2, A3, A4, and A5;

[0018] Step 2: The stress control circuit applies two short-circuit electrical stresses to the field-effect transistor (DUT) under test based on the received drive signal. The stress control circuit has a built-in multi-layer safety protection mechanism, which includes: a transient voltage suppressor (TVS) to clamp the drain voltage to prevent breakdown; real-time current monitoring using a Rogowski coil, triggering a rapid shutdown when the current exceeds the limit; and an infrared sensor to detect device temperature, initiating forced cooling when the temperature exceeds the limit.

[0019] Step 3: After the two short-circuit electrical stresses are applied, the stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that it is in the dynamic characteristic recovery stage;

[0020] Step 4: Measure the detection current flowing through the field effect transistor DUT under test through the Rogowski coil, and collect the on-state voltage drop between the source and drain of the field effect transistor DUT under test. Use the processing and display component to calculate the on-state resistance based on the detection current and the on-state voltage drop, and display the on-state resistance; and calculate the gate-source voltage and source-drain current of the field effect transistor DUT under test based on the voltage drop of the series capacitor Cm at the source of the field effect transistor DUT under test to represent the threshold voltage.

[0021] Furthermore, the stress control circuit applies two short-circuit electrical stresses to the field effect transistor DUT according to the received drive signal, including:

[0022] By controlling the on and off of the switching transistors S1, S2, S3, and P, the electrical stress of the field effect transistor DUT to be tested is regulated, so that the field effect transistor DUT is subjected to hard switch short circuit stress and load short circuit stress; specifically, the process includes:

[0023] Applying hard-switching short-circuit stress to the field-effect transistor DUT is as follows: applying a constant gate stress to the field-effect transistor DUT, turning on the switching transistor S1 and the switching transistor P to prepare for applying the short-circuit stress; then turning on the switching transistor S2, and then turning on the field-effect transistor DUT to apply the short-circuit stress; then turning off the switching transistor S2, and the field-effect transistor DUT to be tested is also turned off, and then turning off the switching transistor P and the switching transistor S1, and the application of the hard-switching short-circuit stress is completed;

[0024] Applying a load short-circuit stress to the field effect transistor DUT under test is specifically as follows: applying a constant gate stress to the field effect transistor DUT under test, first turning on the switching transistor P, then turning on the switching transistor S2, thereby turning on the field effect transistor DUT under test, keeping the switching transistor S1 and the switching transistor S3 off, and the field effect transistor DUT under test operating normally; then, when the field effect transistor DUT under test is operating normally, turning on the switching transistor S1 to apply the load short-circuit stress to the field effect transistor DUT under test; then turning off the switching transistor S2 to turn off the field effect transistor DUT under test, ending the application of the load short-circuit stress, and then turning off the switching transistor S1 and the switching transistor P;

[0025] Furthermore, after the two short-circuit electrical stresses are applied, the stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that the DUT is in a dynamic characteristic recovery stage, including:

[0026] During the dynamic characteristic recovery phase, the on-resistance of the field effect transistor DUT under test is measured without applying additional electrical stress. Specifically, the switching transistor S1 is kept off, and the switching transistor P is kept off first. The switching transistor S2 and the field effect transistor DUT under test are turned on, and the drain voltage of the field effect transistor DUT under test is zero. Then, the switching transistor P is turned on to soft-turn on the field effect transistor DUT under test. Next, the switching transistor P is turned off to reduce the current of the field effect transistor DUT under test to zero. Thereafter, the switching transistor S2 and the field effect transistor DUT under test are turned off again to soft-turn off the field effect transistor DUT under test. The second pulse is the same as the first.

[0027] During the dynamic characteristic recovery phase, the threshold voltage of the field effect transistor DUT to be tested is measured without applying additional electrical stress. Specifically, a constant gate voltage is first applied to the field effect transistor DUT to be tested, and the switching transistor S1 and the switching transistor S2 are kept turned off; then the switching transistor P is turned on, the capacitor Cm is charged, the gate-source voltage of the field effect transistor DUT to be tested gradually decreases, and the field effect transistor DUT to be tested is turned off; then the switching transistor P is turned off, and the switching transistor P bears the high voltage; then the switching transistor S3 is turned on, the drain charge of the field effect transistor DUT to be tested is discharged, the charge of the capacitor Cm is released, and the field effect transistor DUT to be tested is turned on.

[0028] Furthermore, the method further includes: simulating the performance degradation of the field effect transistor DUT under the composite working condition by sequentially superimposing the hard switch short circuit stress and the off-state drain voltage stress, wherein the specific steps are as follows:

[0029] Apply hard switch short circuit stress; specifically: control the switch transistor S1 to turn on, short-circuit the load resistor RL and the inductor L; turn on the switch transistor P, so that the field effect transistor DUT under test is subjected to the high voltage V BUS Turn on the switching transistor S2 and the field-effect transistor under test (DUT) to trigger a hard switch short circuit event, which lasts for t1. Record the drain-source current I during the short circuit. S_DUT Peak and recovered drain-source voltage V DS_DUT ;

[0030] Superimpose the off-state drain voltage stress; specifically: keep the switch transistor P on, turn off the switch transistor S2 and the field effect transistor under test DUT; by adjusting the high voltage power supply V BUS The voltage amplitude is , and the off-state drain voltage stress is applied for a duration of t2;

[0031] Based on the calculated change in on-resistance of the field effect transistor DUT, a synergy factor K is defined and a synergy factor threshold is set; the synergy factor is used to quantify the accelerating effect of hard-switching short-circuit stress and off-state drain voltage stress on the degradation of the field effect transistor DUT; wherein,

[0032]

[0033] In the above formula, K represents the synergistic factor, ΔR on-复合 Represents the change in the on-resistance Ron of the field effect transistor DUT under the conditions of applying hard switching short-circuit stress and off-state drain voltage stress; ΔR on-单一 It indicates the change in the on-resistance Ron of the field effect transistor DUT under the single stress condition of hard switching short circuit stress or off-state drain voltage stress;

[0034] Based on the Arrhenius equation and combined with temperature data, a thermal-electric coupling degradation model is established, specifically:

[0035]

[0036] ΔR on represents the predicted degradation of the field effect transistor under test (DUT); A represents the material constant, which characterizes the inherent sensitivity of the material to electrothermal stress; E a represents the activation energy, which indicates the minimum energy threshold required to initiate the degradation process; k β is the Boltzmann constant, T is the junction temperature of the field effect transistor DUT, and n is the voltage stress index; V DS Represents the voltage applied between the drain and source of the field effect transistor DUT under test; t s Represents the duration of voltage stress application; if the synergy factor is greater than the synergy factor threshold, it is determined to be a strong synergistic effect, and the stress application period is automatically shortened and the sampling frequency is increased; if ΔR on If the voltage exceeds the set threshold, the protection mechanism is triggered to turn off the switching transistor S1, the switching transistor S2, the switching transistor S3, the switching transistor P and the field effect transistor DUT under test.

[0037] Compared with the existing technology, the present invention has the following advantages and beneficial effects: it can achieve comprehensive and accurate characterization of the dynamic characteristics of power switching devices, especially field-effect transistors, under a variety of complex stress conditions; it not only improves the accuracy and efficiency of the test, but also greatly enhances the safety and reliability of the test process; in addition, by introducing a multi-layer safety protection mechanism and a composite stress testing strategy, it effectively simulates the performance degradation of the device under actual working conditions, providing strong technical support for the research and development, production and maintenance of power switching devices.

[0038] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0039] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0041] Figure 1 The figure is a schematic diagram of the structure of a device for characterizing the dynamic characteristics of a power switching device;

[0042] Figure 2 This is a schematic diagram of the internal connections of the device for characterizing the dynamic characteristics of a power switching device;

[0043] Figure 3 A schematic diagram of the steps of a method for characterizing the dynamic characteristics of a power switching device;

[0044] Figure 4 Schematic diagram of control waveform for applying hard switch short circuit stress to the field effect transistor DUT;

[0045] Figure 5 This is a schematic diagram of a control waveform for applying a load short-circuit stress to the field effect transistor DUT;

[0046] Figure 6 This is a schematic diagram of the on-resistance measurement control waveform without applying additional electrical stress to the field effect transistor DUT;

[0047] Figure 7 Schematic diagram of the threshold voltage measurement control waveform without applying additional electrical stress to the field effect transistor DUT. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0049] The present invention provides a device for characterizing the dynamic characteristics of a power switching device, such as Figure 1 As shown, including:

[0050] Dynamic feature characterization circuit module and data acquisition module; the dynamic feature characterization circuit module is connected to the data acquisition module;

[0051] The dynamic characteristic characterization circuit module includes a signal excitation and regulation system, a stress control circuit, and a measurement implementation circuit; the signal excitation and regulation system is connected to the stress control circuit, and the stress control circuit is connected to the measurement implementation circuit; the signal excitation and regulation system is used to generate a drive signal for controlling the stress control circuit; the stress control circuit is used to apply two short-circuit electrical stresses to the field effect transistor under test according to the drive signal; and the measurement implementation circuit is used to measure the on-state voltage drop between the source and drain of the field effect transistor under test;

[0052] The data acquisition module is used to sample and obtain the detection current flowing between the source and drain of the field effect transistor to be tested and the gate-source voltage of the field effect transistor to be tested, and calculate based on the detection current and gate-source voltage to obtain the on-resistance and threshold voltage and characterize them.

[0053] The working principle of this technical solution is as follows: the signal excitation and regulation system generates drive signals with specific waveforms and frequencies, which are transmitted to the stress control circuit. The stress control circuit accurately adjusts and applies a variety of preset electrical stress conditions to the field-effect transistor to be tested based on the received drive signals. These electrical stress conditions can include different voltage amplitudes, durations or frequencies to comprehensively evaluate the dynamic performance of the field-effect transistor under different stress states; the measurement implementation circuit is responsible for accurately measuring the on-state voltage drop between the source and drain of the field-effect transistor during the stress application period; at the same time, the data acquisition module synchronously collects the detection current flowing through the source and drain of the field-effect transistor and the gate-source voltage data. By processing and analyzing these data, key parameters such as on-resistance and threshold voltage can be calculated; finally, the device achieves a comprehensive characterization of the dynamic characteristics of the field-effect transistor by comparing the parameter values ​​obtained under different stress conditions.

[0054] The beneficial effect of the above technical solution is that the solution provided by this embodiment can accurately simulate various electrical stress conditions that field effect transistors may encounter in actual working environments, thereby comprehensively and accurately evaluating their dynamic performance.

[0055] In one embodiment, the signal excitation and regulation system is a field programmable gate array chip; the signal excitation and regulation system includes an output terminal A1, an output terminal A2, an output terminal A3, an output terminal A4 and an output terminal A5.

[0056] The working principle of this technical solution is as follows: the field programmable gate array chip can generate driving signals with various waveforms and frequencies through programming control. The output terminals A1, A2, A3, A4 and A5 are respectively connected to different input terminals of the stress control circuit. These output terminals output signals with specific waveforms and frequencies according to preset programs. The signal excitation and regulation system achieves comprehensive drive of the stress control circuit by precisely controlling the signals at these output terminals. After receiving these signals, the stress control circuit applies corresponding electrical stress to the field effect transistor according to the waveform, frequency and preset electrical stress conditions of the signal to simulate various stress states that may be encountered in the actual working environment.

[0057] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, it is possible to achieve precise control of field-effect transistors under different stress states, thereby more accurately evaluating their dynamic performance. The high flexibility and programmability of the field programmable gate array chip enable the device to adapt to a variety of testing requirements. The waveform, frequency, and amplitude of the output signal can be changed simply by modifying the program, thereby adjusting the electrical stress conditions applied to the field-effect transistor. This flexibility greatly improves test efficiency and accuracy, and provides strong support for the research and development and quality control of power switching devices.

[0058] In one embodiment, the stress control circuit includes a high voltage power supply V BUS , input capacitor C BUS , load resistance RL, capacitor Cm, inductor L, freewheeling diode D1, switching transistor S1, switching transistor S2, switching transistor S3, switching transistor P and field effect transistor under test DUT; input capacitor C BUS The positive terminal of the high voltage power supply V BUS The positive terminal of the input capacitor C BUS The negative pole of the high voltage power supply V BUS The negative pole of the load resistor RL is connected to the high voltage power supply V BUS The positive pole of the load resistor RL is connected to one end of the load inductor L; the cathode of the freewheeling diode D1 is connected to the high voltage power supply V BUS The positive electrode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, and the source of the switching transistor S1 is connected to the drain of the switching transistor P; the source of the switching transistor P is connected to the drain of the field effect transistor DUT to be tested; the switching transistor S2 is connected to the source of the field effect transistor DUT to be tested; the source of the switching transistor S2 is connected to the ground; the drain of the switching transistor S3 is connected to the source of the switching transistor P; and the source of the switching transistor S3 is connected to the ground.

[0059] The working principle of this technical solution is as follows: When the high voltage power supply V BUS To the input capacitor C BUS When charging, the circuit enters the pre-charging stage. At this time, the switching transistors S1, S2 and S3 are all in the off state, and the switching transistor P is in the on state, so that a conductive path is formed between the drain of the field effect transistor DUT and the ground. BUS For input capacitance C BUS The charging of the input capacitor C BUS The voltage on the load increases gradually until it reaches the preset test voltage value; then, it enters the test phase. At this time, the control switch transistor S1 is turned on and the switch transistor P is turned off, so that the load inductor L and the input capacitor C BUS, the field effect transistor DUT to be tested and the freewheeling diode D1 form a discharge loop. During this process, by monitoring the changes in parameters such as the drain current and drain-source voltage of the field effect transistor DUT to be tested, its dynamic characteristics, such as turn-on time, turn-off time, reverse recovery time, etc., can be characterized; at the same time, the switching transistors S2 and S3 play an auxiliary role in the test process. For example, when it is necessary to measure the reverse recovery characteristics of the field effect transistor DUT to be tested, the source current of the field effect transistor DUT to be tested can be quickly changed by controlling the conduction and shutdown of S2, thereby triggering its reverse recovery process, and the switching transistor S3 can work with the switching transistor S1 after the test to safely isolate the field effect transistor DUT to be tested from the circuit for the next test.

[0060] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, through the designed stress control circuit, it is possible to achieve comprehensive and accurate characterization of the dynamic characteristics of the power switching device, providing strong technical support for the research and development, production and application of the device.

[0061] In one embodiment, the output terminal A1 is connected to the gate of the switching transistor S1 to control the on and off of the switching transistor S1; the output terminal A2 is connected to the gate of the switching transistor P to control the on and off of the switching transistor P; the output terminal A3 is connected to the gate of the field effect transistor DUT to be tested to control the on and off of the field effect transistor DUT to be tested; the output terminal A4 is connected to the gate of the switching transistor S3 to control the on and off of the switching transistor S3; the output terminal A5 is connected to the gate of the switching transistor S2 to control the on and off of the switching transistor S2.

[0062] The working principle of this technical solution is as follows: when the test starts, the control unit outputs a control signal to each output terminal A1 to A5. Specifically, the output terminal A1 sends a conduction signal to the gate of the switching transistor S1, turning on the switching transistor S1. At the same time, the output terminal A2 sends a shutdown signal to the gate of the switching transistor P, turning off the switching transistor P. At this time, the load inductor L and the input capacitor C BUS , the field effect transistor DUT and the freewheeling diode D1 form a discharge circuit, and the dynamic characteristics test process begins;

[0063] During the test, output terminal A3 adjusts and monitors parameters such as the DUT's drain current and drain-source voltage by controlling the voltage at the gate of the field-effect transistor (DUT) under test. At the same time, output terminals A4 and A5 work together as needed. For example, when measuring the reverse recovery characteristics, output terminal A4 sends a control signal to keep the switching transistor S3 in the off state, while output terminal A5 sends a rapidly changing control signal to the gate of the switching transistor S2 to achieve a rapid change in the source current of the field-effect transistor (DUT) under test, triggering the reverse recovery process.

[0064] The beneficial effects of the above technical solution are: by adopting the solution provided in this embodiment, by controlling the conduction and shutdown of each switching transistor, not only a comprehensive and accurate characterization of the dynamic characteristics of the power switching device is achieved, but also the safety and efficiency of the test process are guaranteed, providing strong technical support for the research and development, production and application of the device.

[0065] In one embodiment, one end of the clamp circuit is connected to the drain of the field effect transistor DUT under test, and the other end of the clamp circuit is connected to the source of the switching transistor S2; when the field effect transistor DUT under test is in the on state, the clamp circuit samples and obtains the on-state voltage drop V1 between the drain of the field effect transistor DUT under test and the switching transistor S2; the capacitor Cm connected in series with the source of the field effect transistor DUT under test samples and obtains the source voltage V S The drain-source voltage V2 of the field effect transistor DUT to be tested is given by the formula V2=V1-V S Calculated; channel current Im is obtained according to the formula Im=Cm*dV S / dt is calculated; where dt is the time differential, dV S is the voltage V S Differential, dV S / dt is the source voltage V S The derivative of the time t, Cm is the capacitance value; the dynamic threshold voltage is obtained according to the volt-ampere characteristic curve of the field effect transistor DUT to be tested; the horizontal axis of the volt-ampere characteristic curve is V S , the vertical axis coordinate is Im.

[0066] The working principle of this technical solution is as follows: the clamping circuit accurately controls the voltage and current to ensure that when the field effect transistor DUT is turned on, the on-state voltage drop V1 between the drain and the switching transistor S2 can be accurately sampled. At the same time, the source voltage V S Sampling is performed. This step is crucial for the subsequent calculation of the drain-source voltage V2. The calculation formula for the drain-source voltage V2 is V2 = V1-V S , which directly reflects the voltage characteristics of the field effect transistor DUT under working state; further, the acquisition of the channel current Im depends on the source voltage V S Accurate measurement of changes over time, through the formula Im=Cm*dV S / dt, the channel current can be calculated in real time;

[0067] In addition, the dynamic threshold voltage is obtained by analyzing the volt-ampere characteristic curve of the field effect transistor DUT to be tested, which intuitively shows the V SThe relationship between Im and the dynamic threshold voltage can be determined by reading the voltage and current values ​​under specific conditions.

[0068] The beneficial effect of the above technical solution is: by adopting the solution provided by this embodiment, a comprehensive characterization of the dynamic characteristics of the power switching device is achieved through precise measurement and calculation, providing strong support for subsequent circuit design and optimization.

[0069] In one embodiment, the data acquisition module includes an oscilloscope, a Rogowski coil, and a processing and display component; the measurement point of the Rogowski coil is connected to the source of the field effect transistor DUT to be tested, and the source-drain current I1 when the field effect transistor DUT to be tested is sampled and obtained; the dynamic on-resistance Ron of the field effect transistor DUT to be tested is calculated according to the formula Ron=V2 / I1; the oscilloscope is used to display the detection current, the on-state voltage drop, and the source potential of the field effect transistor DUT to be tested; the processing and display component is used to calculate the on-resistance and threshold voltage based on the detection current and the on-state voltage drop, and display the on-resistance and threshold voltage.

[0070] The working principle of this technical solution is as follows: the oscilloscope is responsible for capturing and displaying various electrical signal changes of the field-effect transistor (DUT) under test during operation, such as the real-time waveforms of the detection current and source potential; the Rogowski coil closely monitors the changes in the source-drain current I1. Its high precision and fast response capability ensure the accuracy of current measurement, which is crucial for the subsequent calculation of the dynamic on-resistance Ron. The processing and display component, as the core of data processing, receives data from the oscilloscope and Rogowski coil, uses built-in algorithms to conduct in-depth analysis of the detection current and on-state voltage drop, calculates key parameters such as the on-resistance Ron and threshold voltage, and clearly displays the results on the user interface.

[0071] The beneficial effects of the above technical solution are: adopting the solution provided by this embodiment not only improves the test efficiency, but also significantly enhances the accuracy and reliability of the test results, providing solid data support for the research and development and performance optimization of power switching devices.

[0072] A method for characterizing the dynamic characteristics of a power switching device is implemented based on a device for characterizing the dynamic characteristics of a power switching device. The on-resistance and threshold voltage of a field effect transistor (DUT) under test are obtained and characterized by the following steps:

[0073] Step 1: The signal excitation and regulation system generates a driving signal and sends the driving signal to the stress control circuit through output terminals A1, A2, A3, A4, and A5;

[0074] Step 2: The stress control circuit applies two short-circuit electrical stresses to the field-effect transistor (DUT) under test based on the received drive signal. The stress control circuit has a built-in multi-layer safety protection mechanism, which includes: a transient voltage suppressor (TVS) to clamp the drain voltage to prevent breakdown; real-time current monitoring using a Rogowski coil, triggering a rapid shutdown when the current exceeds the limit; and an infrared sensor to detect device temperature, initiating forced cooling when the temperature exceeds the limit.

[0075] Step 3: After the two short-circuit electrical stresses are applied, the stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that it is in the dynamic characteristic recovery stage;

[0076] Step 4: Measure the detection current flowing through the field effect transistor DUT under test through the Rogowski coil, and collect the on-state voltage drop between the source and drain of the field effect transistor DUT under test. Use the processing and display component to calculate the on-state resistance based on the detection current and the on-state voltage drop, and display the on-state resistance; and calculate the gate-source voltage and source-drain current of the field effect transistor DUT under test based on the voltage drop of the series capacitor Cm at the source of the field effect transistor DUT under test to represent the threshold voltage.

[0077] The working principle of this technical solution is as follows: First, the signal excitation and conditioning system generates a series of precisely controlled drive signals. These signals are sent to the stress control circuit through five output terminals A1 to A5. After receiving these drive signals, the stress control circuit applies specific electrical stress to the field-effect transistor (DUT) under test according to preset parameters. This process ensures that the field-effect transistor (DUT) under test can be fully tested under various stress conditions to evaluate its dynamic characteristics.

[0078] During the electrical stress application process, the multi-layer safety protection mechanism within the stress control circuit plays a crucial role. The transient voltage suppressor effectively limits the drain voltage, preventing device breakdown and damage. Simultaneously, the Rogowski coil monitors the current in real time. Once the current exceeds the preset safety limit, the shutdown mechanism is quickly triggered to protect the field-effect transistor (DUT) under test from damage. In addition, the infrared sensor continuously monitors the device temperature. Once the temperature exceeds the safe range, the forced cooling system is activated to ensure that the field-effect transistor (DUT) under test operates within a safe operating temperature range.

[0079] After the two short-circuit electrical stresses are applied, the stress control circuit again accurately controls the field effect transistor DUT to enter the dynamic characteristics recovery stage based on the received drive signal. In the dynamic characteristics recovery stage, the on-resistance and threshold voltage of the field effect transistor DUT are measured without additional electrical stress. This stage is crucial for accurately evaluating the dynamic characteristics of the field effect transistor DUT because it allows the field effect transistor DUT to recover to a stable state without being affected by electrical stress.

[0080] Finally, the detection current flowing through the field-effect transistor DUT under test is accurately measured using a Rogowski coil, and the on-state voltage drop between the source and drain of the field-effect transistor DUT under test is collected using a high-precision instrument. These data are transmitted to the processing and display component, which accurately calculates the detection current and on-state voltage drop to obtain the on-state resistance of the field-effect transistor DUT under test and displays it in real time on the display screen. At the same time, by measuring and calculating the voltage drop of the series capacitance Cm at the source of the field-effect transistor DUT under test, the gate-source voltage and source-drain current of the field-effect transistor DUT under test can be obtained, thereby characterizing its threshold voltage.

[0081] The beneficial effect of the above technical solution is that: by adopting the solution provided in this embodiment, the dynamic characteristics of the field effect transistor DUT under different stress conditions can be comprehensively and accurately evaluated, including but not limited to its key parameters such as on-resistance and threshold voltage.

[0082] In one embodiment, the stress control circuit applies two short-circuit electrical stresses to the field effect transistor under test (DUT) according to the received driving signal, including:

[0083] By controlling the on and off of the switching transistors S1, S2, S3, and P, the electrical stress of the field effect transistor DUT to be tested is regulated, so that the field effect transistor DUT is subjected to hard switch short circuit stress and load short circuit stress; specifically, the process includes:

[0084] Apply hard switching short circuit stress to the field effect transistor DUT. Figure 4 The figure shows the control waveform diagram of applying hard switch short circuit stress to the field effect transistor DUT under test. Specifically, a constant gate stress is applied to the field effect transistor DUT under test. Before time t0, the switch transistor S1 is turned on and the high voltage V BUS The switching transistor P bears the high voltage, and the field effect transistor DUT under test does not bear the high voltage. The source-drain voltage V DS_DUT In low voltage state; at t0, the switch transistor P is turned on, and the high voltage V BUSThe source-drain voltage V DS_DUT In a high voltage state, ready to apply short-circuit stress; at time t1, first turn on the switch transistor S2, then turn on the field effect transistor DUT to apply short-circuit stress, a hard switch short circuit occurs, and the source-drain voltage V DS_DUT First it drops and then returns to the high voltage state. The source-drain current I DS_DUT It rises rapidly and then falls slowly; at time t2, the switch transistor S2 is turned off, and the field effect transistor DUT to be tested is also turned off. The source-drain voltage V DS_DUT In the high voltage state, the source-drain current I DS_DUT Rapidly decreases; at time t3, the switching transistor P and the switching transistor S1 are turned off, and the application of the hard switch short-circuit stress ends;

[0085] Apply load short-circuit stress to the field effect transistor DUT. Figure 5 The figure shows the control waveform diagram of applying load short-circuit stress to the field effect transistor DUT under test; specifically: a constant gate stress is applied to the field effect transistor DUT under test. At time t0, the switching transistor S1 is in the off state, the switching transistor P is turned on, and the high voltage V BUS The source-drain voltage V DS_DUT At t1, the switch transistor S2 and the field effect transistor DUT to be tested are turned on successively, the circuit works normally, and the source-drain voltage V DS_DUT In the low voltage state, the source-drain current I DS_DUT Slowly rises; at time t2, the switch transistor S1 is turned on, a load short circuit occurs, and a load short circuit stress is applied to the field effect transistor DUT under test. The source-drain voltage V DS_DUT Rapidly increases, the source-drain current I DS_DUT It rises quickly first, then slowly drops to a non-zero constant value; at time t3, the switch transistor S2 and the field effect transistor under test DUT are turned off, and the high voltage V BUS The source-drain voltage V DS_DUT In the high voltage state, the source-drain current I DS_DUT The voltage drops rapidly, and the load short-circuit stress application ends; at time t4, the switching transistor P is turned off, and the switching transistor P bears the high voltage; at time t5, the switching transistor S1 is turned off.

[0086] The working principle of this technical solution is as follows: The stress control circuit can apply hard switching short-circuit stress and load short-circuit stress to the field effect transistor (DUT) under test by precisely controlling the switching states of the switching transistors S1, S2, S3, and P, thereby comprehensively evaluating the dynamic characteristics of the field effect transistor (DUT) under different stress conditions. This control strategy ensures that the field effect transistor (DUT) under test can experience the complete stress spectrum from normal operation to abnormal conditions (short circuit, hard switching) during the test process.

[0087] During the application of hard-switching short-circuit stress, the short-circuit conditions that may be encountered in actual circuits are simulated by rapidly switching the switching transistor, thereby evaluating the tolerance of the field-effect transistor DUT under extreme conditions. The application of load short-circuit stress simulates the situation of sudden load short circuit, further verifying the short-circuit protection mechanism of the field-effect transistor DUT under test.

[0088] The beneficial effect of the above technical solution is: by adopting the solution provided in this embodiment, by simulating the stress conditions in actual work, the device can comprehensively and accurately evaluate the dynamic characteristics of the field-effect transistor DUT to be tested, providing strong technical support for the research and development and production of power switching devices.

[0089] In one embodiment, after the two short-circuit electrical stresses are applied, the stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that the DUT is in a dynamic characteristic recovery stage, including:

[0090] During the dynamic characteristics recovery phase, the on-resistance of the field effect transistor DUT is measured without applying additional electrical stress. Figure 6 The figure shows a schematic diagram of the on-resistance measurement control waveform of the field effect transistor DUT under test without additional electrical stress. Specifically, the switching transistor S1 is kept off. At time t0, the switching transistor P is kept off, the switching transistor S2 and the field effect transistor DUT under test are turned on, and the drain voltage of the field effect transistor DUT under test is zero. At time t1, the switching transistor P is turned on, and the drain-source voltage of the field effect transistor DUT under test is zero. DS_DUT At t2, the switch transistor P is turned off to make the current drop to zero; at t3, the switch transistor S2 and the field effect transistor DUT are turned off to make the field effect transistor DUT soft-turn off, and the high voltage V BUS Applied to both ends of the drain and source of the switching transistor P, the drain of the field effect transistor DUT under test does not bear high voltage;

[0091] During the dynamic characteristics recovery phase, the threshold voltage of the field effect transistor DUT is measured without applying additional electrical stress. Figure 7The figure shows a threshold voltage measurement control waveform diagram of the field effect transistor DUT under test without applying additional electrical stress. Specifically, before time t0, a constant gate voltage is applied to the field effect transistor under test, and the switching transistor S1 and the switching transistor S2 are kept off. At time t0, the switching transistor P is turned on, the capacitor Cm is charged, and the gate-source voltage of the field effect transistor DUT under test gradually decreases. The field effect transistor DUT under test is turned off, and the source-drain voltage V DS_DUT It gradually rises; at time t1, the switching transistor P is turned off, and the switching transistor P bears the high voltage; at time t2, the switching transistor S3 is turned on, the drain voltage stress is discharged, the charge of the capacitor Cm is released, and the field effect transistor DUT to be tested is turned on.

[0092] The working principle of this technical solution is as follows: In order to explore the mechanism of controlling the field effect transistor DUT under test to be free from the influence of electrical stress and to make it in the dynamic characteristics recovery stage, the on-resistance and threshold voltage of the field effect transistor DUT under test are measured without additional electrical stress during the dynamic characteristics recovery stage;

[0093] During the dynamic characteristics recovery phase, the on-resistance of the field effect transistor DUT under test is measured without applying additional electrical stress. Specifically, the switching transistor S1 is kept off, and the switching transistor P is kept off first. The switching transistor S2 and the field effect transistor DUT under test are turned on, and the drain voltage of the field effect transistor DUT under test is zero. Then, the switching transistor P is turned on to soft-turn on the field effect transistor DUT under test. Then, the switching transistor P is turned off to reduce the current of the field effect transistor DUT under test to zero. Thereafter, the switching transistor S2 and the field effect transistor DUT under test are turned off to soft-turn off the field effect transistor DUT under test.

[0094] During the dynamic characteristic recovery phase, the threshold voltage of the field effect transistor DUT to be tested is measured without applying additional electrical stress. Specifically, a constant gate voltage is first applied to the field effect transistor to be tested, and the switching transistor S1 and the switching transistor S2 are kept turned off; then the switching transistor P is turned on, the capacitor Cm is charged, the gate-source voltage of the field effect transistor DUT to be tested gradually decreases, and the field effect transistor DUT to be tested is turned off; then the switching transistor P is turned off, and the switching transistor P bears the high voltage; then the switching transistor S3 is turned on, the drain charge of the field effect transistor DUT to be tested is discharged, the charge of the capacitor Cm is released, and the field effect transistor DUT to be tested is turned on.

[0095] The beneficial effects of the above technical solution are: using the solution provided in this embodiment, the control process in the recovery phase is accurate and efficient, and the on-resistance and threshold voltage of the field effect transistor DUT to be tested are measured without applying additional electrical stress during the dynamic characteristics recovery phase.

[0096] In one embodiment, the method further includes: simulating the performance degradation of the field effect transistor DUT under the composite working condition by sequentially superimposing the hard switch short circuit stress and the off-state drain voltage stress, wherein the specific steps are as follows:

[0097] Apply hard switch short circuit stress; specifically: control the switch transistor S1 to turn on, short-circuit the load resistor RL and the inductor L; turn on the switch transistor P, so that the field effect transistor DUT under test is subjected to the high voltage V BUS Turn on the switching transistor S2 and the field-effect transistor under test (DUT) to trigger a hard switch short circuit event, which lasts for t1. Record the drain-source current I during the short circuit. S_DUT Peak and recovered drain-source voltage V DS_DUT ;

[0098] Superimpose the off-state drain voltage stress; specifically: keep the switch transistor P on, turn off the switch transistor S2 and the field effect transistor under test DUT; by adjusting the high voltage power supply V BUS The voltage amplitude is , and the off-state drain voltage stress is applied for a duration of t2;

[0099] Based on the calculated change in on-resistance of the field effect transistor DUT, a synergy factor K is defined and a synergy factor threshold is set; the synergy factor is used to quantify the accelerating effect of hard-switching short-circuit stress and off-state drain voltage stress on the degradation of the field effect transistor DUT; wherein,

[0100]

[0101] In the above formula, K represents the synergistic factor, ΔR on-复合 Represents the change in the on-resistance Ron of the field effect transistor DUT under the conditions of applying hard switching short-circuit stress and off-state drain voltage stress; ΔR on-单一 It indicates the change in the on-resistance Ron of the field effect transistor DUT under the single stress condition of hard switching short circuit stress or off-state drain voltage stress;

[0102] Based on the Arrhenius equation and combined with temperature data, a thermal-electric coupling degradation model is established, specifically:

[0103]

[0104] ΔR on represents the predicted degradation of the field effect transistor under test (DUT); A represents the material constant, which characterizes the inherent sensitivity of the material to electrothermal stress; E a represents the activation energy, which indicates the minimum energy threshold required to initiate the degradation process; k β is the Boltzmann constant, T is the junction temperature of the field effect transistor DUT, and n is the voltage stress index; V DSRepresents the voltage applied between the drain and source of the field effect transistor DUT under test; t s Represents the duration of voltage stress application; if the synergy factor is greater than the synergy factor threshold, it is determined to be a strong synergistic effect, and the stress application period is automatically shortened and the sampling frequency is increased; if ΔR on If the voltage exceeds the set threshold, the protection mechanism is triggered to turn off the switching transistor S1, the switching transistor S2, the switching transistor S3, the switching transistor P and the field effect transistor DUT under test.

[0105] The working principle of this technical solution is as follows: By precisely controlling the on and off state of the switching transistor, this technical solution simulates the performance degradation of the field-effect transistor (DUT) under the combined working conditions of applying hard-switching short-circuit stress and superimposing off-state drain voltage stress. During the hard-switching short-circuit stress stage, the on-off states of the switching transistors S1, P, and S2 are controlled to simulate a hard-switching short-circuit event. The peak value of the drain-source current IS_DUT during the short-circuit period and the drain-source voltage VDS_DUT after recovery are recorded. These data provide key basis for subsequent analysis.

[0106] In the off-state drain voltage stress superposition stage, the off-state drain voltage stress is applied by keeping the switching transistor P on and turning off the switching transistor S2 and the field-effect transistor under test (DUT). At the same time, the voltage amplitude of the high-voltage power supply VBUS is adjusted. This step further simulates the degradation of the field-effect transistor under test (DUT) under the composite working condition.

[0107] By calculating the change in on-resistance of the field-effect transistor (DUT) under test, defining the synergy factor K, and setting the synergy factor threshold, the accelerated degradation effect of the combined hard-switching short-circuit stress and the off-state drain voltage stress can be quantified. When the synergy factor is greater than the synergy factor threshold, it is determined to be a strong synergy effect. In this case, the stress application period is automatically shortened and the sampling frequency is increased to improve the accuracy and efficiency of the test.

[0108] Finally, based on the Arrhenius equation and combined with temperature data, a thermal-electrical coupling degradation model was established to predict the degradation amount of the field-effect transistor (DUT) under test. When the predicted degradation amount exceeds the set threshold, the protection mechanism is triggered to shut down all switching transistors and the field-effect transistor (DUT) under test, thereby preventing further damage to the device.

[0109] The beneficial effect of the above technical solution is as follows: by adopting the solution provided in this embodiment, by accurately simulating the performance degradation of the field-effect transistor DUT under the two stress composite conditions of hard switching short-circuit stress and off-state drain voltage stress, and combining the synergy factor and thermal-electric coupling degradation model, effective characterization of the dynamic characteristics of the power switching device is achieved, providing strong support for the reliability evaluation and optimized design of the device.

[0110] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A device for characterizing the dynamic characteristics of a power switching device, characterized in that: include: Dynamic feature characterization circuit module and data acquisition module; The dynamic feature characterization circuit module is connected to the data acquisition module; The dynamic characteristic characterization circuit module includes a signal excitation and regulation system, a stress control circuit, and a measurement implementation circuit; the signal excitation and regulation system is connected to the stress control circuit, and the stress control circuit is connected to the measurement implementation circuit; the signal excitation and regulation system is used to generate a drive signal for controlling the stress control circuit; the stress control circuit is used to apply two short-circuit electrical stresses to the field effect transistor under test according to the drive signal; and the measurement implementation circuit is used to measure the on-state voltage drop between the source and drain of the field effect transistor under test; The data acquisition module is used to sample and obtain the detection current flowing between the source and drain of the field effect transistor to be tested and the gate-source voltage of the field effect transistor to be tested, and calculate based on the detection current and gate-source voltage to obtain the on-resistance and threshold voltage and characterize them.

2. A power switching device dynamic characteristics characterization device according to claim 1, characterized in that: The signal excitation and regulation system is a field programmable gate array chip; the signal excitation and regulation system includes an output terminal A1, an output terminal A2, an output terminal A3, an output terminal A4 and an output terminal A5.

3. The device for characterizing dynamic characteristics of a power switching device according to claim 1, wherein: The stress control circuit includes a high voltage power supply V BUS , input capacitor C BUS , load resistance RL, capacitor Cm, inductor L, freewheeling diode D1, switching transistor S1, switching transistor S2, switching transistor S3, switching transistor P and field effect transistor under test DUT; input capacitor C BUS The positive terminal of the high voltage power supply V BUS The positive terminal of the input capacitor C BUS The negative pole of the high voltage power supply V BUS The negative pole of the load resistor RL is connected to the high voltage power supply V BUS The positive pole of the load resistor RL is connected to one end of the load inductor L; the cathode of the freewheeling diode D1 is connected to the high voltage power supply V BUS The positive electrode of the freewheeling diode D1 is connected to the other end of the load inductor L; the drain of the switching transistor S1 is connected to the other end of the load inductor L, the source of the switching transistor S1 is connected to the drain of the switching transistor P; the source of the switching transistor P is connected to the drain of the field effect transistor DUT to be tested; The switching transistor S2 is connected to the source of the field effect transistor DUT to be tested; The source of the switching transistor S2 is connected to the ground; the drain of the switching transistor S3 is connected to the source of the switching transistor P; and the source of the switching transistor S3 is connected to the ground.

4. A power switching device dynamic characteristics characterization device according to claim 3, characterized in that: The output terminal A1 is connected to the gate of the switching transistor S1 to control the on and off of the switching transistor S1; the output terminal A2 is connected to the gate of the switching transistor P to control the on and off of the switching transistor P; the output terminal A3 is connected to the gate of the field effect transistor DUT to be tested to control the on and off of the field effect transistor DUT to be tested; The output terminal A4 is connected to the gate of the switching transistor S3 to control the on and off of the switching transistor S3; the output terminal A5 is connected to the gate of the switching transistor S2 to control the on and off of the switching transistor S2.

5. The device for characterizing dynamic characteristics of a power switching device according to claim 3, wherein: One end of the clamp circuit is connected to the drain of the field effect transistor DUT under test, and the other end of the clamp circuit is connected to the source of the switching transistor S2. When the field effect transistor DUT under test is in the on state, the clamp circuit samples and obtains the on-state voltage drop V1 between the drain of the field effect transistor DUT under test and the switching transistor S2. The capacitor Cm connected in series with the source of the field effect transistor DUT under test samples and obtains the source voltage V S The drain-source voltage V2 of the field effect transistor DUT to be tested is given by the formula V2=V1-V S Calculated; channel current Im is obtained according to the formula Im=Cm*dV S / dt is calculated; where dt is the time differential, dV S is the voltage V S Differential, dV S / dt is the source voltage V S The derivative of the time t, Cm is the capacitance value; the dynamic threshold voltage is obtained according to the volt-ampere characteristic curve of the field effect transistor DUT to be tested; the horizontal axis of the volt-ampere characteristic curve is V S , the vertical axis coordinate is Im.

6. The device for characterizing dynamic characteristics of a power switching device according to claim 5, characterized in that: The data acquisition module includes an oscilloscope, a Rogowski coil and a processing and display component; the measurement point of the Rogowski coil is connected to the source of the field effect transistor DUT to be tested, and the source-drain current I1 when the field effect transistor DUT to be tested is sampled and obtained; the dynamic on-resistance Ron of the field effect transistor DUT to be tested is calculated according to the formula Ron = V2 / I1; the oscilloscope is used to display the detection current, on-state voltage drop and source potential of the field effect transistor DUT to be tested; the processing and display component is used to calculate the on-resistance and threshold voltage based on the detection current and on-state voltage drop, and display the on-resistance and threshold voltage.

7. A method for characterizing the dynamic characteristics of a power switching device, characterized in that: According to the power switching device dynamic characteristics characterization device according to any one of claims 1 to 6, the on-resistance and threshold voltage of the field effect transistor DUT to be tested are obtained and characterized by the following steps: Step 1: The signal excitation and regulation system generates a driving signal and sends the driving signal to the stress control circuit through output terminals A1, A2, A3, A4, and A5; Step 2: The stress control circuit applies two short-circuit electrical stresses to the field-effect transistor (DUT) under test based on the received drive signal. The stress control circuit has a built-in multi-layer safety protection mechanism, which includes: a transient voltage suppressor (TVS) to clamp the drain voltage to prevent breakdown; real-time current monitoring using a Rogowski coil, triggering a rapid shutdown when the current exceeds the limit; and an infrared sensor to detect device temperature, initiating forced cooling when the temperature exceeds the limit. Step 3: After the two short-circuit electrical stresses are applied, the stress control circuit controls the field effect transistor DUT to be free from the influence of the electrical stress according to the received driving signal, so that it is in the dynamic characteristic recovery stage; Step 4: Measure the detection current flowing through the field effect transistor DUT under test through the Rogowski coil, and collect the on-state voltage drop between the source and drain of the field effect transistor DUT under test. Use the processing and display component to calculate the on-state resistance based on the detection current and the on-state voltage drop, and display the on-state resistance; and calculate the gate-source voltage and source-drain current of the field effect transistor DUT under test based on the voltage drop of the series capacitor Cm at the source of the field effect transistor DUT under test to represent the threshold voltage.

8. A method for characterizing dynamic characteristics of a power switching device according to claim 7, characterized in that: The stress control circuit applies two short-circuit electrical stresses to the field-effect transistor under test (DUT) based on the received drive signal, including: By controlling the on and off of the switching transistors S1, S2, S3, and P, the electrical stress of the field effect transistor DUT is regulated, so that the field effect transistor DUT withstands hard switch short circuit stress and load short circuit stress; specifically, the following steps are included: Applying hard-switching short-circuit stress to the field-effect transistor DUT is as follows: applying a constant gate stress to the field-effect transistor DUT, turning on the switching transistor S1 and the switching transistor P to prepare for applying the short-circuit stress; then turning on the switching transistor S2, and then turning on the field-effect transistor DUT to apply the short-circuit stress; then turning off the switching transistor S2, and the field-effect transistor DUT to be tested is also turned off, and then turning off the switching transistor P and the switching transistor S1, and the application of the hard-switching short-circuit stress is completed; A load short-circuit stress is applied to the field effect transistor DUT under test, specifically as follows: a constant gate stress is applied to the field effect transistor DUT under test, the switching transistor P is first turned on, and then the switching transistor S2 is turned on, thereby turning on the field effect transistor DUT under test, keeping the switching transistor S1 and the switching transistor S3 off, and the field effect transistor DUT under test working normally; then, when the field effect transistor DUT under test is working normally, the switching transistor S1 is turned on to apply the load short-circuit stress to the field effect transistor DUT under test; then, the switching transistor S2 is turned off to turn off the field effect transistor DUT under test, and the application of the load short-circuit stress is ended, and then the switching transistor S1 and the switching transistor P are turned off.

9. A method for characterizing dynamic characteristics of a power switching device according to claim 7, characterized in that: After the two short-circuit electrical stresses are applied, the stress control circuit controls the field effect transistor DUT to be unaffected by the electrical stress according to the received drive signal, so that it is in the dynamic characteristic recovery stage, including: During the dynamic characteristics recovery phase, the on-resistance of the field effect transistor DUT under test is measured without applying additional electrical stress. Specifically, the switching transistor S1 is kept off, and the switching transistor P is kept off first. The switching transistor S2 and the field effect transistor DUT under test are turned on, and the drain voltage of the field effect transistor DUT under test is zero. Then, the switching transistor P is turned on to soft-turn on the field effect transistor DUT under test. Then, the switching transistor P is turned off to reduce the current of the field effect transistor DUT under test to zero. Thereafter, the switching transistor S2 and the field effect transistor DUT under test are turned off to soft-turn off the field effect transistor DUT under test. During the dynamic characteristic recovery phase, the threshold voltage of the field effect transistor DUT to be tested is measured without applying additional electrical stress. Specifically, a constant gate voltage is first applied to the field effect transistor DUT to be tested, and the switching transistor S1 and the switching transistor S2 are kept turned off; then the switching transistor P is turned on, the capacitor Cm is charged, the gate-source voltage of the field effect transistor DUT to be tested gradually decreases, and the field effect transistor DUT to be tested is turned off; then the switching transistor P is turned off, and the switching transistor P bears the high voltage; then the switching transistor S3 is turned on, the drain charge of the field effect transistor DUT to be tested is discharged, the charge of the capacitor Cm is released, and the field effect transistor DUT to be tested is turned on.

10. The method for characterizing dynamic characteristics of a power switching device according to claim 7, wherein: Also includes: By sequentially superimposing hard-switching short-circuit stress and off-state drain voltage stress, the performance degradation of the field-effect transistor (DUT) under the composite working condition is simulated. The specific steps are as follows: Apply hard switch short circuit stress; specifically: control the switching transistor S1 to turn on, short-circuit the load resistor RL and the inductor L; turn on the switching transistor P, so that the field effect transistor DUT under test is subjected to the high voltage V BUS Turn on the switching transistor S2 and the field effect transistor under test DUT to trigger a hard switch short circuit event, which lasts for t1; record the drain-source current I during the short circuit. S_DUT Peak and recovered drain-source voltage V DS_DUT ; Superimpose the off-state drain voltage stress; specifically: keep the switch transistor P on, turn off the switch transistor S2 and the field effect transistor under test DUT; by adjusting the high voltage power supply V BUS The voltage amplitude is , and the off-state drain voltage stress is applied for a duration of t2; Based on the calculated change in on-resistance of the field effect transistor DUT, a synergy factor K is defined and a synergy factor threshold is set; the synergy factor is used to quantify the accelerating effect of hard-switching short-circuit stress and off-state drain voltage stress on the degradation of the field effect transistor DUT; wherein, In the above formula, K represents the synergistic factor, ΔR on-复合 Represents the change in on-resistance Ron of the field effect transistor DUT under the conditions of hard switching short-circuit stress and off-state drain voltage stress; ΔR on-单一 It indicates the change in the on-resistance Ron of the field effect transistor DUT under the single stress condition of hard switching short circuit stress or off-state drain voltage stress; Based on the Arrhenius equation and combined with temperature data, a thermal-electric coupling degradation model is established, specifically: ΔR on represents the predicted degradation of the field effect transistor under test (DUT); A represents the material constant, which characterizes the inherent sensitivity of the material to electrothermal stress; E a represents the activation energy, which indicates the minimum energy threshold required to initiate the degradation process; k β is the Boltzmann constant, T is the junction temperature of the field effect transistor DUT, and n is the voltage stress index; V DS Represents the voltage applied between the drain and source of the field effect transistor DUT under test; t s Represents the duration of voltage stress application; if the synergy factor is greater than the synergy factor threshold, it is determined to be a strong synergistic effect, and the stress application period is automatically shortened and the sampling frequency is increased; if ΔR on If the voltage exceeds the set threshold, the protection mechanism is triggered to turn off the switching transistor S1, the switching transistor S2, the switching transistor S3, the switching transistor P and the field effect transistor DUT under test.

Images