Chip testing system and method and electronic equipment

Abstract

The invention relates to the technical field of computers, in particular to a chip testing system and method and electronic equipment, and the method comprises a testing signal source module which is used for providing a clock signal and a data signal; a plurality of blocks, each of the blocks comprising a plurality of target modules connected in series, the target modules transmitting the clock signals and the data signals according to a serial connection sequence, and clock skew caused by on-chip difference and signal crosstalk in a single block being within a range allowed by a timing margin; and the clock path of the starting module of each block is directly connected with the test signal source module. According to the embodiment of the invention, the stability and reliability of chip testing can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a chip testing system, method, and electronic device. Background Art

[0002] In the field of integrated circuit (IC) design, the continuous expansion and increasing complexity of chips place higher demands on chip Design for Testability (DFT). Traditional DFT methods face numerous challenges when dealing with large-scale chips, such as difficulty in timing closure, high test resource consumption, and low test efficiency. To address these issues, the industry has developed a variety of chip Design for Testability solutions, among which technologies based on Streaming Scan Networks (SSNs) have gained widespread adoption.

[0003] However, traditional SSN technology still has inherent limitations when applied to VLSI chips. Due to its route-dependent architecture, clock signals must pass through multiple transit modules before reaching the end module, limiting clock length and planning distribution. This not only increases clock path latency but can also introduce significant on-chip variation (OCV) and signal crosstalk, impacting timing signoff convergence. Summary of the Invention

[0004] The present disclosure proposes a chip testing technology solution.

[0005] According to one aspect of the present disclosure, a chip testing system is provided, comprising:

[0006] A test signal source module, used for providing clock signals and data signals;

[0007] a plurality of blocks, each of the blocks including a plurality of target modules connected in series, the target modules transmitting the clock signal and the data signal in a serially connected order, wherein a clock skew caused by on-chip differences and signal crosstalk in a single block is within a range allowed by a timing margin;

[0008] The clock path of the starting module of each block is directly connected to the test signal source module.

[0009] In one possible implementation, the starting module is a continuous streaming scanning control unit in a streaming scanning network, and / or the target module is a functional module including the continuous streaming scanning control unit; wherein, the continuous streaming scanning control unit is used to transmit the clock signal and data signal, and the functional module is a module in the chip used to implement the chip function.

[0010] In one possible implementation, the number n of modules in a single block satisfies the following design conditions:

[0011]

[0012] Where T is the maximum value allowed for clock skew in a single block due to on-chip differences and signal crosstalk, Max(TL i ,TW i ) is the length TL of the i-th module i and width TW i The maximum value in, D / L is the delay of the module unit length to the clock signal, D is the total delay, L is the total length, M scale is the delay change rate, and n is a positive integer.

[0013] In a possible implementation, the system further includes:

[0014] The redistribution layer RDL is used to directly transmit the clock signal of the test signal source module to the start module of each block.

[0015] In a possible implementation, the system further includes:

[0016] The delay module is used to maintain the clock balance between the end module of the main path block and the head end module of the sub-path block in the streaming scanning network; wherein the signal of the sub-path block comes from the main path block.

[0017] In a possible implementation, the target module includes:

[0018] A data transmission port, and a first register connected to the data transmission port, wherein the first register is used to transmit data received by the data transmission port, and a distance between the data transmission port and the first register is less than a first distance.

[0019] In a possible implementation, a clock tree in the system is generated based on a non-default routing rule, the clock trees between the target modules are connected by line segments, and the clock trees are used to transmit the clock signal.

[0020] In a possible implementation, a bifurcation point of the clock signal line closest to the clock signal output port in the target module is adjacent to a register connected in a straight line to the bifurcation point.

[0021] According to another aspect of the present disclosure, a chip testing method is provided, which is applied to a chip testing system. The chip testing system includes a test signal source module and multiple blocks, each of which includes multiple serially connected target modules. The method includes:

[0022] The test signal source module outputs a clock signal and a data signal;

[0023] The target module transmits the clock signal and data signal in the order of serial connection, and the clock skew caused by on-chip differences and signal crosstalk in a single block is within the range allowed by the timing margin; the clock path of the starting module of each block is directly connected to the test signal source module.

[0024] In one possible implementation, the starting module is a continuous streaming scanning control unit in a streaming scanning network, and / or the target module is a functional module including the continuous streaming scanning control unit; wherein, the continuous streaming scanning control unit is used to transmit the clock signal and data signal, and the functional module is a module in the chip used to implement the chip function.

[0025] In one possible implementation, the number n of modules in a single block satisfies the following design conditions:

[0026]

[0027] Where T is the maximum value allowed for clock skew in a single block due to on-chip differences and signal crosstalk, Max(TL i ,TW i ) is the length TL of the i-th module i and width TW i The maximum value in, D / L is the delay of the module unit length to the clock signal, D is the total delay, L is the total length, M scale is the delay change rate, and n is a positive integer.

[0028] In a possible implementation, the method further includes:

[0029] The redistribution layer (RDL) directly transmits the clock signal of the test signal source module to the start module of each block.

[0030] In a possible implementation, the method further includes:

[0031] The delay module maintains the clock balance between the end module of the main path block and the head end module of the sub-path block in the streaming scanning network; wherein the signal of the sub-path block comes from the main path block.

[0032] In a possible implementation, the target module includes: a data transmission port, and a first register connected to the data transmission port;

[0033] The first register transmits data received by the data transmission port, and a distance between the data transmission port and the first register is less than a first distance.

[0034] In a possible implementation, a clock tree in the system is generated based on a non-default routing rule, the clock trees between the target modules are connected by line segments, and the clock trees are used to transmit the clock signal.

[0035] In a possible implementation, a bifurcation point of the clock signal line closest to the clock signal output port in the target module is adjacent to a register connected in a straight line to the bifurcation point.

[0036] According to another aspect of the present disclosure, an electronic device is provided, comprising the above system.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0039] Figure 1 A schematic diagram showing the structure of a continuous streaming scanning network is shown.

[0040] Figure 2 A framework diagram of a chip testing system according to an embodiment of the present disclosure is shown.

[0041] Figure 3 A schematic structural diagram of a chip testing system provided by an embodiment of the present disclosure is shown.

[0042] Figure 4 A schematic diagram of an SSN inter-module communication structure provided by an embodiment of the present disclosure is shown.

[0043] Figure 5 A flowchart of a chip testing method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0045] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0046] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0047] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0048] Figure 1 A schematic diagram of a continuous streaming scan network is shown. This network comprises a streaming scan host (SSH) and a scan compression module (EDT). SSH is the unit that controls SSN data. Four modules, A, B, C, and D, are used. Module A serves as the starting module, and its scan test data (ssn data) and scan clock (ssn clock) are driven by chip pins. Subsequent modules B, C, and D receive their scan test data (ssn data) and scan clock (ssn clock) from the previous module, respectively. The overall structure is cascaded, and each module's data port uses registers based on the SSN clock to transmit data.

[0049] This continuous stream scanning network has some limitations. First, due to its route-dependent structure, the clock and data paths are closely linked, and the clock signal must pass through multiple transit modules before reaching the end module, resulting in limited clock length and planning distribution. This not only increases the delay of the clock path, but also may introduce a large amount of on-chip variation (OCV) and signal crosstalk, affecting the convergence of timing check. Second, as chip size increases, the server computing resources, disk resources, and inspection time required for timing check also increase significantly, further exacerbating the consumption of test resources.

[0050] In the disclosed embodiments, by dividing the continuous stream scanning network into multiple blocks and directly connecting the clock path of the starting module of each block to the test signal source module, the delay of the clock signal by the intermediate modules is avoided, reducing the transmission distance of the clock signal and potential timing issues. Furthermore, the clock skew within each block is controlled within the timing margin, which can significantly reduce the overall clock skew, ensure the stability and accuracy of the clock signal during transmission, and help improve the stability of test frequency and timing convergence. In this way, even the clock skew of the last target module in each block is within the timing margin, which helps improve the stability and reliability of chip testing.

[0051] Figure 2 A framework diagram of a chip testing system according to an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the chip testing system includes:

[0052] A test signal source module 11 is used to provide clock signals and data signals;

[0053] a plurality of blocks 12, each of which includes a plurality of target modules connected in series, wherein the target modules transmit the clock signal and the data signal in a serially connected order, and the clock skew caused by on-chip differences and signal crosstalk in a single block is within a range allowed by a timing margin;

[0054] The clock path of the starting module of each block is connected to the test signal source module.

[0055] The test signal source module (SSN source) is a module that provides clock signals and data signals. In integrated circuit testing, the clock signal is used to synchronize the operations of various modules, while the data signal carries the information required for testing or operation.

[0056] A block is a group or area into which multiple serially connected target modules are divided. The target modules are responsible for sequentially transmitting clock and data signals. Blocks may be organized based on the division of functional modules for easier management and testing. When dividing the target modules into blocks, the length of the internal clock path within the block can be considered. Using a pre-set algorithm, clock skew caused by on-chip variations and signal crosstalk can be controlled within the allowable range of timing margin. For details, please refer to the possible implementation methods provided in this disclosure and will not be detailed here.

[0057] Clock skew is the difference in the time it takes for a clock signal to arrive at different registers on a chip. In an SSN architecture, clock signals are transmitted along the path, which can introduce clock skew, impacting test frequency and timing closure. This variation can be caused by a variety of factors, including physical layout, signal path length, on-chip variations, and signal crosstalk. On-chip variation refers to performance differences between different locations on the same chip due to process variations.

[0058] Timing margin is the time margin reserved during circuit design to ensure proper operation. It is used to compensate for clock skew and other timing issues caused by factors such as process variations, temperature variations, and voltage variations. Signal crosstalk, on the other hand, is electromagnetic interference between different signal lines, which can lead to signal quality degradation and timing issues. In an SSN structure, since clock and data signals are transmitted along the same path, they may be affected by signal crosstalk.

[0059] A block consists of multiple serially connected target modules, with the modules within the block transmitting clock and data signals sequentially. Clock skew within each block (caused by on-chip variations and signal crosstalk) is controlled within the allowed range of timing margin. Consequently, despite adverse factors such as process variations and signal crosstalk, the clock signal within each block remains sufficiently consistent, preventing excessive clock skew during transmission, thereby ensuring stable test frequency and timing closure.

[0060] The clock path of the starting module of each block is directly connected to the test signal source module, ensuring that the clock signal differences between different blocks are reduced. The specific connection method can refer to the possible implementation methods provided in this disclosure and will not be described here.

[0061] In the disclosed embodiments, by dividing the continuous stream scanning network into multiple blocks and directly connecting the clock path of the starting module of each block to the test signal source module, the delay of the clock signal by the intermediate modules is avoided, reducing the transmission distance of the clock signal and potential timing issues. Furthermore, the clock skew within each block is controlled within the timing margin, which can significantly reduce the overall clock skew, ensure the stability and accuracy of the clock signal during transmission, and help improve the stability of test frequency and timing convergence. In this way, even the clock skew of the last target module in each block is within the timing margin, which helps improve the stability and reliability of chip testing.

[0062] In one possible implementation, the starting module is a continuous streaming scanning control unit in a streaming scanning network, and / or the target module is a functional module including the continuous streaming scanning control unit; the continuous streaming scanning control unit is used to transmit the clock signal and data signal, and the functional module is a module in the chip used to implement the chip function.

[0063] As previously mentioned, a streaming scan network (SSN) is a structure used for large-scale chip design for testability. It allows test data (i.e., data signals) and clock signals to be transmitted within the chip through a specific scan module (continuous streaming scan control unit). This structure facilitates post-manufacturing chip testing to ensure proper chip functionality.

[0064] The SSH (Continuous Streaming Scan Control Unit) is the fundamental unit in the SSN, responsible for transmitting clock and data signals. They are typically cascaded together to form a continuous scan path, allowing clock and data signals to flow throughout the chip. Functional modules are the parts of the chip that implement specific functions. Each functional module can contain a SSH control unit, enabling access to the SSN during testing.

[0065] In this implementation, the SSN is partitioned based on the functional modules, which means that designers can divide the SSN into different blocks based on the physical location and functional requirements of the functional modules in the chip.

[0066] Within each block, the start module serves as the continuous stream scanning control unit within the stream scanning network. This means that the start module serves as the entry point to the SSN, responsible for receiving and transmitting clock and data signals from the test equipment. Designers can select the appropriate SSN sub-route start module. Furthermore, the SSN's SSH can be directly added to the functional module as the target module within the block. This allows the SSN to be efficiently integrated with the functional module while maintaining test data integrity and clock signal stability.

[0067] This allows SSN timing signoff (the process of checking the transmission timing of clock and data signals within the SSN) to share a common testing environment with functional timing signoff. This means that during testing, the timing performance of both the SSN and the functional module can be checked simultaneously, eliminating the need for separate, independent tests. This not only reduces the resources required for testing but also improves test efficiency and accuracy.

[0068] In one possible implementation, the number n of modules in a single block satisfies the following design conditions:

[0069]

[0070] Where T is the maximum value allowed for clock skew in a single block due to on-chip differences and signal crosstalk, Max(TL i ,TW i ) is the length TL of the i-th module i and width TW i The maximum value in, D / L is the delay of the module unit length to the clock signal, D is the total delay, L is the total length, M scale is the delay change rate, and n is a positive integer.

[0071] The number of modules n in a single block is controlled by this design condition to partition the block so that the clock skew caused by on-chip differences and signal crosstalk in a single block does not exceed the maximum allowed value.

[0072] Among them, the length of each module can be expressed as TL1, TL2, ... TL i ,…TL n ; The width of each module can be expressed as TW1, TW2, ... TW i ,TW n ; Delay change rate M scale It can be expressed as:

[0073] M scale =(W ratio *w scale )+(D ratio *d scale )+N noise

[0074] Where: W ratio Refers to the proportion of line delay in unit delay, w scale Refers to the change ratio of line delay; D ratio Refers to the proportion of standard unit delay in unit delay, d scale Refers to the variation ratio of the standard cell delay; N noise Refers to the delay ratio introduced by crosstalk.

[0075] To determine n, we can solve the above inequality (i.e., the design condition), as shown below:

[0076] First, calculate M scale Next, we need to consider how to effectively divide the blocks so that the total clock skew of each block is as small as possible.

[0077] Calculate the Max(TL) of each module i ,TW i), that is, for each module, calculate the larger of its length and width. Then, accumulate these values, starting with the smallest value, until the accumulated value makes the above inequality (design condition) invalid. Then stop accumulating. At this point, the number of accumulated modules minus 1 is n.

[0078] Example Calculation

[0079] Assume the following module dimensions and parameters:

[0080] TL1=5,TW1=3

[0081] TL2=4,TW2=6

[0082] TL3=7,TW3=2

[0083] …

[0084] T=100

[0085] D=10

[0086] L=100

[0087] W ratio =0.3

[0088] w scale =0.05

[0089] D ratio =0.7

[0090] d scale =0.08

[0091] N noise =0.02

[0092] First calculate M scale =(0.3×0.05)+(0.7×0.08)+0.02=0.015+0.056+0.02=0.091

[0093] Then calculate the Max(TL i ,TW i ) and sort:

[0094] Max(5,3)=5

[0095] Max(4,6)=6

[0096] Max(7,2)=7

[0097] …

[0098] Then start adding and checking inequalities: 100 > 2 × (5 + 6 + 7 + ...) × 10 ÷ 100 × 0.091

[0099] Continue to accumulate until the condition is no longer met and determine the value of n.

[0100] In the disclosed embodiment, the number of modules n in a single block can be effectively determined to ensure that the clock skew does not exceed the maximum allowed value. This helps to improve the stability and consistency of the clock signal when designing a chip test system.

[0101] In a possible implementation, the system further includes: a redistribution layer (RDL) configured to directly transmit the clock signal of the test signal source module to the start module of each of the blocks.

[0102] In integrated circuit design, a redistribution layer (RDL) is one or more additional wiring layers located above the metal layer inside the chip, used to redistribute or redirect signals from inside or outside the chip. The RDL layer allows designers to connect different components on the chip more flexibly, especially in advanced packaging technologies such as system-level packaging (SiP) and three-dimensional packaging (3D Packaging), where the role of the RDL layer is particularly critical. In the embodiment of the present disclosure, the RDL is used to transmit the clock signal of the test signal source module directly to the starting module of each block.

[0103] In traditional streaming scan network (SSN) architectures, clock and data signals are transmitted along the path, meaning they are passed between modules in a cascaded fashion. However, in large-scale chip designs, this along-path architecture can lead to excessively long clock paths, increasing clock latency and potentially introducing significant on-chip variation (OCV) and signal crosstalk, impacting timing closure.

[0104] To address this issue, a redistribution layer (RDL) can be used to optimize clock signal transmission. Specifically, the RDL layer is used to transmit the clock signal from the test signal source module directly to the start module of each block, rather than passing it step by step through the accompanying modules. This significantly shortens the transmission distance of the clock signal, reduces clock latency, and minimizes the impact of OCV and signal crosstalk.

[0105] In the disclosed embodiment, the clock signal is transmitted directly to the block start module through the RDL layer, avoiding the delay of the clock signal by the intermediate module, thereby reducing the overall clock delay. The reduction of the follow-up structure means that the impact of process deviation and signal crosstalk on the clock signal during transmission is also reduced, which helps to improve the stability of timing convergence. Since the transmission of the clock signal is more efficient and stable, it helps to increase the frequency and efficiency of chip testing while reducing the additional resources required for testing.

[0106] In addition to the redistribution layer (RDL), a high-drive device can also be used to improve the stability and accuracy of the clock signal. The high-drive device in the embodiment of the present disclosure can be a standard buffer unit with a high drive value (for example, a drive value of 16, 20 or higher), which is used to shorten the clock delay and reduce on-chip variation (OCV) and signal crosstalk.

[0107] High-drive devices can transmit clock signals more efficiently by providing stronger driving capabilities, thereby reducing clock delays. At the same time, since high-drive devices can reduce signal attenuation during transmission, they also help reduce the impact of OCV and signal crosstalk.

[0108] Redistribution layers (RDLs) and high-drive devices can be used together to further optimize clock signal transmission. RDLs are used to transmit clock signals from the test signal source module directly to the start module of each block, eliminating clock signal delays caused by intermediate modules. High-drive devices are used to enhance clock signal transmission capabilities, ensuring that the clock signal reaches the target module stably and accurately.

[0109] By combining RDL with high-drive devices, it effectively addresses the problems of strong clock path dependency, high latency, over-voltage crosstalk, and severe signal crosstalk found in traditional architectures. At the same time, it inherits the advantages of the Streaming Scan Network (SSN) architecture for rapid timing convergence between modules, thereby improving the efficiency and accuracy of testability design for large-scale chips.

[0110] In one possible implementation, the system further includes: a delay module for maintaining a clock balance between the end module of the main path block and the head end module of the sub-path block in the streaming scanning network; wherein the signal of the sub-path block originates from the main path block.

[0111] In this implementation, each block is divided into a main path block and a sub-path block. The main path block is the upstream block for the sub-path block's signals, meaning that signals flow from the main path module to the sub-path module. Based on block division and clock optimization, clock balance between the main path block and the sub-path block can also be maintained.

[0112] Specifically, the clock signals of the end modules in the main path block and the head-end modules in the sub-path blocks are synchronized. Clock discrepancies between the two can cause errors or loss of test data during transmission. Therefore, a series of measures are required during the design process to ensure clock balance. The delay module adjusts the clock signal delay to ensure that the end modules in the main path block and the head-end modules in the sub-path blocks maintain clock synchronization. This reduces the risk of data errors or loss caused by clock discrepancies.

[0113] The delay module can use various technologies to implement the delay adjustment of the clock signal, such as using delay lines, clock buffers, etc. During the design process, the parameters and configuration of the delay module can be determined according to the specific chip layout, clock frequency and timing requirements.

[0114] Figure 3 A schematic structural diagram of a chip testing system provided by an embodiment of the present disclosure is shown. Figure 3 In the figure, M1~Mn are functional modules including the continuous stream scanning control unit SSH. According to the flow order of the signal, it can be agreed here that when M1 is the main path block, M2 / M2' / M3 / M5 are sub-paths of M1; when M3 is the main path of sub-path M3, M4~Mn are sub-paths of M3; the clock signals 1~3 provided by the test signal source module are transmitted to the first module M2', M3 and M5 of each sub-path respectively through the redistribution layer RDL.

[0115] In one possible implementation, the target module includes: a data transmission port, and a first register connected to the data transmission port, the first register is used to transmit data received by the data transmission port, and the distance between the data transmission port and the first register is less than a first distance.

[0116] In addition to maintaining clock balance, data path latency also needs to be considered. In chip design, the data path refers to the path along which data signals are transmitted between various modules within the chip. Excessive data path latency can degrade chip performance and even fail to meet design requirements.

[0117] The data transfer port is an interface on the target module that receives and sends data signals, ensuring that test data can be effectively transferred between modules within the chip. The first register, a component directly connected to the data transfer port, temporarily stores data received from the port and transmits it to the next target module or other components within the target module when needed.

[0118] In this implementation, the distance between the data transmission port and the first register can be controlled when designing the target module. Specifically, the first register can be designed to be as close as possible to the data transmission port, that is, the distance between the first register and the data transmission port can be set to a smaller value (less than the first distance) to reduce data path delay.

[0119] Data path latency is the time it takes for data to travel from the source (in this case, the data transfer port) to the destination (in this case, the first register). This latency is determined by a variety of factors, including signal line length, line impedance, and signal transmission speed. By shortening the distance between the data transfer port and the first register, signal attenuation and interference during transmission can be reduced, thereby improving data transmission speed and accuracy.

[0120] In summary, by manually concentrating the registers corresponding to the SSN data ports in the module near the ports, the delay of the data path can be significantly reduced, the timing impact caused by clock skew can be compensated, and the performance and test efficiency of the chip can be optimized.

[0121] Figure 4 The following is a schematic diagram of an SSN inter-module communication structure provided by an embodiment of the present disclosure. The clock signal is the SSN clock, which provides a clock to the DFT-related registers inside module 1 and also provides a clock to the subsequent module 2. Then, the registers related to the data transmission port (such as Figure 4 A and B) are placed within 100 μm of the data transmission port.

[0122] In a possible implementation, a clock tree in the system is generated based on a non-default routing rule, the clock trees between the target modules are connected by line segments, and the clock trees are used to transmit the clock signal.

[0123] In digital circuit design, a clock tree is a network used to distribute clock signals from a clock source to all registers and other synchronous components within a chip that require clock signals. The design of a clock tree is crucial to ensuring that all components within a chip operate accurately and synchronously.

[0124] During chip placement and routing, a set of default routing rules typically guides the placement and connection of signal lines. However, in some cases, non-default routing rules (NDRs) may be employed to optimize circuit performance or meet specific design requirements. These rules may include stricter line width and spacing requirements, or specific routing directions.

[0125] In this implementation, the clock tree is generated using non-default routing rules (NDR). That is, during the clock tree placement and routing process, the conventional routing method is not followed. Instead, the clock tree is designed to be shorter and straighter without unnecessary detours.

[0126] In the disclosed embodiment, by adopting non-default winding rules, the segments of the clock tree are designed to be shorter and straighter, which helps to reduce the delay of the clock signal during transmission. The reduction of clock delay is crucial to improving the overall performance and timing convergence of the chip. In addition, by optimizing the layout and routing of the clock tree, problems such as clock skew and clock jitter can be reduced, thereby improving timing convergence. This helps to ensure that the chip can operate stably and reliably under various operating conditions. The use of non-default winding rules can also help optimize the layout of the chip. By more flexibly controlling the direction and length of the segments of the clock tree, the space resources inside the chip can be better utilized, and the integration and performance of the chip can be improved.

[0127] In a possible implementation, a bifurcation point of the clock signal line closest to the clock signal output port in the target module is adjacent to a register connected in a straight line to the bifurcation point.

[0128] The clock signal output port is a node in the clock tree that provides the clock signal to the next target module. In the clock tree, the clock signal line may branch to provide the clock signal to multiple target modules or registers. Figure 4 As shown, the clock signal is bifurcated in module 1 to provide clock signals to register B and module 2.

[0129] Registers are circuit elements used to store data in digital circuits. Registers usually require a synchronized clock signal to ensure the correct transmission and processing of data.

[0130] In this implementation, the design goal is to optimize the timing balance of the registers in the target module. To achieve this goal, the bifurcation point of the clock signal line closest to the clock signal output port in the target module can be placed at a specific register in the target module (for example, Figure 4 The bifurcation point is then connected to these registers via straight lines. The proximity here can mean that there are no other clock signal processing components between the bifurcation point and the register, and they are directly connected via straight line wiring, or that the distance between the bifurcation point and the register is less than a preset distance threshold. The preset distance threshold can be determined based on actual experience. When the distance is less than the preset distance threshold, the skew of the clock signal during transmission can be reduced, thereby improving the accuracy of the timing.

[0131] like Figure 4 As shown, the bifurcation point of the clock signal close to the next tile is placed as close to the B register as possible, so that the timing of the B register in module 1 and the A2 register in module 2 are balanced; similarly, the B2 register in module 1 and the A register in module 2 are also kept in timing balance using the above method.

[0132] In the disclosed embodiments, by placing bifurcation points close to specific registers and ensuring a straight line connection, the time differences in clock signals reaching these registers can be minimized. This helps maintain timing balance between different registers, ensuring they operate correctly within the same clock cycle. By placing bifurcation points close to registers and connecting them with straight lines, clock signal skew during transmission can be reduced, thereby improving timing accuracy.

[0133] In traditional design-for-test (DFT) system architectures, the data and clock sources for all functional modules originate from the same starting point. This results in lengthy data paths and makes clock tree lengths difficult to balance due to differences in module size. This in turn increases the difficulty of timing closure, making Engineering Change Orders (ECOs) a heavy workload and limiting DFT performance improvements. In contrast, the SSN structure effectively shortens the data path by designing data and clocks along the path, and provides more common clock paths for the along-path modules, significantly reducing clock skew. However, the SSN structure still faces problems such as long clock paths, signal crosstalk, and excessive OCV.

[0134] In this disclosed embodiment, while inheriting the ease of timing closure offered by the SSN architecture, it successfully addresses the issues of excessively long slave clocks and excessive number of modules, effectively reducing the impact of OCV and signal crosstalk, and optimizing resource utilization for timing checkoff. By planning the location of registers at the ports, the data path is further shortened, and the ECO phase's operating scope is limited to the interface between the master slave and each block, accelerating timing closure.

[0135] In one possible implementation, the chip testing system can be executed by electronic devices such as terminal devices and servers. The terminal devices can be user equipment (UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (PDAs), handheld devices, computing devices, vehicle-mounted devices, wearable devices, etc. The system can be implemented by a processor calling computer-readable instructions stored in a memory.

[0136] In addition, the present disclosure also provides a chip testing method and electronic equipment, which can be used to implement any chip testing system provided by the present disclosure. The corresponding technical solutions and descriptions can be found in the corresponding records in the method section and will not be repeated here.

[0137] Figure 5 A flow chart of a chip testing method according to an embodiment of the present disclosure is shown as follows: Figure 5As shown, the method is applied to a chip test system, the chip test system includes a test signal source module and multiple blocks, each of the blocks includes multiple serially connected target modules, and the method includes:

[0138] In step S21, the test signal source module outputs a clock signal and a data signal;

[0139] In step S22, the target module transmits the clock signal and the data signal in the order of serial connection, and the clock skew caused by on-chip differences and signal crosstalk in a single block is within the range allowed by the timing margin; the clock path of the starting module of each block is directly connected to the test signal source module.

[0140] In one possible implementation, the starting module is a continuous streaming scanning control unit in a streaming scanning network, and / or the target module is a functional module including the continuous streaming scanning control unit; wherein, the continuous streaming scanning control unit is used to transmit the clock signal and data signal, and the functional module is a module in the chip used to implement the chip function.

[0141] In one possible implementation, the number n of modules in a single block satisfies the following design conditions:

[0142]

[0143] Where T is the maximum value allowed for clock skew in a single block due to on-chip differences and signal crosstalk, Max(TL i ,TW i ) is the length TL of the i-th module i and width TW i The maximum value in, D / L is the delay of the module unit length to the clock signal, D is the total delay, L is the total length, M scale is the delay change rate, and n is a positive integer.

[0144] In a possible implementation, the method further includes:

[0145] The redistribution layer (RDL) directly transmits the clock signal of the test signal source module to the start module of each block.

[0146] In a possible implementation, the method further includes:

[0147] The delay module maintains the clock balance between the end module of the main path block and the head end module of the sub-path block in the streaming scanning network; wherein the signal of the sub-path block comes from the main path block.

[0148] In a possible implementation, the target module includes: a data transmission port, and a first register connected to the data transmission port;

[0149] The first register transmits data received by the data transmission port, and a distance between the data transmission port and the first register is less than a first distance.

[0150] In a possible implementation, a clock tree in the system is generated based on a non-default routing rule, the clock trees between the target modules are connected by line segments, and the clock trees are used to transmit the clock signal.

[0151] In a possible implementation, a bifurcation point of the clock signal line closest to the clock signal output port in the target module is adjacent to a register connected in a straight line to the bifurcation point.

[0152] According to another aspect of the present disclosure, an electronic device is provided, comprising the above system.

[0153] In some embodiments, the functions or modules included in the method provided by the embodiments of the present disclosure can be used to execute the system described in the above system embodiment. Its specific implementation can refer to the description of the above method embodiment. For the sake of brevity, it will not be repeated here.

[0154] Other components of the chip or electronic device in the above embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0155] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0156] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0157] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0158] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0159] The disclosure above provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0160] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip testing system, characterized in that: include: A test signal source module, used for providing clock signals and data signals; a plurality of blocks, each of the blocks including a plurality of target modules connected in series, the target modules transmitting the clock signal and the data signal in a serially connected order, wherein a clock skew caused by on-chip differences and signal crosstalk in a single block is within a range allowed by a timing margin; The clock path of the starting module of each block is directly connected to the test signal source module.

2. The system according to claim 1, wherein: The starting module is a continuous streaming scanning control unit in a streaming scanning network, and / or the target module is a functional module including the continuous streaming scanning control unit; wherein, the continuous streaming scanning control unit is used to transmit the clock signal and data signal, and the functional module is a module in the chip used to implement the chip function.

3. The system according to claim 1, wherein: The number of modules n in a single block satisfies the following design conditions: Where T is the maximum value allowed for clock skew in a single block due to on-chip differences and signal crosstalk, Max(TL i ,TW i ) is the length TL of the i-th module i and width TW i The maximum value in, D / L is the delay of the module unit length to the clock signal, D is the total delay, L is the total length, M scale is the delay change rate, and n is a positive integer.

4. The system according to claim 1, wherein: The system further comprises: The redistribution layer RDL is used to directly transmit the clock signal of the test signal source module to the start module of each block.

5. The system according to claim 1, wherein: The system further comprises: The delay module is used to maintain the clock balance between the end module of the main path block and the head end module of the sub-path block in the streaming scanning network; wherein the signal of the sub-path block comes from the main path block.

6. The system according to claim 1, wherein: The target module includes: A data transmission port, and a first register connected to the data transmission port, wherein the first register is used to transmit data received by the data transmission port, and a distance between the data transmission port and the first register is less than a first distance.

7. The system according to claim 1, wherein: The clock tree in the system is generated based on a non-default winding rule, the clock trees between the target modules are connected by line segments, and the clock tree is used to transmit the clock signal.

8. The system according to claim 1, wherein: The bifurcation point of the clock signal line closest to the clock signal output port in the target module, and the register connected to the bifurcation point in a straight line.

9. A chip testing method, characterized in that: Applied to a chip test system, the chip test system includes a test signal source module and multiple blocks, each of the blocks includes multiple serially connected target modules, the method includes: The test signal source module outputs a clock signal and a data signal; The target module transmits the clock signal and data signal in a serial connection order, and the clock skew caused by on-chip differences and signal crosstalk in a single block is within the range allowed by the timing margin; the clock path of the starting module of each block is directly connected to the test signal source module.

10. An electronic device, characterized in that: Comprising the system as claimed in claims 1 to 8.

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