Chip data detection method and system based on artificial intelligence

Abstract

The application provides a chip data detection method and system based on artificial intelligence, and relates to the technical field of chip detection. The method comprises the following steps: acquiring dynamic power data of a chip; constructing a chip data detection model based on a random forest; judging whether the structural complexity of the chip is less than a preset structural complexity; if yes, performing denoising processing on the dynamic power data by using a Bayesian filtering algorithm to obtain first denoised power data, and performing abnormality detection through the chip data detection model; otherwise, performing denoising processing on the dynamic power data by using a bidirectional long short-term memory network to obtain second denoised power data, acquiring logic activity data of the chip, and jointly using the second denoised power data and the logic activity data to perform abnormality detection through the chip data detection model. In the application, the structural complexity is processed by using the Bayesian filtering algorithm for denoising and the bidirectional long short-term memory network, so that the detection efficiency and accuracy are effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and in particular to a chip data detection method and system based on artificial intelligence. Background Art

[0002] With the rapid development of artificial intelligence technology, various AI-based applications have achieved remarkable results in many fields, especially in the fields of integrated circuit (IC) design, chip manufacturing and testing. As the core component of modern electronic devices, the quality and performance of chips directly determine the overall functionality and stability of electronic products. In order to ensure the design and manufacturing quality of chips, chip data detection plays a vital role in the production process. Traditional detection methods mostly rely on manual analysis and basic testing instruments. These methods often cannot meet the requirements of modern chip design complexity and manufacturing precision in terms of accuracy and efficiency. Therefore, AI-based chip data detection methods have become an important research topic. They can detect potential defects in chips efficiently and accurately in an automated manner.

[0003] With the advancement of artificial intelligence technology, machine learning-based inspection methods are becoming mainstream. These methods are trained on large amounts of chip data, enabling inspection systems to identify defects with higher accuracy.

[0004] However, traditional methods often fail to consider the structural complexity of chip data, resulting in suboptimal denoising when processing chip data of varying complexity. Furthermore, existing technologies typically use a single data source for anomaly detection, failing to comprehensively leverage the chip's diverse data sources. This single-source detection approach can overlook the correlations between different data, leading to low detection accuracy. Summary of the Invention

[0005] In view of the above shortcomings of the existing technology, the purpose of the embodiments of the present invention is to provide an artificial intelligence-based chip data detection method that can address the problem that traditional methods often fail to consider the structural complexity of chip data, resulting in unsatisfactory denoising effects when processing chip data of varying complexity. Furthermore, existing technologies typically use a single data source for anomaly detection, failing to comprehensively utilize the chip's multiple data sources. This single detection approach may ignore the correlations between different data, resulting in technical issues such as low detection accuracy.

[0006] A first aspect of an embodiment of the present invention provides an artificial intelligence-based chip data detection method, comprising:

[0007] S1: Obtain dynamic power data of the chip;

[0008] S2: Build a random forest-based chip data detection model;

[0009] S3: Determine whether the structural complexity of the chip is less than a preset structural complexity; if so, proceed to S4; otherwise, proceed to S5;

[0010] S4: De-noising the dynamic power data using a Bayesian filtering algorithm to obtain first de-noised power data, and then proceeding to S6;

[0011] S5: De-noising the dynamic power data using a bidirectional long short-term memory network to obtain second de-noised power data, and then proceeding to S7;

[0012] S6: Performing anomaly detection using the chip data detection model based on the first denoised power data;

[0013] S7: Obtain logic activity data of the chip, and use the second denoised power data and the logic activity data together to perform anomaly detection using the chip data detection model.

[0014] A second aspect of an embodiment of the present invention provides an artificial intelligence-based chip data detection system, comprising: a processor and a memory;

[0015] The memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the chip data detection method based on artificial intelligence as described in the first aspect are implemented.

[0016] According to a third aspect of an embodiment of the present invention, a readable storage medium is proposed, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the artificial intelligence-based chip data detection method as described in the first aspect are implemented.

[0017] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0018] In this embodiment of the present invention, a Bayesian filtering algorithm is used for denoising chips with lower structural complexity, while a bidirectional long short-term memory (Bi-LSTM) network is used for processing chips with higher structural complexity, effectively improving denoising accuracy. Secondly, when performing joint detection on chips with higher structural complexity, the detection model fully considers the correlations between different data sources (such as dynamic power data and logic activity data), significantly improving the comprehensiveness and accuracy of anomaly detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are only for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the drawings, the same reference symbols represent the same components. Obviously, the drawings described below are only some embodiments of the present invention. It is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 This is a flow chart of an artificial intelligence-based chip data detection method provided by an embodiment of the present invention;

[0021] Figure 2 This is a structural diagram of an artificial intelligence-based chip data detection system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the scope of protection of the present invention.

[0023] The following describes in detail the artificial intelligence-based chip data detection method provided by the embodiment of the present invention through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0024] Reference Manual Figure 1 , shows a flow chart of an artificial intelligence-based chip data detection method provided by an embodiment of the present invention.

[0025] An embodiment of the present invention provides a chip data detection method based on artificial intelligence, which may include the following steps:

[0026] S1: Obtain the dynamic power data of the chip.

[0027] Dynamic power refers to the energy consumed by the internal circuits and components of an electronic device or chip (such as a processor or integrated circuit) during operation. Unlike static power (which refers to the power consumed by a circuit when it is not performing any activity), dynamic power is primarily affected by the device's execution of tasks and switching between states.

[0028] Optionally, the dynamic power consumption data includes computing unit power consumption, memory module power consumption, clock system power consumption, and control unit power consumption.

[0029] It's important to note that acquiring dynamic power data provides real-time insights into the chip's power consumption under varying workloads. This is crucial for performance tuning and power management. Continuous monitoring of dynamic power data can reveal unusual power consumption patterns under certain operations or workloads.

[0030] S2: Build a random forest-based chip data detection model.

[0031] The random forest-based chip data detection model utilizes the random forest algorithm to classify or detect anomalies in chip-related data (such as dynamic power data and logic activity data). Random forest is an ensemble learning method that combines multiple decision trees for prediction and decision-making. Its advantages lie in its high efficiency, robustness, ability to handle high-dimensional data, and suitability for complex classification and regression problems.

[0032] In a possible implementation, S2 specifically includes:

[0033] S201: Perform singular value decomposition on dynamic power data:

[0034]

[0035] in, represents the hth subset of the i-th dynamic power data, U represents the left singular vector matrix containing the left eigenvector after singular value decomposition, represents a diagonal matrix, represents the right singular vector matrix containing the right eigenvectors after singular value decomposition, T Represents a transpose operation.

[0036] S202: Sort the singular values ​​in descending order, select features corresponding to a preset number of singular values ​​to form a high-information feature set, and combine features corresponding to the remaining singular values ​​to form a low-information feature set.

[0037] It should be noted that the singular values ​​refer to the left singular vector matrix, the diagonal matrix and the right singular vector matrix.

[0038] It should be noted that those skilled in the art can set the size of the preset number according to actual needs, and the present invention is not limited thereto.

[0039] In this embodiment of the present invention, dynamic power data is decomposed using singular value decomposition (SVD), which helps extract the most informative features from high-dimensional data. Sorting features by singular value size allows the extraction of important features. These features reflect the primary changes and behaviors in the dynamic power data, while features that are removed may contain no valuable information or contribute little signal.

[0040] S203: performing type sampling from the high-information feature set and the low-information feature set according to a preset ratio to form a merged feature set.

[0041] Optionally, the preset ratio is specifically 0.5.

[0042] It should be noted that those skilled in the art can set the size of the preset ratio according to actual needs, and the present invention is not limited thereto.

[0043] In this embodiment of the present invention, high-information and low-information features are randomly extracted to form a combined feature set, with a preset ratio of 0.5. This method balances the information in different feature sets, avoiding reliance solely on high-information features, thereby improving the robustness of the model. The appropriate inclusion of low-information features can avoid overfitting and enhance the model's generalization capabilities.

[0044] S204: Construct multiple decision trees based on the combined feature set, and select the best splitting feature for each decision tree based on the Gini index:

[0045]

[0046] in, represents the Gini index, K represents the number of categories, represents the proportion of samples belonging to category k in the merged feature set, represents the number of feature samples belonging to category k, Indicates the total number of feature samples in the merged feature set.

[0047] S205: Perform step-by-step splitting according to each optimal splitting feature until the maximum tree depth is reached, completing the training of the decision tree for each lesson.

[0048] In this embodiment of the present invention, the selection of the Gini index ensures that each tree minimizes the uncertainty of the categories when splitting, thereby improving the final prediction accuracy. Through this splitting process, the decision tree can be flexibly adjusted according to the different characteristics of the data, thereby improving the accuracy of the model.

[0049] S206: Combining the trained decision trees to form a random forest-based chip data detection model.

[0050] In a possible implementation, the chip data detection model is specifically:

[0051]

[0052] in, Represents the predicted category of the output, L represents the total number of decision trees, Indicates the The prediction of the decision tree for the input feature x, Represents the indicator function, when When the predicted category of a tree is k, ,otherwise, , It means selecting the prediction category k that maximizes the function from all possible prediction categories k.

[0053] Specifically, by combining singular value decomposition (SVD) with the random forest algorithm, SVD is used to extract high-information features from dynamic power data and perform dimensionality reduction. Feature sampling and merging are then used to optimize the feature set, enabling the random forest model to more efficiently identify and classify abnormal patterns in chip data. Furthermore, by proportionally extracting high- and low-information features and constructing multiple decision trees, the model's robustness and generalization capabilities are effectively improved, avoiding overfitting and thereby enhancing the accuracy and stability of chip data detection.

[0054] S3: Determine whether the chip's structural complexity is less than a preset structural complexity. If so, proceed to S4. Otherwise, proceed to S5.

[0055] Structural complexity refers to a metric that measures the overall complexity of a chip, system, or other engineering design based on its components, modules, connectivity, clock domains, and other factors. In chip design, structural complexity typically involves multiple aspects, including the hardware design hierarchy, the number of modules, signal interaction, and clock distribution.

[0056] It should be noted that those skilled in the art can set the size of the preset structural complexity according to actual needs, and the present invention does not limit this.

[0057] In a possible implementation, the structural complexity is calculated as follows:

[0058]

[0059] Among them, C represents the complexity discrimination coefficient, α and β represent weighting coefficients, Indicates the number of multi-clock domain modules, Indicates the total number of chip modules, p g Indicates the ratio of the number of modules in the gth clock domain to the total number of modules on the chip, G represents the total number of clock domains, represents the logarithmic function with base 2, Represents the entropy of the clock domain distribution.

[0060] In this embodiment of the present invention, the decision to use a simple or complex denoising method is based on the chip's structural complexity. If the structural complexity is low and the chip design is relatively simple, Bayesian filtering can be used. Conversely, if the chip design is complex, potentially including complex structures such as multiple clock domains, more powerful deep learning methods (such as bidirectional LSTM) are required to process complex data. This improves processing efficiency while avoiding the use of inefficient processing methods on complex chips. This optimizes the processing flow, reduces computational overhead, and achieves higher performance and accuracy in complex chip designs.

[0061] S4: Using a Bayesian filtering algorithm to perform denoising on the dynamic power data to obtain first denoised power data, and then proceeding to S6.

[0062] Bayesian filtering, a recursive algorithm based on Bayes' theorem, is widely used in fields such as signal processing, state estimation, target tracking, and data fusion. Its core idea is to recursively estimate the system state, combining prior knowledge with observed data to continuously correct and update the estimate.

[0063] It should be noted that the Bayesian filtering algorithm is a prior art and will not be described in detail in the present invention.

[0064] The primary benefit of Bayesian filtering for denoising dynamic power data is its ability to effectively extract the true signal from the noise. By combining prior information with real-time observations to recursively update the estimate, it reduces noise interference and improves the accuracy, smoothness, and stability of the power data. This not only removes errors caused by instantaneous fluctuations but also provides uncertainty in the estimate, assisting in subsequent decision-making and anomaly detection. It is particularly suitable for real-time data processing in high-noise environments.

[0065] S5: Use a bidirectional long short-term memory network to denoise the dynamic power data to obtain second denoised power data, and enter S7.

[0066] The Bidirectional Long Short-Term Memory (Bi-LSTM) network is an improved recurrent neural network that is particularly suitable for processing and predicting time series data, such as tasks such as speech recognition, natural language processing, and time series analysis. By combining forward LSTM and backward LSTM, it can capture information from both the past and future directions of the data. This makes it more powerful than traditional LSTM and suitable for tasks that require understanding global context.

[0067] In one possible implementation, the bidirectional long short-term memory network includes a forward long short-term memory network and a backward long short-term memory network; S5 specifically includes:

[0068] S501: Initialize the network parameters of the bidirectional long short-term memory network including the forward and backward LSTM modules. In each LSTM unit, the dynamic power data is processed through the gating structure including the input gate, forget gate, and output gate:

[0069]

[0070]

[0071]

[0072] in, represents the output of the input gate at the current time step p, represents the Sigmoid activation function, represents the weight matrix of the input gate, represents the hidden state of the previous time step p-1, represents the dynamic power data of the current time step p, represents the bias vector of the output gate, represents the output of the forget gate at the current time step p, represents the weight matrix of the forget gate, represents the bias vector of the forget gate, represents the output of the output gate at the current time step p, represents the weight matrix of the output gate, Represents the bias vector of the output gate.

[0073] S502: Use the gated value output by the gated structure to update the memory unit state at the current time step:

[0074]

[0075] in, represents the state of the memory cell at the current time step p, represents the state of the memory cell at the previous time step p-1, represents the hyperbolic tangent activation function, represents the weight matrix for updating the memory cell state, Represents the bias vector for updating the memory cell state.

[0076] In this embodiment of the present invention, at each time step of the LSTM, the gating structure of the input gate, forget gate, and output gate effectively determines which information to pass through and which to discard, thereby ensuring that the model focuses on key features and removes irrelevant noise at every moment in the dynamic power data. This gating mechanism ensures that important information is not lost during the denoising process.

[0077] S503: Calculate the hidden state of the timing information extracted from the dynamic power data at the current time step:

[0078]

[0079] in, represents the hidden state at the current time step p.

[0080] S504: Fuse the forward output and the reverse output to form a comprehensive output containing information of the forward and backward long short-term memory networks:

[0081]

[0082] in, represents the combined output of the forward and backward LSTM information, represents the weight of the forward LSTM output, represents the output of the forward LSTM at the current time step p, represents the weight of the backward LSTM output, represents the output of the backward LSTM at the current time step p, Represents the bias term after fusion.

[0083] S505: Based on the comprehensive output, the attention mechanism is introduced to calculate the attention score of each feature:

[0084]

[0085] in, represents the attention score of the feature at the current time step, represents the weight matrix of the attention mechanism, represents the weight matrix of the input features, The weight matrix representing historical features, represents the features of the previous time step, Bias vector representing the attention scores.

[0086] Specifically, the bidirectional LSTM can simultaneously leverage past and future contextual information, which is very useful for processing data with complex temporal dependencies, such as dynamic power data. Through the attention mechanism, the model can adaptively identify and focus on the most important time steps, thereby improving the accuracy and effectiveness of the denoising process.

[0087] S506: Normalize each attention score:

[0088]

[0089] in, represents the normalized attention score, z represents the total number of time steps, Indicates the exponential processing of attention scores.

[0090] S507: Perform weighted summation on the features of each time step according to the normalized attention weights to obtain the final weighted features:

[0091]

[0092] in, represents the final weighted feature, Represents the features of each time step, that is, the hidden state of the LSTM output.

[0093] In this embodiment of the present invention, an attention mechanism is introduced to the output of the Bi-LSTM, enabling the model to adjust feature weights based on the importance of each time step. By normalizing and weighting the attention scores, the model can more accurately focus on key features, further improving the denoising effect.

[0094] S508: Output the final weighted feature as the second denoising power data.

[0095] S6: Perform anomaly detection using a chip data detection model based on the first denoised power data.

[0096] Specifically, the first denoised power data is fed into a trained chip data detection model. The model analyzes and predicts the characteristics of the input data to determine whether the chip is abnormal. Specifically, the model classifies the data based on preset criteria (e.g., a normal power range or mode) and outputs a result indicating whether the chip is in a normal or abnormal state.

[0097] In this embodiment of the present invention, due to the relatively simple chip structure, anomaly detection based solely on de-noised power data can significantly reduce data processing complexity and computational overhead. Without the need to integrate additional complex data (such as logic activity data or other external information), this approach enables rapid judgment, saving time and computing resources, and is particularly suitable for real-time monitoring and rapid response scenarios.

[0098] S7: Obtain logic activity data of the chip, and use the second denoised power data and the logic activity data together to perform anomaly detection through a chip data detection model.

[0099] A chip's logic activity data refers to the signal activity or state changes generated by each module or functional unit within the chip as it executes tasks. This data reflects the activity of different circuits or logic blocks within the chip at a specific moment, such as when the chip performs calculations, transmits data, or executes control signals. Logic activity data is a key indicator of chip behavior and performance and is often used to evaluate chip workloads, optimize performance, and detect and diagnose faults.

[0100] Optionally, the logic activity data of the chip includes basic driving signals for internal chip operations, control signals used to drive different modules of the chip to perform specific tasks, and computing state changes of units performing computing tasks, which are also part of the logic activity data.

[0101] In a possible implementation, the method for obtaining the logical activity data specifically includes:

[0102] Calculate the dynamic power contribution of each module of the chip and select the target module with the largest dynamic power contribution.

[0103] Extract preliminary logic activity data of the chip in the target module.

[0104] The preliminary logic activity data is standardized to obtain the logic activity data of the chip.

[0105] In an embodiment of the present invention, by focusing on the most important modules in the chip that contribute the most to dynamic power consumption and extracting and standardizing logic activity data, data processing efficiency can be improved, subsequent analysis can be simplified, and a more accurate and efficient basis can be provided for subsequent optimization, fault detection, and performance improvement.

[0106] In a possible implementation, using the second denoised power data and the logic activity data together in S7 to perform anomaly detection using a chip data detection model specifically includes:

[0107] S701: Interpolate logic activity data based on the chip's clock tree structure:

[0108]

[0109] in, Indicates the value of the logical activity data after interpolation at time t, L n represents the logic activity vector captured at the nth clock cycle, N represents the total number of clock cycles, t n Indicates the time t corresponding to the nth clock cycle, t indicates the time t, represents the Dirac function, represents the Gaussian function, represents the smoothing factor.

[0110] It's important to note that the primary purpose of the clock tree is to ensure clock signal synchronization between modules within a chip. It distributes clock signals from the chip's clock source (typically a clock generator or external clock input) to all clock domains, ensuring that all modules within the chip receive accurate clock signals at the same time for synchronized operation.

[0111] In this embodiment of the present invention, logic activity is aligned using a Gaussian interpolation method based on the chip's clock tree structure, synchronizing logic activity data with power data in the temporal dimension. This ensures consistent temporal alignment during subsequent feature construction and fusion. This allows for a more realistic restoration of the relationship between logic and power consumption during chip operation, enhancing the model's ability to model causal relationships.

[0112] S702: Based on the interpolated logic activity data, construct a power-related representation of the chip when generating logic activity:

[0113]

[0114] in, represents the power-related representation constructed from the interpolated logical activity data. represents the activation function, represents the weight matrix used to map the input logical activity vector to another space, Indicates the value of the logical activity data after interpolation processing, represents the bias term.

[0115] In this embodiment of the present invention, a neural network is used to perform nonlinear mapping on the aligned logic activity data to obtain a feature representation related to power behavior. This "learning" of features strongly associated with power consumption behavior from the original logic activity makes the logic activity not just an input, but a representation that semantically matches the power data, making it easier to effectively integrate with the power data.

[0116] S703: Dynamically fuse the second denoised power data and the power-related representation of the chip when generating logical activity through a cross-attention mechanism to obtain a fused feature:

[0117]

[0118]

[0119] in, represents the fusion feature, Representation layer normalization, Indicates the weight of controlling dynamic power data, Indicates the weight of the control logic activity data, represents the feature representation of the second denoised power data, Characteristic representation of logical activity data, express activation function, A query matrix representing the logical activity data, represents the weight matrix used to transform logical activity data into query vectors, represents the key matrix of the second denoised power data, represents the weight matrix used to transform the second denoised power data into a query vector, T represents the transpose of the matrix, d represents the vector dimension of the query matrix and the key matrix, represents the query matrix of the second denoised power data, represents a weight matrix for converting the second denoised power data into a key vector, a key matrix representing the logical activity data, Represents the weight matrix used to convert logical activity data into a key vector.

[0120] In this embodiment of the present invention, the cross-attention mechanism not only allows the model to dynamically decide whether to focus on power data or logic activity data based on the current context, but also allows it to explore the interdependence and influence between the two, thereby forming a highly synergistic fusion feature. This mechanism is more flexible and intelligent than simple splicing or averaging fusion methods, and can better adapt to dynamic changes in chip status.

[0121] S704: Input the fused features into the chip data detection model and output the chip anomaly detection results.

[0122] Specifically, the system first extracts features from the denoised power data and logic activity data to obtain their respective feature representations. Next, it uses a cross-attention mechanism to dynamically adjust the weighting relationship between the power and logic activity data through the interaction of query, key, and value matrices. This dynamic weighting enables the model to automatically determine whether to prioritize power data or logic activity data based on the current input features, thereby improving the model's sensitivity and accuracy in detecting chip anomalies. The cross-attention mechanism not only integrates the two types of data but also accurately captures the complex relationships between them through an adaptive weighting strategy. This effectively improves the accuracy and robustness of anomaly detection when dealing with complex chip structures and diverse workloads.

[0123] In a possible implementation, the abnormality detection result of the chip includes: a normal chip and an abnormal chip.

[0124] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0125] In this embodiment of the present invention, a Bayesian filtering algorithm is used for denoising chips with lower structural complexity, while a bidirectional long short-term memory (Bi-LSTM) network is used for processing chips with higher structural complexity, effectively improving denoising accuracy. Secondly, when performing joint detection on chips with higher structural complexity, the detection model fully considers the correlations between different data sources (such as dynamic power data and logic activity data), significantly improving the comprehensiveness and accuracy of anomaly detection.

[0126] Reference Manual Figure 2 , shows a structural diagram of an artificial intelligence-based chip data detection system provided by an embodiment of the present invention.

[0127] The embodiment of the present invention provides an artificial intelligence-based chip data detection system 20, comprising: a processor 201 and a memory 202;

[0128] The memory 202 stores programs or instructions that can be run on the processor 201. When the programs or instructions are executed by the processor 201, the steps of the above-mentioned artificial intelligence-based chip data detection method are implemented and the same technical effects can be achieved. To avoid repetition, the present invention will not go into details.

[0129] It should be understood that the processor 201 in the embodiment of the present invention may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0130] It should also be understood that the memory 202 in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0131] The above embodiments can be implemented in whole or in part via software, hardware (e.g., circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0132] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0133] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0134] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0135] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0136] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0137] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0138] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0139] An embodiment of the present invention provides a readable storage medium including: a program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the above-mentioned artificial intelligence-based chip data detection method are implemented, and the same technical effect can be achieved. To avoid repetition, the present invention will not be repeated.

[0140] Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A chip data detection method based on artificial intelligence, characterized in that: include: S1: Obtain dynamic power data of the chip; S2: Build a random forest-based chip data detection model; S3: Determine whether the structural complexity of the chip is less than a preset structural complexity; if so, proceed to S4; otherwise, proceed to S5; S4: De-noising the dynamic power data using a Bayesian filtering algorithm to obtain first de-noised power data, and then proceeding to S6; S5: De-noising the dynamic power data using a bidirectional long short-term memory network to obtain second de-noised power data, and then proceeding to S7; S6: Performing anomaly detection using the chip data detection model based on the first denoised power data; S7: Acquire logic activity data of the chip, and use the second denoised power data and the logic activity data together to perform anomaly detection using the chip data detection model; The chip data detection model is specifically: ； in, Represents the predicted category of the output, L represents the total number of decision trees, Indicates the The prediction of the decision tree for the input feature x, Represents the indicator function, when When the predicted category of a tree is k, ,otherwise, , Indicates that the prediction category k corresponding to the maximum function is selected from all possible prediction categories k; The calculation method of the structural complexity is specifically as follows: ； Among them, C represents the complexity discrimination coefficient, α and β represent weighting coefficients, Indicates the number of multi-clock domain modules, Indicates the total number of chip modules, p g Indicates the ratio of the number of modules in the gth clock domain to the total number of modules on the chip, G represents the total number of clock domains, represents the logarithmic function with base 2, represents the entropy of the clock domain distribution; The method for obtaining the logical activity data specifically includes: Calculating the dynamic power contribution of each module of the chip and selecting the target module with the maximum dynamic power contribution; extracting preliminary logic activity data of the chip in the target module; The preliminary logic activity data is standardized to obtain logic activity data of the chip.

2. The chip data detection method based on artificial intelligence according to claim 1, characterized in that: The S2 specifically includes: S201: performing singular value decomposition on the dynamic power data; S202: sorting the singular values ​​in descending order, selecting features corresponding to a preset number of singular values ​​to form a high-information feature set, and combining features corresponding to the remaining singular values ​​to form a low-information feature set; S203: performing type sampling from the high-information feature set and the low-information feature set according to a preset ratio to form a merged feature set; S204: constructing multiple decision trees based on the combined feature set, and selecting the best splitting feature for each decision tree based on the Gini index; S205: performing step-by-step splitting according to each of the optimal splitting features until the maximum tree depth is reached, thereby completing the training of each of the decision trees; S206: Combining the trained decision trees to form a random forest-based chip data detection model.

3. The chip data detection method based on artificial intelligence according to claim 1, characterized in that: The bidirectional long short-term memory network includes a forward long short-term memory network and a backward long short-term memory network; S5 specifically includes: S501: Initializing network parameters of a bidirectional long short-term memory network including forward and backward LSTM modules. In each LSTM unit, information processing is performed on the dynamic power data through a gating structure including an input gate, a forget gate, and an output gate. S502: Using the gate value output by the gate structure to update the memory unit state of the current time step; S503: Calculating the hidden state of the timing information extracted from the dynamic power data at the current time step; S504: Fusing the forward output and the backward output to form a comprehensive output containing information of the forward and backward long short-term memory networks; S505: Based on the comprehensive output, introduce an attention mechanism to calculate the attention score of each feature; S506: performing normalization processing on each of the attention scores; S507: Perform weighted summation on the features of each time step according to the normalized attention weights to obtain the final weighted features; S508: Output the final weighted feature as the second denoising power data.

4. The chip data detection method based on artificial intelligence according to claim 1, characterized in that: The use of the second denoised power data and the logic activity data together in S7 to perform anomaly detection using the chip data detection model specifically includes: S701: Performing interpolation processing on the logic activity data based on the clock tree structure of the chip; S702: Constructing a power-related representation of the chip when generating logic activity based on the interpolated logic activity data; S703: Dynamically fuse the second denoised power data and the power-related representation of the chip when generating logical activity through a cross-attention mechanism to obtain a fused feature; S704: Input the fusion features into the chip data detection model, and output the abnormality detection result of the chip.

5. The chip data detection method based on artificial intelligence according to claim 4, characterized in that: The abnormality detection results of the chips include: normal chips and abnormal chips.

6. A chip data detection system based on artificial intelligence, characterized in that: include: processor and memory; The memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the artificial intelligence-based chip data detection method as described in any one of claims 1 to 5 are implemented.

7. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the chip data detection method based on artificial intelligence as described in any one of claims 1 to 5 are implemented.

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