Interrupt processing method and device, equipment, storage medium and program product

Abstract

The invention provides an interrupt processing method and device, equipment, a storage medium and a program product, and the method comprises the steps: obtaining a first interrupt generated by a first virtual processor, and determining the interrupt information of the first interrupt; in response to the first interruption, an interruption sending code is determined in the target memory, the interruption sending code is used for indicating interruption sending in a non-root mode, and the interruption sending code is a code obtained after an original code of sending interruption is updated; and transmitting the first interrupt in a non-root mode according to the interrupt information and the interrupt transmission code. And the transmission interruption efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to an interrupt processing method, apparatus, device, storage medium, and program product. Background Art

[0002] A server may be provided with a virtual machine, which includes a virtual central processing unit (vCPU).

[0003] Cloud applications (e.g., cloud games) can run in virtual machines. In related technologies, when running cloud applications, a virtual processor generates a large number of inter-processor interrupts (IPIs), sending IPIs to other virtual processors. However, each IPI sent requires two switches between root mode and non-root mode, resulting in low interrupt sending efficiency. Summary of the Invention

[0004] Various aspects of the present application provide an interrupt handling method, apparatus, device, storage medium, and program product to improve the efficiency of sending interrupts.

[0005] In a first aspect, an embodiment of the present application provides an interrupt handling method, comprising:

[0006] Obtaining a first interrupt generated by a first virtual processor, and determining interrupt information of the first interrupt;

[0007] In response to the first interrupt, determining an interrupt sending code in a target memory, wherein the interrupt sending code is used to instruct interrupt sending in a non-root mode, and the interrupt sending code is a code that is updated from an original code for sending the interrupt;

[0008] Send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

[0009] In a possible implementation, the target memory further includes at least one issued interrupt PI description information; and sending the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code includes:

[0010] Call the interrupt sending code to perform the following steps:

[0011] determining a second virtual processor according to the interrupt information;

[0012] Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information.

[0013] In a possible implementation, sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information includes:

[0014] Determining PI description information corresponding to the second virtual processor from the at least one PI description information;

[0015] Performing configuration processing on the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information;

[0016] The first interrupt is sent to the second virtual processor according to the target PI description information and a preset PI interrupt vector corresponding to the first virtual processor.

[0017] In a possible implementation, sending the first interrupt to the second virtual processor according to the target PI description information and the preset PI interrupt vector includes:

[0018] Writing the preset PI interrupt vector into the preset register;

[0019] In response to the completion of writing the preset PI interrupt vector into the preset register, the first interrupt is sent to the second virtual processor according to the target PI description information.

[0020] In a possible implementation, determining the PI description information corresponding to the second virtual processor in the at least one PI description information includes:

[0021] Acquire a preset mapping relationship in the target memory, where the preset mapping relationship includes an identifier of at least one virtual processor and PI description information corresponding to the identifier of each virtual processor;

[0022] The PI description information corresponding to the second virtual processor is determined according to the identifier of the second virtual processor and the preset mapping relationship.

[0023] In one possible implementation, determining the interrupt sending code in the target memory includes:

[0024] Obtaining a flag value from the virtual machine control structure VMCS information corresponding to the first virtual processor;

[0025] When the flag value is a first preset value and there is a code in the second storage space of the target memory, determining the code in the second storage space as the interrupt sending code;

[0026] The first preset value is used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor.

[0027] In a possible implementation manner, if the flag value is a second preset value, the second preset value is used to indicate that the first interrupt is the first interrupt generated by the first virtual processor, and the method further includes:

[0028] Sending the first interruption according to the interruption information and the original code for sending the interruption;

[0029] Updating the flag value to the first preset value, determining the preset PI interrupt vector in the VMCS information, and storing the preset PI interrupt vector in a first storage space;

[0030] The original code is updated to the interrupt sending code.

[0031] In a possible implementation, updating the original code to the interrupt sending code includes:

[0032] generating a replacement code according to a starting position of the interrupt sending code in the second storage space, wherein the replacement code is used to instruct execution of the interrupt sending code at the starting position;

[0033] The original code is updated to the replacement code.

[0034] In a possible implementation, the first virtual processor is a virtual processor in a virtual machine, and the method further includes:

[0035] When the virtual machine is initialized, allocating the target memory to the virtual machine;

[0036] At least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information are generated in the target memory.

[0037] In a second aspect, an embodiment of the present application provides an interrupt processing method, including:

[0038] Obtaining a first interrupt generated by a first virtual processor and determining interrupt information of the first interrupt, where the first virtual processor is used to process cloud services, including cloud gaming services and cloud rendering services;

[0039] In response to the first interrupt, determining an interrupt sending code in a target memory, wherein the interrupt sending code is used to instruct interrupt sending in a non-root mode, and the interrupt sending code is a code that is updated from an original code for sending the interrupt;

[0040] Send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

[0041] In a possible implementation, the target memory further includes at least one issued interrupt PI description information; and sending the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code includes:

[0042] Call the interrupt sending code to perform the following steps:

[0043] determining a second virtual processor according to the interrupt information;

[0044] Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information.

[0045] In a possible implementation, sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information includes:

[0046] Determining PI description information corresponding to the second virtual processor from the at least one PI description information;

[0047] Performing configuration processing on the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information;

[0048] The first interrupt is sent to the second virtual processor according to the target PI description information and a preset PI interrupt vector corresponding to the first virtual processor.

[0049] In a possible implementation, sending the first interrupt to the second virtual processor according to the target PI description information and the preset PI interrupt vector includes:

[0050] Writing the preset PI interrupt vector into the preset register;

[0051] In response to the completion of writing the preset PI interrupt vector into the preset register, the first interrupt is sent to the second virtual processor according to the target PI description information.

[0052] In a possible implementation, determining the PI description information corresponding to the second virtual processor in the at least one PI description information includes:

[0053] Acquire a preset mapping relationship in the target memory, where the preset mapping relationship includes an identifier of at least one virtual processor and PI description information corresponding to the identifier of each virtual processor;

[0054] The PI description information corresponding to the second virtual processor is determined according to the identifier of the second virtual processor and the preset mapping relationship.

[0055] In one possible implementation, determining the interrupt sending code in the target memory includes:

[0056] Obtaining a flag value from the virtual machine control structure VMCS information corresponding to the first virtual processor;

[0057] When the flag value is a first preset value and there is a code in the second storage space of the target memory, determining the code in the second storage space as the interrupt sending code;

[0058] The first preset value is used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor.

[0059] In a possible implementation manner, if the flag value is a second preset value, the second preset value is used to indicate that the first interrupt is the first interrupt generated by the first virtual processor, and the method further includes:

[0060] Sending the first interruption according to the interruption information and the original code for sending the interruption;

[0061] Updating the flag value to the first preset value, determining the preset PI interrupt vector in the VMCS information, and storing the preset PI interrupt vector in a first storage space;

[0062] The original code is updated to the interrupt sending code.

[0063] In a possible implementation, updating the original code to the interrupt sending code includes:

[0064] generating a replacement code according to a starting position of the interrupt sending code in the second storage space, wherein the replacement code is used to instruct execution of the interrupt sending code at the starting position;

[0065] The original code is updated to the replacement code.

[0066] In a possible implementation, the first virtual processor is a virtual processor in a virtual machine, and the method further includes:

[0067] When the virtual machine is initialized, allocating the target memory to the virtual machine;

[0068] At least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information are generated in the target memory.

[0069] In a third aspect, an embodiment of the present application provides an interrupt processing device, comprising: an acquisition module, a determination module, and a first sending module, wherein:

[0070] The acquisition module is used to acquire a first interrupt generated by a first virtual processor and determine interrupt information of the first interrupt;

[0071] The determining module is configured to, in response to the first interrupt, determine an interrupt sending code in a target memory, wherein the interrupt sending code is used to indicate that an interrupt is sent in a non-root mode, and the interrupt sending code is a code updated from an original code for sending the interrupt;

[0072] The first sending module is configured to send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

[0073] In a possible implementation manner, the target memory further includes at least one issued interrupt PI description information; and the first sending module is specifically configured to:

[0074] Call the interrupt sending code to perform the following steps:

[0075] determining a second virtual processor according to the interrupt information;

[0076] Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information.

[0077] In a possible implementation manner, the first sending module is specifically configured to:

[0078] Determining PI description information corresponding to the second virtual processor from the at least one PI description information;

[0079] Performing configuration processing on the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information;

[0080] The first interrupt is sent to the second virtual processor according to the target PI description information and a preset PI interrupt vector corresponding to the first virtual processor.

[0081] In a possible implementation manner, the first sending module is specifically configured to:

[0082] Writing the preset PI interrupt vector into the preset register;

[0083] In response to the completion of writing the preset PI interrupt vector into the preset register, the first interrupt is sent to the second virtual processor according to the target PI description information.

[0084] In a possible implementation manner, the first sending module is specifically configured to:

[0085] Acquire a preset mapping relationship in the target memory, where the preset mapping relationship includes an identifier of at least one virtual processor and PI description information corresponding to the identifier of each virtual processor;

[0086] The PI description information corresponding to the second virtual processor is determined according to the identifier of the second virtual processor and the preset mapping relationship.

[0087] In a possible implementation, the determining module is specifically configured to:

[0088] Obtaining a flag value from the virtual machine control structure VMCS information corresponding to the first virtual processor;

[0089] When the flag value is a first preset value and there is a code in the second storage space of the target memory, determining the code in the second storage space as the interrupt sending code;

[0090] The first preset value is used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor.

[0091] In a possible implementation manner, if the flag value is a second preset value, the second preset value is used to indicate that the first interrupt is the first interrupt generated by the first virtual processor, and the apparatus further includes: a second sending module and an updating module, wherein,

[0092] The second sending module is used to send the first interruption according to the interruption information and the original code for sending the interruption;

[0093] The updating module is configured to update the flag value to the first preset value, determine the preset PI interrupt vector in the VMCS information, and store the preset PI interrupt vector in the first storage space;

[0094] The updating module is used for updating the original code to the interrupt sending code.

[0095] In a possible implementation, the update module is specifically configured to:

[0096] generating a replacement code according to a starting position of the interrupt sending code in the second storage space, wherein the replacement code is used to instruct execution of the interrupt sending code at the starting position;

[0097] The original code is updated to the replacement code.

[0098] In a possible implementation, the first virtual processor is a virtual processor in a virtual machine, and the apparatus further includes an allocation module and a generation module, wherein:

[0099] The allocation module is used to allocate the target memory to the virtual machine when the virtual machine is initialized;

[0100] The generating module is used to generate at least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information in the target memory.

[0101] In a fourth aspect, an embodiment of the present application provides an interrupt processing device, comprising: an acquisition module, a determination module, and a first sending module, wherein:

[0102] The acquisition module is configured to acquire a first interrupt generated by a first virtual processor and determine interrupt information of the first interrupt, wherein the first virtual processor is configured to process cloud services, including cloud gaming services and cloud rendering services;

[0103] The determining module is configured to, in response to the first interrupt, determine an interrupt sending code in a target memory, wherein the interrupt sending code is used to indicate that an interrupt is sent in a non-root mode, and the interrupt sending code is a code updated from an original code for sending the interrupt;

[0104] The first sending module is configured to send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

[0105] In a possible implementation manner, the target memory further includes at least one issued interrupt PI description information; and the first sending module is specifically configured to:

[0106] Call the interrupt sending code to perform the following steps:

[0107] determining a second virtual processor according to the interrupt information;

[0108] Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information.

[0109] In a possible implementation manner, the first sending module is specifically configured to:

[0110] Determining PI description information corresponding to the second virtual processor from the at least one PI description information;

[0111] Performing configuration processing on the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information;

[0112] The first interrupt is sent to the second virtual processor according to the target PI description information and a preset PI interrupt vector corresponding to the first virtual processor.

[0113] In a possible implementation manner, the first sending module is specifically configured to:

[0114] Writing the preset PI interrupt vector into the preset register;

[0115] In response to the completion of writing the preset PI interrupt vector into the preset register, the first interrupt is sent to the second virtual processor according to the target PI description information.

[0116] In a possible implementation manner, the first sending module is specifically configured to:

[0117] Acquire a preset mapping relationship in the target memory, where the preset mapping relationship includes an identifier of at least one virtual processor and PI description information corresponding to the identifier of each virtual processor;

[0118] The PI description information corresponding to the second virtual processor is determined according to the identifier of the second virtual processor and the preset mapping relationship.

[0119] In a possible implementation, the determining module is specifically configured to:

[0120] Obtaining a flag value from the virtual machine control structure VMCS information corresponding to the first virtual processor;

[0121] When the flag value is a first preset value and there is a code in the second storage space of the target memory, determining the code in the second storage space as the interrupt sending code;

[0122] The first preset value is used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor.

[0123] In a possible implementation manner, if the flag value is a second preset value, the second preset value is used to indicate that the first interrupt is the first interrupt generated by the first virtual processor, and the apparatus further includes: a second sending module and an updating module, wherein,

[0124] The second sending module is used to send the first interruption according to the interruption information and the original code for sending the interruption;

[0125] The updating module is configured to update the flag value to the first preset value, determine the preset PI interrupt vector in the VMCS information, and store the preset PI interrupt vector in the first storage space;

[0126] The updating module is used for updating the original code to the interrupt sending code.

[0127] In a possible implementation, the update module is specifically configured to:

[0128] generating a replacement code according to a starting position of the interrupt sending code in the second storage space, wherein the replacement code is used to instruct execution of the interrupt sending code at the starting position;

[0129] The original code is updated to the replacement code.

[0130] In a possible implementation, the first virtual processor is a virtual processor in a virtual machine, and the apparatus further includes an allocation module and a generation module, wherein:

[0131] The allocation module is used to allocate the target memory to the virtual machine when the virtual machine is initialized;

[0132] The generating module is used to generate at least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information in the target memory.

[0133] In a fifth aspect, an embodiment of the present application provides an electronic device, including: a memory and a processor;

[0134] The memory stores computer-executable instructions;

[0135] The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of the first aspects.

[0136] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, which are used to implement the method described in any one of the first aspects when the computer-executable instructions are executed by a processor.

[0137] In a seventh aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which, when executed by a processor, implements the method shown in any one of the first aspects.

[0138] Embodiments of the present application provide an interrupt handling method, apparatus, device, storage medium, and program product that can obtain a first interrupt generated by a first virtual processor and determine interrupt information of the first interrupt; can determine an interrupt sending code in a target memory, and can then send the first interrupt in non-root mode based on the interrupt information and the interrupt sending code. Because the interrupt sending code can be executed to send the first interrupt in non-root mode, compared to the prior art, there is no need to switch between root mode and non-root mode, thereby improving the efficiency of sending interrupts. BRIEF DESCRIPTION OF THE DRAWINGS

[0139] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0140] Figure 1 A schematic diagram of a scenario provided for an exemplary embodiment of the present application;

[0141] Figure 2 A process diagram of an interrupt handling method in related art;

[0142] Figure 3 A flowchart of an interrupt handling method provided by an exemplary embodiment of the present application;

[0143] Figure 4 A flowchart of another interrupt handling method provided by an exemplary embodiment of the present application;

[0144] Figure 5 A schematic diagram of a target memory provided for an exemplary embodiment of the present application;

[0145] Figure 6 A schematic diagram of a process of an interrupt handling method provided by an exemplary embodiment of the present application;

[0146] Figure 7 A schematic diagram of the structure of an interrupt processing device is provided for an embodiment of the present application;

[0147] Figure 8 A schematic structural diagram of another interrupt processing device provided by an exemplary embodiment of the present application;

[0148] Figure 9 A schematic structural diagram of an electronic device provided as an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0149] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0150] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0151] Figure 1 This is a schematic diagram of a scenario provided by an exemplary embodiment of this application. Figure 1 , the server may include at least one virtual machine.

[0152] A virtual machine may include multiple virtual processors. For example, virtual machine 1 may include n virtual processors, namely virtual processor 0, virtual processor 1, ..., virtual processor n.

[0153] A virtual machine may be equipped with a cloud application. Multiple threads may be generated while the virtual machine is running a cloud application. Because the mutual notification mechanism between these multiple threads is based on IPIs, a large number of IPIs may be generated while the virtual machine is running a cloud application. Within a virtual machine, any virtual processor can send an interrupt to other virtual processors. For example, virtual processor 0 can send an interrupt to virtual processor 1.

[0154] In the related art, when running cloud applications, virtual processors generate a large number of IPIs and send IPIs to other virtual processors. However, each IPI transmission requires two switches between root mode and non-root mode, which takes a long time and results in low interrupt transmission efficiency.

[0155] In an embodiment of the present application, an interrupt sending code may be provided in the target memory. A first interrupt generated by a first virtual processor may be obtained, and an interrupt sending code may be determined in the target memory. Then, based on the interrupt sending code and interrupt information, the first interrupt may be sent in non-root mode. Because the interrupt sending code may be executed to send the first interrupt in non-root mode, compared to the prior art, there is no need to switch between root mode and non-root mode, thereby improving the efficiency of sending interrupts.

[0156] Next, an interrupt handling method in related art is introduced.

[0157] Figure 2 This is a process diagram of an interrupt handling method in related technology. Figure 2 , the server includes root mode and non-root mode.

[0158] The server can support Extended Advanced Programmable Interrupt Controller (x2APIC) mode. x2APIC mode is an extended advanced programmable interrupt controller (xAPIC) mode used to manage and distribute interrupts in multiprocessor systems. Compared to the traditional APIC mode, x2APIC provides higher performance and flexibility.

[0159] A virtual machine may be run in the server, and the virtual machine includes at least one virtual processor. The virtual processor is run based on a physical core in a physical processor. A first virtual processor may be run based on a first physical core in a first physical processor.

[0160] For any virtual processor, the virtual processor may have a corresponding virtual interrupt command register (ICR).

[0161] For example, under the condition that the server supports x2APIC mode, in non-root mode, after virtual processor 1 generates interrupt 1, if virtual processor 1 is running based on physical core 1 and if virtual processor 1 corresponds to virtual ICR register 1, physical core 1 can determine interrupt information 1 of interrupt 1 and write interrupt information 1 in virtual ICR register 1.

[0162] Physical core 1 can switch from non-root mode to root mode. In root mode, physical core 1 can obtain interrupt information 1 from virtual ICR register 1 through a kernel-based virtual machine (KVM), and determine that the second virtual processor is virtual processor 1 based on interrupt information 1.

[0163] Physical core 1 may determine posted interrupt (PI) description information 1 corresponding to virtual processor 1 and set PI description information 1 according to interrupt information 1 to send interrupt 1 to virtual processor 1 .

[0164] Physical core 1 can switch from root mode to non-root mode and continue to execute the next instruction in non-root mode.

[0165] exist Figure 2In the related art shown, each time an interrupt is sent, the first physical core needs to switch between the root mode and the non-root mode twice, resulting in low efficiency in sending interrupts.

[0166] The technical solutions shown in this application are described in detail below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be repeated in different embodiments.

[0167] Figure 3 This is a flowchart of an interrupt handling method provided by an exemplary embodiment of the present application. Figure 3 , the method may include:

[0168] S301: Acquire a first interrupt generated by a first virtual processor, and determine interrupt information of the first interrupt.

[0169] The execution subject of the embodiment of the present application can be the server where the first virtual processor is located, or the first physical processor corresponding to the first virtual processor, or the first physical core corresponding to the first virtual processor, or an interrupt processing device set in the first physical core. The interrupt processing device can be implemented by software or by a combination of software and hardware. For ease of understanding, the following description takes the execution subject as the first physical core as an example.

[0170] A virtual machine may be running in the server, and the virtual machine includes at least one virtual processor. The first virtual processor is a virtual processor in the virtual machine.

[0171] The first interrupt may be a processor interrupt generated by the first virtual processor. Since the first virtual processor runs based on the first physical core in the physical processor, the first interrupt generated by the first virtual processor is the first interrupt generated by the first physical core.

[0172] For the first interrupt, the interrupt information of the first interrupt may include the interrupt type, the distribution mode, the identifier of at least one second virtual processor, and the interrupt vector of the first interrupt.

[0173] Among them, the interrupt type may include a non-maskable interrupt (NMI) type, an initialization (INIT) interrupt type, a startup inter-processor interrupt (SIPI) type, and a generic inter-processor (Generic) interrupt type.

[0174] The distribution mode may include a bus broadcast mode and a direct interrupt mode, etc. The bus broadcast mode may be used to send interrupts to multiple virtual processors; the direct interrupt mode may be used to send interrupts to a specific virtual processor.

[0175] There may be at least one second virtual processor, and thus the interrupt information may include an identifier of at least one second virtual processor.

[0176] The interrupt vector can be used to configure the PI description information. For example, the interrupt vector can be "18".

[0177] The first physical core may obtain a first interrupt generated by the first virtual processor and determine interrupt information for the first interrupt. For example, if the first physical core is physical core 0 and the first virtual processor is virtual processor 0, physical core 0 may obtain a first interrupt 1 generated by virtual processor 0 and determine interrupt information 1 for the first interrupt 1. Assume that interrupt information 1 may include an interrupt type of Generic interrupt, a distribution mode of Direct interrupt mode, an identifier of the second virtual processor of vCPU-1, and an interrupt vector of 18.

[0178] After determining the interrupt information of the first interrupt, the first physical core may write the interrupt information into the virtual ICR register corresponding to the first virtual processor.

[0179] S302: In response to the first interrupt, determine an interrupt sending code in the target memory.

[0180] The target memory is the memory corresponding to the first virtual machine in the server. The first virtual machine is the virtual machine where the first virtual processor is located. The target memory is pre-stored with an interrupt sending code.

[0181] The interrupt sending code may be a code updated from the original code for sending the interrupt. The interrupt sending code may be used to indicate that the interrupt is sent in a non-root mode.

[0182] In an optional embodiment, the interrupt sending code can be determined in the target memory in the following manner: a flag value is obtained in the virtual machine control structure VMCS information corresponding to the first virtual processor; if the flag value is a first preset value and there is code in the second storage space of the target memory, the code in the second storage space is determined as the interrupt sending code.

[0183] For any virtual processor, the virtual processor may have corresponding Virtual Machine Control Structure (VMCS) information. The VMCS information may include the operation information of the virtual processor and the operation information of the physical core where the virtual processor resides. The VMCS information may include a target bit, and the value of the target bit may be a flag value.

[0184] The flag value may be a first preset value or a second preset value.

[0185] The first preset value may be used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor. For example, the first preset value may be "1".

[0186] The second preset value may be used to indicate that the first interrupt is the first interrupt generated by the first virtual processor. For example, the second preset value may be "0".

[0187] By using the flag value in the VMCS information, it is determined whether the first interrupt is the first interrupt generated by the first virtual processor. The judgment logic is simple and convenient, which improves the efficiency of determining whether the first interrupt is the first interrupt, thereby improving the efficiency of sending the first interrupt.

[0188] Optionally, the target memory may include a second storage space. The second storage space may be used to store the interrupt sending code so as to call the interrupt sending code.

[0189] For example, if the first physical core is physical core 0 and the first virtual processor is virtual processor 0, physical core 0 may determine VMCS information 0 corresponding to virtual processor 0 and obtain a flag value from VMCS information 0. If the flag value is a first preset value 1 and code 1 exists in the second storage space of the target memory, code 1 may be determined as the interrupt sending code.

[0190] S303: Send a first interrupt in a non-root mode according to the interrupt information and the interrupt sending code.

[0191] Optionally, the target memory may further include at least one PI description information. The PI description information corresponds one-to-one to the virtual processor. The PI description information may include an interrupt vector.

[0192] In an optional embodiment, the first interrupt can be sent in non-root mode according to the interrupt information and the interrupt sending code in the following manner: calling the interrupt sending code to perform the following steps: determining the second virtual processor according to the interrupt information; sending the first interrupt to the second virtual processor according to the interrupt information and at least one PI description information.

[0193] Since the first physical core can call the interrupt sending code, the second virtual processor is determined according to the interrupt information in the non-root mode, and then the first interrupt is sent to the second virtual processor according to the interrupt information and at least one PI description information. There is no need to switch between the root mode and the non-root mode, which reduces the resource overhead of sending interrupts and improves the efficiency of sending interrupts.

[0194] Since the interrupt information includes the identifier of the second virtual processor, the identifier of the second virtual processor can be determined from the interrupt information, and then the second virtual processor can be determined according to the identifier of the second virtual processor.

[0195] For example, if the first physical core is physical core 0, and if interrupt information 1 includes the identifier of the second virtual processor as vCPU-1, physical core 0 can call the interrupt sending code to determine, based on the identifier vCPU-1, that the corresponding second virtual processor is virtual processor 1. If the target memory includes 64 PI descriptions, physical core 0 can call the interrupt sending code to send the first interrupt 1 to virtual processor 1 based on interrupt information 1 and the 64 PI descriptions.

[0196] In an embodiment of the present application, the first physical core can obtain the first interrupt generated by the first virtual processor and determine the interrupt information of the first interrupt. In response to the first interrupt, the first physical core can determine the interrupt sending code in the target memory, and then send the first interrupt in non-root mode based on the interrupt information and the interrupt sending code. Since the interrupt sending code can be executed to send the first interrupt in non-root mode, compared with the existing technology, there is no need to switch between root mode and non-root mode, thereby improving the efficiency of sending interrupts.

[0197] In another optional embodiment, the technical solution of the present application also provides an interrupt processing method. The method may include: obtaining a first interrupt generated by a first virtual processor and determining the interrupt information of the first interrupt; in response to the first interrupt, determining an interrupt sending code in the target memory, the interrupt sending code is used to indicate interrupt sending in non-root mode, and the interrupt sending code is an updated code of the original code for sending the interrupt; according to the interrupt information and the interrupt sending code, sending the first interrupt in non-root mode. The first virtual processor can be used to process cloud services, which may include cloud gaming services, cloud rendering services, and other services.

[0198] In cloud scenarios, virtual processors generate a large number of interrupts. The technical solution of this application improves the efficiency of sending interrupts, thereby improving the efficiency of virtual processors in running cloud services.

[0199] Below, in Figure 3 Based on the embodiment shown, combined Figure 4 , the above interrupt handling method is explained in detail.

[0200] Figure 4 This is a flowchart of another interrupt handling method provided by an exemplary embodiment of the present application. Figure 4 , the method may include:

[0201] S401. When a virtual machine is initialized, target memory is allocated to the virtual machine.

[0202] When the virtual machine is started in the server, the first physical core may initialize the virtual machine through KVM and may allocate target memory for the virtual machine.

[0203] For example, if virtual machine 1 is started in a server, and if the first physical core is physical core 0, physical core 0 may allocate target memory 1 for virtual machine 1 when initializing virtual machine 1.

[0204] S402: Generate at least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information in the target memory.

[0205] For example, the preset mapping relationship may be as shown in Table 1:

[0206] Table 1

[0207] Virtual processor ID PI description information vCPU-1 PI description information 1 vCPU-2 PI description information 2 vCPU-3 PI description information 3 …… ……

[0208] Next, combine Figure 5 , describe the target memory.

[0209] Figure 5 A schematic diagram of a target memory provided for an exemplary embodiment of the present application. Figure 5 The target memory may include at least one PI description information and a preset mapping relationship, wherein the at least one PI description information may be PI description information 1, PI description information 2, ..., PI description information n.

[0210] For any PI description information, the PI description information may include multiple bits, which may include a bit corresponding to an interrupt vector and a bit corresponding to an interrupt incomplete flag.

[0211] S403: Acquire a first interrupt generated by the first virtual processor, and determine interrupt information of the first interrupt.

[0212] It should be noted that step S403 may refer to step S301 and will not be described in detail here.

[0213] S404: Obtain a flag value from the VMCS information corresponding to the first virtual processor.

[0214] Optionally, the first physical core may determine the VMCS information corresponding to the first virtual processor and obtain a flag value from the VMCS information. If the flag value is a first preset value, it indicates that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor. The first physical core may determine whether there is code in the second storage space of the target memory. If there is code in the second storage space, steps S408 to S412 may be executed. If the flag value is a second preset value, it indicates that the first interrupt is the first interrupt generated by the first virtual processor, and steps S405 to S407 may be executed.

[0215] S405 : When the flag value is the second preset value, send a first interrupt according to the interrupt information and the original code for sending the interrupt.

[0216] If the flag value is the second preset value, it means that the first interrupt is the first interrupt generated by the first virtual processor, and the first physical core can execute the original code for sending the interrupt and send the first interrupt to the second virtual processor according to the interrupt information.

[0217] For example, if the first physical core is physical core 0, if the interrupt information 1 of the first interrupt 1 includes the interrupt type as Generic interrupt, the distribution mode as direct interrupt mode, the identifier of the second virtual processor as vCPU-1, and the interrupt vector as 18, then physical core 0 can execute the original code for sending the interrupt and send the first interrupt 1 to virtual processor 1 according to the interrupt information 1.

[0218] S406 : Update the flag value to a first preset value, determine a preset PI interrupt vector in the VMCS information, and store the preset PI interrupt vector in the first storage space.

[0219] Since the flag value is the second preset value 0, the first physical core may update the flag value to the first preset value 1, so that when an interrupt is subsequently executed, step S408 may be determined to be executed according to the flag value being the first preset value.

[0220] The first physical core may further determine a preset PI interrupt vector corresponding to the first virtual processor from the VMCS information corresponding to the first virtual processor, and store the preset PI interrupt vector in a first storage space in the target memory so that the preset PI interrupt vector can be obtained when the interrupt sending code is subsequently executed to send an interrupt in non-root mode. The first storage space is accessible to the first physical core in non-root mode.

[0221] For example, if the first virtual processor is virtual processor 0, the preset PI interrupt vector 0 corresponding to virtual processor 0 may be stored in the first storage space.

[0222] S407: Update the original code to an interruption sending code.

[0223] In an optional embodiment, the original code for sending the interruption may be updated to the interruption sending code in the following manner: generating a replacement code according to the starting position of the interruption sending code in the second storage space; and updating the original code to the replacement code.

[0224] The original code for sending interrupts is the code that requires switching between root mode and non-root mode to send interrupts.

[0225] The replacement code may be used to indicate the interrupt sending code at the start location of execution.

[0226] The first physical core may determine the starting position of the interrupt sending code in the second storage space, and generate a replacement code according to the starting position, thereby updating the original code for sending the interrupt to the replacement code.

[0227] For example, if the first physical core is physical core 0, and if physical core 0 can determine that the starting location of the interrupt sending code in the second storage space is address A, then replacement code 1 can be generated based on address A, and the original code for sending the interrupt can be updated to replacement code 1. Replacement code 1 is used to indicate the execution of the interrupt sending code at address A.

[0228] S408: When the flag value is the first preset value and there is a code in the second storage space, determine the code in the second storage space as an interruption transmission code.

[0229] Since the second storage space is used to store the interruption sending code, if there is a code in the second storage space, the code can be determined as the interruption sending code.

[0230] For example, if the first physical core is physical core 0, and if code 1 exists in the second storage space, physical core 0 may determine code 1 as the interrupt sending code.

[0231] S409: Call the interrupt sending code to determine the second virtual processor according to the interrupt information.

[0232] Since the interrupt information includes the identifier of the second virtual processor, the first physical core can call the interrupt sending code to determine the identifier of the second virtual processor in the interrupt information, and then determine the second virtual processor according to the identifier of the second virtual processor.

[0233] For example, if the first physical core is physical core 0, and if the interrupt information includes an identifier of the second virtual processor as vCPU-1, physical core 0 may determine that the second virtual processor is virtual processor 1 according to the identifier vCPU-1.

[0234] S410: Call an interrupt sending code to determine PI description information corresponding to a second virtual processor in at least one PI description information.

[0235] In an optional embodiment, the PI description information corresponding to the second virtual processor can be determined in at least one PI description information in the following manner: obtaining a preset mapping relationship in the target memory; and determining the PI description information corresponding to the second virtual processor based on the identifier of the second virtual processor and the preset mapping relationship.

[0236] For example, if the first physical core is physical core 0, physical core 0 can call the interrupt sending code to obtain the preset mapping relationship in target memory 1, as shown in Table 1. If the identifier of the second virtual processor is vCPU-1, the second virtual processor can be determined in Table 1 based on the identifier vCPU-1, that is, the PI description information corresponding to virtual processor 1 is PI description information 1.

[0237] S411 : Calling an interrupt sending code to configure and process the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information.

[0238] The target PI description information may include multiple bits, and the multiple bits may include bits corresponding to the interrupt vector of the first interrupt.

[0239] Since the interrupt information includes the interrupt type, interrupt vector, and identifier of the second virtual processor of the first interrupt, the first physical core can call the interrupt sending code to configure and process the PI description information corresponding to the second virtual processor according to the interrupt information to obtain the target PI description information.

[0240] Optionally, the first physical core can call the interrupt sending code, determine the bit corresponding to the interrupt vector in the PI description information corresponding to the second virtual processor according to the interrupt vector, and update the initial value 0 of the bit to the target value 1. The bit corresponding to the interrupt incomplete flag in the PI description information (outstanding notification bit) can also be set to 1 to configure the PI description information and obtain the target PI description information.

[0241] For example, if the second virtual processor is virtual processor 1, virtual processor 1 corresponds to PI description information 1. If the interrupt information 1 includes the interrupt type as Generic interrupt, the identifier of the second virtual processor as vCPU-1, and the interrupt vector as 18, then the physical core 0 can call the interrupt sending code, determine the 18th bit in the PI description information 1 according to the interrupt vector 18 in the interrupt information 1, and update the value of the 18th bit to the target value 1. The bit position corresponding to the interrupt incomplete flag in the PI description information 1 can also be set to 1 to obtain the target PI description information 1.

[0242] S412: Call the interrupt sending code to send a first interrupt to the second virtual processor according to the target PI description information and the preset PI interrupt vector corresponding to the first virtual processor.

[0243] Since the preset PI interrupt vector corresponding to the first virtual processor has been determined in the VMCS information corresponding to the first virtual processor when executing the first interrupt generated by the first virtual processor, and the preset PI interrupt vector has been stored in the first storage space in the target memory, when executing a non-first interrupt, the first physical core can call the interrupt sending code in non-root mode and directly obtain the preset PI interrupt vector in the first storage space without switching to root mode to obtain the preset PI interrupt vector in the VMCS information.

[0244] For example, if the first virtual processor is virtual processor 0, the first physical core may obtain the preset PI interrupt vector 0 corresponding to virtual processor 0 in the first storage space.

[0245] In an optional embodiment, the first interrupt can be sent to the second virtual processor according to the target PI description information and the preset PI interrupt vector in the following manner: writing the preset PI interrupt vector in the preset register; in response to completing the writing of the preset PI interrupt vector in the preset register, sending the first interrupt to the second virtual processor according to the target PI description information.

[0246] Any physical core may include a register. Optionally, the register may be a real physical ICR register.

[0247] The preset register may be a register in the first physical core.

[0248] The first physical core can call the interrupt sending code to write the preset PI interrupt vector in the preset register to trigger the sending of the first interrupt to the second physical core where the second virtual processor is located; the first physical core can respond to the completion of writing the preset PI interrupt vector in the preset register, and when sending the first interrupt, send the first interrupt to the second virtual processor according to the target PI description information.

[0249] For example, if the first physical core is physical core 0, if the preset register in physical core 0 is physical ICR register 0, if the second virtual processor is virtual processor 1, and virtual processor 1 runs based on physical core 1, then physical core 0 can write the preset PI interrupt vector in physical ICR register 0 to trigger the sending of the first interrupt; the first physical core can then send the first interrupt 1 to physical core 1 according to the target PI description information 1.

[0250] In an embodiment of the present application, the first physical core may allocate target memory for the virtual machine during virtual machine initialization and generate at least one PI description information and a preset mapping relationship between the virtual processor identifier and the PI description information in the target memory. The first physical core may obtain a first interrupt generated by the first virtual processor, determine interrupt information of the first interrupt, and then obtain a flag value from the VMCS information corresponding to the first virtual processor. If the flag value is a second preset value, the first interrupt can be processed based on the interrupt information and the original code for sending the interrupt, and the flag value can be updated to the first preset value. The preset PI interrupt vector can be determined in the VMCS information, the preset PI interrupt vector can be stored in the first storage space, and the original code can be updated to the interrupt sending code. If the flag value is the first preset value and if there is code in the second storage space, the first physical core can determine the code in the second storage space as the interrupt sending code, and call the interrupt sending code to determine the second virtual processor based on the interrupt information. The interrupt sending code can be called to determine the PI description information corresponding to the second virtual processor in at least one PI description information. The interrupt sending code can be called to configure and process the PI description information corresponding to the second virtual processor based on the interrupt information to obtain the target PI description information. The interrupt sending code can be called to send the first interrupt to the second virtual processor based on the target PI description information and the preset PI interrupt vector corresponding to the first virtual processor. Since the interrupt sending code can be executed to send the first interrupt in non-root mode, compared with the existing technology, there is no need to switch between root mode and non-root mode, thereby improving the efficiency of sending interrupts.

[0251] Below, in Figure 4 Based on the embodiment shown, combined Figure 6 , the above interrupt handling method is further described in detail.

[0252] Figure 6 This is a process diagram of an interrupt handling method provided by an exemplary embodiment of the present application. Figure 6 , including the process of sending the interrupt for the first time and the process of sending the interrupt for the second time.

[0253] The process of sending the interrupt for the first time may include steps ①②③④⑤⑥⑦; the process of sending the interrupt for the second time may include steps ⑧⑨⑩

[0254] During the first send interrupt:

[0255] In step ①, when the interrupt is sent for the first time, in non-root mode, if virtual processor 0 generates interrupt 1, physical core 0 determines interrupt information 1 of interrupt 1 and writes interrupt information 1 of interrupt 1 into virtual ICR register 0 corresponding to virtual processor 0.

[0256] In step ②, physical core 0 can obtain the flag value from VMCS information 0 corresponding to virtual processor 0. Since this is the first time an interrupt is sent, the flag value has not yet been updated to the first preset value 1, so physical core 0 can determine that the flag value is the second preset value 0.

[0257] In step ③, physical core 0 can fall into KVM, that is, switch from non-root mode to root mode.

[0258] In step 4, since this is the first interrupt being sent, physical core 0 can process interrupt 1 based on interrupt information 1 and the original code that sent the interrupt. For example, if interrupt information 1 includes the identifier of the second virtual processor, vCPU-1, physical core 0 can send interrupt 1 to virtual processor 1 based on interrupt information 1.

[0259] In step ⑤, physical core 0 may update the flag value in VMCS information 0 to a first preset value 1, determine a preset PI interrupt vector 0 in VMCS information 0, and store the preset PI interrupt vector 0 in the first storage space.

[0260] In step 6, physical core 0 may update the original code to the interrupt sending code. Optionally, physical core 0 may generate a replacement code based on the starting location of the interrupt sending code in the second storage space. The replacement code indicates the interrupt sending code at the starting location for execution. Physical core 0 may update the original code to the replacement code, thereby updating the original code to the interrupt sending code so that the interrupt sending code can be called when the interrupt is sent a second time.

[0261] In step ⑦, physical core 0 can switch from root mode to non-root mode and continue to execute the next instruction.

[0262] During the second sending interrupt:

[0263] In step ⑧, when sending the interrupt for the second time, in non-root mode, if virtual processor 0 generates interrupt 2, physical core 0 determines interrupt information 2 of interrupt 2 and writes interrupt information 2 of the first interrupt 2 into virtual ICR register 0 corresponding to virtual processor 0.

[0264] In step 9, physical core 0 may obtain the flag value from VMCS information 0 corresponding to virtual processor 0. Since the flag value in VMCS information 0 is updated to the first preset value 1 during the first sending of interrupt 1, physical core 0 may determine that the flag value is the second preset value 1.

[0265] In step ⑩, physical core 0 can determine the interrupt sending code in the second storage space, call the interrupt sending code in non-root mode, and determine the second virtual processor according to interrupt information 2. It is assumed that the second virtual processor can be determined to be virtual processor 2.

[0266] In step In the non-root mode, the physical core 0 can call the interrupt sending code and send the interrupt 2 to the virtual processor 2 according to the interrupt information and at least one PI description information.

[0267] Optionally, physical core 0 may call the interrupt sending code to determine PI description information 2 corresponding to virtual processor 2, and configure PI description information 2 according to interrupt information 2 to obtain target PI description information 2. Physical core 0 may call the interrupt sending code to obtain preset PI interrupt vector 0 corresponding to virtual processor 0 in the first storage space, write the preset PI interrupt vector 0 into the preset register, and send interrupt 2 to virtual processor 2 according to target PI description information 2.

[0268] In step , you can continue to execute the next interrupt.

[0269] In the technical solution of the present application, the PI description information can be established in a memory area visible to the virtual machine, and the original code for sending interrupts can be modified to fully utilize the PI function of the CPU and realize a user-imperceptible interrupt sending method. When the physical core sends an interrupt, there is no need to switch back and forth between root mode and non-root mode, which reduces virtualization loss, improves the efficiency of sending interrupts, and thereby improves the operating efficiency of applications in the virtual machine.

[0270] In an embodiment of the present application, the first physical core can allocate target memory for the virtual machine when the virtual machine is initialized, and generate at least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information in the target memory. The first physical core can obtain the first interrupt generated by the first virtual processor, and determine the interrupt information of the first interrupt, and then obtain the flag value in the VMCS information corresponding to the first virtual processor. If the flag value is a second preset value, the first interrupt can be processed according to the interrupt information and the original code for sending the interrupt, and the flag value can be updated to the first preset value, and the preset PI interrupt vector can be determined in the VMCS information, the preset PI interrupt vector can be stored in the first storage space, and the original code can be updated to the interrupt sending code; if the flag value is the first preset value, the first physical core can determine the interrupt sending code and call the interrupt sending code to determine the second virtual processor according to the interrupt information, and send the first interrupt to the second virtual processor according to the interrupt information and at least one PI description information. Since it is only necessary to switch between root mode and non-root mode when sending an interrupt for the first time, so as to update the original code for sending the interrupt to the interrupt sending code in the root mode; in the subsequent process of sending interrupts, the interrupt sending code can be called to send the first interrupt in the non-root mode. Compared with the existing technology, there is no need to switch between root mode and non-root mode, thereby improving the efficiency of sending interrupts.

[0271] Figure 7 The present invention provides a schematic diagram of the structure of an interrupt processing device. Figure 7 The interrupt processing device 10 includes: an acquisition module 11, a determination module 12 and a first sending module 13, wherein,

[0272] The acquisition module 11 is used to acquire a first interrupt generated by a first virtual processor and determine interrupt information of the first interrupt;

[0273] The determining module 12 is configured to, in response to the first interrupt, determine an interrupt sending code in the target memory, wherein the interrupt sending code is used to indicate that an interrupt is sent in a non-root mode, and the interrupt sending code is a code that is an updated version of an original code for sending the interrupt;

[0274] The first sending module 13 is configured to send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

[0275] The interrupt processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0276] In a possible implementation manner, the target memory further includes at least one issued interrupt PI description information; and the first sending module 13 is specifically configured to:

[0277] Call the interrupt sending code to perform the following steps:

[0278] determining a second virtual processor according to the interrupt information;

[0279] Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information.

[0280] In a possible implementation manner, the first sending module 13 is specifically configured to:

[0281] Determining PI description information corresponding to the second virtual processor from the at least one PI description information;

[0282] Performing configuration processing on the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information;

[0283] The first interrupt is sent to the second virtual processor according to the target PI description information and a preset PI interrupt vector corresponding to the first virtual processor.

[0284] In a possible implementation manner, the first sending module 13 is specifically configured to:

[0285] Writing the preset PI interrupt vector into the preset register;

[0286] In response to the completion of writing the preset PI interrupt vector into the preset register, the first interrupt is sent to the second virtual processor according to the target PI description information.

[0287] In a possible implementation manner, the first sending module 13 is specifically configured to:

[0288] Acquire a preset mapping relationship in the target memory, where the preset mapping relationship includes an identifier of at least one virtual processor and PI description information corresponding to the identifier of each virtual processor;

[0289] The PI description information corresponding to the second virtual processor is determined according to the identifier of the second virtual processor and the preset mapping relationship.

[0290] In a possible implementation, the determining module 12 is specifically configured to:

[0291] Obtaining a flag value from the virtual machine control structure VMCS information corresponding to the first virtual processor;

[0292] When the flag value is a first preset value and there is a code in the second storage space of the target memory, determining the code in the second storage space as the interrupt sending code;

[0293] The first preset value is used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor.

[0294] The interrupt processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0295] Figure 8 This is a structural diagram of another interrupt processing device provided by an exemplary embodiment of the present application. Figure 8 ,exist Figure 7 Based on the embodiment shown, the interrupt processing device 10 may further include: a second sending module 14 and an updating module 15, wherein:

[0296] The second sending module 14 is used to send the first interruption according to the interruption information and the original code for sending the interruption;

[0297] The updating module 15 is configured to update the flag value to the first preset value, determine the preset PI interrupt vector in the VMCS information, and store the preset PI interrupt vector in the first storage space;

[0298] The updating module 15 is used to update the original code to the interrupt sending code.

[0299] The interrupt processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0300] In a possible implementation, the updating module 15 is specifically configured to:

[0301] generating a replacement code according to a starting position of the interrupt sending code in the second storage space, wherein the replacement code is used to instruct execution of the interrupt sending code at the starting position;

[0302] The original code is updated to the replacement code.

[0303] In a possible implementation, the first virtual processor is a virtual processor in a virtual machine, and the interrupt processing device 10 further includes an allocation module 16 and a generation module 17, wherein:

[0304] The allocation module 16 is used to allocate the target memory to the virtual machine when the virtual machine is initialized;

[0305] The generating module 17 is configured to generate at least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information in the target memory.

[0306] The interrupt processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0307] Figure 9 This is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present application. Figure 9 The electronic device 20 may include a processor 21 and a memory 22. Exemplarily, the processor 21 and the memory 22 are interconnected via a bus 23.

[0308] The memory 22 stores computer-executable instructions;

[0309] The processor 21 executes the computer-executable instructions stored in the memory 22 , so that the processor 21 performs the method shown in the above method embodiment.

[0310] Figure 9 The electronic device shown may be the server described in the above embodiment.

[0311] Accordingly, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method described in the above method embodiment.

[0312] Accordingly, an embodiment of the present application may also provide a computer program product, including a computer program, which, when executed by a processor, may implement the method shown in the above method embodiment.

[0313] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0314] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0315] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0316] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0317] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0318] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0319] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0320] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0321] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. An interrupt processing method, characterized in that: include: Obtaining a first interrupt generated by a first virtual processor, and determining interrupt information of the first interrupt; In response to the first interrupt, determining an interrupt sending code in a target memory, wherein the interrupt sending code is used to instruct interrupt sending in a non-root mode, and the interrupt sending code is a code that is updated from an original code for sending the interrupt; Send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

2. An interrupt processing method, characterized in that: include: Obtaining a first interrupt generated by a first virtual processor and determining interrupt information of the first interrupt, where the first virtual processor is used to process cloud services, including cloud gaming services and cloud rendering services; In response to the first interrupt, determining an interrupt sending code in a target memory, wherein the interrupt sending code is used to instruct interrupt sending in a non-root mode, and the interrupt sending code is a code that is updated from an original code for sending the interrupt; Send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

3. The method according to claim 1 or 2, characterized in that The target memory also includes at least one issued interrupt PI description information; Sending the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code includes: Call the interrupt sending code to perform the following steps: determining a second virtual processor according to the interrupt information; Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information.

4. The method according to claim 3, characterized in that Sending the first interrupt to the second virtual processor according to the interrupt information and the at least one PI description information includes: Determining PI description information corresponding to the second virtual processor from the at least one PI description information; Performing configuration processing on the PI description information corresponding to the second virtual processor according to the interrupt information to obtain target PI description information; The first interrupt is sent to the second virtual processor according to the target PI description information and a preset PI interrupt vector corresponding to the first virtual processor.

5. The method according to claim 4, characterized in that Sending the first interrupt to the second virtual processor according to the target PI description information and the preset PI interrupt vector includes: Writing the preset PI interrupt vector into the preset register; In response to the completion of writing the preset PI interrupt vector into the preset register, the first interrupt is sent to the second virtual processor according to the target PI description information.

6. The method according to claim 4, characterized in that Determining, from the at least one PI description information, PI description information corresponding to the second virtual processor includes: Acquire a preset mapping relationship in the target memory, where the preset mapping relationship includes an identifier of at least one virtual processor and PI description information corresponding to the identifier of each virtual processor; The PI description information corresponding to the second virtual processor is determined according to the identifier of the second virtual processor and the preset mapping relationship.

7. The method according to any one of claims 1 to 6, characterized in that Identify the interrupt sending code in the target memory, including: Obtaining a flag value from the virtual machine control structure VMCS information corresponding to the first virtual processor; When the flag value is a first preset value and there is a code in the second storage space of the target memory, determining the code in the second storage space as the interrupt sending code; The first preset value is used to indicate that the first interrupt is an interrupt other than the first interrupt generated by the first virtual processor.

8. The method according to claim 7, characterized in that If the flag value is a second preset value, the second preset value is used to indicate that the first interrupt is the first interrupt generated by the first virtual processor, the method further includes: Sending the first interruption according to the interruption information and the original code for sending the interruption; Updating the flag value to the first preset value, determining the preset PI interrupt vector in the VMCS information, and storing the preset PI interrupt vector in a first storage space; The original code is updated to the interrupt sending code.

9. The method according to claim 8, characterized in that Updating the original code to the interrupt sending code includes: generating a replacement code according to a starting position of the interrupt sending code in the second storage space, wherein the replacement code is used to instruct execution of the interrupt sending code at the starting position; The original code is updated to the replacement code.

10. The method according to any one of claims 1 to 9, characterized in that The first virtual processor is a virtual processor in a virtual machine, and the method further includes: When the virtual machine is initialized, allocating the target memory to the virtual machine; At least one PI description information and a preset mapping relationship between the identifier of the virtual processor and the PI description information are generated in the target memory.

11. An interrupt processing device, characterized in that: include: An acquisition module, a determination module and a first sending module, wherein: The acquisition module is used to acquire a first interrupt generated by a first virtual processor and determine interrupt information of the first interrupt; The determining module is configured to, in response to the first interrupt, determine an interrupt sending code in a target memory, wherein the interrupt sending code is used to indicate that an interrupt is sent in a non-root mode, and the interrupt sending code is a code updated from an original code for sending the interrupt; The first sending module is configured to send the first interrupt in the non-root mode according to the interrupt information and the interrupt sending code.

12. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the electronic device to perform the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method according to any one of claims 1 to 10 is implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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