Instruction separation method and tool chain generation tool

Abstract

The invention discloses an instruction separation method and a tool chain generation tool. Relates to the technical field of computers. Identifying the source program to be processed to obtain a plurality of instruction operation codes and initial function bodies corresponding to the instruction operation codes; and processing the initial function body according to an instruction operation code in the plurality of instruction operation codes to obtain a target function body corresponding to the instruction operation code in the plurality of instruction operation codes so as to realize instruction separation of the plurality of instruction operation codes. According to the instruction separation method and device, the technical problem that the accuracy of instruction separation is low due to the fact that multiple instructions in the source program are separated by rewriting the abstract syntax tree corresponding to the source program in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction separation method and a tool chain generation tool. Background Art

[0002] Custom programming languages ​​(e.g., high-level description languages ​​like Sail) are widely used in today's processor instruction set architecture design. These languages ​​offer rich syntax and functionality, allowing designers to describe complex instruction behaviors in an intuitive and compact manner. However, the flexibility of these languages ​​also comes with challenges in automatic toolchain generation, especially when dealing with mixed descriptions of multiple instructions within the instruction set.

[0003] Automated toolchain generation tools play a vital role in the design and implementation of custom instruction sets and their supporting toolchains. They can automatically generate corresponding compiler and simulator plug-ins based on the custom instruction descriptions provided by users to support the newly added instructions. This process requires the tools to accurately identify and separate the independent behavioral descriptions of each instruction, thereby ensuring that the generated toolchain can handle each instruction correctly. Although existing technologies can attempt to achieve instruction separation by rewriting the abstract syntax tree (AST) of the source program, this approach has fundamental shortcomings. It relies too much on specific grammatical structures, which means that any instruction description that does not conform to the preset pattern may cause separation failure or inaccuracy.

[0004] Currently, no effective solution has been proposed to the technical problem that the accuracy of instruction separation is relatively low, as a result of separating multiple instructions in the source program by rewriting the abstract syntax tree corresponding to the source program in the above-mentioned related technologies. Summary of the Invention

[0005] An embodiment of the present application provides an instruction separation method and a tool chain generation tool to at least solve the technical problem in the related art of separating multiple instructions in a source program by rewriting the abstract syntax tree corresponding to the source program, resulting in relatively low accuracy of instruction separation.

[0006] According to one aspect of an embodiment of the present application, an instruction separation method is provided, including: obtaining a source program to be processed; identifying the source program to be processed to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; processing the initial function body according to the instruction opcodes in the multiple instruction opcodes to obtain a target function body corresponding to the instruction opcodes in the multiple instruction opcodes, so as to realize instruction separation of the multiple instruction opcodes.

[0007] Furthermore, identifying the source program to be processed and obtaining multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes includes: identifying the instruction group defined in the source program to be processed, obtaining the multiple instruction opcodes, and storing the multiple instruction opcodes in an instruction set; identifying the function defined in the source program to be processed, and obtaining the initial function body.

[0008] Furthermore, the initial function body is processed according to the instruction opcode in the multiple instruction opcodes to obtain the target function body corresponding to the instruction opcode in the multiple instruction opcodes, including: determining the first instruction opcode in the instruction set; processing the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode; repeatedly determining the next instruction opcode in the instruction set until the target function body corresponding to the last execution opcode is obtained.

[0009] Furthermore, processing the initial function body according to the first instruction opcode to obtain a target function body corresponding to the first instruction opcode includes: performing constant propagation on the initial function body according to the first instruction opcode to obtain a processed initial function body; and performing dead code deletion on the processed initial function body to obtain a target function body corresponding to the first instruction opcode.

[0010] Furthermore, constant propagation is performed on the initial function body according to the first instruction opcode to obtain the processed initial function body, including: generating an assignment statement according to the first instruction opcode and the instruction variables in the initial function body; adding the assignment statement to the initial function body to obtain the added initial function body; and executing constant propagation on the added initial function body to obtain the processed initial function body.

[0011] Furthermore, dead code is deleted from the processed initial function body to obtain a target function body corresponding to the first instruction opcode, including: generating a control flow chart based on the processed initial function body; identifying dead code in the processed initial function body based on the control flow chart to obtain dead code information; and deleting dead code from the processed initial function body based on the dead code information to obtain a target function body corresponding to the first instruction opcode.

[0012] Furthermore, after processing the initial function body according to the instruction opcodes among the multiple instruction opcodes to obtain the target function body corresponding to the instruction opcodes among the multiple instruction opcodes, the method includes: parsing the target function body corresponding to the instruction opcodes among the multiple instruction opcodes, and generating a tool chain supporting the source program based on the parsing results, wherein the tool chain includes at least: a compiler and a simulator.

[0013] According to another aspect of an embodiment of the present application, a tool chain generation tool is also provided, including: an instruction separation tool, wherein the instruction separation tool is used to perform instruction separation on the source program to be processed to obtain a target function body corresponding to an instruction opcode among multiple instruction opcodes; a generation tool, wherein the target function body is parsed by the generation tool, and a tool chain supporting the source program is generated based on the parsing result, wherein the tool chain includes at least: a compiler and a simulator.

[0014] According to another aspect of an embodiment of the present application, an instruction separation device is also provided, including: an acquisition unit for acquiring a source program to be processed; an identification unit for identifying the source program to be processed, and obtaining multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; a processing unit for processing the initial function body based on an instruction opcode in the multiple instruction opcodes, and obtaining a target function body corresponding to an instruction opcode in the multiple instruction opcodes, so as to realize instruction separation of the multiple instruction opcodes.

[0015] Furthermore, the identification unit includes: a first identification module, used to identify the instruction group defined in the source program to be processed, obtain the multiple instruction operation codes, and store the multiple instruction operation codes in an instruction set; a second identification module, used to identify the function defined in the source program to be processed, and obtain the initial function body.

[0016] Furthermore, the processing unit includes: a first determination module, used to determine the first instruction opcode in the instruction set; a processing module, used to process the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode; a second determination module, used to repeatedly execute and determine the next instruction opcode in the instruction set until the target function body corresponding to the last execution opcode is obtained.

[0017] Furthermore, the processing module includes: a propagation submodule, used to perform constant propagation on the initial function body according to the first instruction opcode to obtain a processed initial function body; a deletion submodule, used to delete dead code on the processed initial function body to obtain a target function body corresponding to the first instruction opcode.

[0018] Furthermore, the propagation sub-module includes: a first generation sub-module, used to generate an assignment statement based on the first instruction opcode and the instruction variables in the initial function body; an addition sub-module, used to add the assignment statement to the initial function body to obtain the added initial function body; and a propagation sub-module, used to perform constant propagation on the added initial function body to obtain the processed initial function body.

[0019] Furthermore, the deletion submodule includes: a second generation submodule, used to generate a control flow chart based on the processed initial function body; an identification submodule, used to identify dead code in the processed initial function body based on the control flow chart to obtain dead code information; and a deletion submodule, used to delete dead code from the processed initial function body based on the dead code information to obtain the target function body corresponding to the first instruction opcode.

[0020] Furthermore, the device includes: a parsing unit, which is used to process the initial function body according to the instruction opcodes in the multiple instruction opcodes to obtain the target function body corresponding to the instruction opcodes in the multiple instruction opcodes, and then parse the target function body corresponding to the instruction opcodes in the multiple instruction opcodes, and generate a tool chain supporting the source program based on the parsing results, wherein the tool chain includes at least: a compiler and a simulator.

[0021] According to another aspect of an embodiment of the present invention, a computing device is provided, including: a memory storing an executable program; and a processor for running the program, wherein any one of the above instruction separation methods is executed when the program is running.

[0022] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, which stores a program, wherein when the program is running, the device where the storage medium is located is controlled to execute any one of the above instruction separation methods.

[0023] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program or instructions, which implements any one of the above instruction separation methods when executed by a processor.

[0024] In an embodiment of the present application, the following steps are adopted: obtaining a source program to be processed; identifying the source program to be processed to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; processing the initial function body according to the instruction opcodes in the multiple instruction opcodes to obtain a target function body corresponding to the instruction opcodes in the multiple instruction opcodes, so as to realize instruction separation of the multiple instruction opcodes, thereby solving the technical problem in the related art of separating multiple instructions in the source program by rewriting the abstract syntax tree corresponding to the source program, resulting in relatively low accuracy of instruction separation.

[0025] In this solution, the acquired source program is identified, and multiple instruction opcodes and their associated initial function bodies are extracted therefrom. The initial function bodies are then separated and processed according to the instruction opcodes in the multiple instruction opcodes, thereby obtaining target function bodies corresponding to the instruction opcodes in the multiple instruction opcodes. Compared with the instruction separation technology implemented by simply rewriting the abstract syntax tree in the prior art, the embodiment of the present application can accurately identify and separate the independent behavior descriptions of the instruction opcodes when processing mixed descriptions of instructions, thereby avoiding inaccurate separation or missed separation caused by mismatch of syntax patterns, thereby achieving the technical effect of improving the accuracy of instruction separation. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 This is a hardware structure block diagram of a computer terminal provided according to the first embodiment of the present application;

[0028] Figure 2 This is a flowchart of the instruction separation method provided in Example 1 of the present application;

[0029] Figure 3 is a schematic diagram of the instruction separation method provided according to the first embodiment of the present application;

[0030] Figure 4 Schematic diagram of a tool chain generation tool provided according to the second embodiment of the present application;

[0031] Figure 5 is a schematic diagram of an instruction separation device provided according to the third embodiment of the present application;

[0032] Figure 6 This is a structural block diagram of a computing device provided according to Example 4 of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0036] Example 1

[0037] According to an embodiment of the present application, an instruction separation method is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0038] The instruction separation method embodiment provided in the first embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 FIG1 shows a hardware structure block diagram of a computer terminal (or mobile device) for implementing the instruction separation method. Figure 1As shown, the computer terminal (or mobile device) 10 may include a processor set 102 (the processor set 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA, and the processor set 102 may include a processor set, Figure 1 102a, 102b, ..., 102n are used to illustrate), a memory 104 for storing data, and a transmission module 106 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which can be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0039] It should be noted that the one or more processors 102 and / or other data processing circuits described above may generally be referred to herein as "data processing circuitry". The data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuitry may be a single independent processing module, or may be incorporated in whole or in part into any of the other components of the computer terminal 10 (or mobile device). As described in the embodiments of the present application, the data processing circuitry serves as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0040] The memory 104 can be used to store software programs and modules of application software, such as the program instruction / data storage device corresponding to the instruction separation method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned instruction separation method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0041] The transmission device 106 is used to receive or send data via a network. A specific example of the network may include a wireless network provided by the communications provider of the computer terminal 10. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0042] The display may be, for example, a touch screen liquid crystal display that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

[0043] Under the above operating environment, this application provides Figure 2 The instruction separation method shown. Figure 2 1 is a flow chart of an instruction separation method according to Embodiment 1 of the present application. The instruction separation method includes:

[0044] Step S201: Obtain the source program to be processed.

[0045] Optionally, a file containing a custom instruction description is read or imported to obtain a source program to be processed. For example, the source program may be a program based on Sail language, which is a custom instruction set description language that allows the behavior of multiple different instructions to be described in a single function.

[0046] For example, in a source program, an enumeration type function defining instruction operations is used to define multiple instruction opcodes, and a function defining a function body is used to define a specific function body. For example, the enumeration type defining instruction operations = {immediate addition instruction, immediate OR instruction}, and the function definition = {read the value in the register, set the result = match instruction variable {immediate addition instruction => value + immediate value. Immediate OR instruction => bitwise exclusive OR result of value and immediate value};}.

[0047] Step S202 : Identify the source program to be processed and obtain a plurality of instruction operation codes and initial function bodies corresponding to the plurality of instruction operation codes.

[0048] Optionally, instruction opcodes of all custom instructions are obtained by parsing and identifying the source program, and then initial function bodies corresponding to multiple instruction opcodes are obtained by parsing and identifying the source program.

[0049] For example, several recognized instruction opcodes are the immediate addition instruction and the immediate OR instruction. The immediate addition instruction adds the value in a register to an immediate value and stores the result back in the register. The immediate value is a value directly encoded as part of the instruction. The immediate exclusive OR instruction performs a bit-level exclusive OR operation, combining an immediate value with the value in a register.

[0050] For example, the initial function body is: define function = {read the value in the register, set the result = match instruction variable {immediate value addition instruction => value + immediate value. Immediate value OR operation instruction => bitwise exclusive OR operation result of value and immediate value};}.

[0051] Step S203 , processing the initial function body according to the instruction operation code in the plurality of instruction operation codes to obtain a target function body corresponding to the instruction operation code in the plurality of instruction operation codes, so as to realize instruction separation of the plurality of instruction operation codes.

[0052] Optionally, the initial function body is processed using the instruction opcodes from the multiple instruction opcodes. For example, the instruction opcodes are assigned to instruction variables in the initial function body, constant propagation and dead code deletion are performed, and then a target function body corresponding to the instruction opcodes from the multiple instruction opcodes is obtained to achieve instruction separation for the multiple instruction opcodes. The target function body no longer contains descriptions of other instruction opcodes or redundant branches, but only describes the behavior of the current instruction opcode. It should be noted that dead code refers to code in the program that will not be executed.

[0053] To sum up, in this solution, the acquired source program is identified, and multiple instruction opcodes and their associated initial function bodies are extracted therefrom. Then, the initial function body is separated and processed according to the instruction opcodes in the multiple instruction opcodes, and then the target function body corresponding to the instruction opcodes in the multiple instruction opcodes is obtained. Compared with the instruction separation technology implemented by simply rewriting the abstract syntax tree in the previous technology, the embodiment of the present application can accurately identify and separate the independent behavior description of the instruction opcode when processing the mixed description of instructions, avoiding the inaccurate separation or missed separation caused by the mismatch of the syntax pattern, thereby achieving the technical effect of improving the accuracy of instruction separation.

[0054] In order to improve the accuracy of obtaining instruction opcodes and initial function bodies, in the instruction separation method provided in Example 1 of the present application, the source program to be processed is identified to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes, including: identifying the instruction group defined in the source program to be processed, obtaining multiple instruction opcodes, and storing the multiple instruction opcodes in an instruction set; identifying the function defined in the source program to be processed, and obtaining the initial function body.

[0055] Optionally, the source program to be processed typically contains an enumeration type or constant definition that includes the instruction opcodes for all custom instructions. For example, in the Sail language, this enumeration is defined as enumiop and includes instruction opcodes such as immediate addition instructions and immediate or arithmetic instructions. Therefore, the instruction group defined in the source program to be processed is identified to obtain multiple instruction opcodes in the source program, and the multiple instruction opcodes are stored in an instruction set for subsequent instruction separation.

[0056] If the source program being processed is written in the Sail language, the function body is typically defined using the FunctionClauseExecute (i.e., the function defined above). Therefore, the function defined in the source program is identified to obtain an initial function body. Identifying and obtaining the initial function body ensures that the algorithm can accurately locate the core code segment that describes the instruction behavior without being disturbed by irrelevant code.

[0057] Through the above-mentioned identification steps, the instruction opcodes and initial function bodies in the source program can be obtained more accurately and comprehensively, avoiding misidentification and omissions caused by complex code structure or diverse description methods, and ensuring the accuracy and completeness of subsequent processing.

[0058] In order to improve the accuracy of obtaining the target function body, in the instruction separation method provided in Example 1 of the present application, the initial function body is processed according to the instruction opcode among multiple instruction opcodes to obtain the target function body corresponding to the instruction opcode among multiple instruction opcodes, including: determining the first instruction opcode in the instruction set; processing the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode; repeatedly executing the next instruction opcode in the determined instruction set until the target function body corresponding to the last execution opcode is obtained.

[0059] Optionally, the first instruction opcode is determined from the previously identified and constructed instruction set. This is the beginning of the loop processing, and the goal is to generate a specific function body description for this opcode. Based on the selected first instruction opcode, the reference to the instruction opcode in the initial function body is replaced, and it is regarded as a constant that will not change, and the target function body corresponding to the first instruction opcode is obtained. For example, the instruction variable in the initial function body is replaced with the specific value of the current instruction opcode, such as an immediate addition instruction. After completing the processing of the first instruction opcode, the next instruction opcode will continue to be selected, and the above processing process will be repeated until the last instruction opcode in the instruction set is processed. Ultimately, this loop mechanism will generate a series of target function bodies, one target function body corresponding to an instruction opcode in the instruction set, and only contains behavioral descriptions directly related to the instruction.

[0060] The loop processing mechanism avoids the risk of misoperation when processing multiple instructions. Traditional one-shot processing methods can lead to incorrect separation results when multiple instructions are described in the same context due to complex code structure. However, the one-by-one processing method significantly reduces this risk and improves the accuracy of the target function body.

[0061] In order to further improve the accuracy of the target function body, in the instruction separation method provided in Example 1 of the present application, the initial function body is processed according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode, including: performing constant propagation on the initial function body according to the first instruction opcode to obtain the processed initial function body; and performing dead code deletion on the processed initial function body to obtain the target function body corresponding to the first instruction opcode.

[0062] Optionally, the currently processed instruction opcode (e.g., an immediate addition instruction) is replaced with an instruction variable in the initial function body, and constant propagation is performed. For example, all references to the instruction variable in the initial function body are identified and replaced with the specific value of the current instruction opcode, the immediate addition instruction. For example, in a branch that matches an instruction variable, the instruction variable is replaced with an immediate addition instruction, so that the initial function body, which was originally used to describe the behavior of multiple instructions, now only focuses on the behavior of the current immediate addition instruction, resulting in the processed initial function body described above.

[0063] After constant propagation, code paths in the processed initial function body that do not involve the current instruction opcode are marked as dead code. For example, if the current instruction is an immediate addition instruction, the code paths in the match instruction variable branch involving immediate or arithmetic instructions or other instructions will no longer apply. To improve subsequent operational efficiency, a dead code removal step is performed to remove all code segments marked as dead code, thereby obtaining the target function body corresponding to the first instruction opcode mentioned above. This step eliminates redundant code unrelated to the current instruction, ensuring that the target function body only contains behavioral descriptions directly related to the current instruction opcode.

[0064] By performing constant propagation and dead code elimination on the initial function body, unnecessary calculations and logic branches are removed, improving the accuracy of the target function body.

[0065] In the instruction separation method provided in Example 1 of the present application, constant propagation is performed on the initial function body according to the first instruction opcode, and the processed initial function body includes: generating an assignment statement according to the first instruction opcode and the instruction variables in the initial function body; adding the assignment statement to the initial function body to obtain the added initial function body; performing constant propagation on the added initial function body to obtain the processed initial function body.

[0066] Optionally, the first instruction opcode to be processed is determined from the instruction set, such as an immediate addition instruction. Based on this instruction opcode, an assignment statement is generated, such as "Let instruction variable = immediate addition instruction", to set the value of the instruction variable to the value of the current instruction opcode. The generated assignment statement "Let instruction variable = immediate addition instruction" is inserted into the starting position of the initial function body to create the added initial function body. This is done to ensure that before any operational semantic analysis is performed, all subsequent code clearly knows the specific value of the instruction variable, that is, which instruction is currently being processed.

[0067] The constant propagation algorithm is executed on the initial function body with the added assignment statement. This algorithm traverses the entire function body, identifying all references to instruction variables and replacing them with immediate addition instructions with the specific value of the current instruction opcode. Constant propagation propagates the value of the current instruction opcode to all code paths that depend on the instruction variable, including conditional branches, function call parameters, and so on. This means that all dynamic branches that originally depended on the value of the instruction variable are now static branches that operate only on the current instruction opcode. After constant propagation is complete, all instruction variable references in the function body are replaced with the specific instruction opcode value, resulting in the processed initial function body described above.

[0068] By assigning instruction opcodes to instruction variables and performing constant propagation, all operations within a function body are ensured to be specific to the current instruction opcode. This not only improves the accuracy of instruction descriptions but also prevents the behavior of instructions within the function body from being affected by other instruction opcodes, improving the accuracy of instruction separation.

[0069] In order to improve the accuracy of dead code, in the instruction separation method provided in Example 1 of the present application, dead code is deleted from the processed initial function body to obtain the target function body corresponding to the first instruction opcode, including: generating a control flow chart based on the processed initial function body; identifying dead code in the processed initial function body based on the control flow chart to obtain dead code information; and deleting dead code from the processed initial function body based on the dead code information to obtain the target function body corresponding to the first instruction opcode.

[0070] Optionally, a control flow graph (CFG) is constructed based on the processed initial function body. A control flow graph is a graphical representation that shows the branches and jump paths that may occur during program execution. In a control flow graph (CFG), nodes represent basic blocks and edges represent control flow transfers. By analyzing the generated CFG, code paths that cannot be executed or code segments that are no longer referenced are identified. These code segments are caused by constant propagation, which causes certain conditional branches to be always false. All nodes and code segments identified as dead code are recorded to form a dead code information list.

[0071] According to the dead code information list, all code segments marked as dead codes are deleted from the processed initial function body to obtain a target function body after removing redundant codes.

[0072] Through dead code removal, only the code related to the current instruction opcode is retained in the target function body, eliminating the interference of irrelevant instructions and improving the accuracy of the target function body.

[0073] After processing the initial function body according to the instruction opcodes among multiple instruction opcodes to obtain the target function body corresponding to the instruction opcodes among the multiple instruction opcodes, in the instruction separation method provided in Example 1 of the present application, the method includes: parsing the target function body corresponding to the instruction opcodes among the multiple instruction opcodes, and generating a tool chain supporting the source program based on the parsing results, wherein the tool chain includes at least: a compiler and a simulator.

[0074] Optionally, the target function body is parsed for syntax and semantics, extracting key instruction information from the target function body, including instruction format, opcode, operand type, execution logic, and so on. Based on this information, a compiler plug-in is generated to enable the compiler to recognize and correctly compile custom instructions. This includes generating syntax processing code, type conversion code, and optimization code for each instruction, ensuring that the compiler can accurately convert custom instructions into machine code when encountering them.

[0075] Similarly, a simulator plug-in is generated to enable the simulator to execute custom instructions in the source program. This requires converting the instruction execution logic in the target function body into code that the simulator can understand, including instruction decoding, execution, and result verification, to ensure that the simulator can accurately simulate the execution effect of the instruction.

[0076] By streamlining and optimizing the target function body, the compiler and simulator no longer need to execute redundant code paths and conditional judgments when processing custom instructions, thereby improving the efficiency of the compilation and simulation process.

[0077] In an optional embodiment, the pseudo code of the instruction separation method provided in the embodiment of the present application may be as follows:

[0078] {Store all instruction opcodes collected from the instruction set into the set;

[0079] Assign the function body content to the variable body; / / This function body contains the code that describes the instruction execution logic and is the original code block for instruction separation. / /

[0080] Initialize an empty set new_bodies to store the separated function body version of each instruction;

[0081] For each instruction opcode in the set, do the following:

[0082] Insert a new statement at the beginning of the body: Set the value of the instruction variable to the opcode of the instruction currently being processed;

[0083] Apply the constant propagation algorithm to body0 to obtain the optimized function body1; / / Constant propagation replaces the value of the instruction variable to all relevant locations in the function body, reducing the conditional judgment and calculation at runtime, making certain code paths or operations in the function body constant or deterministic operations / /

[0084] Execute the dead code removal algorithm based on body1 to obtain the further optimized function body body2;

[0085] Add the optimized function body body2 to the new_bodies collection, ready to be used as one of the results after instruction separation;

[0086] After traversing and processing all instructions, return the new_bodies collection} / / This collection contains independent and optimized function body versions for instructions / / .

[0087] It should be noted that the instruction separation method provided in the embodiment of the present application can be applied to the RISC-V architecture, as well as to the ARM or x86 architecture.

[0088] For example, under the RISC-V architecture, the pseudo code of the instruction separation algorithm based on constant propagation is as follows:

[0089]

[0090]

[0091] Under the RISC-V architecture, the source code to be processed is as follows: enumiop = {RISCV_ADDI, RISCV_SLTI}; function clause execute(ITYPE(imm, rs1, rd, op)) = {let rs1_val = X(rs1); let immext: xlenbits = sign_extend(imm); let result: xlenbits = match op {RISCV_ADDI = > rs1_val + immext, RISCV_SLTI = > zero_extend(bool_to_bits(rs1_val < _simmext))}; X(rd) = result; RETIRE_SUCCESS}.

[0092] Among them, enumiop is the instruction set defined in the source code, op is the instruction variable, RISCV_ADDI is the immediate addition instruction, RISCV_SLTI is the unsigned immediate comparison instruction, and function clause execute is the defined function.

[0093] In the first few lines of pseudocode for the constant-propagation-based instruction splitting algorithm, the involved data structures are initialized. insns is an instruction set, collecting all instructions from the enumiop definition; body is the body of the execute function; and new_bodies is initialized to empty to hold the new body of each instruction. For example, insns = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, RISCV_XORI, RISCV_ORI, RISCV_ANDI}, and body is initialized to: let rs1_val = X(rs1); let immext: xlenbits = sign_extend(imm); let result: xlenbits = match op {RISCV_ADDI => rs1_val + immext, RISCV_SLTI => zero_extend(bool_to_bits(rs1_val < _simmext))}; X(rd) = result; RETIRE_SUCCESS.

[0094] The core of the algorithm is in lines 5 to 9. It iterates over all instructions in the insns set and performs the following steps on all instruction insns:

[0095] 1. Add a statement let op = insn; at the beginning of body to get body 0. For example, when op is RISCV_ADDI:

[0096]

[0097] 2. Perform constant propagation on body0 to obtain body1 (note that op is replaced with RISCV_ADDI):

[0098]

[0099] 3. Perform dead code removal on body1 to obtain body2:

[0100] let rs1_val=X(rs1); let immext:xlenbits=sign_extend(imm); let result:xlenbits=RISCV_ADDI=>rs1_val+immext; X(rd)=result; RETIRE_SUCCESS.

[0101] 4. Store the obtained body2 in the new_bodies container.

[0102] Finally, line 11 returns new_bodies, which is the new function body corresponding to the instruction after the instruction is separated.

[0103] In an optional embodiment, the schematic diagram of the instruction separation method is as follows Figure 3 As shown, the mixed instruction code to be processed is obtained, and the variables representing the instructions in the mixed instruction code are replaced with the current specific instruction opcode, the variables are converted into constants, and then constant propagation is performed on the mixed instruction code to convert the statements involving other instructions into dead codes. Then, through dead code deletion, all other instructions irrelevant to the current instruction are eliminated, and finally a "pure" code containing only the semantics of the current instruction is obtained for further instruction analysis by subsequent modules.

[0104] In the instruction separation method provided in Example 1 of the present application, a source program to be processed is obtained; the source program to be processed is identified to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; the initial function body is processed according to the instruction opcodes in the multiple instruction opcodes to obtain target function bodies corresponding to the instruction opcodes in the multiple instruction opcodes, so as to realize instruction separation of multiple instruction opcodes, thereby solving the technical problem in the related art of separating multiple instructions in the source program by rewriting the abstract syntax tree corresponding to the source program, resulting in relatively low accuracy of instruction separation.

[0105] In this solution, the acquired source program is identified, and multiple instruction opcodes and their associated initial function bodies are extracted therefrom. The initial function bodies are then separated and processed according to the instruction opcodes in the multiple instruction opcodes, thereby obtaining target function bodies corresponding to the instruction opcodes in the multiple instruction opcodes. Compared with the instruction separation technology implemented by simply rewriting the abstract syntax tree in the prior art, the embodiment of the present application can accurately identify and separate the independent behavior descriptions of the instruction opcodes when processing mixed descriptions of instructions, thereby avoiding inaccurate separation or missed separation caused by mismatch of syntax patterns, thereby achieving the technical effect of improving the accuracy of instruction separation.

[0106] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0107] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0108] Example 2

[0109] According to an embodiment of the present application, a tool chain generation tool is also provided. Figure 4 Schematic diagram of a tool chain generation tool according to the second embodiment of the present application. The tool chain generation tool includes:

[0110] An instruction separation tool is used to separate instructions from a source program to be processed, thereby obtaining a target function body corresponding to an instruction operation code among a plurality of instruction operation codes;

[0111] A generation tool is used to parse the target function body and generate a tool chain supporting the source program based on the parsing result, wherein the tool chain includes at least: a compiler and a simulator.

[0112] It should be noted that the specific processing method of the tool chain generation tool for the instruction opcode is the same as that in Example 1 and will not be repeated here.

[0113] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0115] Example 3

[0116] According to an embodiment of the present application, an instruction separation device for implementing the above instruction separation method is also provided, such as Figure 5 As shown, the device includes: an acquisition unit 501, an identification unit 502 and a processing unit 503.

[0117] An acquisition unit 501 is used to acquire a source program to be processed;

[0118] An identification unit 502 is used to identify the source program to be processed and obtain multiple instruction operation codes and initial function bodies corresponding to the multiple instruction operation codes;

[0119] The processing unit 503 is used to process the initial function body according to the instruction operation code in the multiple instruction operation codes to obtain the target function body corresponding to the instruction operation code in the multiple instruction operation codes, so as to realize instruction separation of the multiple instruction operation codes.

[0120] In the instruction separation device provided in Example 3 of the present application, the source program to be processed is acquired by the acquisition unit 501; the identification unit 502 identifies the source program to be processed to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; the processing unit 503 processes the initial function body according to the instruction opcodes in the multiple instruction opcodes to obtain the target function body corresponding to the instruction opcodes in the multiple instruction opcodes, so as to realize instruction separation of multiple instruction opcodes, and solves the technical problem in the related art that the accuracy of instruction separation is relatively low due to the separation of multiple instructions in the source program by rewriting the abstract syntax tree corresponding to the source program.

[0121] In this solution, the acquired source program is identified, and multiple instruction opcodes and their associated initial function bodies are extracted therefrom. The initial function bodies are then separated and processed according to the instruction opcodes in the multiple instruction opcodes, thereby obtaining target function bodies corresponding to the instruction opcodes in the multiple instruction opcodes. Compared with the instruction separation technology implemented by simply rewriting the abstract syntax tree in the prior art, the embodiment of the present application can accurately identify and separate the independent behavior descriptions of the instruction opcodes when processing mixed descriptions of instructions, thereby avoiding inaccurate separation or missed separation caused by mismatch of syntax patterns, thereby achieving the technical effect of improving the accuracy of instruction separation.

[0122] Optionally, in the instruction separation device provided in Example 3 of the present application, the identification unit includes: a first identification module, used to identify the instruction group defined in the source program to be processed, obtain multiple instruction opcodes, and store the multiple instruction opcodes in an instruction set; a second identification module, used to identify the function defined in the source program to be processed, and obtain the initial function body.

[0123] Optionally, in the instruction separation device provided in Example 3 of the present application, the processing unit includes: a first determination module, used to determine the first instruction opcode in the instruction set; a processing module, used to process the initial function body according to the first instruction opcode to obtain a target function body corresponding to the first instruction opcode; and a second determination module, used to repeatedly execute the next instruction opcode in the determined instruction set until the target function body corresponding to the last execution opcode is obtained.

[0124] Optionally, in the instruction separation device provided in Example 3 of the present application, the processing module includes: a propagation sub-module, used to perform constant propagation on the initial function body according to the first instruction opcode to obtain the processed initial function body; and a deletion sub-module, used to delete dead code on the processed initial function body to obtain the target function body corresponding to the first instruction opcode.

[0125] Optionally, in the instruction separation device provided in Example 3 of the present application, the propagation sub-module includes: a first generation sub-module, used to generate an assignment statement based on the first instruction opcode and the instruction variables in the initial function body; an addition sub-module, used to add the assignment statement to the initial function body to obtain the added initial function body; and a propagation sub-module, used to perform constant propagation on the added initial function body to obtain the processed initial function body.

[0126] Optionally, in the instruction separation device provided in Example 3 of the present application, the deletion sub-module includes: a second generation sub-module, used to generate a control flow chart based on the processed initial function body; an identification sub-module, used to identify dead code in the processed initial function body based on the control flow chart to obtain dead code information; and a deletion sub-module, used to delete dead code from the processed initial function body based on the dead code information to obtain a target function body corresponding to the first instruction opcode.

[0127] Optionally, in the instruction separation device provided in Example 3 of the present application, the device includes: a parsing unit, which is used to process the initial function body according to the instruction opcode in multiple instruction opcodes, obtain the target function body corresponding to the instruction opcode in multiple instruction opcodes, and then parse the target function body corresponding to the instruction opcode in multiple instruction opcodes, and generate a tool chain supporting the source program based on the parsing results, wherein the tool chain includes at least: a compiler and a simulator.

[0128] It should be noted that the acquisition unit 501, identification unit 502, and processing unit 503 described above correspond to steps S201 to S203 in Example 1. The examples and application scenarios implemented by the three units and the corresponding steps are the same, but are not limited to the contents disclosed in Example 1. It should be noted that the above modules, as part of the device, can be run in the computer terminal 10 provided in Example 1.

[0129] It should be noted that the preferred implementation scheme involved in the above embodiments of this application is the same as the scheme provided in Example 1, as well as the application scenario and implementation process, but is not limited to the scheme provided in Example 1.

[0130] Example 4

[0131] The embodiment of the present application may provide a computing device, which may be any computing device in a computing device terminal group. Optionally, in this embodiment, the computing device may also be replaced by a terminal device such as a mobile terminal.

[0132] Optionally, in this embodiment, the computing device may be located in at least one network device among a plurality of network devices of a computer network.

[0133] In this embodiment, the above-mentioned computing device can execute the program code of the following steps in the instruction separation method: obtaining the source program to be processed; identifying the source program to be processed to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; processing the initial function body according to the instruction opcodes in the multiple instruction opcodes to obtain the target function body corresponding to the instruction opcodes in the multiple instruction opcodes, so as to realize instruction separation of multiple instruction opcodes.

[0134] The above-mentioned computing device can execute the program code of the following steps in the instruction separation method: identifying the source program to be processed, obtaining multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes, including: identifying the instruction group defined in the source program to be processed, obtaining multiple instruction opcodes, and storing the multiple instruction opcodes in an instruction set; identifying the function defined in the source program to be processed, and obtaining the initial function body.

[0135] The above-mentioned computing device can execute the program code of the following steps in the instruction separation method: processing the initial function body according to the instruction opcode in multiple instruction opcodes to obtain the target function body corresponding to the instruction opcode in multiple instruction opcodes, including: determining the first instruction opcode in the instruction set; processing the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode; repeating the execution to determine the next instruction opcode in the instruction set until the target function body corresponding to the last execution opcode is obtained.

[0136] The above-mentioned computing device can execute the program code of the following steps in the instruction separation method: processing the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode, including: performing constant propagation on the initial function body according to the first instruction opcode to obtain the processed initial function body; deleting dead code on the processed initial function body to obtain the target function body corresponding to the first instruction opcode.

[0137] The above-mentioned computing device can execute the program code of the following steps in the instruction separation method: performing constant propagation on the initial function body according to the first instruction opcode, and obtaining the processed initial function body includes: generating an assignment statement according to the first instruction opcode and the instruction variables in the initial function body; adding the assignment statement to the initial function body to obtain the added initial function body; performing constant propagation on the added initial function body to obtain the processed initial function body.

[0138] The above-mentioned computing device can execute the program code of the following steps in the instruction separation method: performing dead code deletion on the processed initial function body to obtain the target function body corresponding to the first instruction opcode, including: generating a control flow chart based on the processed initial function body; identifying the dead code in the processed initial function body based on the control flow chart to obtain dead code information; performing dead code deletion on the processed initial function body based on the dead code information to obtain the target function body corresponding to the first instruction opcode.

[0139] The above-mentioned computing device can execute the program code of the following steps in the instruction separation method: after processing the initial function body according to the instruction opcode among multiple instruction opcodes to obtain the target function body corresponding to the instruction opcode among multiple instruction opcodes, the method includes: parsing the target function body corresponding to the instruction opcode among multiple instruction opcodes, and generating a tool chain supporting the source program based on the parsing results, wherein the tool chain includes at least: a compiler and a simulator.

[0140] Optionally, Figure 6 This is a structural block diagram of a computing device according to an embodiment of the present application. Figure 6 As shown, the computing device 60 may include: one or more ( Figure 6 Only one is shown in the figure) processor 602 and memory 604. The computing device 60 may also include a memory controller to control and manage the memory 604; the computing device 60 may also include a peripheral interface to connect to a radio frequency module, an audio module, and a display screen, etc.

[0141] Among them, the memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the instruction separation method and the tool chain generation tool in the embodiment of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, realizing the above-mentioned instruction separation method. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories can be connected to the computing device 60 via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0142] The processor can call the information and application programs stored in the memory through the transmission device to perform the following steps: obtain the source program to be processed; identify the source program to be processed to obtain multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes; process the initial function body according to the instruction opcodes in the multiple instruction opcodes to obtain the target function body corresponding to the instruction opcodes in the multiple instruction opcodes to realize instruction separation of the multiple instruction opcodes.

[0143] Optionally, the above-mentioned processor can also execute the program code of the following steps: identifying the source program to be processed, obtaining multiple instruction opcodes and initial function bodies corresponding to the multiple instruction opcodes, including: identifying the instruction group defined in the source program to be processed, obtaining multiple instruction opcodes, and storing the multiple instruction opcodes in an instruction set; identifying the function defined in the source program to be processed, and obtaining the initial function body.

[0144] Optionally, the above-mentioned processor can also execute the program code of the following steps: processing the initial function body according to the instruction opcode in multiple instruction opcodes to obtain the target function body corresponding to the instruction opcode in multiple instruction opcodes, including: determining the first instruction opcode in the instruction set; processing the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode; repeating the execution to determine the next instruction opcode in the instruction set until the target function body corresponding to the last execution opcode is obtained.

[0145] Optionally, the above-mentioned processor can also execute the program code of the following steps: processing the initial function body according to the first instruction opcode to obtain the target function body corresponding to the first instruction opcode, including: performing constant propagation on the initial function body according to the first instruction opcode to obtain the processed initial function body; deleting dead code on the processed initial function body to obtain the target function body corresponding to the first instruction opcode.

[0146] Optionally, the above-mentioned processor can also execute the program code of the following steps: performing constant propagation on the initial function body according to the first instruction opcode, and obtaining the processed initial function body includes: generating an assignment statement according to the first instruction opcode and the instruction variables in the initial function body; adding the assignment statement to the initial function body to obtain the added initial function body; performing constant propagation on the added initial function body to obtain the processed initial function body.

[0147] Optionally, the processor may also execute the following program code steps: performing dead code deletion on the processed initial function body to obtain a target function body corresponding to the first instruction opcode, including: generating a control flow chart based on the processed initial function body; identifying dead code in the processed initial function body based on the control flow chart to obtain dead code information; performing dead code deletion on the processed initial function body based on the dead code information to obtain a target function body corresponding to the first instruction opcode.

[0148] Optionally, the above-mentioned processor can also execute the program code of the following steps: after processing the initial function body according to the instruction opcode among multiple instruction opcodes to obtain the target function body corresponding to the instruction opcode among multiple instruction opcodes, the method includes: parsing the target function body corresponding to the instruction opcode among multiple instruction opcodes, and generating a tool chain supporting the source program based on the parsing results, wherein the tool chain includes at least: a compiler and a simulator.

[0149] It can be understood by those skilled in the art that Figure 6The structure shown is for illustration only, and the computing device 60 may also be a terminal device such as a smart phone, a tablet computer, a PDA, a mobile Internet device (MID), or a PAD. Figure 6 It does not limit the structure of the above electronic device. For example, the computing device 60 may also include Figure 6 More or fewer components (such as network interfaces, display devices, etc.) shown in, or with Figure 6 Different configurations shown.

[0150] A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0151] Example 5

[0152] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product can be used to store the program code executed by the instruction separation method provided in the first embodiment.

[0153] Optionally, in this embodiment, the computer program product may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group.

[0154] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0155] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0156] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0157] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0158] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0159] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0160] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An instruction separation method, characterized in that: include: Obtain the source program to be processed; Identifying the source program to be processed to obtain a plurality of instruction operation codes and initial function bodies corresponding to the plurality of instruction operation codes; The initial function body is processed according to the instruction operation code in the multiple instruction operation codes to obtain the target function body corresponding to the instruction operation code in the multiple instruction operation codes, so as to realize instruction separation of the multiple instruction operation codes.

2. The method according to claim 1, characterized in that Identifying the source program to be processed, obtaining a plurality of instruction operation codes and initial function bodies corresponding to the plurality of instruction operation codes, including: Identifying an instruction group defined in the source program to be processed, obtaining the plurality of instruction operation codes, and storing the plurality of instruction operation codes in an instruction set; The functions defined in the source program to be processed are identified to obtain the initial function body.

3. The method according to claim 2, characterized in that The initial function body is processed according to the instruction operation code in the multiple instruction operation codes to obtain the target function body corresponding to the instruction operation code in the multiple instruction operation codes, including: determining a first instruction opcode in the instruction set; Processing the initial function body according to the first instruction operation code to obtain a target function body corresponding to the first instruction operation code; Repeat the execution to determine the next instruction operation code in the instruction set until the target function body corresponding to the last execution operation code is obtained.

4. The method according to claim 3, characterized in that Processing the initial function body according to the first instruction operation code to obtain a target function body corresponding to the first instruction operation code includes: Performing constant propagation on the initial function body according to the first instruction opcode to obtain a processed initial function body; Dead code is deleted from the processed initial function body to obtain a target function body corresponding to the first instruction opcode.

5. The method according to claim 4, characterized in that The initial function body is subjected to constant propagation according to the first instruction opcode, and the processed initial function body includes: generating an assignment statement according to the first instruction opcode and the instruction variables in the initial function body; Adding the assignment statement to the initial function body to obtain an added initial function body; Constant propagation is performed on the added initial function body to obtain the processed initial function body.

6. The method according to claim 4, characterized in that Dead code is deleted from the processed initial function body to obtain a target function body corresponding to the first instruction opcode, including: Generate a control flow graph based on the processed initial function body; Identifying dead code in the processed initial function body according to the control flow chart to obtain dead code information; Dead code is deleted from the processed initial function body according to the dead code information to obtain a target function body corresponding to the first instruction opcode.

7. The method according to claim 1, characterized in that After processing the initial function body according to the instruction operation code among the multiple instruction operation codes to obtain the target function body corresponding to the instruction operation code among the multiple instruction operation codes, the method includes: The target function bodies corresponding to the instruction opcodes in the plurality of instruction opcodes are parsed, and a tool chain supporting the source program is generated based on the parsing result, wherein the tool chain includes at least a compiler and a simulator.

8. A tool chain generation tool, characterized in that: include: An instruction separation tool is used to separate instructions from a source program to be processed, thereby obtaining a target function body corresponding to an instruction operation code among a plurality of instruction operation codes; A generation tool is provided, wherein the target function body is parsed by the generation tool, and a tool chain supporting the source program is generated based on the parsing result, wherein the tool chain includes at least: a compiler and a simulator.

9. An instruction separation device, characterized in that: include: An acquisition unit, used for acquiring a source program to be processed; an identification unit, configured to identify the source program to be processed and obtain a plurality of instruction operation codes and initial function bodies corresponding to the plurality of instruction operation codes; The processing unit is used to process the initial function body according to the instruction operation code in the multiple instruction operation codes to obtain the target function body corresponding to the instruction operation code in the multiple instruction operation codes, so as to realize instruction separation of the multiple instruction operation codes.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the instruction separation method according to any one of claims 1 to 7.

11. A computing device, characterized in that include: a memory storing an executable program; A processor, configured to run the program, wherein the program executes the instruction separation method according to any one of claims 1 to 7 when running.

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