Processing method and device for satellite-borne processor instruction Cache multi-bit flipping
By identifying and isolating multi-bit flip errors in the onboard processor instruction cache and utilizing parity check and machine check interrupts, the onboard processor is able to respond quickly and recover stability, solving the multi-bit flip problem of the onboard processor in a radiation environment and improving the system's fault tolerance and mission continuity.
Patent Information
- Application Number
- CN202510625215.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-09-12
AI Technical Summary
Onboard processors are susceptible to single-particle upset effects in the space radiation environment, resulting in multi-bit upset errors. Existing technologies cannot effectively deal with this, affecting the reliability and stability of the processor and system.
By identifying multiple bit flips in the instruction cache, using parity error detection and machine check interrupts, we can quickly respond to and isolate errors, restore processor flow, and use the PowerPC 460 processor and data processing module for error correction.
It improves the reliability and stability of the onboard processor, ensures rapid recovery, adapts to different onboard processing architecture requirements, and has high flexibility.
Smart Images
Figure CN120631446A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of aerospace electronics technology, and in particular relates to a method and device for processing multi-bit flipping of an instruction cache of an onboard processor. Background Art
[0002] In the aerospace field, onboard processors are constantly exposed to radiation from high-energy particles such as heavy ions and protons, which can easily trigger single-event upsets (SEEs). With the continued scaling of CMOS device process sizes, the incidence of multi-bit upset errors (MBEs) caused by SEEs is increasing significantly. As the CPU's internal cache used to mitigate external memory access latency, the instruction cache is a critical time channel for the processor. Its high frequency of access means that MEBEs occurring in this area can directly threaten the reliability of the processor and the entire system. However, conventional onboard computer memory unit designs only have the capability to detect two errors and correct one error, failing to effectively handle single-event multi-bit upset failures. Existing solutions often rely on triggering an operating system reset after a multi-bit upset in the instruction cache. This passive approach struggles to meet the high-reliability requirements of onboard processors in the extreme space environment. Summary of the Invention
[0003] To solve the above problems, the present invention proposes a method and device for processing multi-bit flips in the instruction cache of an onboard processor. By detecting and processing multi-bit flips in the instruction cache, the risk of processor failure caused by erroneous data is reduced, and the reliability of the onboard processor is improved; it ensures that the processor can quickly return to normal when facing multi-bit flips in the instruction cache, thereby enhancing the stability of the onboard system; the method can be adjusted and optimized according to different onboard processing architectures and application requirements, and has high flexibility.
[0004] A first aspect of the present invention provides a method for processing multi-bit flips in an onboard processor instruction cache, comprising: Based on the instruction cache, the error correction code of the processor module is used to identify the instruction cache with multiple bits flipped and marked as the instruction cache with parity error; The instruction cache based on the parity check error obtains a machine check interrupt status, an interrupt type and a parity check result by starting a machine check interrupt; Data of the instruction cache based on the parity error and a cache valid identifier; The machine checks the interrupt status and the interrupt type, and restores the processor module workflow.
[0005] Preferably, the step of obtaining a machine check interrupt status and an interrupt type by starting a machine check interrupt based on the instruction cache having the parity check error further comprises: Start machine check interrupt to obtain machine check interrupt status and interrupt type; The instruction cache based on the parity check error obtains a parity check result through a parity check.
[0006] Preferably, the step of starting a machine check interrupt to obtain a machine check interrupt status and an interrupt type further comprises: Save the currently executed instruction flow and set the stack to the machine check interrupt stack; Update the interrupt type and the interrupt status of the MCSR register; The currently executed instruction flow of the processor module is paused.
[0007] Preferably, the step of obtaining a parity check result through a parity check based on the instruction cache having the parity check error further comprises: Acquire the data of the instruction cache with the parity error and identify the check module and the data module; The parity check result is obtained based on the data module and the check module. The specific logic is: verify the data module through the check module to determine whether the data module generates more than 2 bits of error compared with the check module. If so, the parity check result is wrong, otherwise it is correct.
[0008] Preferably, the step of updating the data of the instruction cache with the parity check error and the cache valid flag based on the parity check result further includes: If the check result is an error, updating the instruction cache valid flag of the parity check error to invalid; The data of the instruction cache with the parity check error is updated to be preset data, and the preset data satisfies the parity check.
[0009] Preferably, the step of updating the machine check interrupt status and the interrupt type further comprises: Clear the interrupt type and the interrupt status of the MCSR register; Remove the machine check interrupt stack that sets up the stack; Starts the instruction flow before the interrupt.
[0010] A second aspect of the present invention provides a processing device for multi-bit flipping of an instruction cache of an onboard processor, comprising: A processor module is used to identify an instruction cache with multiple bits flipped in an instruction cache and mark it as an instruction cache with a parity error, mark a machine check interrupt status, interrupt type, cache valid flag, and drive a start-up machine check interrupt process; The data processing module is used to obtain the machine check interrupt status and interrupt type by judging the parity check of the instruction cache and to restore the working status of the instruction cache and the processor module.
[0011] Preferably, the processor module adopts a PowerPC 460 processor.
[0012] The third aspect of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored on the memory and runnable on the processor. When the computer program is executed by the processor, the steps of a processing method for multi-bit flipping of an onboard processor instruction cache as described in any one of the above items are implemented.
[0013] A fourth aspect of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by a processor, implement any of the above-mentioned methods for processing multi-bit flipping of an onboard processor instruction cache.
[0014] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: 1. Improve reliability: By timely detecting and handling multi-bit flips in the instruction cache, the risk of processor failure caused by erroneous data is reduced, and the reliability of the onboard processor is improved.
[0015] 2. Enhanced stability: Ensures that the processor can quickly recover to normal when facing multiple-bit flips in the instruction cache, thereby enhancing the stability of the onboard system.
[0016] 3. Flexible adaptation: This method can be adjusted and optimized according to different onboard processing architectures and application requirements, and has high flexibility. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings, wherein: Figure 1 The present invention is a flowchart of a method for processing multi-bit flips in an onboard processor instruction cache. DETAILED DESCRIPTION
[0018] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact ratios, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.
[0019] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0020] First embodiment See also Figure 1 A first aspect of the present invention provides a method for processing multi-bit flips in an onboard processor instruction cache, comprising: S100: Identifying an instruction cache with multiple bits flipped based on an error correction code of a processor module and marking it as an instruction cache with a parity error; S200: Based on the instruction cache of the parity check error, a machine check interrupt is started to obtain a machine check interrupt status, an interrupt type, and a parity check result; S300: Data of instruction cache based on parity check error and cache valid flag; S400: Update the machine to check the interrupt status and interrupt type, and restore the processor module workflow.
[0021] To address the problem of single-event upsets (SEFs) causing program errors in high-performance processors used in onboard computers, the present invention provides a method for handling multi-bit upsets in the instruction cache of an onboard processor. The processor in this embodiment uses a PowerPC 460, but other processor models can also be used. This embodiment is not limiting. The specific process is as follows: S100: Identify multiple bits flipped in the instruction cache through a hardware mechanism and mark it as an instruction cache parity error; S200: When a parity check error is detected in the instruction cache, a machine check interrupt is started. Before starting the machine check interrupt, the following steps need to be implemented: saving the currently executed instruction flow, setting the stack as the machine check interrupt stack; and updating the interrupt type and the interrupt status of the MCSR register. The parity check result is obtained through a parity check based on the instruction cache with the parity check error. The logic of the parity check result is as follows: obtaining the data of the instruction cache with the parity check error and identifying the check module and the data module; obtaining the parity check result based on the data module and the check module. The specific logic is as follows: verifying the data module through the check module to determine whether the data module has an error of more than 2 bits compared to the check module. If so, the parity check result is an error; otherwise, it is correct.
[0022] S300: If the parity check result is an error, the data of the instruction cache with the parity check error and the cache valid flag need to be reset; the specific logic is: if the check result is an error, the instruction cache valid flag of the parity check error is updated to invalid; the data of the instruction cache with the parity check error is updated to the preset data, and the preset data satisfies the parity check. The instruction cache valid flag of the parity check error is invalid in order to ensure that the corresponding data will not be executed by the processor. The data of the instruction cache with the parity check error is updated to the preset data, and the correct check bit is ensured to be written by the newly filled data; the instruction data is read from the volatile memory, and the correction calculation is performed, and then filled into the instruction cache.
[0023] S400: Starting the workflow before the machine check interrupt: clearing the interrupt type and the interrupt status of the MCSR register; removing the machine check interrupt stack set up; starting the instruction flow before the interrupt.
[0024] Preferably, the step of obtaining a machine check interrupt status and an interrupt type by starting a machine check interrupt based on a parity error instruction cache further includes: Start machine check interrupt to obtain machine check interrupt status and interrupt type; The instruction cache based on the parity error obtains a parity result through a parity check.
[0025] By combining parity checks with machine check interrupts, instruction cache error handling implements a full process of "detection-location-isolation-recovery." This allows for rapid error response to prevent escalation and precise location of the error source, supporting efficient diagnosis.
[0026] Preferably, the step of starting a machine check interrupt to obtain a machine check interrupt status and an interrupt type further comprises: Save the currently executed instruction flow and set the stack to the machine check interrupt stack; Update the interrupt type and interrupt status of the MCSR register; The currently executed instruction flow of the processor module is paused.
[0027] Through context preservation, stack isolation, and error status recording, rapid response, accurate diagnosis, and efficient recovery of hardware errors are achieved, significantly improving the system's fault tolerance and data integrity.
[0028] Preferably, the step of obtaining a parity check result by performing a parity check on the instruction cache based on the parity check error further includes: Obtain the data of the instruction cache with parity error and identify the check module and data module; The parity check result is obtained based on the data module and the check module. The specific logic is: verify the data module through the check module to determine whether the data module generates more than 2 bits of error compared with the check module. If so, the parity check result is wrong, otherwise it is correct.
[0029] The parity of the instruction cache is checked to ensure data consistency during storage and retrieval. If the parity check result is "error," a machine check interrupt (MCE) is immediately triggered, pausing the current task and initiating error handling. This prevents further execution of the erroneous instruction, preventing the error from propagating and causing system crashes, while also providing a time window for subsequent error correction or recovery. This allows for rapid and cost-effective detection of single-bit errors, and isolates the error through an interrupt mechanism, safeguarding instruction cache data integrity and system stability.
[0030] Preferably, the step of updating the data of the instruction cache with the parity check error and the cache valid flag based on the parity check result further includes: If the check result is an error, the instruction cache valid flag of the parity error instruction is updated to invalid; The data of the instruction cache with the parity check error is updated to the preset data, and the preset data satisfies the parity check.
[0031] Through the combination of invalidation and padding, a rapid response and isolation to parity errors is achieved, ensuring that the system can maintain basic functions in the event of hardware failures while providing a basis for subsequent data recovery.
[0032] Preferably, the step of updating the machine check interrupt status and the interrupt type further comprises: Clear the interrupt type and interrupt status of the MCSR register; Remove the machine check interrupt stack that sets up the stack; Starts the instruction flow before the interrupt.
[0033] By clearing the MCSR and removing the interrupt stack, all traces of the hardware error are eliminated, preventing the error from being repeatedly triggered or interfering with subsequent operations. Interrupt stack resources are released, hardware resources are reclaimed, and stack isolation prevents the error from spreading to the main task. By restoring the instruction flow before the interrupt, tasks can be seamlessly transitioned, ensuring that the onboard processor can continue to efficiently execute critical tasks after error handling. In a spaceborne environment, this rapid recovery mechanism is crucial to mission continuity and system stability, preventing single points of failure from causing the entire mission to fail. Lightweight operations (clearing registers, removing the stack, and restoring the context) meet the low power and high real-time requirements of onboard equipment, while also achieving a closed-loop error handling process through the collaboration of hardware and software.
[0034] Second embodiment A second aspect of the present invention provides a processing device for multi-bit flipping of an instruction cache of an onboard processor, comprising: A processor module is used to identify an instruction cache with multiple bits flipped in an instruction cache and mark it as an instruction cache with a parity error, mark the machine check interrupt status, interrupt type, cache valid flag, and drive the process of starting the machine interrupt check; The data processing module is used to obtain the machine check interrupt status and interrupt type by judging the parity check of the instruction cache and to restore the working status of the instruction cache and the processor module.
[0035] The processor module is used to identify multi-bit flips in the instruction cache and mark them as instruction cache parity errors and trigger the start of a machine check interrupt. Before starting the machine check interrupt, it is also necessary to implement the following: save the currently executed instruction flow, set the stack as the machine check interrupt stack; and update the interrupt type and interrupt status of the MCSR register. Based on the instruction cache with the parity check error, a parity check result is obtained through parity check. The logic of the parity check result is as follows: obtain the data of the instruction cache with the parity check error and identify the check module and the data module; obtain the parity check result based on the data module and the check module. The specific logic is as follows: verify the data module through the check module to determine whether the data module has more than 2 bits of error compared to the check module. If so, the parity check result is an error, otherwise it is correct.
[0036] The functions implemented by the data processing module include the following: if the parity check result is an error, the data and cache valid flag of the instruction cache with the parity check error need to be reset; the specific logic is: if the check result is an error, the instruction cache valid flag of the parity check error is updated to invalid; the data of the instruction cache with the parity check error is updated to the preset data, and the preset data satisfies the parity check. The instruction cache valid flag of the parity check error is invalid in order to ensure that the corresponding data will not be executed by the processor. The data of the instruction cache with the parity check error is updated to the preset data, and the correct check bit is written by the newly filled data; the instruction data is read from the volatile memory, and the correction calculation is performed, and then filled into the instruction cache. The workflow before starting the machine check interrupt: clear the interrupt type and the interrupt status of the MCSR register; remove the machine check interrupt stack set on the stack; start the instruction flow before the interrupt.
[0037] Preferably, the processor module adopts a PowerPC 460 processor.
[0038] The PowerPC 460 can respond to external events (such as attitude adjustment instructions) in real time and trigger with low latency to ensure the priority of critical tasks.
[0039] Third embodiment The third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the computer program is executed by the processor, the steps of any one of the above-mentioned methods for processing multi-bit flipping of an onboard processor instruction cache are implemented.
[0040] This embodiment provides an electronic device, which runs a computer program. The computer program implements any of the steps of the above-mentioned method for processing multi-bit flipping of an onboard processor instruction cache.
[0041] Fourth embodiment A fourth aspect of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by a processor, implement any one of the above-mentioned methods for processing multi-bit flipping of an onboard processor instruction cache.
[0042] This embodiment provides a readable storage medium, on which a processing program is stored. When the processing program is executed by a processor, any one of the above-mentioned processing methods for multi-bit flipping of an onboard processor instruction cache is implemented.
[0043] In the description of this application, it should be noted that the terms "inner" and "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships in which the product of this application is typically placed when in use. These terms are used solely to facilitate the description of this application and to simplify the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" and the like are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0044] It should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0045] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the identification content specifically executed by the above-described system and device can refer to the corresponding process in the aforementioned method embodiment.
[0046] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the scope of protection of the present invention.
Claims
1. A method for processing multi-bit flips in an onboard processor instruction cache, characterized in that: include: Based on the instruction cache, the error correction code of the processor module is used to identify the instruction cache with multiple bits flipped and marked as the instruction cache with parity error; The instruction cache based on the parity check error obtains a machine check interrupt status, an interrupt type and a parity check result by starting a machine check interrupt; Update the data of the instruction cache with the parity check error and the cache valid flag based on the parity check result; The machine checks the interrupt status and the interrupt type, and restores the processor module workflow.
2. The method for processing multi-bit flip of instruction cache of onboard processor according to claim 1, characterized in that: The step of obtaining a machine check interrupt status and an interrupt type by starting a machine check interrupt based on the instruction cache having the parity check error further includes: Start machine check interrupt to obtain machine check interrupt status and interrupt type; The instruction cache based on the parity check error obtains a parity check result through a parity check.
3. The method for processing multi-bit flip of instruction cache of onboard processor according to claim 2, characterized in that: The step of starting a machine check interrupt to obtain a machine check interrupt status and interrupt type further includes: Save the currently executed instruction flow and set the stack to the machine check interrupt stack; Update the interrupt type and the interrupt status of the MCSR register; The currently executed instruction flow of the processor module is paused.
4. The method for processing multi-bit flips in instruction cache of a spaceborne processor according to claim 2, characterized in that: The step of obtaining a parity check result by performing a parity check on the instruction cache having the parity check error further includes: Acquire the data of the instruction cache with the parity error and identify the check module and the data module; The parity check result is obtained based on the data module and the check module. The specific logic is: verify the data module through the check module to determine whether the data module generates more than 2 bits of error compared with the check module. If so, the parity check result is wrong, otherwise it is correct.
5. The method for processing multi-bit flip of instruction cache of onboard processor according to claim 1, characterized in that: The step of updating the data of the instruction cache with the parity check error and the cache valid flag based on the parity check result further includes: If the check result is an error, updating the instruction cache valid flag of the parity check error to invalid; The data of the instruction cache with the parity check error is updated to be preset data, and the preset data satisfies the parity check.
6. The method for processing multi-bit flip of instruction cache of onboard processor according to claim 1, characterized in that: The step of updating the machine check interrupt status and the interrupt type further comprises: Clear the interrupt type and the interrupt status of the MCSR register; Remove the machine check interrupt stack that sets up the stack; Starts the instruction flow before the interrupt.
7. A processing device for multi-bit flipping of an onboard processor instruction cache, characterized in that: include: A processor module is used to identify an instruction cache with multiple bits flipped in an instruction cache and mark it as an instruction cache with a parity error, mark the machine check interrupt status, interrupt type, cache valid flag, and drive the process of starting the machine check interrupt; The data processing module is used to obtain the machine check interrupt status and interrupt type by judging the parity check of the instruction cache and to restore the working status of the instruction cache and the processor module.
8. The device for multi-bit flipping of an onboard processor instruction cache according to claim 7, characterized in that: The processor module adopts PowerPC 460 processor.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by a processor, the steps of a method for processing multi-bit flipping of an onboard processor instruction cache as described in any one of claims 1 to 6 are implemented.
10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instruction is executed by the processor, a processing method for multi-bit flipping of an onboard processor instruction cache according to any one of claims 1 to 6 is implemented.