Admittance matrix processing module and power flow type parallel computing device

Abstract

The invention relates to an admittance matrix processing module and a power flow type parallel computing device, and the admittance matrix processing module comprises an admittance matrix flow type computing module which is used for receiving branch data, judging whether a branch contains a transformer or not according to the value of the transformation ratio of a non-standard transformer, and computing a branch equivalent circuit, mutual admittance calculation of the current node frombus to the target node tobus is completed within the interval of receiving the data of the two branches, and a calculation result is synchronously written into an admittance matrix queue; and the admittance matrix access module is used for receiving the mutual admittance value in the upper triangular form in the admittance matrix queue and writing the mutual admittance value in the upper triangular form into the memory when the write burst length of the memory is reached. According to the method, the admittance matrix value and the parallel pipeline calculation of the power flow are calculated in a dynamic streaming manner.

Description

Technical Field

[0001] The present invention relates to the technical field of power flow calculation, and in particular to an admittance matrix processing module and a power flow parallel calculation device. Background Art

[0002] Power flow calculation is a very important analytical calculation for power systems. It calculates the electrical quantities of the power system under steady-state operation, including active power, reactive power, and voltage distribution in the power grid, based on the power system's wiring method, parameters, and operating conditions. Power flow calculation is also the basis for system safety, stability, and reliability analysis, and is used to study various issues raised in system planning and operation. For planned power systems, power flow calculation can verify whether the proposed power system planning scheme can meet the requirements of various operating modes; for operating power systems, power flow calculation can predict whether various load changes and changes in network structure will endanger system safety, whether the voltage of all buses in the system is within the allowable range, whether various components in the system (lines, transformers, etc.) will be overloaded, and what preventive measures should be taken in advance when overload is likely to occur.

[0003] Existing literature (Nwankpa C, Johnson J, Nagvajara P, et al.FPGA hardware results for power system computation[C] / / 2009 IEEE / PES Power Systems Conference and Exposition.0[2023-09-26].DOI:10.1109 / PSCE.2009.4839953.) proposes a power flow calculation FPGA system based on the Newton-Raphson method by collecting data from real-time SCADA system network and telemetry transmission.

[0004] This solution, based on the traditional Newton-Raphson method, suffers from long solution times and even non-convergence when the matrix dimensions are large, preventing it from providing a solution to the system of equations. Furthermore, faced with the dynamic changes in massive amounts of power grid data, this solution suffers from high storage resource consumption and slow computation speeds when calculating power flows, failing to fully leverage the speed advantages of FPGAs in data pipelining and matrix parallelism. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an admittance matrix processing module and a power flow parallel computing device, which can realize parallel pipeline computing of power flow.

[0006] The technical solution adopted by the present invention to solve the technical problem is to provide an admittance matrix processing module, including:

[0007] The admittance matrix streaming calculation module is used to receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval of receiving two branch data, and synchronously write the calculation results to the admittance matrix queue;

[0008] The admittance matrix access module is used to receive the upper triangular transadmittance values ​​in the admittance matrix queue and write the upper triangular transadmittance values ​​into the memory when the memory write burst length is reached.

[0009] When performing mutual admittance calculation, the admittance matrix streaming calculation module maps the mutual admittance value of the current node from_bus to the target node to_bus in the upper triangular form to the contribution value to the target node to_bus in the lower triangular form of the admittance matrix, and accumulates the mutual admittance value of the target node to_bus into the self-admittance matrix register corresponding to the label of the target node to_bus. When all rows of the current node from_bus are read, the self-admittance of the node is synchronously calculated. When all branch data are read, the self-admittance registers of each node are synchronously accumulated and updated.

[0010] When the current branch does not contain a transformer, the calculation process of the admittance matrix flow calculation module is as follows:

[0011] Calculate the square sum of impedances, the real part of branch admittance, the imaginary part of branch admittance, and the mutual admittance of the current node from_bus to the target node to_bus; pull high the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue, and write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue; write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the mutual admittance and write of the current node from_bus to the target node to_bus, increment the row data count counter of the current node from_bus by 1;

[0012] Calculate the self-admittance of the target node to_bus, where the self-admittance is the real and imaginary parts of the branch admittance plus half of the susceptance of the branch to the ground at both ends; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the target node to_bus to the low bit of the self-admittance register of the target node to_bus;

[0013] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, and update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

[0014] When the current branch contains a transformer, the calculation process of the admittance matrix flow calculation module is as follows:

[0015] Calculate the sum of squares of the transformation ratio, the sum of squares of the impedance, the real part of the branch admittance and the imaginary part of the branch admittance when the transformer is not included, and the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part; pull up the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, and write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the calculation and writing of the mutual admittance including the transformer conversion part of the current node from_bus to the target node to_bus, add 1 to the row data number counter of the current node from_bus;

[0016] Calculate the self-admittance of the current node from_bus end including the transformer conversion, and the self-admittance of the target node to_bus end including the transformer conversion;

[0017] Calculate the self-admittance of the target node to_bus, which is the self-admittance of the target node to_bus including the transformer conversion plus half of the susceptance of the branch to ground; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the current node to_bus to the low bit of the self-admittance register of the target node to_bus;

[0018] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus; update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

[0019] When the admittance matrix access module writes the upper triangular mutual admittance value into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​less than or equal to the maximum burst length, the following writing process is performed:

[0020] Setting a preset multiple of the non-zero elements in the current row of the admittance matrix as the read / write burst length of the memory; when the read / write burst length of the memory does not reach the read / write burst length of the memory after the data of one row of the admittance matrix is ​​retrieved, continuing to retrieve the data of the next row, determining the accumulated value of the non-zero elements of the next row, setting a GB_row_num_FIFO queue to store the number of non-zero elements in each row of the admittance matrix, and writing the number of non-zero elements in the current row of the admittance matrix into the GB_row_num_FIFO queue;

[0021] Calculate the number of non-zero elements of the next row of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, calculate the number of non-zero elements of the current row; update the value of the row accumulation counter pointed to by the address pointer register of the current row of the admittance matrix;

[0022] Update the number of bytes that need to be transmitted in the current accumulated admittance matrix;

[0023] Repeat the above steps. When the number of bytes to be transmitted in the currently accumulated admittance matrix is ​​greater than the maximum burst length, set the read / write burst length of the memory to the maximum burst length, extract the non-zero elements in the row pointed to by the current row address pointer register of the admittance matrix, and update the register for the number of remaining untaken elements. If the value in the register for the number of remaining untaken elements is greater than the maximum burst length, directly write the data read from the memory into the admittance matrix queue and update the value of the register for the number of remaining untaken elements.

[0024] Repeat the above data reading operation until the value in the register for the number of remaining unread elements is less than the maximum burst length; take out the number of non-zero elements in the next row from the GB_row_num_FIFO queue, update the current row address pointer register of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, calculate the number of non-zero elements in the current row; update the value of the row cumulative non-zero element counter; accumulate the number of elements to be read in the next row to the byte number register.

[0025] When the admittance matrix access module writes the mutual admittance value in upper triangular form into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​greater than the maximum burst length, the value in the register for the number of remaining untaken elements is updated to the sum of the preset multiple of the non-zero elements in the current row of the admittance matrix and the maximum burst length, and the writing process is executed.

[0026] The technical solution adopted by the present invention to solve the technical problem is to provide an admittance matrix processing method, including:

[0027] Receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval of receiving two branch data, and synchronously write the calculation results to the admittance matrix queue;

[0028] The upper triangular transadmittance values ​​in the admittance matrix queue are received, and when a memory write burst length is reached, the upper triangular transadmittance values ​​are written into the memory.

[0029] The technical solution adopted by the present invention to solve the technical problem is: to provide a power flow parallel computing device, including the above-mentioned admittance matrix processing module.

[0030] The power flow parallel computing device further comprises:

[0031] The data receiving module is used to receive the binary data sequence of the power grid, parse the branch data format, shift the valid byte data obtained by parsing, and assemble them into branch data;

[0032] A power imbalance dynamic increment calculation module is used to calculate the dynamic increment of the power imbalance of a node according to the node type;

[0033] Jacobian matrix dynamic incremental calculation module, used to calculate the partial derivatives of the power and voltage of the i-th node with respect to the j-th node voltage according to the node type;

[0034] A hybrid compression storage module for the Jacobian matrix, which is used to store the row elements of the Jacobian matrix in a row-compressed format and establish a column data element linked list to implement read and write operations on the rows and columns of the Jacobian matrix;

[0035] Jacobian matrix block partitioning calculation module, used to divide the Jacobian matrix into blocks for calculation;

[0036] A Jacobian matrix node sorting module is used to sort the nodes of the Jacobian submatrix structure calculated by the Jacobian matrix block partitioning calculation module;

[0037] The tree topology calculation module of the matrix node is used to dynamically calculate the column data element linked list to obtain the Jacobi parallel hierarchical elimination tree;

[0038] Matrix sub-node resource allocation module, used to allocate computing resources to each node in the Jacobi parallel hierarchical elimination tree;

[0039] Jacobian matrix parallel elimination tree calculation module, used to optimize the node ordering of the Jacobian matrix;

[0040] A node merging assembly tree calculation module is used to merge nodes with the same non-zero element structure in the Jacobi parallel hierarchical elimination tree into super nodes, and calculate the parallel hierarchical assembly tree of the Jacobi matrix based on the super nodes;

[0041] The iterative parallel computing module is used to perform sub-matrix decomposition calculations from the lower layer to the upper layer of the parallel hierarchical assembly tree of the Jacobian matrix, and then allocate the optimal number of computing resources to each node to perform parallel calculations on the subtree composed of all descendant nodes of the root node in the tree.

[0042] The technical solution adopted by the present invention to solve its technical problem is: providing a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned admittance matrix processing method are implemented.

[0043] Beneficial effects

[0044] Due to the adoption of the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the existing technology: the present invention targets the characteristics of power grid data flow and realizes the mutual admittance calculation by utilizing the symmetry of line impedance data without storing the original line data, thereby realizing the calculation of the lower triangular part of the admittance matrix data, completing the dynamic streaming calculation of the admittance matrix value and the parallel pipeline calculation of the power flow, improving the computational efficiency of the power flow calculation mode, reducing resource consumption, and accelerating the power flow calculation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a timing diagram of the flow calculation of the admittance matrix in the first embodiment of the present invention;

[0046] Figure 2 It is a storage timing logic diagram of the power flow branch data sequence in the first embodiment of the present invention;

[0047] Figure 3 2 is a schematic diagram of the storage structure of the admittance matrix queue in the first embodiment of the present invention;

[0048] Figure 4 This is a flow chart of calculating the admittance matrix using flow branch data stream method in the first embodiment of the present invention;

[0049] Figure 5 1 is a timing diagram of an SDRAM read admittance matrix in a first embodiment of the present invention;

[0050] Figure 6 It is a structural diagram of a power flow parallel computing device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0051] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0052] A first embodiment of the present invention relates to an admittance matrix processing module, comprising:

[0053] The admittance matrix streaming calculation module is used to receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval of receiving two branch data, and synchronously write the calculation results to the admittance matrix queue;

[0054] The admittance matrix access module is used to receive the upper triangular transadmittance values ​​in the admittance matrix queue and write the upper triangular transadmittance values ​​into the memory when the memory write burst length is reached.

[0055] like Figure 1 The figure shows the timing logic for the FPGA to receive the non-zero binary data sequence branch_data in the form of a triplet of power flow calculation branches transmitted from the serial port. Here, branch_data = {frombus[31:0], tobus[31:0], impedance_R[31:0], impedance_X[31:0], susceptance_B[31:0], tranf_ratio[31:0]}. Each row of branch data in branch_data is 24 bytes, consisting of six data blocks, each with four bytes. Frombus and tobus represent the 32-bit branch start and end point numbers, respectively; impedance_R and impedance_X represent the 32-bit branch resistance and reactance, respectively; susceptance_B represents the 32-bit branch susceptance to ground; and tranf_ratio represents the non-standard transformation ratio coefficient for branches containing transformers. The FPGA does not need to store the original input data as a cache when receiving data from the serial port. It can directly complete the calculation of the network admittance matrix data within the interval between two data receptions. This implementation method designs a pipelined data writing method to save the admittance matrix results to the synchronous dynamic random access memory (SDRAM).

[0056] Figure 2This is the storage timing logic for the FPGA power flow branch data sequence. The FPGA power flow board is set to a clock frequency of 50 MHz, a period of 20 ns, and a serial port receive baud rate of 115200 Bps. First, each data block in the branch is assembled into four-byte units by the serial port receive module. When the branch receive signal branch_sig is asserted, the FPGA receives a byte of data, data_out, every 434 clock cycles. The data is stored in the data register after a one-cycle delay. count_data represents the number of branch data rows received, and data_type represents the data type identifier. data_type is a cyclic count from 1 to 6. Within each counting interval, data is assembled every four clock cycles and stored in registers frombus, tobus, impedance_R, impedance_X, susceptance_B, and tranf_ratio. When a row of data units in a branch is received, the row reception completion signal one_row_flag is pulled high (←1). The serial port receives one data bit every 434 clock cycles. Receiving one byte requires 434 × 8 cycles. Each data type is 4 bytes long, and a data unit has 6 data units. Therefore, transmitting one data unit requires 434 × 8 × 4 × 6 cycles. Whenever data_type = 6 and one_row_flag = 1, the data_type = 1 cycle begins. During the interval between each row of data being passed to the FPGA, the mutual admittance calculation between from_bus and to_bus begins, and the accumulated self-admittance of from_bus is saved in the corresponding register. Furthermore, since the branch data only retains the upper triangular matrix data, directly calculating the self-admittance data for each row in the admittance matrix would be impossible due to the lack of the lower triangular matrix data. This implementation proposes a dynamic incremental calculation process for the lower triangular admittance matrix, storing the diagonal self-admittance values ​​of the admittance matrix separately in the dig_GB[63:0][n-1:0] register. dig_GB is 64 bits long and has a depth of n cells, where n is the number of network nodes. When calculating the admittance value of from_bus to other nodes, the admittance value of the target to_bus is dynamically accumulated and saved in the self-admittance diagonal matrix dig_GB. When the i-th row data is read, dig_GB[i] is also calculated synchronously. When the entire branch triplet data binary sequence is transmitted, the upper triangular GB matrix streaming calculation is synchronously completed and the result is saved in SDRAM.

[0057] Figure 3This is an admittance matrix queue storage structure. A data unit contains the mutual admittance from_bus to to_bus, stored in the order {conductance G, admittance B, admittance column index GB_col}. The GB matrix uses a row-compressed storage format and includes three registers: GB_row_ptr[31:0][n:0], GB_col[31:0][max_GB-1:0], and GB_data[63:0][max_GB-1:0]. n and max_GB represent the register depth, with n representing the number of power flow calculation nodes and max_GB being the preset maximum non-zero element storage capacity of the matrix. GB_row_ptr stores the row address of the first non-zero element in each row of the admittance matrix, GB_col represents the column index of the non-zero element, and GB_data represents the data value of the non-zero element.

[0058] Figure 4For the streaming calculation process of branch data of the tidal current branch and the GB admittance matrix. The streaming calculation of the admittance matrix is divided into 3 steps: Step 1, save the relevant lower triangular mutual admittance values of the historical to_bus to the diagonal register dig_GB of the admittance matrix in advance; Step 2, calculate the mutual admittance of the current form_bus to the to_bus (i < j); Step 3, write all the accumulated values of the mutual admittance of the current from_bus row to the target node. When the FPGA receives the from_bus of the i-th data, every time it receives a to_bus data, it starts to calculate the corresponding mutual admittance value of the from_bus to the to_bus and sends the result to the GB_FIFO queue. According to the read transformer turn ratio tranf_ratio value, it is judged whether there is a transformer in the branch. If tranf_ratio = 1, it means the branch does not contain a transformer, then the branch mutual admittance value is directly the equivalent calculation of the branch impedance value and the shunt admittance to the ground at both ends; if tranf_ratio ≠ 1, it indicates that the branch contains a non-standard turn ratio transformer, and it needs to be calculated according to the equivalent circuit of the transformer. When all the data of the node from_bus to all to_bus nodes are read and calculated, the self-admittance of the node from_bus is also accumulated and saved to the dia_GB[from_bus] register. At the same time, during the process of calculating the mutual admittance value of the from_bus to the to_bus each time, the corresponding mutual admittance value is synchronously accumulated and saved to dia_GB, that is, dia_GB[to_bus] ← dia_GB[to_bus] + the mutual admittance value of the current from_bus to the to_bus. Finally, when the entire branch is read, the correct self-admittance value of each node is saved in the dia_GB register. Each unit of the GB_FIFO[31:0][255:0] queue is 32 bits, and the depth is 256 cells, which stores the upper triangular mutual admittance part of the GB admittance matrix, and stores the conductance B, susceptance B, and column label value GB_col in three consecutive cells respectively.

[0059] When the admittance matrix streaming calculation module in this embodiment performs mutual admittance calculation, it maps the upper triangular form of the mutual admittance value of the current node from_bus to the target node to_bus to the contribution value to the lower triangular target node to_bus of the admittance matrix, accumulates the mutual admittance value of the target node to_bus to the self-admittance matrix register corresponding to the label of the target node to_bus. When all the rows of the current node from_bus are read, the self-admittance of the node is synchronously calculated. When all the branch data are read, the self-admittance registers of each node are synchronously accumulated and updated. Specifically as follows:

[0060] Initialize the branch counter for reads (count_branch←0). The total number of branches is branch_num. When the FPGA data reading module receives the valid read branch signal (read_branch_sig=1), it begins receiving the branch binary sequence from the serial port. Initialize the valid data byte counter (cnt_bit) (cnt_bit←0). cnt_bit receives a valid bit of data every 434 clock cycles and begins counting repeatedly. Initialize the read byte counter (cnt_byte←0). Initialize the data type identifier register (data_type←1), indicating that the data being received is of the from_bus type. Initialize the data counter (cnt_one_data) (cnt_one_data←0), indicating the number of cycles required to read a complete 4-byte data stream.

[0061] When the number of branches read in, count_branch, is less than the total number of branches, branch_num, the following process is repeated to perform the flow calculation of the mutual admittance and self-admittance of the admittance matrix.

[0062] When the data counter cnt_one_data = 434 × 8 × 4, it indicates that a complete data has been read in. The data valid signal is pulled high, that is, data_flga←1. When data_flga = 1, the current data type register data_type is determined. When data_type = 1, 2, 3, 4, 5, or 6, the data is written to the from_bus, to_bus, impedance_R, impedance_X, susceptance_B, and tranf_ratio registers respectively.

[0063] Then determine whether the current branch contains a transformer, and consider two situations based on whether the transformer is contained, and perform different calculation processes.

[0064] If the transformer ratio register tranf_ratio=1, it means that the current branch does not contain a transformer. The calculation process includes two parts, namely the mutual admittance part and the self-admittance accumulation part.

[0065] First, calculate the mutual admittance of the current node from_bus to the target node to_bus:

[0066] First calculate the square sum of impedance, that is , and then calculate the real part of the branch admittance and the imaginary part of the branch admittance respectively, that is, , , then calculate the mutual admittance of the current node from_bus to the target node to_bus, including the conductance data from_to_G and the susceptance data from_to_B, that is, from_to_G←-real_admittance, from_to_B←-imag_admittance. Then pull high the write valid signal W_GB_FIFO of the write admittance matrix queue GB_FIFO, that is, set W_GB_FIFO←1, execute the operation of writing the conductance data from_to_G into the admittance matrix queue GB_FIFO, that is, write_FIFO[GB_FIFO,from_to_G], then execute the operation of writing the admittance data from_to_B into the admittance matrix queue GB_FIFO, that is, write_FIFO[GB_FIFO,from_to_B], then execute the operation of writing the column label value of the target node to_bus into the admittance matrix queue GB_FIFO, that is, write_FIFO[GB_FIFO,to_bus], finally, clear the write valid signal W_GB_FIFO of the admittance matrix queue GB_FIFO, that is, W_GB_FIFO←0. After the mutual admittance calculation and writing of the current node from_bus to the target node to_bus is completed, the row data number counter branch_row_num of the current node from_bus is increased by 1, that is, branch_row_num←branch_row_num+1.

[0067] Accumulate the self-admittance values ​​of the lower triangular part of the admittance matrix related to the target node to_bus and store them in the diagonal self-admittance dig_GB register, that is, write the lower triangular part of the target node to_bus end. Process: First calculate the self-admittance of the target node to_bus, including the conductance part self_to_bus_G and the susceptance part self_to_bus_B. The self-admittances are the real and imaginary parts of the branch admittance plus half of the susceptance of the branch to the ground, that is, self_to_bus_G←real_admittance+susceptance / 2, self_to_bus_B←imag_admittance+susceptance / 2. Then, the conductance value and susceptance value in the self-admittance register dig_GB of the target node to_bus are updated respectively. The self-admittance register dig_GB of the target node to_bus is 64 bits, the upper 32 bits [63:32] store the conductance value, and the lower 32 bits [31:0] store the susceptance value. Specifically, the conductance value self_to_bus_G of the accumulated target node to_bus is updated to the upper bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][63:32]←dig_GB[to_bus][63:32]+ self_to_bus_G, and the susceptance value self_to_bus_B of the accumulated target node to_bus is updated to the lower bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][31:0]←dig_GB[to_bus][31:0]+ self_to_bus_B.

[0068] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus and update the self-admittance register dig_GB[from_bus] of the current node from_bus, including the conductance value and the susceptance value. Specifically, update the accumulated conductance value self_to_bus_G of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, that is, dig_GB[from_bus][63:32]←dig_GB[from_bus][63:32]+ self_to_bus_G, and update the accumulated susceptance value self_to_bus_B of the current node from_bus to the low bit of the self-admittance register of the current node from_bus, that is, dig_GB[from_bus][31:0]←dig_GB[from_bus][31:0]+ self_to_bus_B.

[0069] If the transformer ratio register tranf_ratio≠1, it means that the branch contains a non-standard ratio transformer. The value of tranf_ratio is the ratio value. First calculate the transformer branch The equivalent circuit is then calculated, and the mutual admittance and self-admittance accumulation values ​​of the current node from_bus to the target node to_bus are calculated. This process consists of two parts: the mutual admittance part and the self-admittance accumulation part.

[0070] Calculate the mutual admittance of the current branch from_bus to the target node to_bus:

[0071] Calculate the sum of squares of the ratio, i.e. k_square← , calculate the impedance sum-squared term , calculate the real part of the branch admittance real_admittance and the imaginary part of the branch admittance imag_admittance when the transformer is not included, that is, , ; Then calculate the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part, including the conductance data from_to_G and the susceptance data from_to_B, that is, from_to_G←-real_admittance / tranf_ratio, from_to_B←-imag_admittance / tranf_ratio. Then, the write valid signal W_GB_FIFO of the write admittance matrix queue GB_FIFO is pulled high, that is, W_GB_FIFO←1, and the operation of writing the conductance data from_to_G into the admittance matrix queue GB_FIFO is executed, that is, write_FIFO[GB_FIFO,from_to_G]. Then, the operation of writing the admittance data from_to_B into the admittance matrix queue GB_FIFO is executed, that is, write_FIFO[GB_FIFO,from_to_B]. Then, the operation of writing the column label value of the target node to_bus into the admittance matrix queue GB_FIFO is executed, that is, write_FIFO[GB_FIFO,to_bus]. Finally, the write valid signal W_GB_FIFO of the write admittance matrix queue GB_FIFO is cleared, that is, W_GB_FIFO←0. After the branch mutual admittance calculation and writing of the current node from_bus to the target node to_bus is completed, the data number counter branch_row_num of the current node from_bus row is increased by 1, that is, branch_row_num←branch_row_num+1.

[0072] The self-admittance values ​​of the lower triangular part of the admittance matrix associated with the target node to_bus are accumulated and stored in the diagonal self-admittance dig_GB register.

[0073] According to the transformer This equivalent circuit calculates the self-admittance values ​​on both sides of the transformer, including calculations for the current node from_bus and the target node to_bus. Specifically, the self-admittance of the current node from_bus, including the transformer conversion, is calculated, including the conductance component from_transf_G and the susceptance component from_transf_B, that is, from_transf_G ← real_admittance, from_transf_B ← imag_admittance. The self-admittance of the target node to_bus, including the transformer conversion, is calculated, including the conductance component to_transf_G and the susceptance component to_transf_B, that is, to_transf_G ← real_admittance / k_square, to_transf_B ← imag_admittance / k_square.

[0074] Next, calculate the self-admittance value of the relevant target node to_bus after the transformer ratio conversion, and add the self-admittance value to dig_GB[to_bus] and write it into the lower triangle of the target node to_bus. The process is as follows: first calculate the self-admittance of the target node to_bus, including the conductance part self_to_bus_G and the susceptance part self_to_bus_B, where the self-admittance is the susceptance value to_transf_B of the target node to_bus after the transformer ratio conversion plus half of the susceptance of the branch to the ground, that is, self _to_bus_G←to_transf_B+susceptance / 2, self_to_bus_B←to_transf_B+susceptance / 2; then update the conductance and susceptance values ​​in the self-admittance register dig_GB of the target node to_bus respectively, specifically: update and accumulate the conductance value self_to_bus_G of the current target node to_bus to the high bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][63:32]←dig_GB[to_bus][63:32]+ self_to_bus_G, update and accumulate the susceptance value self_to_bus_B of the current node to_bus to the low bit of the self-admittance register of the target node to_bus, that is, dig_GB[to_bus][31:0]←dig_GB[to_bus][31:0]+ self_to_bus_B.

[0075] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus and update the conductance and susceptance parts of the self-admittance register dig_GB[from_bus] of the current node from_bus. Specifically, update the accumulated conductance value self_to_bus_G of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, that is, dig_GB[from_bus][63:32]←dig_GB[from_bus][63:32]+ self_to_bus_G, and update the accumulated susceptance value self_to_bus_B of the current node from_bus to the low bit of the self-admittance register of the current node from_bus, that is, dig_GB[from_bus][31:0]←dig_GB[from_bus][31:0]+ self_to_bus_B.

[0076] In this embodiment, the upper triangular admittance matrix is ​​stored in the SDRAM in a row-compressed format. The read and write burst length register of the SDRAM is set to RW_burst_length[7:0]. When the read SDRAM signal read_sdram is valid, the SDRAM delays delay_out clock cycles before retrieving the first data. During each data read and write, the address cannot cross the current partition.

[0077] The GB admittance matrix is ​​stored in row compression format. The GB_row_ptr[31:0] internal register represents the row address of the first non-zero element in each row of the GB matrix, GB_col[31:0] represents the column number corresponding to the non-zero element in each row, and GB_data[63:0] represents the admittance value of the non-zero element in each row. ,in, 64 bits in total, high 32 bits Indicates conductivity G, lower 32 bits Indicates susceptance B. In SDRAM, the admittance matrix data GB_data and column label value GB_col are packed and linearly stored in the GB_data_col[95:0] register in sequence, that is, GB_data_col[95:0]={GB_data[63:0],GB_col[31:0]}, and each data unit includes 12 bytes. GB_data_col[95:64] represents the conductance value , GB_data_col[63:32] represents the susceptance value , GB_data_col[31:0] indicates Column index number of the admittance value.

[0078] Figure 5 This diagram shows the timing of reading GB admittance values ​​from an SDRAM. WDATA_GB[31:0] represents the 32-bit data bus of the SDRAM, and head_addr represents the first address of the GB admittance matrix in the SDRAM. The SDRAM read / write burst length register, RW_burst_length, is assigned a value (RW_burst_length←4), allowing each transfer to retrieve 4 bytes of data. After three transfers, a 12-byte unit of data from the GB admittance matrix is ​​retrieved. The assembled GB_data_col is then sent to the data bus, WDATA_GB[31:0], and simultaneously stored in the GB_FIFO for data caching.

[0079] First, calculate the number of elements in each row of the GB admittance matrix. The current_GB_ptr pointer register points to the current address in GB_row_ptr. When the row counter k searches the entire GB_row_ptr register address from 0 to the matrix dimension n, starting from the current row k, get the data in the adjacent cells in GB_row_ptr in sequence, get the row address of the next row next_row_addr←GB_row_ptr[current_GB_ptr+1], get the address of the current row current_row_addr←GB_row_ptr[current_GB_ptr], and calculate the number of non-zero elements in the current row current_row_num←(next_row_addr-current_row_addr) / 12.

[0080] Let num_GB be the number of data points retrieved from the GB matrix, and num_trans be the number of data transfers from the SDRAM. When the SDRAM data output valid signal SDRAM_data_valid = 1, the num_trans counter increments by 1, num_trans ← num_trans + 1. When num_trans = 3, the num_GB counter increments by 1, num_GB ← num_GB + 1. When the SDRAM read signal RD_SDRAM is valid, data is sequentially read from the SDRAM and stored in the GB_FIFO queue. Repeat these steps repeatedly. When the value of the num_GB counter, the number of data points retrieved from the GB matrix, equals the number of non-zero data points in the current row of the admittance matrix, current_row_num, all non-zero elements in the row pointed to by current_GB_ptr have been read.

[0081] For the current row in the GB matrix, there are a total of current_row_num non-zero elements, and the byte number register current_row_byte←current_row_num×12. The following compares the value of the byte number register current_row_byte and the maximum burst length max_burst_length, setting different SDRAM read and write control processes, divided into two cases, as follows:

[0082] First, the cumulative calculation register acc_GB_num of the row data taken out of the GB matrix is ​​recorded, acc_GB_num←current_row_num, and the remaining data counter of the current row of the GB matrix remaining_elements_GB←0.

[0083] If the value of the byte count register current_row_byte is less than or equal to the maximum burst length max_burst_length, the following write process is executed:

[0084] Set the SDRAM read / write burst length RW_burst_length to the value of the byte count register current_row_byte, that is, RW_burst_length←current_row_byte. A total of current_row_byte + SDRAM output data delay delay_out clock cycles are required to retrieve the current row from the GB matrix and store it in FIGO. When the maximum burst length is not reached after retrieving a row of data from the GB matrix, continue to retrieve the data from the next row, determine the accumulated value acc_GB_num of the non-zero elements in the next row, set the GB_row_num_FIFO queue to store the number of non-zero elements in each row of the GB matrix, and execute the write operation to write the number of non-zero elements in the current row of the GB matrix, current_row_num, into the GB_row_num_FIFO queue, that is, write_FIFO[GB_row_num_FIFO, current_row_num]. At this time, the data read from GB_row_num_FIFO represents the number of non-zero elements in the current row.

[0085] Set the GB matrix current row address pointer register current_GB_ptr to current_GB_ptr+1. Calculate the number of nonzero elements in the next row of the GB matrix and obtain the row address of the next row, i.e., next_row_addr ← GB_row_ptr[current_GB_ptr+1]. Get the address of the current row, i.e., current_row_addr ← GB_row_ptr[current_GB_ptr]. Calculate the number of nonzero elements in the current row, i.e., current_row_num ← (next_row_addr - current_row_addr) / 12. Update the value of the row accumulation counter acc_GB_num pointed to by the current row address pointer register current_GB_ptr, i.e., acc_GB_num ← acc_GB_num + current_row_num.

[0086] Next, the number of bytes that need to be transmitted in the current accumulated GB matrix, current_row_byte, is updated, that is, current_row_byte←current_row_byte+current_row_num×12.

[0087] Finally, repeat the above steps and determine the relationship between the number of bytes to be transmitted in the current accumulated GB matrix, current_row_byte, and the maximum burst length, max_burst_length. When the number of bytes to be transmitted in the current accumulated GB matrix, current_row_byte, exceeds the maximum burst length, max_burst_length, the SDRAM read / write burst length, RW_burst_length, is set to the maximum burst length, max_burst_length, i.e., RW_burst_length ← max_burst_length. The non-zero elements in the row pointed to by the current row address pointer register, current_GB_ptr, of the admittance matrix are retrieved. Then, the remaining unretrieved elements register, remaining_elements_GB, is updated, i.e., remaining_elements_GB ← current_row_byte - max_burst_length. Determine the relationship between the value in the remaining untaken elements number register and the maximum burst length max_burst_length. If the value in the remaining untaken elements number register is greater than the maximum burst length max_burst_length, directly write the data read from the SDRAM into the admittance matrix queue GB_FIFO. At the same time, update the remaining untaken elements number register, that is, remaining_elements_GB←remaining_elements_GB-max_burst_length.

[0088] Repeat the above data read operation until the value in the register for the number of remaining unread elements is less than the maximum burst length max_burst_length. Then, the number of non-zero elements in the next row is retrieved from the GB_row_num_FIFO queue, and the current row address pointer register of the GB matrix is ​​updated (i.e., current_GB_ptr←current_GB_ptr+1). The row address of the next row is obtained (i.e., next_row_addr←GB_row_ptr[current_GB_ptr+1]). The address of the current row is obtained (i.e., current_row_addr←GB_row_ptr[current_GB_ptr]). The number of non-zero elements in the current row is calculated (current_row_num←(next_row_addr-current_row_addr) / 12). The row cumulative non-zero element counter acc_GB_num is updated (i.e., acc_GB_num←acc_GB_num+current_row_num). The number of elements to be taken in the next row, current_row_num, is accumulated into the byte number register, current_row_byte, that is, current_row_byte←remaining_elements_GB+current_row_num×12.

[0089] If the value in the byte count register is greater than the maximum burst length, the value in the remaining untaken element count register is directly updated to the sum of the preset multiples of the non-zero elements in the current row of the admittance matrix and the maximum burst length, that is, remaining_elements_GB←current_row_byte+max_burst_length, and then the above write process is executed.

[0090] It is not difficult to find that the present invention, based on the characteristics of power grid data flow, realizes the calculation of the lower triangular data of the admittance matrix by utilizing the symmetry of the line impedance data without storing the original line data, completes the dynamic streaming calculation of the admittance matrix value, and the parallel pipeline calculation of the current, thereby improving the computational efficiency of the current calculation mode, reducing resource consumption, and accelerating the current calculation time.

[0091] The second embodiment of the present invention relates to a power flow parallel computing device, such as Figure 6 Shown, including:

[0092] The data receiving module is used to receive binary data sequences from the power grid, parse the branch data format, shift the valid byte data obtained from the parsing, and assemble them into branch data. Specifically, it is responsible for receiving binary data sequences from the power grid read in from the serial port, parsing the branch data format, shifting the valid byte data received from the serial port in units of four bytes according to the serial port baud rate and clock frequency, assembling them into 32-bit raw data and saving them to the data[31:0] register. When the data valid signal data_flag=1 is valid, the data type identifier counter data_type is used to identify the value. When data_type=1, 2, 3, 4, 5, 6, the data in data is assigned to the six registers frombus, tobus, impedance_R, impedance_X, susceptance_B, and tranf_ratio respectively, and the data is sent to the admittance matrix streaming calculation module in synchronization with the clock beat.

[0093] The admittance matrix streaming calculation module in the first embodiment is responsible for receiving the 32-bit branch data assembled by the data receiving module, determining whether the branch contains a transformer calculation branch equivalent circuit based on the value of the non-standard transformer ratio tranf_ratio, and completing the from_bus to to_bus transadmittance calculation within the interval between two branch data inputs from the data receiving module, and synchronously writing the data into the GB_FIFO queue. Furthermore, when calculating each row of branch data, the upper triangular transadmittance value of from_bus to to_bus is mapped to the contribution value of the to_bus node in the lower triangular admittance matrix. The transadmittance value of the target node of to_bus is accumulated into the self-admittance matrix register dig_GB[to_bug] corresponding to the to_bus index. When all rows of from_bus = i are read, the self-admittance of node i is also calculated and stored in dig_GB[i]. When all branch rows are read, the self-admittance register dig_GB of each node is also accumulated and updated, completing the calculation. This allows the admittance matrix calculation to be completed without the need for intermediate data caching.

[0094] The sparse compressed data access module includes three parts, namely the admittance matrix access module in the first embodiment, the Jacobian matrix jacoby_FIFO queue read and write control module, and the SDRAM read and write control module that maintains the Jacobian matrix. The admittance matrix access module is responsible for receiving the upper triangular mutual admittance value in the admittance matrix streaming calculation module. When the SDRAM write burst length is reached, it is written into the SDRAM memory by the SDRAM control module. The Jacobian matrix jacoby_FIFO queue read and write control module is responsible for caching the admittance matrix value read from the SDRAM when calculating the Jacobian matrix; at the same time, it caches the partial derivatives of each node power and voltage with respect to the node voltage when calculating the Jacobian matrix. When the SDRAM write burst length is reached, it is written into the SDRAM memory by the SDRAM control module. The SDRAM read and write control module that maintains the Jacobian matrix is ​​responsible for controlling the access operations of the row-compressed format admittance matrix and the Jacobian matrix.

[0095] The power imbalance dynamic increment calculation module is used to calculate the partial derivatives of the power and voltage of the i-th node with respect to the j-th node with respect to the node voltage based on the node type. Specifically, the admittance matrix data in the SDRAM is read row by row through the GB_FIFO control module and the SDRAM control module and cached in the SDRAM. The read and write burst length burst_length of the SDRAM is determined based on the number of non-zero elements in each row of data in the admittance matrix. The PQ node and PU node types are judged, and the dynamic incremental calculation of the power imbalance of each node is calculated separately. Because the upper triangular form of the admittance matrix is ​​stored in SDRAM, the power accumulation of node i to the lower triangular matrix of node j (here, j<=i) is missing when calculating the power imbalance of node i. Therefore, when calculating the dynamic increment of the power imbalance, this embodiment reads the admittance matrix data in the i-th row and simultaneously accumulates the power contribution value to node j to the register labeled j corresponding to the power imbalance. This eliminates the need to repeatedly address the admittance values ​​of the upper triangular portion of the admittance matrix after each row of admittance matrix values ​​is read. Once the admittance data in the i-th row is read, the power imbalance of the i-th node can be synchronously calculated and updated.

[0096] The Jacobian matrix dynamic incremental calculation module is used to calculate the partial derivatives of the power and voltage of the i-th node with respect to the j-th node voltage based on the node type. Specifically, the admittance matrix data in the SDRAM is read row by row and cached in the SDRAM through the GB_FIFO control module and the SDRAM control module. The read and write burst length burst_length of the SDRAM is determined based on the number of non-zero elements in each row of data in the admittance matrix. The PQ node and PU node types are judged, and the partial derivatives of the power and voltage of the i-th node with respect to the j-th node voltage are calculated. Since the admittance matrix read from the SDRAM is in upper triangular form, in order to synchronously calculate a row of elements in the Jacobian matrix after each row of admittance data is read, the dynamic incremental calculation process of the Jacobian matrix in this embodiment is as follows: when reading the i-th row of admittance matrix data, the upper triangular partial derivative part above the diagonal of the Jacobian matrix is ​​preferentially calculated, that is, node i to j (here, j>i), and the partial derivative calculation results are synchronously written into the active power partial derivative register derivative_P_FIFO, the column label register of the active power partial derivative derivative_P_col_FIFO, the reactive power and voltage partial derivative register derivative_QU_FIFO, and the column label register of the reactive power and voltage partial derivative derivative derivative_QU_col_FIFO. At the same time, the power contribution value of the upper triangular part of node i to j is mapped to the lower triangular part of the Jacobian matrix, and the value is accumulated in the Jacobian matrix power contribution value registers acc_M and acc_N. Subsequently, the k-th row (k>i) is read without re-addressing the lower triangular part of the admittance matrix, that is, the data in the 1st to k-1 columns. The data in the power contribution value registers acc_M and acc_N corresponding to the label k is directly read, and the power of the upper triangular part of the k-th row is continued to be accumulated in the acc_M and acc_N registers. When the k-th row data is read, the value in the power cumulative contribution value registers acc_M and acc_N is the accumulated power value of node k to all nodes in that row.

[0097] The hybrid compression storage module for the Jacobian matrix stores the row elements of the Jacobian matrix in a row-compressed format and establishes a linked list of column data elements to enable read and write operations on the rows and columns of the Jacobian matrix. To facilitate the calculation of sparse power flow equations, the matrix LU decomposition facilitates row and column data reading, saving logical resources and timing waste in data addressing. The Jacobian column data linked list facilitates data search during subsequent Jacobian matrix partitioning, optimal node sorting, and node parallel elimination tree calculations, allowing for quick location of a node's parent and child nodes. When the i-th node calculates the elements of the Jacobian matrix for the j-th node, a local 2×2 partial derivative submatrix is ​​generated. To maintain the structural integrity of the Jacobian matrix during writing to SDRAM, this local 2×2 submatrix is ​​first written row-wise into the active power partial derivative register derivative_P_FIFO, the active power partial derivative column register derivative_P_col_FIFO, the reactive power and voltage partial derivative register derivative_QU_FIFO, and the reactive power and voltage partial derivative column register derivative_QU_col_FIFO. A FIFO read / write control module is designed to rearrange the active power partial derivative data, along with the reactive power and voltage partial derivative data, into a single 12-byte data set. This data is then written to the SDRAM in the order of active power partial derivatives first, followed by reactive power and voltage partial derivatives. While the data is being written to the SDRAM, the next row of Jacobian matrix data is synchronously read from the FIFO and pipelined.

[0098] The Jacobian matrix block partitioning calculation module is used to perform block partitioning calculations on the Jacobian matrix. Due to the special characteristics of the Jacobian matrix being an upper triangular matrix and asymmetric, in order to reduce the number of non-zero elements generated during the LU decomposition of the Jacobian matrix and reduce the utilization of storage resources, this embodiment uses a multi-objective genetic annealing algorithm to partition the Jacobian matrix. This method constructs a graph data structure of the Jacobian matrix. This method can calculate the optimal block structure of the Jacobian matrix. Under the condition of satisfying the load balancing of each parallel matrix decomposition module, the minimum number of non-zero elements is generated during the sub-matrix decomposition process, while minimizing the data dependency between each sub-matrix, thereby improving the computational efficiency of the parallel decomposition of the sub-matrix.

[0099] The Jacobian matrix node sorting module is used to sort the nodes of the Jacobian submatrix structure calculated by the Jacobian matrix block division calculation module. During the power flow calculation process, the Jacobian matrix of the node is calculated by the admittance matrix. Sum power voltage squared imbalance , the power flow imbalance equation is constructed , the Jacobian matrix The optimal node sorting can improve the computational efficiency of the Jacobian matrix decomposition of the power flow equation. At the same time, it improves the parallelism of the Jacobian matrix decomposition, thereby speeding up the power flow calculation time.

[0100] The tree-topology calculation module for matrix nodes dynamically computes linked lists of column data elements to generate a Jacobi parallel hierarchical elimination tree. This module utilizes a hybrid storage structure of Jacobi matrix column linked lists and row-compressed sparse matrices, enabling fast transposition calculation of sparse Jacobi matrix elements. This improves the Jacobi matrix decomposition of sparse power flow equations by simultaneously retrieving all elements of a particular row or column in the Jacobi matrix, reducing column data addressing time and accelerating solution efficiency. Furthermore, this module utilizes a child-parent hybrid storage structure of the Jacobi matrix elimination tree structure, including a parent node number for each node and a linked list for each child. This allows for efficient computation and data storage of the node hierarchical ordering sequence during the elimination tree computation. This module also provides the parallel solution module for the multi-front power flow sparse equation system with a number for each node's computational resource allocation and storage of submatrix decomposition results. Furthermore, linked list storage is allocated for the contribution submatrix of a lower-level submatrix to an upper-level node, and the contribution of the lower-level node's contribution submatrix is ​​superimposed on the corresponding upper-level node number for storage.

[0101] The matrix subnode resource allocation module is used to allocate computing resources to each node in the Jacobi parallel hierarchical elimination tree, improving the computational efficiency of Jacobi matrix decomposition tasks while ensuring load balancing across nodes and computational branches, minimizing the overall power flow equation computation time. The resource allocation process consists of two phases: forward search and reverse search. In the forward search phase, resource allocation estimates are generated for all nodes in the Jacobi hierarchical elimination tree. In the reverse search phase, resource numbers are allocated to the node sub-matrix computation modules (SMCs) and resource quantities are corrected.

[0102] The Jacobian Matrix Parallel Elimination Tree Calculation Module optimizes the node ordering of the Jacobian matrix. This module constructs a hierarchical elimination tree structure, where all subtree branches on the same branch under the same root node have no data dependencies. Each branch can be calculated in parallel, improving the parallelism of the matrix decomposition. This also minimizes the amount of non-zero elements in the Jacobian matrix decomposition process during power flow equation calculations, reducing storage resource consumption and speeding up power flow calculations.

[0103] The node merging assembly tree calculation module is used to merge nodes with the same non-zero element structure in the Jacobi parallel hierarchical elimination tree into supernodes and calculate the parallel hierarchical assembly tree of the Jacobi matrix based on the supernodes. This module performs data dimensionality reduction on the original Jacobi matrix and calculates a parallel hierarchical assembly tree of the Jacobi matrix. Each node in the assembly tree is a collection of nodes in the original Jacobi matrix. The assembly tree can more efficiently perform parallel hierarchical partitioning of the Jacobi matrix, synchronously decomposing sub-matrices of non-interdependent sub-branches in parallel, and accelerating the efficiency of matrix decomposition of sparse equation systems in power flow calculations.

[0104] The multi-frontal power flow sparse equations matrix hierarchical iterative parallel computation module performs sub-matrix decomposition calculations from the bottom to the top of the parallel hierarchical assembly tree of the Jacobian matrix. It then allocates an optimal amount of computing resources to each node to perform parallel computations on the subtree consisting of all descendants of the root node in the tree. This module assigns all descendants of the same node to the same sub-matrix computation module (sub_matrix_compute, SMC). After the sub-matrix decomposition calculations are completed, iterative matrix decomposition calculations are performed layer by layer, starting from the end node and moving upwards. The contribution results are gradually accumulated to the upper root node, ultimately completing the decomposition of the entire Jacobian matrix, accelerating the computational speed of the matrix decomposition of the power sparse equations for power flow calculations.

[0105] A third embodiment of the present invention relates to a method for processing an admittance matrix, comprising the following steps:

[0106] Receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval of receiving two branch data, and synchronously write the calculation results to the admittance matrix queue;

[0107] The upper triangular transadmittance values ​​in the admittance matrix queue are received, and when a memory write burst length is reached, the upper triangular transadmittance values ​​are written into the memory.

[0108] When the mutual admittance calculation of the current node from_bus to the target node to_bus is completed within the interval of receiving two branch data, the mutual admittance value of the current node from_bus to the target node to_bus in the upper triangular form is mapped to the contribution value of the target node to_bus in the lower triangular form of the admittance matrix, and the mutual admittance value of the target node to_bus is accumulated into the self-admittance matrix register corresponding to the label of the target node to_bus. When all rows of the current node from_bus are read, the self-admittance of the node is synchronously calculated and completed. When all branch data are read, the self-admittance registers of each node are synchronously accumulated and updated and calculated.

[0109] When the current branch does not contain a transformer, the calculation process is as follows:

[0110] Calculate the square sum of impedances, the real part of branch admittance, the imaginary part of branch admittance, and the mutual admittance of the current node from_bus to the target node to_bus; pull high the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue, and write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue; write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the mutual admittance and write of the current node from_bus to the target node to_bus, increment the row data count counter of the current node from_bus by 1;

[0111] Calculate the self-admittance of the target node to_bus, where the self-admittance is the real and imaginary parts of the branch admittance plus half of the susceptance of the branch to the ground at both ends; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the target node to_bus to the low bit of the self-admittance register of the target node to_bus;

[0112] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, and update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

[0113] When the current branch contains a transformer, the calculation process is as follows:

[0114] Calculate the sum of squares of the transformation ratio, the sum of squares of the impedance, the real part of the branch admittance and the imaginary part of the branch admittance when the transformer is not included, and the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part; pull up the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, and write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the calculation and writing of the mutual admittance including the transformer conversion part of the current node from_bus to the target node to_bus, add 1 to the row data number counter of the current node from_bus;

[0115] Calculate the self-admittance of the current node from_bus end including the transformer conversion, and the self-admittance of the target node to_bus end including the transformer conversion;

[0116] Calculate the self-admittance of the target node to_bus, which is the self-admittance of the target node to_bus including the transformer conversion plus half of the susceptance of the branch to ground; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the current node to_bus to the low bit of the self-admittance register of the target node to_bus;

[0117] Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus; update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

[0118] When writing the upper triangular mutual admittance value into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​less than or equal to the maximum burst length, the following writing process is performed:

[0119] Setting a preset multiple of the non-zero elements in the current row of the admittance matrix as the read / write burst length of the memory; when the read / write burst length of the memory does not reach the read / write burst length of the memory after the data of one row of the admittance matrix is ​​retrieved, continuing to retrieve the data of the next row, determining the accumulated value of the non-zero elements of the next row, setting a GB_row_num_FIFO queue to store the number of non-zero elements in each row of the admittance matrix, and writing the number of non-zero elements in the current row of the admittance matrix into the GB_row_num_FIFO queue;

[0120] Calculate the number of non-zero elements of the next row of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, calculate the number of non-zero elements of the current row; update the value of the row accumulation counter pointed to by the address pointer register of the current row of the admittance matrix;

[0121] Update the number of bytes that need to be transmitted in the current accumulated admittance matrix;

[0122] Repeat the above steps. When the number of bytes to be transmitted in the currently accumulated admittance matrix is ​​greater than the maximum burst length, set the read / write burst length of the memory to the maximum burst length, extract the non-zero elements in the row pointed to by the current row address pointer register of the admittance matrix, and update the register for the number of remaining untaken elements. If the value in the register for the number of remaining untaken elements is greater than the maximum burst length, directly write the data read from the memory into the admittance matrix queue and update the value of the register for the number of remaining untaken elements.

[0123] Repeat the above data reading operation until the value in the register for the number of remaining unread elements is less than the maximum burst length; take out the number of non-zero elements in the next row from the GB_row_num_FIFO queue, update the current row address pointer register of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, calculate the number of non-zero elements in the current row; update the value of the row cumulative non-zero element counter; accumulate the number of elements to be read in the next row to the byte number register.

[0124] When writing the mutual admittance value in the upper triangular form into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​greater than the maximum burst length, the value in the register of the number of remaining untaken elements is updated to the sum of the preset multiple of the non-zero elements in the current row of the admittance matrix and the maximum burst length, and the writing process is executed.

[0125] A fourth embodiment of the present invention relates to a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements the steps of the admittance matrix processing method of the third embodiment.

[0126] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage) containing computer-usable program code.

[0127] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0128] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction method, which is implemented in the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0129] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0130] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An admittance matrix processing module, characterized in that: include: The admittance matrix streaming calculation module is used to receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and use the symmetry of the line impedance data to complete the mutual admittance calculation of the current node from_bus to the target node to_bus within the interval between receiving two branch data, and synchronously write the calculation results to the admittance matrix queue; The admittance matrix access module is used to receive the upper triangular transadmittance values ​​in the admittance matrix queue and write the upper triangular transadmittance values ​​into the memory when the memory write burst length is reached.

2. The admittance matrix processing module according to claim 1, characterized in that: When performing mutual admittance calculation, the admittance matrix streaming calculation module maps the mutual admittance value of the current node from_bus to the target node to_bus in the upper triangular form to the contribution value to the target node to_bus in the lower triangular form of the admittance matrix, and accumulates the mutual admittance value of the target node to_bus into the self-admittance matrix register corresponding to the label of the target node to_bus. When all rows of the current node from_bus are read, the self-admittance of the node is synchronously calculated. When all branch data are read, the self-admittance registers of each node are synchronously accumulated and updated.

3. The admittance matrix processing module according to claim 2, characterized in that: When the current branch does not contain a transformer, the calculation process of the admittance matrix flow calculation module is as follows: Calculate the square sum of impedances, the real part of branch admittance, the imaginary part of branch admittance, and the mutual admittance of the current node from_bus to the target node to_bus; pull high the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue, and write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus into the admittance matrix queue; write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the mutual admittance and write of the current node from_bus to the target node to_bus, increment the row data count counter of the current node from_bus by 1; Calculate the self-admittance of the target node to_bus, where the self-admittance is the real and imaginary parts of the branch admittance plus half of the susceptance of the branch to the ground at both ends; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the target node to_bus to the low bit of the self-admittance register of the target node to_bus; Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus, and update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

4. The admittance matrix processing module according to claim 2, characterized in that: When the current branch contains a transformer, the calculation process of the admittance matrix flow calculation module is as follows: Calculate the sum of squares of the transformation ratio, the sum of squares of the impedance, the real part of the branch admittance and the imaginary part of the branch admittance when the transformer is not included, and the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part; pull up the write valid signal of the write admittance matrix queue, write the conductance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, write the admittance data in the mutual admittance of the current node from_bus to the target node to_bus including the transformer conversion part into the admittance matrix queue, and write the column label value of the target node to_bus into the admittance matrix queue; clear the write valid signal of the write admittance matrix queue; after completing the calculation and writing of the mutual admittance including the transformer conversion part of the current node from_bus to the target node to_bus, add 1 to the row data number counter of the current node from_bus; Calculate the self-admittance of the current node from_bus end including the transformer conversion, and the self-admittance of the target node to_bus end including the transformer conversion; Calculate the self-admittance of the target node to_bus, which is the self-admittance of the target node to_bus including the transformer conversion plus half of the susceptance of the branch to ground; update the accumulated conductance value of the target node to_bus to the high bit of the self-admittance register of the target node to_bus, and update the accumulated susceptance value of the current node to_bus to the low bit of the self-admittance register of the target node to_bus; Calculate the accumulated sum of the self-admittance values ​​of the current node from_bus, and update the accumulated conductance value of the current node from_bus to the high bit of the self-admittance register of the current node from_bus; update the accumulated susceptance value of the current node from_bus to the low bit of the self-admittance register of the current node from_bus.

5. The admittance matrix processing module according to claim 1, characterized in that: When the admittance matrix access module writes the upper triangular mutual admittance value into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​less than or equal to the maximum burst length, the following writing process is performed: Setting a preset multiple of the non-zero elements in the current row of the admittance matrix as the read / write burst length of the memory; when the read / write burst length of the memory does not reach the read / write burst length of the memory after the data of one row of the admittance matrix is ​​retrieved, continuing to retrieve the data of the next row, determining the accumulated value of the non-zero elements of the next row, setting a GB_row_num_FIFO queue to store the number of non-zero elements in each row of the admittance matrix, and writing the number of non-zero elements in the current row of the admittance matrix into the GB_row_num_FIFO queue; Calculate the number of non-zero elements in the next row of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, and calculate the number of non-zero elements in the current row; Update the value of the row accumulation counter pointed to by the current row address pointer register of the admittance matrix; Update the number of bytes that need to be transmitted in the current accumulated admittance matrix; Repeat the above steps. When the number of bytes to be transmitted in the currently accumulated admittance matrix is ​​greater than the maximum burst length, set the read / write burst length of the memory to the maximum burst length, extract the non-zero elements in the row pointed to by the current row address pointer register of the admittance matrix, and update the register for the number of remaining untaken elements. If the value in the register for the number of remaining untaken elements is greater than the maximum burst length, directly write the data read from the memory into the admittance matrix queue and update the value of the register for the number of remaining untaken elements. Repeat the above data reading operation until the value in the register for the number of remaining unread elements is less than the maximum burst length; take the number of non-zero elements in the next row from the GB_row_num_FIFO queue, update the current row address pointer register of the admittance matrix, obtain the row address of the next row, obtain the address of the current row, and calculate the number of non-zero elements in the current row; Update the row cumulative non-zero element counter value; accumulate the number of elements to be taken in the next row into the byte number register.

6. The admittance matrix processing module according to claim 5, characterized in that: When the admittance matrix access module writes the mutual admittance value in upper triangular form into the memory, if the preset multiple of the non-zero elements in the current row of the admittance matrix is ​​greater than the maximum burst length, the value in the register for the number of remaining untaken elements is updated to the sum of the preset multiple of the non-zero elements in the current row of the admittance matrix and the maximum burst length, and the writing process is executed.

7. A method for processing an admittance matrix, characterized in that: The following steps are involved: Receive branch data, determine whether the branch contains a transformer based on the value of the non-standard transformer ratio, calculate the branch equivalent circuit, and complete the mutual admittance calculation of the current node from_bus to the target node to_bus using the symmetry of the line impedance data within the interval between receiving two branch data, and synchronously write the calculation results to the admittance matrix queue; The upper triangular transadmittance values ​​in the admittance matrix queue are received, and when a memory write burst length is reached, the upper triangular transadmittance values ​​are written into the memory.

8. A power flow parallel computing device, characterized in that: The method comprises the admittance matrix processing module as claimed in any one of claims 1 to 6.

9. The power flow parallel computing device according to claim 8, characterized in that: Also includes: The data receiving module is used to receive the binary data sequence of the power grid, parse the branch data format, shift the valid byte data obtained by parsing, and assemble them into branch data; A power imbalance dynamic increment calculation module is used to calculate the dynamic increment of the power imbalance of a node according to the node type; Jacobian matrix dynamic incremental calculation module, used to calculate the partial derivatives of the power and voltage of the i-th node with respect to the j-th node voltage according to the node type; A hybrid compression storage module for the Jacobian matrix, which is used to store the row elements of the Jacobian matrix in a row-compressed format and establish a column data element linked list to implement read and write operations on the rows and columns of the Jacobian matrix; Jacobian matrix block partitioning calculation module, used to divide the Jacobian matrix into blocks for calculation; A Jacobian matrix node sorting module is used to sort the nodes of the Jacobian submatrix structure calculated by the Jacobian matrix block partitioning calculation module; The tree topology calculation module of the matrix node is used to dynamically calculate the column data element linked list to obtain the Jacobi parallel hierarchical elimination tree; Matrix sub-node resource allocation module, used to allocate computing resources to each node in the Jacobi parallel hierarchical elimination tree; Jacobian matrix parallel elimination tree calculation module, used to optimize the node ordering of the Jacobian matrix; A node merging assembly tree calculation module is used to merge nodes with the same non-zero element structure in the Jacobi parallel hierarchical elimination tree into super nodes, and calculate the parallel hierarchical assembly tree of the Jacobi matrix based on the super nodes; The iterative parallel computing module is used to perform sub-matrix decomposition calculations from the lower layer to the upper layer of the parallel hierarchical assembly tree of the Jacobian matrix, and then allocate the optimal number of computing resources to each node to perform parallel calculations on the subtree composed of all descendant nodes of the root node in the tree.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the admittance matrix processing method according to claim 7 are implemented.

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