Data processing method, data processing device and chip

Abstract

The invention provides a data processing method, a data processing device and a chip. The data processing method comprises the following steps: receiving to-be-processed data and storing the to-be-processed data into a cache; obtaining to-be-processed column data according to the to-be-processed data in columns; performing first convolution calculation by using a first one-dimensional operator in the vertical direction and the column data to obtain an intermediate calculation result; a second one-dimensional operator in the horizontal direction and the intermediate calculation result are used for second convolution calculation, a convolution calculation result of a target two-dimensional operator and the column data is obtained, the target two-dimensional operator comprises N rows and N columns of data, the data in the target two-dimensional operator are symmetrical in the vertical direction and / or the horizontal direction, and the data in the target two-dimensional operator are symmetrical in the vertical direction and / or the horizontal direction. The first one-dimensional operator and the second one-dimensional operator are obtained from the target two-dimensional operator through operation splitting, and N is a natural number. The data processing method provided by the invention is beneficial to saving hardware overhead and reducing chip area and power consumption.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of integrated circuit design, and relates to a data processing method, and in particular to a data processing method, a data processor, and a chip. Background Art

[0002] As a common data processing method, convolution extracts local signal features by performing a weighted summation of input data with a kernel of a specific structure. Currently, convolution has been widely used in many fields, such as image processing, computer vision, natural language processing, and artificial intelligence. For example, in the field of computer vision, convolutional neural networks (CNNs) can extract image features such as edges, textures, and shapes layer by layer through multi-layer convolution operations, ultimately achieving efficient classification of image content. Summary of the Invention

[0003] The embodiments of the present disclosure provide a data processing method, a data processor, and a chip for reducing the number of multipliers and adders required for a convolution operation process, saving hardware resources, and reducing power consumption.

[0004] In a first aspect, an embodiment of the present disclosure provides a data processing method. The data processing method includes: receiving data to be processed and storing the data to be processed in a cache; obtaining column data to be processed by column according to the data to be processed; performing a first convolution calculation on the column data using a first one-dimensional operator in a vertical direction to obtain an intermediate calculation result; and performing a second convolution calculation on the intermediate calculation result using a second one-dimensional operator in a horizontal direction to obtain a convolution calculation result of a target two-dimensional operator and the column data, wherein the target two-dimensional operator includes N rows and N columns of data, the data in the target two-dimensional operator is symmetrical in the vertical direction and / or symmetrical in the horizontal direction, and the first one-dimensional operator and the second one-dimensional operator are obtained by splitting the target two-dimensional operator through operation, wherein N is a natural number.

[0005] In some implementations, obtaining the column data to be processed by column according to the data to be processed includes: selecting multiple column data each having N rows by column from the data to be processed through a sliding window, wherein using the first one-dimensional operator in the vertical direction to perform a first convolution calculation with the column data includes: using the first one-dimensional operator with N rows to perform the first convolution calculation with each of the column data in the vertical direction, respectively, wherein using the second one-dimensional operator in the horizontal direction to perform a second convolution calculation with the intermediate calculation result includes: using the second one-dimensional operator with N columns to perform the second convolution calculation with each of the intermediate calculation results in the horizontal direction, respectively.

[0006] In some implementations, the data processing method further includes: obtaining a convolution calculation result of the data to be processed and the target two-dimensional operator based on a convolution calculation result of the target two-dimensional operator and each of the column data.

[0007] In some implementations, receiving the data to be processed and storing the data to be processed in a cache includes: receiving the data to be processed row by row and storing the data to be processed in a row cache.

[0008] In some implementations, obtaining the column data to be processed by column according to the data to be processed includes: after receiving the Nth row of data, obtaining the column data to be processed according to N-1 rows of data to be processed stored in the row cache and the Nth row of data.

[0009] In some implementations, the data processing method further includes: storing the intermediate calculation result in a register.

[0010] In some implementations, the number of registers is N.

[0011] In some implementations, the first convolution calculation and the second convolution calculation are implemented by 2N multipliers and 2(N-1) adders.

[0012] In some implementations, the data in the target two-dimensional operator is also symmetric about a diagonal line.

[0013] In some implementations, performing a first convolution calculation on the column data using the first one-dimensional operator in the vertical direction includes: multiplying the sum of the i-th row data and the (Ni)-th row data in the column data by the operator of the corresponding row in the first one-dimensional operator, and adding the multiplication results, where i is a natural number not greater than N / 2, and performing a second convolution calculation on the intermediate calculation result using the second one-dimensional operator in the horizontal direction includes: multiplying the sum of the intermediate calculation result in the j-th register and the intermediate calculation result in the (Nj)-th register by the operator of the corresponding column in the second one-dimensional operator, and adding the multiplication results, where j is a natural number not greater than N / 2.

[0014] In some implementations, the first convolution calculation and the second convolution calculation are implemented by N+1 multipliers and 2(N-1) adders.

[0015] In some implementations, the data processing method further includes: splitting the target two-dimensional operator through a division operation to obtain the first one-dimensional operator and the second one-dimensional operator.

[0016] In a second aspect, an embodiment of the present disclosure provides a data processing device. The data processing device includes: a cache configured to receive and store data to be processed; a register configured to store intermediate calculation results; and a data processor configured to: obtain column data to be processed by column according to the data to be processed; perform a first convolution calculation on the column data using a first one-dimensional operator in the vertical direction to obtain the intermediate calculation result; and perform a second convolution calculation on the intermediate calculation result using a second one-dimensional operator in the horizontal direction to obtain a convolution calculation result of a target two-dimensional operator and the column data, wherein the target two-dimensional operator includes N rows and N columns of data, the data in the target two-dimensional operator is symmetrical in the vertical direction and / or symmetrical in the horizontal direction, and the first one-dimensional operator and the second one-dimensional operator are obtained by splitting the target two-dimensional operator through operation, wherein N is a natural number.

[0017] In a third aspect, embodiments of the present disclosure provide a chip. The chip includes: a memory configured to store data associated with a convolution operation; and at least one processor electrically coupled to the memory and configured to execute the data processing method according to any one of the first aspects of the embodiments of the present disclosure.

[0018] In the disclosed embodiments, the target two-dimensional operator is split into two one-dimensional operators to implement convolution operations. This reduces the number of multipliers and adders required for the convolution operation, saving chip area and reducing chip power consumption. When applied to image signal processors (ISPs), this allows for more flexible window selection during image processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a schematic diagram of an overall implementation environment of an embodiment of the present disclosure.

[0020] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown.

[0021] Figure 3 and Figure 4 Shown is a schematic diagram of the first convolution calculation in an embodiment of the present disclosure.

[0022] Figure 5 Shown is a schematic structural diagram of a chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present disclosure through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0024] It should be noted that the illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present disclosure. Therefore, the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0025] Taking image processing as an example, when the ISP performs image processing, there will be a large number of two-dimensional operator convolution operations. This process can be described as the corresponding multiplication of image data and two-dimensional operators (Kernel), and then the multiplication results are added. For example, for a 3×3 window, the above process is as follows:

[0026]

[0027] Here, d0 to d8 represent the data to be processed, and k0 to k8 represent the data in the two-dimensional operator. For the aforementioned 3×3 window, 9 multipliers and 8 adders are required to obtain the final result. If the window is increased to 5×5, the convolution calculation requires 25 multipliers and 24 adders. These multipliers and adders not only increase the chip area but also consume a lot of power. Furthermore, as the window size increases, such as 7×7, 9×9, or even larger, the number of multipliers and adders increases exponentially. Sometimes, to reduce the number of multipliers and adders, the window must be reduced, but this approach can compromise image processing performance.

[0028] To address at least the aforementioned issues, embodiments of the present disclosure provide a data processing method applicable to two-dimensional convolution operations in image processing, particularly symmetric operators such as Gaussian operators. By splitting the target two-dimensional operator into two one-dimensional operators, this method reduces the number of multipliers and adders, conserving hardware resources without sacrificing accuracy.

[0029] Figure 1 Shown is a schematic diagram of an overall implementation environment of an embodiment of the present disclosure. Figure 1 As shown, the data processing device includes caches in_col_0 to in_col_N-1, a data processor, and registers ver_0 to ver_N-1.

[0030] Figure 2 Shown is a flow chart of the data processing method provided by the embodiment of the present disclosure. Figure 2 As shown, the data processing method provided by the embodiment of the present disclosure includes the following steps S21 to S24.

[0031] S21, receiving data to be processed and storing the data to be processed in a cache. For example, the data to be processed may be image data, but the present disclosure is not limited thereto.

[0032] S22, obtaining column data to be processed according to the data to be processed.

[0033] S23, using the first one-dimensional operator in the vertical direction to perform a first convolution calculation on the column data to obtain an intermediate calculation result. In this embodiment, the intermediate calculation result can be stored in a register, but the present disclosure is not limited thereto.

[0034] S24: Perform a second convolution calculation using the second one-dimensional operator in the horizontal direction and the intermediate calculation result to obtain a convolution calculation result of the target two-dimensional operator and the column data. The target two-dimensional operator includes N rows and N columns of data, the data in the target two-dimensional operator is symmetric in the vertical direction and / or symmetric in the horizontal direction, and the first one-dimensional operator and the second one-dimensional operator are obtained by splitting the target two-dimensional operator through calculation, where N is a natural number.

[0035] For example, a target two-dimensional operator that is symmetrical above and below is The first and third rows of the operator are symmetric about the middle row (row 2). The target two-dimensional operator with bilateral symmetry is as follows: The first and fourth columns of this operator are symmetrical, and the second and third columns are symmetrical.

[0036] Exemplarily, the target two-dimensional operator may include a Gaussian operator, a Sobel operator, a Laplace operator, a Prewitt operator, a Scharr operator, and the like.

[0037] In some implementations, the data processing method provided by the embodiments of the present disclosure may further include: splitting the target two-dimensional operator into a first one-dimensional operator and a second one-dimensional operator through a division operation.

[0038] Taking a 5×5 Gaussian operator as an example, it can be split into a first-dimensional operator and a second-dimensional operator through division. In other words, the 5×5 Gaussian operator can be obtained by performing matrix operations on the first-dimensional operator and the second-dimensional operator. This process can be expressed as follows:

[0039]

[0040] If the convolution operation is performed using the two-dimensional operator on the left side of the above equation, 25 multipliers and 24 adders are required to obtain the final result. If the convolution operation is performed using the one-dimensional operator on the right side of the above equation, 2 × 5 = 10 multipliers and 2 × 4 = 8 adders are required, which reduces the number of multipliers by 60% and the number of adders by 67%.

[0041] In some implementations, obtaining column data to be processed by column based on the data to be processed includes: selecting, by column, a plurality of column data, each having N rows, from the data to be processed by column using a sliding window. Performing a first convolution calculation on the column data using a first one-dimensional operator in a vertical direction includes: performing a first convolution calculation on each column data in the vertical direction using the first one-dimensional operator having N rows. Furthermore, performing a second convolution calculation on the intermediate calculation results using a second one-dimensional operator in a horizontal direction includes: performing a second convolution calculation on each intermediate calculation result in the horizontal direction using the second one-dimensional operator having N columns.

[0042] In some implementations, the data processing method provided by the embodiments of the present disclosure may further include: obtaining a convolution calculation result of the data to be processed and the target two-dimensional operator based on the convolution calculation result of the target two-dimensional operator and each column of data.

[0043] In some implementations, receiving the data to be processed and storing the data to be processed in the cache includes: receiving the data to be processed row by row and storing the data to be processed in the row cache.

[0044] In some implementations, obtaining the column data to be processed by column according to the data to be processed includes: after receiving the Nth row of data, obtaining the column data to be processed according to the N-1th row of data to be processed stored in the row cache and the Nth row of data.

[0045] In some implementations, the data processing method provided by the embodiments of the present disclosure may further include: storing the intermediate calculation results in a register, where the number of registers is, for example, N.

[0046] Taking N=5 as an example, the data to be processed is input into the data processing device in real time by row. The data processing device uses a row cache to store the first 4 rows of data received. When the 5th row of data arrives, the data processor reads the data of the first column of the first 4 rows from the row cache, and uses these data and the first column data of the 5th row as the column data to be processed. Thereafter, the data of the second column of the first 4 rows is read, and these data and the second column data of the 5th row are used as the next column data to be processed, and so on. In the above process, only N-1=4 row caches can be used, and in the process of reading the row cache, it is not necessary to form a 5×5 window for calculation. In some other technical solutions, it is necessary to wait for the 5th row of data to arrive, and then read out the data of the first 4 rows, and together with the 5th row of data, form a 5×5 window for calculation. Compared with these technical solutions, the data processing method provided by the embodiment of the present disclosure does not require a 5×5 window to be formed for calculation, which is conducive to shortening the time required for calculation.

[0047] After the data processor performs a first convolution calculation on the column data to be processed using the first one-dimensional operator in the vertical direction, it obtains the corresponding intermediate calculation result and stores the intermediate calculation result in a register. After the intermediate calculation results are stored in all five registers, all the intermediate calculation results are read from these registers and a second convolution calculation is performed with the second one-dimensional operator in the horizontal direction. The calculation result obtained is the convolution calculation result of the target two-dimensional operator and the data to be processed. In the above process, only N = 5 registers are required. Compared with some other technical solutions that require N × N = 25 registers, the data processing method provided by the embodiment of the present disclosure requires fewer registers.

[0048] In some implementations, the first convolution calculation and the second convolution calculation are implemented by 2N multipliers and 2(N-1) adders.

[0049] For example, Figure 3The diagram shows a schematic diagram of the first convolution calculation when N=5. Specifically, 5 data in_data_00 to in_data_40 are read from the data to be processed as the column data to be processed. In_data_00 and k0 are multiplied by a multiplier, in_data_10 and k1 are multiplied by a multiplier, and the results of the multiplication of the two are added by an adder. In_data_20 and k2 are multiplied by a multiplier, in_data_30 and k3 are multiplied by a multiplier, and the results of the multiplication of the two are added by an adder. In_data_40 and k4 are multiplied by a multiplier. The calculation results of the above three are added by an adder to obtain an intermediate calculation result. It can be seen from this that the first convolution calculation can be implemented using 5 multipliers and 4 adders in the embodiment of the present disclosure. Similarly, the second convolution calculation can be implemented using 5 multipliers and 4 adders. Therefore, in the embodiment of the present disclosure, the convolution calculation result of the target two-dimensional operator and the column data can be obtained by using 2N = 10 multipliers and 2(N-1) = 8 adders. Compared with some other technical solutions that require 25 multipliers and 24 adders, the data processing method provided by the embodiment of the present disclosure can reduce the number of multipliers and adders required for convolution calculation.

[0050] In some implementations, the data in the target two-dimensional operator is also symmetric about the diagonal line, and the target two-dimensional operator is, for example, a Gaussian operator. In this case, the number of multipliers required for the calculation can be further reduced according to the associative law of multiplication.

[0051] In some implementations, when the data in the target two-dimensional operator is symmetric about the diagonal, performing a first convolution calculation using the first one-dimensional operator in the vertical direction and the column data includes: multiplying the sum of the i-th row data and the (Ni)-th row data in the column data by the operator of the corresponding row in the first one-dimensional operator, and adding the multiplication results, where i is a natural number not greater than N / 2. In addition, performing a second convolution calculation using the second one-dimensional operator in the horizontal direction and the intermediate calculation result includes: multiplying the sum of the intermediate calculation result in the j-th register and the intermediate calculation result in the (Nj)-th register by the operator of the corresponding column in the second one-dimensional operator, and adding the multiplication results, where j is a natural number not greater than N / 2.

[0052] Exemplarily, when the data in the target two-dimensional operator is still symmetric about the diagonal line, the first convolution calculation and the second convolution calculation can be implemented by N+1 multipliers and 2(N-1) adders.

[0053] For example, Figure 4It shows a schematic diagram of the first convolution calculation when N=5. Specifically, 5 data in_data_00 to in_data_40 are read from the data to be processed as the column data to be processed. After in_data_00 and in_data_40 are added by an adder, 1 multiplier can be saved by multiplying them with k0 through a multiplier. After adding in_data_10 and in_data_30 and multiplying them with k1, 1 multiplier can be saved. The center data in_data_30 is multiplied with k2, and then the three multiplication results are added through an adder to obtain the intermediate calculation result. It can be seen from this that the first convolution calculation can be implemented using 3 multipliers and 4 adders in the embodiment of the present disclosure. Similarly, the second convolution calculation can be implemented using 3 multipliers and 4 adders. Therefore, in the embodiment of the present disclosure, the convolution calculation result of the target two-dimensional operator and the column data can be obtained by N+1=6 multipliers and 2(N-1)=8 adders. Compared with some other technical solutions that require the use of 25 multipliers and 24 adders, when the data of the target two-dimensional operator is symmetric about the diagonal, the data processing method provided by the embodiment of the present disclosure can further reduce the number of multipliers and adders required for convolution calculation.

[0054] The protection scope of the data processing method provided by the embodiment of the present disclosure is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing, or replacing steps in the existing technology based on the principles of the present disclosure are included in the protection scope of the present disclosure.

[0055] An embodiment of the present disclosure also provides a data processing device, which can implement the data processing method described in the present disclosure. However, the implementation device of the data processing method described in the present disclosure includes but is not limited to the structure of the data processing device listed in this embodiment. All structural deformations and replacements of the existing technology made according to the principles of the present disclosure are included in the protection scope of the present disclosure.

[0056] The data processing device provided by the embodiment of the present disclosure includes a cache, a register and a data processor. The cache is configured to receive and store data to be processed. The register is configured to store intermediate calculation results. The data processor is configured to obtain column data to be processed by column according to the data to be processed. The data processor is configured to perform a first convolution calculation with the column data using a first one-dimensional operator in the vertical direction to obtain an intermediate calculation result. In addition, the data processor is configured to perform a second convolution calculation with the intermediate calculation result using a second one-dimensional operator in the horizontal direction to obtain a convolution calculation result of a target two-dimensional operator and the column data. The target two-dimensional operator includes N rows and N columns of data, the data in the target two-dimensional operator is symmetrical in the vertical direction and / or symmetrical in the horizontal direction, and the first one-dimensional operator and the second one-dimensional operator are obtained by splitting the target two-dimensional operator through operation, where N is a natural number.

[0057] The embodiment of the present disclosure also provides a chip. Figure 5 FIG. 5 is a schematic diagram showing the structure of a chip 500 according to an embodiment of the present disclosure. Figure 5 As shown, chip 500 includes a memory 510 and at least one processor 520. Memory 510 is configured to store data associated with convolution operations. Processor 520 is electrically coupled to memory 510 and configured to execute the data processing method provided in the embodiments of the present disclosure.

[0058] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0059] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0060] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0061] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0062] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (program) are loaded and executed on a computer, the process or function according to the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method.

[0063] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0064] In summary, the present invention splits the target two-dimensional operator into two one-dimensional operators to implement convolution operations. This reduces the number of multipliers and adders required for the convolution operation, saving chip area and reducing chip power consumption. When applied to image signal processors, this allows for greater freedom in window selection during image processing.

[0065] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein shall be covered by the claims of this disclosure.

Claims

1. A data processing method, characterized in that: include: Receiving data to be processed and storing the data to be processed in a cache; Obtaining column data to be processed according to the data to be processed; Performing a first convolution calculation on the column data using a first one-dimensional operator in a vertical direction to obtain an intermediate calculation result; as well as Perform a second convolution calculation using a second one-dimensional operator in the horizontal direction and the intermediate calculation result to obtain a convolution calculation result of the target two-dimensional operator and the column data. The target two-dimensional operator includes N rows and N columns of data, the data in the target two-dimensional operator is symmetrical in the vertical direction and / or in the horizontal direction, and the first one-dimensional operator and the second one-dimensional operator are obtained by splitting the target two-dimensional operator through operation, where N is a natural number.

2. The data processing method according to claim 1, wherein: Obtaining the column data to be processed by column according to the data to be processed includes: selecting multiple column data each having N rows by column from the data to be processed through a sliding window, wherein using the first one-dimensional operator in the vertical direction and the column data to perform a first convolution calculation includes: using the first one-dimensional operator with N rows to perform the first convolution calculation on each of the column data in the vertical direction, respectively; wherein using the second one-dimensional operator in the horizontal direction to perform a second convolution calculation on the intermediate calculation result includes: using the second one-dimensional operator with N columns to perform the second convolution calculation on each of the intermediate calculation results in the horizontal direction, respectively.

3. The data processing method according to claim 2, characterized in that: Also includes: The convolution calculation result of the data to be processed and the target two-dimensional operator is obtained based on the convolution calculation result of the target two-dimensional operator and each of the column data.

4. The data processing method according to claim 1, wherein: Receiving the data to be processed and storing the data to be processed in a cache includes: The data to be processed is received row by row and stored in a row buffer.

5. The data processing method according to claim 4, characterized in that: Acquiring column data to be processed by column according to the data to be processed includes: After receiving the Nth row of data, the column data to be processed is obtained according to the N-1th row of data to be processed stored in the row buffer and the Nth row of data.

6. The data processing method according to claim 1, wherein: Also includes: The intermediate calculation result is stored in a register.

7. The data processing method according to claim 6, characterized in that: The number of the registers is N.

8. The data processing method according to claim 1, wherein: The first convolution calculation and the second convolution calculation are implemented by 2N multipliers and 2(N-1) adders.

9. The data processing method according to claim 1, wherein: The data in the target two-dimensional operator is also symmetric about the diagonal line.

10. The data processing method according to claim 9, characterized in that: Performing a first convolution calculation on the column data using a first one-dimensional operator in a vertical direction includes: multiplying the sum of the i-th row data and the (Ni)-th row data in the column data by the operator of the corresponding row in the first one-dimensional operator, and adding the multiplication results, where i is a natural number not greater than N / 2, The second convolution calculation using the second one-dimensional operator in the horizontal direction and the intermediate calculation result includes: multiplying the sum of the intermediate calculation result in the j-th register and the intermediate calculation result in the (Nj)-th register with the operators of the corresponding columns in the second one-dimensional operator, and adding each multiplication result, where j is a natural number not greater than N / 2.

11. The data processing method according to claim 9, characterized in that: The first convolution calculation and the second convolution calculation are implemented by N+1 multipliers and 2(N-1) adders.

12. The data processing method according to claim 1, wherein: Also includes: The target two-dimensional operator is split into the first one-dimensional operator and the second one-dimensional operator through a division operation.

13. A data processing device, characterized in that: include: a cache, configured to receive and store data to be processed; registers, configured to store intermediate computation results; as well as A data processor is configured to: Obtaining column data to be processed according to the data to be processed; Performing a first convolution calculation on the column data using a first one-dimensional operator in a vertical direction to obtain the intermediate calculation result; as well as Perform a second convolution calculation using a second one-dimensional operator in the horizontal direction and the intermediate calculation result to obtain a convolution calculation result of the target two-dimensional operator and the column data. The target two-dimensional operator includes N rows and N columns of data, the data in the target two-dimensional operator is symmetrical in the vertical direction and / or in the horizontal direction, and the first one-dimensional operator and the second one-dimensional operator are obtained by splitting the target two-dimensional operator through operation, where N is a natural number.

14. A chip, characterized in that: include: a memory configured to store data associated with the convolution operation; as well as At least one processor is electrically coupled to the memory and configured to execute the data processing method according to any one of claims 1 to 12.

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