Display panel, display module and electronic equipment

Abstract

The invention relates to the technical field of display, particularly provides a display panel, a display module and electronic equipment, and aims to solve the problem of how to optimize fan-out area wiring and realize further narrowing of a lower frame. The display panel includes: a substrate; a plurality of functional layers including: a plurality of data lines; the plurality of data multiplexers are positioned in the fan-out region and comprise a first type of data multiplexers and a second type of data multiplexers; the fan-out wires in the panel comprise a first wire part, a second wire part and a third wire part which are connected in sequence, the first wire part extends from the fan-out area to the central area of the display area in the second direction, and the second wire part extends from the central area to the edge area in the first direction; and the third wiring part extends to the input end of the first-class data multiplexer from the edge region along the second direction. The number of fan-out wires is reduced, further narrowing of the lower frame is achieved by optimizing fan-out area wiring, and meanwhile the fan-out application range in the panel is expanded.

Description

Technical Field

[0001] The present application relates to the field of display technology, and specifically provides a display panel, a display module, and an electronic device. Background Art

[0002] With the continuous advancement of display panel manufacturing technology, narrow bezels and ultra-thin designs have become the mainstream trends in display product development. Demand for high resolution, large size, high-definition, and high-refresh rates is also increasing. To ensure optimal transmission performance and manufacturing feasibility, the number of data lines in display panels has increased significantly, and the size of the fan-out area has also increased accordingly. This problem is particularly prominent in display panels with dual-source drive architectures and the use of data multiplexers (Mux).

[0003] However, existing display panel wiring solutions limit the further reduction of the lower frame, making it difficult to meet the space requirements of extremely narrow frame products.

[0004] Therefore, how to optimize the fan-out area wiring and further narrow the bottom border has become an urgent problem to be solved.

[0005] Accordingly, the art requires a new display panel design solution to solve the above problems. Summary of the Invention

[0006] In order to overcome the above-mentioned defects, the present application is proposed to provide a display panel, a display module and an electronic device to solve or at least partially solve the technical problem of how to optimize the fan-out area wiring and further narrow the bottom frame.

[0007] In a first aspect, the present application provides a display panel having a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a fan-out area provided on one side of the display area, and the display panel includes:

[0008] substrate;

[0009] Multiple functional layers on the substrate, including:

[0010] a plurality of data lines arranged at intervals along a first direction and extending along a second direction intersecting the first direction, wherein the plurality of data lines include a plurality of first-category data lines and a plurality of second-category data lines, the first-category data lines being located at two edge regions of the display area along the first direction, and the second-category data lines being located at a central region between the two edge regions;

[0011] a plurality of data multiplexers located in the fan-out region, each of the data multiplexers comprising an input end and an output end, the output end being connected to at least two data lines, wherein the plurality of data multiplexers comprises a first type of data multiplexer connected to the first type of data lines and a second type of data multiplexer connected to the second type of data lines;

[0012] A plurality of intra-panel fan-out traces, each intra-panel fan-out trace comprising a first trace portion, a second trace portion, and a third trace portion connected in sequence, wherein the first trace portion extends from the fan-out region to a central region of the display region along the second direction, the second trace portion extends from the central region to an edge region along the first direction, and the third trace portion extends from the edge region to an input end of the first-type data multiplexer along the second direction; wherein a projection of the third trace portion on the substrate is located on one side of a projection of the first-type data multiplexer connected thereto on the substrate, or the projection of the third trace portion on the substrate partially overlaps with the projection of the first-type data multiplexer connected thereto on the substrate.

[0013] In one technical solution of the above display panel, the data multiplexer is

[0014] 1-way input, 2-way time-sharing output multiplexer; or

[0015] 1-way input, 3-way time-sharing output multiplexer; or

[0016] 1-channel input, 4-channel time-sharing output multiplexer.

[0017] In a technical solution of the above display panel, the display panel further includes a driver chip, the first wiring portion is connected to the driver chip in the fan-out region, and the input end of the second-type data multiplexer is connected to the driver chip.

[0018] In a technical solution of the above-mentioned display panel, the projection of each first routing portion on the substrate is located on one side of the projection of a second-type data multiplexer on the substrate, or the projection of each first routing portion on the substrate partially overlaps with the projection of a second-type data multiplexer on the substrate.

[0019] In a technical solution of the above display panel, the output end of each of the data multiplexers is connected to at least two adjacent data lines.

[0020] In a technical solution of the above display panel, the display panel has a rounded corner portion on the fan-out area side, and the data multiplexers located at the rounded corner portion among the plurality of data multiplexers surround the display area in a stepped manner.

[0021] In one technical solution of the above display panel, the central area includes two first central areas respectively adjacent to the two edge areas and a second central area therebetween, wherein the first wiring portion extends from the fan-out area to the first central area along the second direction;

[0022] The display panel further includes a low voltage power line VSS and an auxiliary power line disposed in the second central area and extending along a second direction, wherein the auxiliary power line is connected to the low voltage power line VSS.

[0023] In one technical solution of the above display panel, the display panel further includes:

[0024] a first source-drain electrode layer located on the substrate, wherein the second wiring portion is arranged on the first source-drain electrode layer; and

[0025] A second source-drain electrode layer is located above the first source-drain electrode layer, and the first routing portion and the third routing portion are arranged in the second source-drain electrode layer and are respectively connected to the second routing portion via holes.

[0026] In one technical solution of the above display panel, the display panel further includes:

[0027] a first source-drain electrode layer located on the substrate, wherein the second wiring portion is arranged in the first source-drain electrode layer;

[0028] A second source-drain electrode layer is located above the first source-drain electrode layer, wherein the first routing portion includes a main portion arranged in the second source-drain electrode layer and a jumper portion located in the first source-drain electrode layer, and the main portion and the jumper portion are connected by vias; the third routing portion is arranged in the second source-drain electrode layer and is connected to the second routing portion by vias.

[0029] In a technical solution of the above display panel, the first wiring portion further includes a switching piece located at the first source-drain electrode layer, and the second wiring portion is connected to the first wiring portion via the switching piece.

[0030] In a technical solution of the above display panel, the width of the main body portion is greater than the width of the jumper portion.

[0031] In one technical solution of the above display panel, the display panel further includes: a high-voltage power line VDD, which is arranged on the second source-drain electrode layer; a planarization layer, which is arranged between the second source-drain electrode layer and the first source-drain electrode layer;

[0032] The fan-out region further includes a metal layer, which is disposed on the second source-drain electrode layer and connected to the high-voltage power line VDD, wherein the metal layer has an opening to expose the planarization layer.

[0033] In one technical solution of the above display panel, the display panel further comprises a gate layer provided on the substrate and located below the first source-drain electrode layer; and

[0034] A data multiplexer connection line, the data multiplexer connection line including a first portion extending along a first direction and arranged on the first source-drain electrode layer and a second portion arranged on the gate layer, the projection of the metal layer on the substrate covering the data multiplexer and the projection of the first portion on the substrate.

[0035] In a second aspect, the present application provides a display module, comprising a display panel as described in any one of the above-mentioned display panel technical solutions.

[0036] In a third aspect, the present application provides an electronic device comprising the above-mentioned display module.

[0037] The above one or more technical solutions of this application have at least one or more of the following Beneficial effects:

[0038] In implementing the technical solution of the present application, the number of fan-out lines is reduced by a data multiplexer, and the lower frame is further narrowed by optimizing the fan-out area wiring, while the scope of application of the fan-out within the panel is expanded. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The disclosure of this application will be more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Furthermore, similar numbers in the figures represent similar components, where:

[0040] Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;

[0041] Figures 2A-2B are schematic diagrams of a data multiplexer according to an embodiment of the present application, wherein Figure 2A It is a 1-way input, 4-way time-sharing output multiplexer. Figure 2B It is a 1-way input and 2-way time-sharing output multiplexer;

[0042] Figure 3 is a schematic diagram of a rounded corner portion of a display panel on the fan-out area side according to an embodiment of the present application;

[0043] Figure 4 is a MUX 1:4 wiring diagram according to one embodiment of the present application;

[0044] Figure 5 is a MUX 1:2 wiring diagram according to one embodiment of the present application;

[0045] Figure 6 is a MUX 1:3 wiring diagram according to one embodiment of the present application;

[0046] Figures 7A-7C They are partial schematic diagrams of data lines according to embodiments of the present application, wherein Figure 7A For an embodiment of the layout, Figure 7B is a cross-sectional view along AB in one embodiment, Figure 7C is a cross-sectional view along AB in another embodiment;

[0047] Figures 8A-8C They are partial schematic diagrams of data lines according to embodiments of the present application, wherein Figure 8A For an embodiment of the layout, Figure 8B Schematic diagram of the first source-drain electrode layer and the second source-drain electrode layer in one embodiment. Figure 8C Schematic diagram of a first source-drain electrode layer and a second source-drain electrode layer in another embodiment;

[0048] Figure 9A-9B is a schematic diagram of a metal layer in a fan-out area according to one embodiment of the present application;

[0049] Figure 10 is a partial layout according to an embodiment of the present application;

[0050] Figure 11 This is a partial schematic diagram of a data line according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the scope of protection of the present application.

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0054] Currently, the height of the bottom frame of a display panel is limited by the wiring method of the fan-out lines. The present application provides a display panel that centrally arranges the fan-out lines in the display area, reduces the space occupied by the fan-out lines extending diagonally, and thereby narrows the bottom frame of the display panel.

[0055] See attached Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application. Figure 1 As shown, the display panel in the embodiment of the present application has a display area AA and a peripheral area surrounding the display area, wherein the peripheral area includes a fan-out area FOA provided on one side of the display area. The display panel includes:

[0056] substrate;

[0057] Multiple functional layers on the substrate, including:

[0058] a plurality of data lines arranged at intervals along a first direction H and extending along a second direction V intersecting the first direction H, wherein the plurality of data lines include a plurality of first-type data lines 101 and a plurality of second-type data lines 102, wherein the first-type data lines 101 are located in two edge regions A1 and A2 of the display area AA along the first direction H, and the second-type data lines 102 are located in a central region B between the two edge regions;

[0059] Multiple data multiplexers (MUX) Figure 1 ), located in the fan-out area, each of the data multiplexers includes an input end and an output end, the output end is connected to at least two data lines, wherein the plurality of data multiplexers include a first type of data multiplexer connected to the first type of data line 101 and a second type of data multiplexer connected to the second type of data line;

[0060] Multiple intra-panel fan-out traces 103 are provided. Each intra-panel fan-out trace 104 includes a first trace portion 104a, a second trace portion 104b, and a third trace portion 104c, which are sequentially connected. The first trace portion 104a extends from the fan-out area FOA along a second direction V to the central region B of the display area AA. The second trace portion 104b extends from the central region B to the edge region A1 along a first direction H. The third trace portion 104c extends from the edge region to the input end of the first type of data multiplexer along the second direction V. The central region B may also be referred to as a plugged trace area.

[0061] Those skilled in the art will appreciate that the plurality of data lines are evenly spaced along the first direction H. Figure 1 Only one first-type data line 101 and one second-type data line 102 are shown.

[0062] Furthermore, the output end of each data multiplexer is connected to at least two adjacent data lines.

[0063] Specifically, in the above display panel, the data multiplexer is a 1-way input, 2-way time-sharing output multiplexer, referred to as MUX 1:2; or

[0064] 1-input, 3-output multiplexer, referred to as MUX 1:3; or

[0065] 1-channel input, 4-channel time-sharing output multiplexer, referred to as MUX 1:4.

[0066] Please see the attached Figures 2A-2B The data multiplexer schematic is shown in Figure 2A It is a 1-way input, 4-way time-sharing output multiplexer. Figure 2B It is a 1-way input and 2-way time-sharing output multiplexer.

[0067] like Figure 2A As shown, in an embodiment using MUX 1:4, there are 200 columns of pixels in the edge area A (i.e., the FIP insertion area). For the Dual Source (dual data line) product, the corresponding data lines are 800. The wiring is performed by adopting the solution of V-FIP (i.e., the first routing part) to H-FIP (i.e., the second routing part) to V-FIP (i.e., the third routing part) and then to the Mux source. Only 200 FIPs need to be inserted in the central area B.

[0068] These 200 FIPs can be routed in area B1. The remaining vertical traces in area B2 can be used as SIP (VSS in Panel) lines to connect to the VSS (negative power supply) signal, reducing VSS voltage drop and improving display uniformity. This embodiment can be used in dual-source display panels.

[0069] Furthermore, the central area B includes two first central areas respectively close to the two edge areas and a second central area therebetween, wherein the first routing portion 104a extends from the fan-out area to the first central area along the second direction V;

[0070] The display panel further includes a low voltage power line VSS and an auxiliary power line disposed in the second central area and extending along a second direction, wherein the auxiliary power line is connected to the low voltage power line VSS.

[0071] like Figure 2B As shown, in an embodiment using MUX 1:2, there are 200 columns of pixels in the edge area A, corresponding to 400 data lines. By adopting the solution of V-FIP to H-FIP to V-FIP and then to the Mux source for routing, only 200 FIPs need to be inserted in the central area B.

[0072] Similarly, these 200 FIPs can be routed in area B1, and the remaining vertical traces in area B2 can be used as SIPs to access VSS signals, reducing VSS voltage drop and improving display uniformity. This also reduces the space occupied by the fan-out area and further narrows the bottom bezel.

[0073] The display panel further includes a driver chip (DDIC), the first wiring portion 104 a is connected to the driver chip in the fan-out area FOA, and the input end of the second-type data multiplexer is connected to the driver chip.

[0074] In one embodiment of this application, please refer to the attached Figure 1 and attached Figure 3 As shown, Figure 3 FIG2 is a schematic diagram of a rounded corner portion of a display panel on the fan-out area side according to an embodiment of the present application. The display panel has a rounded corner portion 103 on the fan-out area side, and a data multiplexer 301 located at the rounded corner portion surrounds the display area AA in a stepped manner.

[0075] The projection of the third wiring portion 104c on the substrate is located on one side of the projection of the first type of data multiplexer connected to it on the substrate (eg Figure 5 ), or the projection of the third wiring portion 104c on the substrate partially overlaps with the projection of the first type of data multiplexer connected thereto on the substrate (as shown in FIG. Figure 4 、 Figure 6 shown).

[0076] Furthermore, the projection of each of the first wiring portions 104a on the substrate is located on one side of the projection of a second type data multiplexer on the substrate (eg Figure 5), or the projection of each of the first wiring portions 104a on the substrate partially overlaps with the projection of a second type data multiplexer on the substrate (as shown in FIG. Figure 4 、 Figure 6 shown).

[0077] Specifically, see Figure 4 、 Figure 5 as well as Figure 6 .in, Figure 4 is a MUX 1:4 wiring diagram according to one embodiment of the present application; Figure 5 is a MUX 1:2 wiring diagram according to one embodiment of the present application; Figure 6 This is a MUX 1:3 wiring diagram according to an embodiment of the present application.

[0078] like Figure 4 As shown, the left side shows the data multiplexer n located in the edge area A1 and connected to the second type of data line 102, and the right side shows the data multiplexer m located in the central area B and connected to the first type of data line 101. The data multiplexer is a 1-way input, 4-way time-sharing output multiplexer, referred to as MUX 1:4. Among them, n, n+1, n+2, n+3 are the numbers of the data lines connected to the output end of the data multiplexer n, and m, m+1, m+2, m+3 are the numbers of the data lines connected to the output end of the data multiplexer m; ①V_FIP is the first routing portion connected to the data multiplexer n, ②V_FIP is the third routing portion connected to the data multiplexer n, and its second routing portion is not shown. Specifically, in this embodiment, as Figure 4 As shown in the left part, the projection of the third routing portion ② V_FIP on the substrate partially overlaps with the projection of the first type of data multiplexer connected thereto on the substrate; Figure 4 As shown in the right part, the projection of the first routing portion ① V_FIP on the substrate partially overlaps with the projection of the first type of data multiplexer connected thereto on the substrate.

[0079] like Figure 5 As shown, the left side shows the data multiplexer n located in the edge area A1 and connected to the second type of data line 102, and the right side shows the data multiplexer m located in the central area B and connected to the first type of data line 101. The data multiplexer is a 1-way input, 2-way time-sharing output multiplexer, referred to as MUX 1:2. Among them, n and n+1 are the numbers of the data lines connected to the output end of the data multiplexer n, and m and m+1 are the numbers of the data lines connected to the output end of the data multiplexer m; ①V_FIP is the first routing portion connected to the data multiplexer n, ②V_FIP is the third routing portion connected to the data multiplexer n, and its second routing portion is not shown. Specifically, in this embodiment, as Figure 5As shown in the left part, the projection of the third routing portion ② V_FIP on the substrate is located to the left of the projection of the first type of data multiplexer connected thereto on the substrate; Figure 5 As shown in the right part, the projection of the first routing portion ① V_FIP on the substrate is located to the left of the projection of the first type of data multiplexer connected thereto on the substrate.

[0080] like Figure 6 As shown, the left side shows the data multiplexer n located in the edge area A1 and connected to the second type of data line 102, and the right side shows the data multiplexer m located in the central area B and connected to the first type of data line 101. The data multiplexer is a 1-way input, 3-way time-sharing output multiplexer, referred to as MUX 1:3. Among them, n, n+1, n+2 are the numbers of the data lines connected to the output end of the data multiplexer n, and m, m+1, m+2, m+3 are the numbers of the data lines connected to the output end of the data multiplexer m; ①V_FIP is the first routing portion connected to the data multiplexer n, ②V_FIP is the third routing portion connected to the data multiplexer n, and its second routing portion is not shown. Specifically, in this embodiment, as Figure 6 As shown in the left part, the projection of the third routing portion ② V_FIP on the substrate partially overlaps with the projection of the first type of data multiplexer connected thereto on the substrate; Figure 6 As shown in the right part, the projection of the first routing portion ① V_FIP on the substrate partially overlaps with the projection of the first type of data multiplexer connected thereto on the substrate.

[0081] For Dual Source products, in order to match two data lines for each column of pixels, the number of data lines increases exponentially. The use of a conventional FIP (fan-out in panel) solution will double the number of fan-out lines, that is, the FIP lines in the center area B will be doubled, and this space cannot meet the need for doubling the FIP.

[0082] With the design of this application, the number of FIP traces not only does not increase, but can actually be reduced. For example, using Mux 1:2 can reduce the number of fan-out traces by 1 / 2; using Mux 1:4 can reduce the number of FIP traces by 3 / 4; and using Mux 1:3 can reduce the number of FIP traces by 2 / 3. The above technical solution greatly reduces the number of FIP traces in the central area B of the plugged area; that is, it reduces the number of fan-out traces in the second direction V of the pixel area and the number of fan-out traces in the lower frame of the display area AA; it can also further reduce the lower frame, while expanding the scope of application of the FIP.

[0083] Further, see Figure 11 . Figure 11 This is a partial schematic diagram of a data line according to an embodiment of the present application.

[0084] like Figure 11 As shown, in one embodiment, the display panel further includes:

[0085] A first source-drain electrode layer SD1 located on the substrate, wherein the second wiring portion 104b is disposed on the first source-drain electrode layer SD1; and

[0086] The second source-drain electrode layer SD2 is located above the first source-drain electrode layer SD1 , and the first routing portion 104 a and the third routing portion 104 c are disposed in the second source-drain electrode layer SD2 and are respectively connected to the second routing portion 104 b via holes. Reference numeral 110 denotes a via hole.

[0087] Furthermore, jumper settings may be performed on the data lines extending along the second direction V.

[0088] See also Figures 7A-7C . Figures 7A-7C They are partial schematic diagrams of data lines according to embodiments of the present application, wherein Figure 7A For an embodiment of the layout, Figure 7B is a cross-sectional view along AB in one embodiment, Figure 7C It is a cross-sectional view along AB in another embodiment.

[0089] in, Figure 7B The figure shows a jumper configuration without an adapter. 700 is a substrate, exemplarily a PI (polyimide) substrate; 702 is an inorganic insulating layer; 703 is an organic planarization layer; Gate1 and Gate2 represent two gate layers. In this embodiment, the SD2 layer 704 is continuous between the two vias 110, meaning both SD1 and SD2 layers conduct electricity. Alternatively, the SD2 layer 704 can be disconnected between the two vias 110, with only the SD1 layer conducting electricity.

[0090] Further, please also refer to Figure 8A and 8B .

[0091] Figures 8A-8C They are partial schematic diagrams of data lines according to embodiments of the present application, wherein Figure 8A For an embodiment of the layout, Figure 8B Schematic diagram of the first source-drain electrode layer and the second source-drain electrode layer in one embodiment. Figure 8C Schematic diagram of the first source-drain electrode layer and the second source-drain electrode layer in another embodiment.

[0092] in Figure 8B for Figure 8A The schematic diagram of the first source-drain electrode layer SD1 and the second source-drain electrode layer SD2 in the region 801 is provided. A person skilled in the art can clearly understand the positional relationship between the electrode layers through this top-down perspective.

[0093] In another embodiment, a transfer plate may be further provided. Figure 7A and 7C As shown, the display panel further includes:

[0094] A first source-drain electrode layer SD1 is located on the substrate, and the second wiring portion 104b is provided in the first source-drain electrode layer SD1;

[0095] The second source-drain electrode layer SD2 is located above the first source-drain electrode layer SD1, wherein the first routing portion 104a includes a main body portion arranged in the second source-drain electrode layer SD2 and a jumper portion located in the first source-drain electrode layer SD1, and the main body portion and the jumper portion are connected by vias; the third routing portion 104c is arranged in the second source-drain electrode layer SD2 and is connected to the second routing portion 104b by vias.

[0096] Specifically, if Figure 7C As shown, 701 is an adapter, 700 is a substrate, which can be, for example, a PI (polyimide) substrate, 702 is an inorganic insulating layer, 703 is an organic planar layer, and Gate1 and Gate2 schematically represent two gate layers. In this embodiment, the SD2 layer 704 is continuous between the two vias 110, i.e., both SD1 and SD2 layers are used for electrical conduction. Alternatively, the SD2 layer 704 can be disconnected between the two vias 110, with only the SD1 layer being used for electrical conduction.

[0097] In this embodiment, the fan-out traces extending along the second direction V do not utilize a single fixed film layer. Instead, a trace jumper design is employed, with SD1 and SD2 being connected as jumpers. Specifically, the jumper can be implemented within the pixel or immediately below the display area AA.

[0098] In one embodiment, the width of the main body portion is greater than the width of the jumper portion.

[0099] Furthermore, the first wiring portion 104 a further includes a transfer sheet 701 located on the first source-drain electrode layer SD1 , and the second wiring portion 104 b is connected to the first wiring portion 104 a via the transfer sheet 701 .

[0100] Further, please also refer to Figure 8A and 8C ,in Figure 8C for Figure 8A Schematic diagram of the first source-drain electrode layer SD1 and the second source-drain electrode layer SD2 in area 801. Those skilled in the art can clearly understand the positional relationship between the electrode layers and the location of the adapter 701 from this top view.

[0101] Furthermore, the second wiring portion 104b is connected to the first wiring portion 104a through a via at the intersection.

[0102] In one embodiment of the present application, the display panel further includes: a high-voltage power line VDD, which is provided on the second source-drain electrode layer SD2; a planarization layer, which is provided between the second source-drain electrode layer SD2 and the first source-drain electrode layer SD1;

[0103] The fan-out region further includes a metal layer, which is disposed on the second source-drain electrode layer SD2 and connected to the high-voltage power line VDD, wherein the metal layer has an opening to expose the planarization layer.

[0104] Please refer to Figure 9. Figure 9A-9B is a schematic diagram of a fan-out area metal layer according to an embodiment of the present application, wherein: Figure 9A This is a top view of the metal layer schematic diagram of the fan-out area. Figure 9A Schematic diagram of the fan-out metal layer disposed in the display panel, wherein 901 is the opening position.

[0105] Furthermore, the above embodiments can be referred to in the attached Figure 10 . Figure 10 This is a partial layout diagram according to an embodiment of the present application, showing the transfer hole and FIP routing method.

[0106] In this embodiment, the metal layer connected to VDD adopts the SD2 film layer, which covers the entire Mux structure. At the same time, a perforated design is adopted to play the role of degassing the organic layer, effectively avoiding the bulging phenomenon of the film layer.

[0107] Furthermore, in some embodiments, the display panel further includes a gate layer Gate disposed on the substrate and located below the first source-drain electrode layer SD1; and

[0108] The data multiplexer connection line includes a first portion extending along the first direction H and arranged on the first source-drain electrode layer SD1 and a second portion arranged on the gate layer. Figure 4 、 Figure 5 and Figure 6 As shown, SD1 extending below the data multiplexer along the first direction H is the first portion. The second portion is used to connect the driver chip and the first portion, and the first portion is used to send the driving signal to each data multiplexer. Specifically, the extension direction of the second portion can be set according to actual needs.

[0109] The projection of the metal layer on the substrate covers the projection of the data multiplexer and the first portion on the substrate. Figure 9BAs shown, the projection of the metal layer on the substrate may also cover a portion of the second portion.

[0110] Based on the above display panel, the number of fan-out lines is reduced through a data multiplexer, and the lower border is further narrowed by optimizing the fan-out area wiring, while the scope of application of the fan-out within the panel is expanded.

[0111] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effect of the present application, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present application.

[0112] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0113] Furthermore, the present application also provides a display module, comprising the display panel described in any one of the above-mentioned display panel technical solutions.

[0114] Furthermore, the present application also provides an electronic device including the aforementioned display module. The electronic device described herein may be a wearable product, a mobile terminal, or other device. The electronic device may have all the features and advantages of the aforementioned display panel and display module, and will not be further elaborated here.

[0115] Those skilled in the art will appreciate that the electronic device described in this application may include but is not limited to the above-mentioned display module, and may also include other components or combinations of components, such as memory, processor, sensor and other components.

[0116] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0117] Thus far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is readily understood by those skilled in the art that the scope of protection of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present application.

Claims

1. A display panel comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a fan-out area arranged on one side of the display area, characterized in that: The display panel includes: substrate; Multiple functional layers on the substrate, including: a plurality of data lines arranged at intervals along a first direction and extending along a second direction intersecting the first direction, wherein the plurality of data lines include a plurality of first-category data lines and a plurality of second-category data lines, the first-category data lines being located at two edge regions of the display area along the first direction, and the second-category data lines being located at a central region between the two edge regions; a plurality of data multiplexers located in the fan-out region, each of the data multiplexers comprising an input end and an output end, the output end being connected to at least two data lines, wherein the plurality of data multiplexers comprises a first type of data multiplexer connected to the first type of data lines and a second type of data multiplexer connected to the second type of data lines; A plurality of intra-panel fan-out traces, each intra-panel fan-out trace comprising a first trace portion, a second trace portion, and a third trace portion connected in sequence, wherein the first trace portion extends from the fan-out region to a central region of the display region along the second direction, the second trace portion extends from the central region to an edge region along the first direction, and the third trace portion extends from the edge region to an input end of the first-type data multiplexer along the second direction; wherein a projection of the third trace portion on the substrate is located on one side of a projection of the first-type data multiplexer connected thereto on the substrate, or the projection of the third trace portion on the substrate partially overlaps with the projection of the first-type data multiplexer connected thereto on the substrate.

2. The display panel according to claim 1, wherein: The data multiplexer is a 1-way input and 2-way time-sharing output multiplexer; or 1-way input, 3-way time-sharing output multiplexer; or 1-channel input, 4-channel time-sharing output multiplexer.

3. The display panel according to claim 1, wherein: The display panel further includes a driving chip, the first wiring portion is connected to the driving chip in the fan-out region, and the input end of the second-type data multiplexer is connected to the driving chip.

4. The display panel according to claim 1, wherein: The projection of each first routing portion on the substrate is located on one side of the projection of a second-type data multiplexer on the substrate, or the projection of each first routing portion on the substrate partially overlaps with the projection of a second-type data multiplexer on the substrate.

5. The display panel according to claim 1, wherein: An output terminal of each data multiplexer is connected to at least two adjacent data lines.

6. The display panel according to claim 1, wherein: The display panel has a rounded corner portion on the fan-out area side, and the data multiplexers located at the rounded corner portion among the plurality of data multiplexers surround the display area in a stepped manner.

7. The display panel according to claim 1, wherein: The central area includes two first central areas respectively close to the two edge areas and a second central area therebetween, wherein the first routing portion extends from the fan-out area to the first central area along the second direction; The display panel further includes a low voltage power line VSS and an auxiliary power line disposed in the second central area and extending along a second direction, wherein the auxiliary power line is connected to the low voltage power line VSS.

8. The display panel according to any one of claims 1 to 7, characterized in that: The display panel further includes: a first source-drain electrode layer located on the substrate, wherein the second wiring portion is arranged on the first source-drain electrode layer; and A second source-drain electrode layer is located above the first source-drain electrode layer, and the first routing portion and the third routing portion are arranged in the second source-drain electrode layer and are respectively connected to the second routing portion via holes.

9. The display panel according to any one of claims 1 to 7, wherein: The display panel further includes: a first source-drain electrode layer located on the substrate, wherein the second wiring portion is arranged in the first source-drain electrode layer; A second source-drain electrode layer is located above the first source-drain electrode layer, wherein the first routing portion includes a main portion arranged in the second source-drain electrode layer and a jumper portion located in the first source-drain electrode layer, and the main portion and the jumper portion are connected by vias; the third routing portion is arranged in the second source-drain electrode layer and is connected to the second routing portion by vias.

10. The display panel according to claim 9, wherein: The first wiring portion further includes a switching piece located at the first source-drain electrode layer, and the second wiring portion is connected to the first wiring portion via the switching piece.

11. The display panel according to any one of claims 9 to 10, characterized in that: The width of the main body portion is greater than the width of the jumper portion.

12. The display panel according to claim 8 or 9, characterized in that: The display panel further includes: a high-voltage power line VDD, which is arranged on the second source-drain electrode layer; a planarization layer, which is arranged between the second source-drain electrode layer and the first source-drain electrode layer; The fan-out region further includes a metal layer, which is disposed on the second source-drain electrode layer and connected to the high-voltage power line VDD, wherein the metal layer has an opening to expose the planarization layer.

13. The display panel according to claim 12, wherein: The display panel further includes a gate layer disposed on the substrate and located below the first source-drain electrode layer; and A data multiplexer connection line, the data multiplexer connection line including a first portion extending along a first direction and arranged on the first source-drain electrode layer and a second portion arranged on the gate layer, the projection of the metal layer on the substrate covering the data multiplexer and the projection of the first portion on the substrate.

14. A display module, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 13.

15. An electronic device, characterized in that: Including the display module according to claim 14.

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