Display substrate, manufacturing method thereof and display device

Abstract

The embodiment of the invention provides a display substrate, a manufacturing method thereof and a display device, relates to the technical field of display, and is used for improving the display quality of a display screen. The display substrate comprises a display area, a hole area and an isolation area. The display substrate comprises a substrate body and isolation columns. The isolation columns are located on one side of the substrate and located in the isolation areas. The isolation column comprises a bottom isolation layer, a first insulation layer, a first metal layer and a second insulation layer which are sequentially arranged in a stacked mode in the thickness direction of the display substrate and in the direction away from the substrate. The second insulating layer covers a side surface of the first metal layer. Edges of the bottom isolation layer and the second insulation layer toward the display area and / or and / or protrude relative to an edge of the first insulation layer. The bottom isolation layer includes a semiconductor material. The display substrate is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] A display screen's display area can be provided with openings for placement of sensors such as camera modules and facial recognition modules, thereby reducing the display's bezel width, increasing the screen-to-body ratio, and enhancing the visual effect. However, the opening design of the display screen increases the difficulty of packaging the display, making it difficult to guarantee display quality. Summary of the Invention

[0003] On the one hand, a display substrate is provided, which includes a display area, a hole area and an isolation area, and the isolation area separates the display area and the hole area. The display substrate specifically includes a base substrate and an isolation column. The isolation column is located on one side of the base substrate, the isolation column is located in the isolation area, and the isolation column separates the display area and the hole area. Along the thickness direction of the display substrate and away from the base substrate, the isolation column includes a bottom isolation layer, a first insulating layer, a first metal layer and a second insulating layer stacked in sequence. The second insulating layer covers the side of the first metal layer. The bottom isolation layer and the second insulating layer protrude relative to the edge of the first insulating layer toward the edge of the display area, and / or, the bottom isolation layer and the second insulating layer protrude relative to the edge of the first insulating layer toward the edge of the hole area. Wherein, the bottom isolation layer includes a semiconductor material.

[0004] In some embodiments, the bottom isolation layer includes a first bottom isolation portion, a second bottom isolation portion, and a third bottom isolation portion. The first bottom isolation portion is located on a side of the second bottom isolation portion closer to the display area. The second bottom isolation portion is connected to the first bottom isolation portion and is located between the first and third bottom isolation portions. The third bottom isolation portion is connected to the second bottom isolation portion and is located on a side of the second bottom isolation portion closer to the hole area. The first and third bottom isolation portions comprise doped semiconductor material, and the doping concentrations of the first and third bottom isolation portions are greater than the doping concentration of the second bottom isolation portion.

[0005] In some embodiments, an edge of the second floor isolation portion is aligned or substantially aligned with an edge of the first metal layer in a thickness direction of the display substrate.

[0006] In some embodiments, an edge of the bottom isolation layer protrudes relative to an edge of the second insulation layer away from a surface of the first insulation layer.

[0007] In some embodiments, the second insulating layer includes a first insulating portion and a second insulating portion. The second insulating portion covers a side surface of the first metal layer, and the first insulating portion is located on a side of the second insulating portion away from the first insulating layer. At least one side edge of the first insulating portion protrudes relative to an edge of the first insulating layer and the second insulating portion.

[0008] In some embodiments, the display substrate further includes a light-emitting stacked structure and a light-emitting stacked structure. The light-emitting stacked structure is located on one side of the base substrate, and the light-emitting stacked structure is located on the side of the isolation column facing the display area and the side facing the hole area. The functional isolation layer is located on the side of the isolation column away from the base substrate. The material of the functional isolation layer is the same as at least part of the material of the light-emitting functional layer. The functional isolation layer is not connected to the light-emitting stacked structure located on the side of the isolation column facing the display area, and / or the functional isolation layer is not connected to the light-emitting stacked structure located on the side of the isolation column facing the hole area.

[0009] In some embodiments, the isolation column further includes a second metal layer and a third insulating layer, wherein the second metal layer is located on a side of the second insulating layer away from the first metal layer, and the third insulating layer is located on a side of the second metal layer away from the second insulating layer.

[0010] In some embodiments, at least one side edge of the second metal layer and / or the third insulating layer protrudes relative to an edge of the first insulating layer.

[0011] In some embodiments, at least one side edge of the second metal layer protrudes relative to an edge of the third insulating layer.

[0012] In some embodiments, the functional isolation layer is connected to at least one side surface of the third insulating layer, and the functional isolation layer is connected to a surface of a portion of the second metal layer protruding from the third insulating layer away from the second insulating layer.

[0013] In some embodiments, the sum of the thicknesses of the first insulating layer and the second insulating layer is greater than the thickness of the light-emitting stacked structure and / or greater than the thickness of the functional isolation layer.

[0014] In some embodiments, a material of any one of the first insulating layer, the second insulating layer, and the third insulating layer includes an inorganic material.

[0015] In some embodiments, the display substrate further includes a pixel circuit disposed in the display area, the pixel circuit including an active layer pattern, a first gate metal layer, and a first gate dielectric layer. The bottom isolation layer of the isolation column is made of the same material as the active layer pattern, the first metal layer of the isolation column is made of the same material as the first gate metal layer, and the first insulating layer of the isolation column is made of the same material as the first gate dielectric layer.

[0016] In some embodiments, the pixel circuit further includes a storage capacitor and a second gate metal layer. At least a portion of the first gate metal layer serves as one plate of the storage capacitor, and at least a portion of the second gate metal layer serves as another plate of the storage capacitor. The second gate metal layer is located on a side of the first gate metal layer away from the substrate, and the second metal layer of the isolation pillar is made of the same material as the second gate metal layer.

[0017] In some embodiments, the pixel circuit further includes a second gate metal layer and a third gate metal layer disposed in the display area. The second gate metal layer is located on a side of the first gate metal layer away from the substrate, and the third gate metal layer is located on a side of the second gate metal layer away from the first gate metal layer. The second metal layer and the third gate metal layer of the isolation pillar are made of the same material.

[0018] In some embodiments, the isolation column further includes a fourth insulating layer. The fourth insulating layer is located on a side of the second insulating layer away from the first metal layer, and the material of the fourth insulating layer includes an organic material.

[0019] In some embodiments, the isolation column further includes an electrostatic shielding layer, which is located between the bottom isolation layer and the base substrate, and the edge of the electrostatic shielding layer does not exceed the edge of the bottom isolation layer.

[0020] In some embodiments, the display substrate further includes a light shielding layer, the light shielding layer overlaps with an active layer pattern of a thin film transistor disposed in the display area, and the electrostatic shielding layer and the light shielding layer are made of the same material.

[0021] On the other hand, a method for manufacturing a display substrate is provided. The display substrate includes a display area, a hole area, and an isolation area, wherein the isolation area separates the display area and the hole area. The manufacturing method includes: forming a semiconductor layer on a base substrate, the semiconductor layer including an active layer pattern of a thin-film transistor located in the display area, and a bottom isolation layer located in the isolation area. Forming a first gate dielectric layer on a side of the active layer pattern away from the base substrate, and forming a first insulating layer on a side of the bottom isolation layer away from the base substrate. Forming a first gate metal layer on a side of the first gate dielectric layer away from the active layer pattern, and forming a first metal layer on a side of the first insulating layer away from the bottom isolation layer. The first gate metal layer includes a gate electrode of the thin-film transistor. Forming a second gate dielectric layer on a side of the first gate metal layer away from the first gate dielectric layer, and forming a second insulating layer on a side of the first metal layer away from the first insulating layer.

[0022] In some embodiments, after forming a second gate dielectric layer on a side of the first gate metal layer away from the first gate dielectric layer and forming a second insulating layer on a side of the first metal layer away from the first insulating layer, the above-mentioned manufacturing method further includes: etching an opening in the second gate dielectric layer along the thickness direction of the display substrate, etching the side of the first insulating layer facing the display area, so that the edges of the bottom isolation layer and the second insulating layer facing the display area protrude relative to the edge of the first insulating layer. And / or, etching an opening in the second gate dielectric layer along the thickness direction of the display substrate, etching the side of the first insulating layer facing the hole area, so that the edges of the bottom isolation layer and the second insulating layer facing the hole area protrude relative to the edge of the first insulating layer.

[0023] In another aspect, a display device is provided, comprising a driving circuit board and the display substrate according to any one of the above embodiments, wherein the driving circuit board is electrically connected to the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] Figure 1 is an appearance diagram of a display device according to some embodiments of the present disclosure;

[0026] Figure 2 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0027] Figure 3 is a top view of a display substrate according to some embodiments of the present disclosure;

[0028] Figure 4 Based on Figure 3 A partial cross-sectional view of the display substrate along the “AA′” direction in the illustrated embodiment;

[0029] Figure 5 is a diagram of a stacking structure of isolation pillars according to some embodiments of the present disclosure;

[0030] Figure 6 is a diagram of a stacking structure of another type of isolation pillars according to some embodiments of the present disclosure;

[0031] Figure 7 is a diagram of a stacking structure of another isolation column according to some embodiments of the present disclosure;

[0032] Figure 8 is a diagram of a stacking structure of another isolation column according to some embodiments of the present disclosure;

[0033] Figure 9 is a diagram of a stacking structure of another isolation column according to some embodiments of the present disclosure;

[0034] Figure 10 is a partial stacking structure diagram of a display substrate according to some embodiments of the present disclosure;

[0035] Figure 11 This is a flowchart of the steps of a method for manufacturing a display substrate according to some embodiments of the present disclosure.

[0036] Reference numerals:

[0037] 1-display device; 2-display substrate; 3-driver circuit board; 4-display driver chip; 201-display area; 202-aperture area; 203-isolation area; 204-frame area; 205-pixel circuit; 21-substrate; 22-isolation column; 24-encapsulation layer; 231-light-emitting stacked structure; 232-functional isolation layer; 2201-first groove; 2202-second groove; 221-bottom isolation layer; 2211-first bottom isolation portion; 2212-second bottom isolation portion; 2213-third bottom isolation portion; 2221-first insulating layer; 2222-second insulating layer; 22221-first insulating portion; 22222-second insulating portion; 2223-third insulating portion Insulation layer; 2224-fourth insulating layer; 2231-first metal layer; 2232-second metal layer; 251-active layer pattern; 252-first gate metal layer; 253-first gate dielectric layer; 254-second gate metal layer; 255-second gate dielectric layer; 256-interlayer dielectric layer; 257-flat layer; 258-pixel definition layer; 259-source / drain metal layer; 2001-first protective substrate; 2002-buffer layer; 2003-first inkjet printed layer; 2004-second inkjet printed layer; 2005-touch insulating layer; 2006-touch layer; 2007-polarizing layer; 2008-optical adhesive layer; 2009-second protective substrate; supporting layer 2010. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0042] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0043] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0044] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0045] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0046] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0047] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0048] Some embodiments of the present disclosure provide a display device. Figure 1As shown, the display device 1 can be any display device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, the display device 1 of the contemplated embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a product), etc.

[0049] The form of the display device and the form of the screen are not limited. Figure 1 As shown, the display device 1 can be a straight-screen mobile phone with a curved display screen. For another example, the display device 1 can also be a mobile phone with a foldable screen.

[0050] Exemplarily, the display device 1 may include but is not limited to an organic light emitting diode (OLED) display device, a microlight emitting diode (microLED) display device, a sub-millimeter light emitting diode (miniLED) display device, a liquid crystal display (LCD), etc.

[0051] In some embodiments, as Figure 2 As shown, the display device 1 may specifically include a display substrate 2 and a driving circuit board 3. The driving circuit board 3 is electrically connected to the display substrate 2.

[0052] In some examples, the display device 1 is an active light-emitting display device (eg, an OLED display device), and the display substrate 2 can be directly used for displaying images. Since the display substrate 2 can emit light itself, there is no need to configure a backlight module.

[0053] In some examples, a display driver chip 4 and other electronic components may be provided on the driver circuit board 3. The display driver chip 4, also known as a display driver integrated circuit (DDIC), is primarily used to control parameters such as the light emission, color, and brightness of the pixels of the display substrate 2 to achieve correct display of images and videos.

[0054] In some embodiments, as Figure 3 As shown, the display substrate 2 includes a display area 201 , a hole area 202 and an isolation area 203 , and the isolation area 203 separates the display area 201 and the hole area 202 .

[0055] Exemplarily, the display substrate 2 further includes a frame area 204, which can surround the display area 201. The frame area 204 can be used to set metal traces. The hole area 202, the isolation area 203, and the frame area 204 are all non-display areas.

[0056] Exemplarily, the isolation region 203 may surround the hole region 202 , and the display region 201 may surround the isolation region 203 , so that the hole region 202 is disposed within the display region.

[0057] The hole area 202 of the display substrate 2 can be provided with an opening, so that sensors such as a camera module and a face recognition module can be placed in the opening surrounded by the display area 201, thereby shrinking the width of the border area 204 of the display substrate 2, increasing the screen-to-body ratio of the display screen, and enhancing the visual effect.

[0058] like Figure 4 As shown, the display substrate 2 includes a base substrate 21 and isolation columns 22 .

[0059] In some examples, the substrate 21 may be a rigid substrate or a flexible substrate. Exemplary materials for the substrate 21 include, but are not limited to, glass and plastic. For example, the substrate 21 may be a flexible substrate, and materials for the substrate 21 include, but are not limited to, polyimide (PI) and polyethylene terephthalate (PET).

[0060] like Figure 4 As shown, the isolation column 22 is located on one side of the base substrate 21 , the isolation column 22 is located in the isolation area 203 , and the isolation column 22 separates the display area 201 and the hole area 202 .

[0061] Exemplarily, the isolation pillars 22 may surround the hole area 202. For example, the display substrate 2 includes a plurality of isolation pillars 22, and the plurality of isolation pillars 22 may respectively surround the hole area 202, thereby improving the packaging effect of the display area 201 around the hole area 202.

[0062] like Figure 5 and Figure 6 As shown, along the thickness direction of the display substrate 2 and away from the base substrate 21 , the isolation column 22 includes a bottom isolation layer 221 , a first insulating layer 2221 , a first metal layer 2231 and a second insulating layer 2222 stacked in sequence.

[0063] For example, Figure 5 and Figure 6 As shown, the thickness direction of the display substrate 2 can be parallel to the first direction Z, and the direction away from the base substrate 21 can be the opposite direction of the first direction Z.

[0064] The bottom isolation layer 221 comprises a semiconductor material. Thus, under certain conditions, the bottom isolation layer 221 can have insulating properties. For example, the conductive portion of the semiconductor material can be conductive. Alternatively, the non-conductive portion of the semiconductor material can be insulating, ensuring the insulation of the isolation column 22.

[0065] For example, Figure 5 and Figure 6 As shown, the display substrate 2 may further include a light-emitting stacked structure 231 and a functional isolation layer 232 .

[0066] The light emitting stacked structure 231 is located on one side of the base substrate 21 and on the side of the isolation column 22 facing the display area 201 and the hole area 202. The light emitting stacked structure 231 has a conductive property.

[0067] The functional isolation layer 232 is located on a side of the isolation column 22 away from the base substrate 21 .

[0068] Exemplarily, the material of the functional isolation layer 232 is the same as at least a portion of the material of the light-emitting stacked structure 231. For example, the material of the functional isolation layer 232 is the same as the material of the light-emitting stacked structure 231.

[0069] The functional isolation layer 232 is not connected to the light emitting stacked structure 231 located on the side of the isolation column 22 facing the display area 201 , and / or the functional isolation layer 232 is not connected to the light emitting stacked structure 231 located on the side of the isolation column 22 facing the hole area 202 .

[0070] The light-emitting stacked structure 231 and the functional isolation layer 232 are simultaneously fabricated material layers. There is a gap between the light-emitting stacked structure 231 and the functional isolation layer 232, or in other words, the light-emitting stacked structure 231 and the functional isolation layer 232 are not connected. The light-emitting stacked structure 231 can be powered, while the functional isolation layer 232 cannot.

[0071] For example, the display substrate 2 may include a light-emitting device, which is located in the display area 201. For example, the light-emitting device may include an anode layer, an electroluminescence layer, and a cathode layer stacked along the thickness direction of the base substrate 21 and away from the base substrate 21. The anode layer is in direct contact with the electroluminescence layer, and the cathode layer is in direct contact with the electroluminescence layer.

[0072] The anode layer can be positively charged, and the cathode layer can be negatively charged. In a light-emitting device, the cathode layer can be configured to transfer charge to the electroluminescent layer, which emits light when energized by the injected charge. For example, the electroluminescent layer can include an organic light-emitting material, and the cathode layer can include a metal material.

[0073] The light emitting stacked structure 231 may include an electroluminescent layer and a cathode layer, and the light emitting stacked structure 231 may extend to the non-display area.

[0074] For example, the function blocking layer 232 may include a material of the electroluminescent layer and a material of the cathode layer.

[0075] The bottom isolation layer 221 is a semiconductor material, which is conducive to making the isolation column 22 insulating, so that the isolation column 22 can isolate the functional isolation layer 232 from the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the display area 201, and / or isolate the functional isolation layer 232 from the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the hole area 202.

[0076] Exemplarily, the semiconductor material includes, but is not limited to, silicon (Si), indium gallium zinc oxide (IGZO), germanium Ge, and gallium arsenide (GaAs). For example, the semiconductor material may be polycrystalline silicon (poly-Si).

[0077] like Figure 5 and Figure 6 As shown, the second insulating layer 2222 covers the side surfaces of the first metal layer 2231 .

[0078] For example, the side surface of the first metal layer 2231 may be an edge surface of the first metal layer 2231 extending along the thickness direction of the first metal layer 2231. For example, the second insulating layer 2222 may cover the surface of the first metal layer 2231 away from the substrate 21, thereby achieving insulation protection for the first metal layer 2231.

[0079] like Figure 5As shown, in the first example, the bottom isolation layer 221 protrudes toward the edge of the display area 201 relative to the edge of the first insulating layer 2221 , and the second insulating layer 2222 protrudes toward the edge of the display area 201 relative to the edge of the first insulating layer 2221 .

[0080] Illustratively, the distance between the first insulating layer 2221 and the display area 201 is greater than the distance between the bottom isolation layer 221 and the display area 201 , and the distance between the first insulating layer 2221 and the display area 201 is greater than the distance between the second insulating layer 2222 and the display area 201 .

[0081] In the above example, the edges of the bottom isolation layer 221 and the second insulating layer 2222 toward the display area 201 protrude relative to the edge of the first insulating layer 2221, so that a first groove 2201 can be formed on the side of the isolation column 22 facing the display area 201. The opening of the first groove 2201 faces the display area 201. The first groove 2201 isolates the functional isolation layer 232 from the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the display area 201, thereby preventing the light-emitting stacked structure 231 located in the display area 201 from being electrically connected to the light-emitting stacked structure 231 located around the hole area 202.

[0082] For example, the first groove 2201 may surround the hole area 202 .

[0083] In the second example, Figure 5 As shown, the edge of the bottom isolation layer 221 toward the hole region 202 protrudes relative to the edge of the first insulating layer 2221 , and the edge of the second insulating layer 2222 toward the hole region 202 protrudes relative to the edge of the first insulating layer 2221 .

[0084] Illustratively, the distance between the first insulating layer 2221 and the hole area 202 is greater than the distance between the bottom isolation layer 221 and the display area 201 , and the distance between the first insulating layer 2221 and the hole area 202 is greater than the distance between the second insulating layer 2222 and the display area 201 .

[0085] In the above example, the edges of the bottom isolation layer 221 and the second insulating layer 2222 facing the hole area 202 protrude relative to the edge of the first insulating layer 2221, so that a second groove 2202 can be formed on the side of the isolation column 22 facing the hole area 202. The opening of the second groove 2202 faces the hole area 202. The second groove 2202 can isolate the functional isolation layer 232 from the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the hole area 202, thereby preventing the light-emitting stacked structure 231 located in the display area 201 from being electrically connected to the light-emitting stacked structure 231 located around the hole area 202.

[0086] For example, the second groove 2202 may surround the hole area 202 .

[0087] The first and second examples can be applied in combination, for example Figure 5 As shown, the edge of the bottom isolation layer 221 facing the display area 201 protrudes relative to the edge of the first insulating layer 2221, and the edge of the second insulating layer 2222 facing the display area 201 protrudes relative to the edge of the first insulating layer 2221. Furthermore, the edge of the bottom isolation layer 221 facing the aperture area 202 protrudes relative to the edge of the first insulating layer 2221, and the edge of the second insulating layer 2222 facing the aperture area 202 protrudes relative to the edge of the first insulating layer 2221. Thus, the isolation column 22 can further enhance the isolation effect on the light-emitting stacked structure 231.

[0088] Either the first example or the second example may be selected and applied.

[0089] For example, Figure 6 As shown, in combination with the first example, the edge of the second insulating layer 2222 facing the hole area 202 can be aligned or approximately aligned with the edge of the first insulating layer 2221 in the thickness direction of the display substrate. Thus, the first groove 2201 is formed only on the side of the isolation column 22 facing the display area 201, simplifying the side structural design of the isolation column 22 and reducing the difficulty of manufacturing the isolation column 22. The functional isolation layer 232 is not connected to the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the display area 201. The functional isolation layer 232 is connected to the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the hole area 202, which still allows the isolation column 22 to achieve a certain degree of isolation effect on the light-emitting stacked structure 231.

[0090] For example, in conjunction with the second example, the edge of the second insulating layer 2222 facing the display area 201 can be aligned or approximately aligned with the edge of the first insulating layer 2221 in the thickness direction of the display substrate. Thus, the second groove 2202 is formed only on the side of the isolation column 22 facing the hole area 202, simplifying the side structural design of the isolation column 22 and reducing the difficulty of manufacturing the isolation column 22. The functional isolation layer 232 is not connected to the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the hole area 202, but is connected to the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the display area 201. This still allows the isolation column 22 to achieve a certain degree of isolation effect on the light-emitting stacked structure 231.

[0091] In the embodiment of the present disclosure, the edge surface of any one of the bottom isolation layer 221, the first insulating layer 2221, and the second insulating layer 2222 may be a smooth surface or an uneven surface, and may extend along the thickness direction or not completely extend along the thickness direction.

[0092] Illustratively, the edge of any one of the bottom isolation layer 221 , the first insulating layer 2221 , and the second insulating layer 2222 may refer to the edge closest to the display area 201 or the hole area 202 .

[0093] like Figure 5 As shown, taking the second insulating layer 2222 as an example, if the edge of the second insulating layer 2222 can be an uneven surface, the edge of the second insulating layer 2222 can refer to the edge of the second insulating layer 2222 closest to the display area 201 or the hole area 202.

[0094] In some examples, such as Figure 5 As shown, the display substrate 2 may further include an encapsulation layer 24. The encapsulation layer 24 may be located on the side of the functional isolation layer 232 away from the isolation pillars 22, or between two adjacent isolation pillars 22. The encapsulation layer 24 may also be located on the side of the light-emitting stacked structure 231 away from the base substrate 21. The encapsulation layer 24 can encapsulate the isolation pillars 22.

[0095] For example, the encapsulation layer 24 may include an inorganic material. For example, the material of the encapsulation layer 24 may include but is not limited to silicon nitride (SiN x The encapsulation layer 24 may be formed by plasma enhanced chemical vapor deposition (PECVD).

[0096] In some related technologies, the isolation column 22 often includes metal aluminum (Al) to match the manufacturing process of the isolation region 203 with that of the display region 201. For example, in some related technologies, at least part of the structure of the isolation column 22 is formed synchronously with the source and drain layers of the display region 201. However, the inventors have discovered that metal aluminum easily undergoes a substitution reaction with silver ions (Ag+) in the display substrate, causing the side of the isolation column 22 to displace metal silver, resulting in electrical connection between the functional isolation layer 232 on the upper surface of the isolation column 22 and the light-emitting stacked structure 231 at the root. This, in turn, electrically connects the light-emitting stacked structure 231 located in the display region 201 to the light-emitting stacked structure 231 located around the hole region 202, causing the packaging of the hole region 202 to fail.

[0097] Through the above-described embodiment, the insulating properties of the bottom isolation layer 221 made of semiconductor material are utilized to provide the isolation column 22 with insulating properties, thereby separating the light-emitting stacked structure 231 located on the side facing the display area 201 from the light-emitting stacked structure 231 located on the side facing the aperture area 202. Furthermore, the edges of the bottom isolation layer 221 and the second insulating layer 2222 facing the display area 201 protrude relative to the edge of the first insulating layer 2221, forming a first groove 2201. And / or, the edges of the bottom isolation layer 221 and the second insulating layer 2222 facing the aperture area 202 protrude relative to the edge of the first insulating layer 2221, forming a second groove 2202. The first groove 2201 and / or the second groove 2202 located on the side of the isolation column 22 can enhance the isolation effect of the isolation column 22 on the light-emitting stacked structure 231, effectively preventing the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the aperture area 202 from being energized.

[0098] In the disclosed embodiment, it is avoided that the light-emitting stacked structure 231 on one side of the hole area 202 is energized, so that it is possible to reduce or avoid the side light-emitting stacked structure 231 being energized to attract water vapor and potassium ions (K+) from the hole area 202 into the isolation area 203. Wherein, potassium ions are components commonly contained in film layers such as the polarizer (POL) 2007 or ultra-thin glass (UTG) of the display substrate 2. If water vapor and potassium ions enter the charged isolation area 203 from the hole area 202, they tend to gather at the isolation column 22. Under the energized condition, water vapor will be electrolyzed to produce hydroxide (OH-), and hydroxide and potassium ions will form a strong alkaline environment, corroding the encapsulation layer 24 for covering the isolation column 22. The encapsulation layer 24 is corroded and expanded to produce holes, resulting in encapsulation failure. After the encapsulation failure around the hole area, water vapor and oxygen easily enter the display area 201, affecting the normal display of the display area 201. For example, water vapor and oxygen may cause abnormalities in the gate driver shift register (GDSH) of the pixel driving circuit of the display substrate 2, resulting in partial or overall brightness unevenness, stripes, flickering, black screen and other display function abnormalities in the display area 201.

[0099] Therefore, in the embodiment of the present disclosure, by preventing the light-emitting stacked structure 231 located on the side of the isolation column 22 facing the hole area 202 from being energized, the packaging effect of the hole area 202 can be effectively improved, and the display abnormality of the display area 201 caused by the poor packaging effect of the hole area 202 can be improved or solved, thereby ensuring the display quality of the display substrate 2.

[0100] In the embodiment of the present disclosure, the isolation pillars 22 around the hole area 202 can adopt a variety of different structures. For example, Figure 4As shown, the isolation pillars 22 can be used in conjunction with isolation pillars of other different structures to enhance the encapsulation effect of the hole region 202 in multiple ways. For example, the isolation pillars with other structures can include a titanium-aluminum-titanium metal structure formed simultaneously with the source and drain metal layers. The isolation pillars with other structures can also include a film layer formed by chemical vapor deposition. For example, the film layer can include polyparaxylene (PVX).

[0101] In the embodiment of the present disclosure, the isolation columns 22 around the hole area 202 can all adopt the same structure. There is no need to use isolation columns with a titanium-aluminum-titanium metal structure formed synchronously with the source and drain metal layers, and there is no need to use isolation columns formed using a PVX process, thereby reducing the production process of the display substrate 2 and reducing the mask design of related processes, thereby improving the production efficiency of the display substrate 2.

[0102] In some examples, such as Figure 4 As shown, the display substrate 2 includes a first protective substrate 2001 , a buffer layer 2002 , a first inkjet printed layer 2003 , a second inkjet printed layer 2004 , a touch insulating layer 2005 , a touch layer 2006 , a polarizing layer 2007 , an optical adhesive layer 2008 , a second protective substrate 2009 , and a support layer 2010 .

[0103] Illustratively, the first protective substrate 2001 is located on a side of the base substrate 21 away from the isolation pillars 22. The first protective substrate 2001 can protect the back surface of the display substrate 2. For example, the first protective substrate 2001 can include, but is not limited to, glass, PI, PET, and other materials.

[0104] Exemplarily, the buffer layer 2002 is located on a side of the base substrate 21 away from the first protective substrate 2001, and the buffer layer 2002 may be located between the base substrate 21 and the isolation pillar. For example, the material of the buffer layer 2002 may include, but is not limited to, aluminum oxide (Al2O3), polyparaxylene, silicon nitride, and silicon oxide (SiO2).

[0105] For example, at least a portion of the buffer layer 2002 may be raised relative to other portions of the structure, with the raised direction being away from the base substrate 21. This portion of the structure may be used as a portion of the isolation column 22 to increase the height of the isolation column 22.

[0106] For example, the first inkjet-printed layer 2003 can be located on a side of at least a portion of the light-emitting stacked structure 231 that is away from the base substrate 21. The first inkjet-printed layer 2003 can also be located between at least a portion of the encapsulation layer 24 and the light-emitting stacked structure 231. The first inkjet-printed layer 2003 can be used to provide light shielding and planarization.

[0107] For example, the second inkjet printed layer 2004 may be located on a side of the encapsulation layer 24 away from the isolation pillars 22. The second inkjet printed layer 2004 may be used to provide light shielding and planarization.

[0108] Illustratively, the touch insulating layer 2005 is located on a side of the second inkjet printed layer 2004 away from the encapsulation layer 24, and the touch layer 2006 is located on a side of the touch insulating layer 2005 away from the second inkjet printed layer 2004. The touch layer 2006 can be used to implement the touch function of the display substrate 2.

[0109] Illustratively, the polarizing layer 2007 is located on a side of the touch layer 2006 away from the touch insulating layer 2005 . The polarizing layer 2007 can optimize the display effect of the display substrate 2 by controlling the polarization direction of light.

[0110] Illustratively, the optical adhesive layer 2008 is located on the side of the polarizing layer 2007 away from the touch layer 2006, and the second protective substrate 2009 is located on the side of the optical adhesive layer 2008 away from the polarizing layer 2007. The second protective substrate 2009 can protect the front surface of the display substrate 2. For example, the material of the second protective substrate 2009 can be flexible or rigid. For example, the material of the second protective substrate 2009 can be the same as that of the first protective substrate 2001.

[0111] Illustratively, the support layer 2010 is located on a side of the first protective substrate 2001 away from the base substrate 21 . The first protective substrate 2001 can provide additional support and protection for the display substrate 2 , and can also be used for electrical conduction and heat dissipation.

[0112] In some embodiments, as Figure 6 As shown, in each isolation column 22 , the bottom isolation layer 221 includes a first bottom isolation portion 2211 , a second bottom isolation portion 2212 and a third bottom isolation portion 2213 .

[0113] In each isolation column 22 , the first bottom isolation portion 2211 is located on a side of the second bottom isolation portion 2212 close to the display area 201 .

[0114] The second bottom isolation portion 2212 is connected to the first bottom isolation portion 2211 . The second bottom isolation portion 2212 is located between the first bottom isolation portion 2211 and the third bottom isolation portion 2213 .

[0115] The third bottom isolation portion 2213 is connected to the second bottom isolation portion 2212 . The third bottom isolation portion 2213 is located on a side of the second bottom isolation portion 2212 close to the hole region 202 .

[0116] The first bottom isolation portion 2211 and the third bottom isolation portion 2213 include doped semiconductor materials. The second bottom isolation portion 2212 may include doped semiconductor materials, or may be undoped semiconductor materials.

[0117] The doping concentrations of the first floor isolation portion 2211 and the third floor isolation portion 2213 are greater than the doping concentration of the second floor isolation portion 2212 .

[0118] In some examples, the first bottom isolation portion 2211 and the third bottom isolation portion 2213 can be doped with a P-type semiconductor material. For example, the material of the bottom isolation layer 221 includes silicon. By doping the region of the bottom isolation layer 221 facing the display area 201 and the aperture area 202 with an impurity element having fewer valence electrons than silicon atoms, such as boron or aluminum, excess "holes" are generated, thereby enabling the material to accept electrons, thereby forming the first bottom isolation portion 2211 and the third bottom isolation portion 2213.

[0119] For example, the doping concentration of the second bottom isolation portion 2212 can be zero. The doping concentration of the second bottom isolation portion 2212 can also be close to zero, or lightly doped, so that the second bottom isolation portion 2212 has insulating properties, thereby ensuring the insulation of the isolation column 22.

[0120] In some embodiments, as Figure 6 As shown, the edge of the second bottom isolation portion 2212 is aligned or substantially aligned with the edge of the first metal layer 2231 in the thickness direction of the display substrate 2. Therefore, during the manufacturing process of the display substrate 2, the first metal layer 2231 can be used to shield a portion of the structure of the bottom isolation layer 221, so that the second bottom isolation portion 2212 is undoped or lightly doped. Furthermore, the protrusion of the first bottom isolation portion 2211 and the third bottom isolation portion 2213 has little impact on the insulation properties of the isolation column 22, and can also be used to form the first groove 2201 or the second groove 2202.

[0121] In some embodiments, as Figure 6 As shown, the edge of the bottom isolation layer 221 protrudes relative to the edge of the second insulation layer 2222 away from the surface of the first insulation layer 2221 .

[0122] Illustratively, the orthographic projection of the second insulating layer 2222 on the base substrate 21 is located within the orthographic projection range of the bottom isolation layer 221 on the base substrate 21 .

[0123] In the embodiment of the present disclosure, the bottom isolation layer 221 is wider, which facilitates the layer-by-layer fabrication of the isolation columns 22 and improves the fabrication yield of the isolation columns 22 and even the display substrate 2 .

[0124] In some embodiments, as Figure 6As shown, the second insulating layer 2222 includes a first insulating portion 22221 and a second insulating portion 22222 .

[0125] Exemplarily, the first insulating portion 22221 and the second insulating portion 22222 are made of the same material. For example, the first insulating portion 22221 and the second insulating portion 22222 can be an integral structure, and can be formed simultaneously.

[0126] In some examples, such as Figure 6 As shown, the second insulating portion 22222 covers the side surface of the first metal layer 2231 , and the first insulating portion 22221 is located on a side of the second insulating portion 22222 away from the first insulating layer 2221 .

[0127] Illustratively, the second insulating portion 22222 may further cover a side of the first metal layer 2231 away from the first insulating layer 2221 .

[0128] At least one side edge of the first insulating portion 22221 protrudes relative to edges of the first insulating layer 2221 and the second insulating portion 22222 .

[0129] In some examples, the first insulating portion 22221 protrudes toward an edge of the display area 201 relative to edges of the first insulating layer 2221 and the second insulating portion 22222 .

[0130] In some other examples, the first insulating portion 22221 protrudes toward an edge of the hole region 202 relative to edges of the first insulating layer 2221 and the second insulating portion 22222 .

[0131] Thus, a first groove 2201 or a second groove 2202 may be formed through the lower surface of the first insulating portion 22221 , the side surface of the second insulating portion 22222 , and the upper surface of the bottom isolation layer 221 .

[0132] In the embodiment of the present disclosure, the second insulating portion 22222 covers the side surface of the first metal layer 2231. The side surface of the second insulating portion 22222 facing the display area 201 can be used as the bottom of the first groove 2201, or the side surface of the second insulating portion 22222 facing the display area 201 can be used as the bottom of the second groove 2202. Furthermore, the first insulating layer 2221 and the second insulating layer 2222 can be formed simultaneously with the gate dielectric layer of the display area 201. The formation of the first insulating portion 22221 and the second insulating portion 22222 can also be synchronized with the etching process of the gate dielectric layer of the display area 201, thereby reducing the difficulty of manufacturing the isolation column 22 and even the display substrate 2.

[0133] In some embodiments, as Figure 7As shown, along the thickness direction of the display substrate 2 and away from the base substrate 21, the isolation column 22 includes a bottom isolation layer 221, a first insulating layer 2221, a first metal layer 2231, a second insulating layer 2222, a second metal layer 2232 and a third insulating layer 2223 stacked in sequence.

[0134] The second metal layer 2232 is located on a side of the second insulating layer 2222 away from the first metal layer 2231 , and the third insulating layer 2223 is located on a side of the second metal layer 2232 away from the second insulating layer 2222 .

[0135] Therefore, by increasing the stacked structure of the isolation columns 22 , the height of the isolation columns 22 can be increased, thereby enhancing the isolation effect of the isolation columns 22 on the light-emitting stacked structure 231 .

[0136] In some embodiments, as Figure 7 As shown, at least one side edge of the second metal layer 2232 and / or the third insulating layer 2223 protrudes relative to the edge of the first insulating layer 2221 .

[0137] Illustratively, the orthographic projection of the first insulating layer 2221 on the base substrate 21 is located within the orthographic projection range of the second metal layer 2232 and / or the third insulating layer 2223 on the base substrate 21 .

[0138] For example, at least one side edge of the second metal layer 2232 and / or the third insulating layer 2223 is aligned or substantially aligned with an edge of the second insulating layer 2222 in the thickness direction of the display substrate 2 .

[0139] For another example, at least one side edge of the second metal layer 2232 and / or the third insulating layer 2223 and the edge of the second insulating layer 2222 are located on the same surface, and the surface may extend along the thickness direction of the base substrate 21. For example, the surface may be an annular surface.

[0140] Therefore, after the isolation column 22 is increased, the second metal layer 2232 and / or the third insulating layer 2223 maintain a larger width synchronously with the second insulating layer 2222, maintaining the shape of the first groove 2201 or the second groove 2202, thereby ensuring the isolation effect of the isolation column 22 on the light-emitting stacked structure 231.

[0141] In some embodiments, as Figure 7 As shown, at least one side edge of the second metal layer 2232 protrudes relative to the edge of the third insulating layer 2223 .

[0142] Illustratively, the orthographic projection of the third insulating layer 2223 on the base substrate 21 is located within the orthographic projection range of the second metal layer 2232 on the base substrate 21 .

[0143] Thus, during the manufacturing process of the display substrate 2, the functional isolation layer 232 can be deposited on the upper surface of the second metal layer 2232 and the third insulating layer 2223 of the isolation column 22, and deposited as little as possible on the side of the isolation column 22, thereby reducing or avoiding the connection between the functional isolation layer 232 and the light-emitting stacked structure 231.

[0144] In some examples, such as Figure 7 As shown, the functional isolation layer 232 is connected to at least one side surface of the third insulating layer 2223. The functional isolation layer 232 is also connected to a surface of the second metal layer 2232 that protrudes from the third insulating layer 2223 and is away from the second insulating layer 2222. This further reduces or prevents the functional isolation layer 232 from being deposited on the side surfaces of the isolation pillars 22, thereby enhancing the isolation effect between the functional isolation layer 232 and the light-emitting stacked structure 231.

[0145] In some examples, such as Figure 7 As shown, the edge of the third insulating layer 2223 and the edge of the first insulating layer 2221 are aligned or approximately aligned in the thickness direction of the display substrate 2. For example, the orthographic projection of the third insulating layer 2223 on the base substrate 21 is aligned with the orthographic projection of the first insulating layer 2221 on the base substrate 21.

[0146] This not only helps the structure of the isolation column 22 to increase in the thickness direction of the base substrate 21, thereby improving the structural stability of the isolation column 22, but also facilitates the reuse of masks used to form the third insulating layer 2223 and the first insulating layer 2221, thereby reducing the production cost of the display substrate 2.

[0147] In some examples, such as Figure 8 As shown, one side edge of the third insulating layer 2223 facing the hole region 202 is aligned or substantially aligned with the edge of the second metal layer 2232 in the thickness direction of the display substrate 2 .

[0148] Illustratively, an edge of the third insulating layer 2223 facing the hole region 202 is aligned or substantially aligned with an edge of the first insulating layer 2221 in the thickness direction of the display substrate 2 .

[0149] Illustratively, an edge of the third insulating layer 2223 facing the hole region 202 is aligned or substantially aligned with an edge of the second insulating layer 2222 in the thickness direction of the display substrate 2 .

[0150] Thus, the first groove 2201 is formed only on the side of the isolation column 22 facing the display area 201, simplifying the side structural design of the isolation column 22 and reducing the difficulty of manufacturing the isolation column 22. The functional isolation layer 232 is not connected to the light-emitting stacked structure 231 on the side of the isolation column 22 facing the display area 201, but is connected to the light-emitting stacked structure 231 on the side of the isolation column 22 facing the aperture area 202. This still allows the isolation column 22 to achieve a certain degree of isolation effect on the light-emitting stacked structure 231.

[0151] In some examples, such as Figure 8 As shown, one edge of the third insulating layer 2223 facing the display area 201 is aligned or substantially aligned with the edge of the second metal layer 2232 in the thickness direction of the display substrate 2 .

[0152] Illustratively, an edge of the third insulating layer 2223 facing the display area 201 is aligned or substantially aligned with an edge of the first insulating layer 2221 in the thickness direction of the display substrate 2 .

[0153] Illustratively, an edge of the third insulating layer 2223 facing the display area 201 is aligned or substantially aligned with an edge of the second insulating layer 2222 in the thickness direction of the display substrate 2 .

[0154] Thus, the second groove 2202 is formed only on the side of the isolation column 22 facing the aperture region 202, which reduces the difficulty of manufacturing the isolation column 22. The functional isolation layer 232 is connected to the light-emitting stacked structure 231 on the side of the isolation column 22 facing the display region 201, but is not connected to the light-emitting stacked structure 231 on the side of the isolation column 22 facing the aperture region 202. However, the isolation column 22 still achieves a certain degree of isolation effect on the light-emitting stacked structure 231.

[0155] In some embodiments, the sum of the thicknesses of the first insulating layer 2221 and the second insulating layer 2222 is greater than the thickness of the light-emitting stacked structure 231 .

[0156] In some other embodiments, the sum of the thicknesses of the first insulating layer 2221 and the second insulating layer 2222 is greater than the thickness of the function isolation layer 232 .

[0157] Exemplarily, the thickness of the light-emitting stacked structure 231 is equal to or approximately equal to the thickness of the functional isolation layer 232 .

[0158] In some examples, the sum of the thicknesses of the first insulating layer 2221 and the second insulating layer 2222 ranges from 0.2 μm to 0.6 μm, and the thickness of the light-emitting stacked structure 231 ranges from 0.05 μm to 0.3 μm.

[0159] For example, the sum of the thicknesses of the first insulating layer 2221 and the second insulating layer 2222 includes, but is not limited to, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm, and the thickness of the light-emitting stacked structure 231 includes, but is not limited to, 0.05 μm, 0.1 μm, 0.15 μm, 0.2 μm, and 0.3 μm.

[0160] Thus, the manufacturing process of the light-emitting stacked structure 231 can be combined. During the process of forming the light-emitting stacked structure 231 and the functional isolation layer 232, the light-emitting stacked structure 231 is deposited on one side of the base substrate 21, the light-emitting stacked structure 231 is deposited on opposite sides of the isolation column 22, and the functional isolation layer 232 is deposited on the isolation column 22. Furthermore, by utilizing the height of the first insulating layer 2221 and the second insulating layer 2222 relative to the base substrate 21, which is greater than the thickness of the light-emitting stacked structure 231, the light-emitting stacked structure 231 and the functional isolation layer 232 can be effectively disconnected, ensuring that the isolation column 22 effectively isolates the light-emitting stacked structure 231.

[0161] In some embodiments, a material of any one of the first insulating layer 2221 , the second insulating layer 2222 , and the third insulating layer 2223 includes an inorganic material.

[0162] Exemplarily, the material of the first insulating layer 2221 may include, but is not limited to, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), and the like.

[0163] For example, the material of the second insulating layer 2222 or the third insulating layer 2223 may be the same as that of the first insulating layer 2221 .

[0164] In this way, the manufacturing process of any one of the first insulating layer 2221, the second insulating layer 2222 and the third insulating layer 2223 can be matched with the manufacturing process of the gate dielectric layer or the interlayer dielectric layer (ILD) of the display area 201, thereby reducing the manufacturing difficulty of the display substrate 2 and reducing the manufacturing cost.

[0165] In some embodiments, the isolation column 22 further includes a fourth insulating layer 2224 . The fourth insulating layer 2224 is located on a side of the second insulating layer 2222 away from the first metal layer 2231 .

[0166] Therefore, by further increasing the stacked structure of the isolation columns 22 , the height of the isolation columns 22 is increased, and the isolation effect of the isolation columns 22 on the light-emitting stacked structure 231 is enhanced.

[0167] In some examples, such as Figure 9As shown, along the thickness direction of the display substrate 2 and away from the base substrate 21, the isolation column 22 includes a bottom isolation layer 221, a first insulating layer 2221, a first metal layer 2231, a second insulating layer 2222, a second metal layer 2232, a third insulating layer 2223 and a fourth insulating layer 2224 stacked in sequence.

[0168] The fourth insulating layer 2224 is located on a side of the second insulating layer 2222 away from the first metal layer 2231 . The material of the fourth insulating layer 2224 includes an organic material.

[0169] For example, the material of the fourth insulating layer 2224 can be the same as the material of the planar layer of the display area 201 of the display substrate 2. For example, during the manufacturing process of the display substrate 2, the fourth insulating layer 2224 can be formed simultaneously with the planar layer of the display area 201 of the display substrate 2.

[0170] For example, the material of the fourth insulating layer 2224 includes, but is not limited to, polyimide (PI), benzocyclobutene (BCB), and acrylic.

[0171] For example, the material of the fourth insulating layer 2224 can be the same as the material of the pixel definition layer of the display area 201 of the display substrate 2. For example, during the manufacturing process of the display substrate 2, the fourth insulating layer 2224 can be formed simultaneously with the pixel definition layer of the display area 201 of the display substrate 2.

[0172] For example, the material of the fourth insulating layer 2224 includes, but is not limited to, photosensitive polyimide (PSPI), photoresist (PR), or other mixed materials.

[0173] Therefore, the fourth insulating layer 2224 can match the structure and manufacturing process of the display area 201 , which helps to simplify the manufacturing process of the isolation column 22 and reduce the manufacturing difficulty of the isolation column 22 and even the display substrate 2 .

[0174] In some embodiments, the isolation column 22 further includes an electrostatic shielding layer. The electrostatic shielding layer is located between the bottom isolation layer 221 and the base substrate 21 , and the edge of the electrostatic shielding layer does not exceed the edge of the bottom isolation layer 221 .

[0175] Therefore, the electrostatic shielding layer can be used to further increase the height of the isolation column 22, and the electrostatic shielding layer can also shield the light-emitting stacked structure on both sides of the isolation column 22 from static electricity, thereby reducing the possibility of the light-emitting stacked structure 231 on the side facing the hole area 202 being charged.

[0176] In some embodiments, as Figure 10As shown, the display substrate 2 further includes a pixel circuit 205 disposed in the display area 201 . The pixel circuit 205 includes an active layer pattern 251 , a first gate metal layer 252 , and a first gate dielectric layer 253 .

[0177] like Figure 10 As shown, the active layer pattern 251 is located on one side of the base substrate 21 , the first gate dielectric layer 253 is located on the side of the active layer 251 away from the base substrate 21 , and the first gate metal layer 252 is located on the side of the first gate dielectric layer 253 away from the active layer pattern 251 .

[0178] Exemplarily, the pixel circuit 205 includes a thin film transistor, and the active layer pattern of the thin film transistor in the pixel circuit 205 includes a channel region and a source region and a drain region located on both sides of the channel portion, and the channel region and the orthographic projection of the first gate metal layer 252 on the base substrate 21 overlap.

[0179] For example, at least a portion of the first gate metal layer 252 may serve as a gate of a thin film transistor in the pixel circuit 205 , and at least a portion of the first gate metal layer 252 may also serve as a gate line in the pixel circuit 205 .

[0180] For example, Figure 4 As shown, the first gate metal layer 252 and the first gate dielectric layer 253 are also located in the isolation region 203 .

[0181] In some examples, the bottom isolation layer 221 of the isolation column 22 is made of the same material as the active layer pattern 251 , the first metal layer 2231 of the isolation column 22 is made of the same material as the first gate metal layer 252 , and the first insulating layer 2221 of the isolation column 22 is made of the same material as the first gate dielectric layer 253 .

[0182] Illustratively, during the manufacturing process of the display substrate 2, the bottom isolation layer 221 of the isolation column 22 and the active layer pattern 251 can be formed simultaneously, the first metal layer 2231 of the isolation column 22 and the first gate metal layer 252 can be formed simultaneously, and the first insulating layer 2221 of the isolation column 22 and the first gate dielectric layer 253 can be formed simultaneously.

[0183] Thus, the manufacturing processes of at least part of the pixel circuit 205 in the display area 201 and at least part of the isolation column 22 in the isolation area 203 are performed synchronously, which can effectively reduce the manufacturing process steps of the display substrate 2 and improve the manufacturing efficiency of the display substrate 2.

[0184] In some examples, such as Figure 10 As shown, the pixel circuit 205 further includes a second gate dielectric layer 255 . The second gate dielectric layer 255 is located on a side of the first gate metal layer 252 away from the first gate dielectric layer 253 .

[0185] For example, Figure 4 As shown, the second gate dielectric layer 255 is also located in the isolation region 203 .

[0186] For example, the second insulating layer 2222 of the isolation column 22 is made of the same material as the second gate dielectric layer 255. For example, the second insulating layer 2222 of the isolation column 22 and the second gate dielectric layer 255 can be formed simultaneously.

[0187] In some embodiments, the pixel circuit 205 further includes a storage capacitor and a second gate metal layer 254 .

[0188] The storage capacitor includes two plates. Exemplarily, at least a portion of the first gate metal layer 252 serves as one plate of the storage capacitor, and at least a portion of the second gate metal layer 254 serves as the other plate of the storage capacitor.

[0189] For example, Figure 4 As shown, the second gate metal layer 254 is also located in the isolation region 203 .

[0190] For convenience, Figure 4 The first gate metal layer 252 and the second gate metal layer 254 are not distinguished from each other, and do not limit the embodiment of the display substrate 2. For example, the first gate metal layer 252 and the second gate metal layer 254 can be arranged in layers.

[0191] The second gate metal layer 254 is located on a side of the first gate metal layer 252 away from the base substrate 21 . The second metal layer 2232 of the isolation column 22 and the second gate metal layer 254 are made of the same material.

[0192] For example, the second metal layer 2232 of the isolation pillar 22 and the second gate metal layer 254 may be formed simultaneously.

[0193] In some examples, the pixel circuit 205 also includes an interlayer dielectric layer 256, which is located on the side of the second gate metal layer 254 away from the second gate dielectric layer 255. The interlayer dielectric layer 256 can also be arranged on the side wall of the overall structure of the second gate metal layer 254 and the second gate dielectric layer 255.

[0194] For example, Figure 4 As shown, the interlayer dielectric layer 256 is also located in the isolation region 203 .

[0195] For example, the third insulating layer 2223 of the isolation column 22 is made of the same material as the interlayer dielectric layer 256. For example, the third insulating layer 2223 of the isolation column 22 and the interlayer dielectric layer 256 can be formed simultaneously.

[0196] In some other examples, the pixel circuit 205 further includes a third gate dielectric layer, which is located on a side of the second gate metal layer 254 away from the second gate dielectric layer 255. Exemplarily, the third insulating layer 2223 of the isolation column 22 is made of the same material as the third gate dielectric layer. For example, the third insulating layer 2223 of the isolation column 22 and the third gate dielectric layer can be formed simultaneously.

[0197] In some other embodiments, the pixel circuit 205 further includes a second gate metal layer 254 and a third gate metal layer disposed in the display area 201 .

[0198] The second gate metal layer 254 is located on a side of the first gate metal layer 252 away from the substrate 21 . The third gate metal layer is located on a side of the second gate metal layer 254 away from the first gate metal layer 252 . The second metal layer 2232 of the isolation column 22 is made of the same material as the third gate metal layer.

[0199] Therefore, the material of the second metal layer 2232 of the isolation column 22 can be set according to the structure of the pixel circuit 205 in the display area 201 of the display substrate 2, so as to flexibly adjust the manufacturing process of each stacked structure of the isolation column 22 and improve the manufacturing yield of the isolation column 22.

[0200] In some embodiments, the display substrate 2 further includes a light shielding layer that overlaps with the active layer pattern 251 of the thin film transistor disposed in the display area 201. Thus, the light shielding layer can reduce or prevent the channel of the thin film transistor in the pixel circuit 205 from being affected by light and causing an increase in leakage current.

[0201] Exemplarily, the electrostatic shielding layer and the light shielding layer of the isolation column 22 are made of the same material.

[0202] In some embodiments, as Figure 10 As shown, the display substrate 2 further includes a planar layer 257 and a pixel definition layer 258 .

[0203] The planar layer 257 is located on a side of the interlayer dielectric layer 256 away from the second gate metal layer 254 , and may also be located on a side of the second gate dielectric layer 255 away from the first gate dielectric layer 253 .

[0204] The pixel definition layer 258 is located on the side of the planar layer 257 away from the interlayer dielectric layer 256 . The pixel definition layer 258 can be used to separate and protect pixels through a physical structure to ensure the stability and reliability of the display effect.

[0205] For example, Figure 4 As shown, the planarization layer 257 is also located in the isolation region 203 .

[0206] For example, the material of the fourth insulating layer 2224 of the isolation column 22 may be the same as the material of the planarization layer 257 and / or the pixel definition layer 258 .

[0207] In some embodiments, as Figure 10 As shown, the pixel circuit 205 further includes a source / drain metal layer 259 . At least a portion of the source / drain metal layer 259 may be used as a source or drain of the pixel circuit 205 , and the source or drain of the pixel circuit 205 may be connected to the first gate metal layer 252 .

[0208] The embodiment of the present disclosure further provides a method for manufacturing a display substrate 2. The display substrate 2 includes a display area 201, a hole area 202, and an isolation area 203. The isolation area 203 separates the display area 201 from the hole area 202.

[0209] like Figure 11 As shown, the manufacturing method of the display substrate 2 specifically includes:

[0210] In step S51 , a semiconductor layer is formed on the base substrate 21 . The semiconductor layer includes an active layer pattern 251 of the thin film transistor located in the display area 201 and a bottom isolation layer 221 located in the isolation area 203 .

[0211] In step S52 , a first gate dielectric layer 253 is formed on a side of the active layer pattern 251 away from the base substrate 21 , and a first insulating layer 2221 is formed on a side of the bottom isolation layer 221 away from the base substrate 21 .

[0212] In step S53, a first gate metal layer 252 is formed on the side of the first gate dielectric layer 253 away from the active layer pattern 251, and a first metal layer 2231 is formed on the side of the first insulating layer 2221 away from the bottom isolation layer 221. The first gate metal layer 252 comprises a gate of the thin film transistor.

[0213] In step S54 , a second gate dielectric layer is formed on a side of the first gate metal layer 252 away from the first gate dielectric layer 253 , and a second insulating layer 2222 is formed on a side of the first metal layer 2231 away from the first insulating layer 2221 .

[0214] In some examples, such as Figure 11 As shown, after the above step S54, the method for manufacturing the display substrate 2 further includes:

[0215] In step S55, an opening is etched in the second gate dielectric layer 255 along the thickness direction of the display substrate 2, and the side of the first insulating layer 2221 facing the display area 201 is etched so that the edges of the bottom isolation layer 221 and the second insulating layer 2222 facing the display area 201 protrude relative to the edge of the first insulating layer 2221.

[0216] Alternatively, in step S55, an opening is etched in the second gate dielectric layer 255 along the thickness direction of the display substrate 2, and the side of the first insulating layer 2221 facing the hole area 202 is etched, so that the edges of the bottom isolation layer 221 and the second insulating layer 2222 facing the hole area 202 protrude relative to the edge of the first insulating layer 2221.

[0217] For example, the openings in the second gate dielectric layer 255 along the thickness direction of the display substrate 2 can be used to implement cross-layer routing of source / drain metal layers or gate metal layers.

[0218] In some examples, in step S55 , while etching the second gate dielectric layer 255 , the side of the second insulating layer 2222 facing the display area 201 and / or the hole area 202 may also be etched to form a first insulating portion 22221 and a second insulating portion 22222 .

[0219] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a display area, a hole area, and an isolation area, wherein the isolation area separates the display area and the hole area; the display substrate comprises: substrate; An isolation column, located on one side of the base substrate, the isolation column is located in the isolation area, and the isolation column separates the display area and the hole area; Along the thickness direction of the display substrate and in a direction away from the base substrate, the isolation column includes a bottom isolation layer, a first insulating layer, a first metal layer and a second insulating layer stacked in sequence; The second insulating layer covers the side surfaces of the first metal layer; the bottom isolation layer and the second insulating layer protrude relative to the edge of the first insulating layer toward the edge of the display area, and / or the bottom isolation layer and the second insulating layer protrude relative to the edge of the first insulating layer toward the edge of the hole area; the bottom isolation layer includes a semiconductor material.

2. The display substrate according to claim 1, wherein The bottom isolation layer includes a first bottom isolation portion, a second bottom isolation portion and a third bottom isolation portion; The first bottom isolation portion is located on a side of the second bottom isolation portion close to the display area; The second bottom isolation portion is connected to the first bottom isolation portion, and the second bottom isolation portion is located between the first bottom isolation portion and the third bottom isolation portion; The third bottom isolation portion is connected to the second bottom isolation portion, and the third bottom isolation portion is located on a side of the second bottom isolation portion close to the hole area; The first floor isolation portion and the third floor isolation portion include doped semiconductor materials, and the doping concentrations of the first floor isolation portion and the third floor isolation portion are greater than the doping concentration of the second floor isolation portion.

3. The display substrate according to claim 2, wherein: An edge of the second floor spacer is aligned or substantially aligned with an edge of the first metal layer in a thickness direction of the display substrate.

4. The display substrate according to any one of claims 1 to 3, wherein: An edge of the bottom isolation layer protrudes relative to an edge of the second insulating layer away from a surface of the first insulating layer.

5. The display substrate according to any one of claims 1 to 4, wherein: The second insulating layer includes a first insulating portion and a second insulating portion; The second insulating portion covers a side surface of the first metal layer, and the first insulating portion is located on a side of the second insulating portion away from the first insulating layer; At least one side edge of the first insulating portion protrudes relative to edges of the first insulating layer and the second insulating portion.

6. The display substrate according to any one of claims 1 to 5, further comprising: a light-emitting stacked structure, located on one side of the base substrate, and located on a side of the isolation column facing the display area and the hole area; a functional isolation layer, located on a side of the isolation column away from the base substrate; The material of the functional isolation layer is the same as at least part of the material of the light-emitting stacked structure; the functional isolation layer is not connected to the light-emitting stacked structure located on the side of the isolation column facing the display area, and / or the functional isolation layer is not connected to the light-emitting stacked structure located on the side of the isolation column facing the hole area.

7. The display substrate according to claim 6, wherein: The isolation column further includes a second metal layer and a third insulating layer; The second metal layer is located on a side of the second insulating layer away from the first metal layer, and the third insulating layer is located on a side of the second metal layer away from the second insulating layer.

8. The display substrate according to claim 7, wherein: At least one side edge of the second metal layer and / or the third insulating layer protrudes relative to an edge of the first insulating layer.

9. The display substrate according to claim 7 or 8, wherein: At least one edge of the second metal layer protrudes relative to an edge of the third insulating layer.

10. The display substrate according to claim 9, wherein: The functional isolation layer is connected to at least one side surface of the third insulating layer, and is connected to a surface of a portion of the second metal layer protruding from the third insulating layer and away from the second insulating layer.

11. The display substrate according to any one of claims 6 to 10, wherein: The sum of the thicknesses of the first insulating layer and the second insulating layer is greater than the thickness of the light-emitting stacked structure and / or greater than the thickness of the functional isolation layer.

12. The display substrate according to any one of claims 7 to 10, wherein: A material of any one of the first insulating layer, the second insulating layer, and the third insulating layer includes an inorganic material.

13. The display substrate according to any one of claims 1 to 12, further comprising a pixel circuit provided in the display area, wherein the pixel circuit comprises an active layer pattern, a first gate metal layer, and a first gate dielectric layer; The bottom isolation layer of the isolation column is made of the same material as the active layer pattern, the first metal layer of the isolation column is made of the same material as the first gate metal layer, and the first insulating layer of the isolation column is made of the same material as the first gate dielectric layer.

14. The display substrate according to claim 13, wherein: The pixel circuit further includes a storage capacitor and a second gate metal layer; At least a portion of the first gate metal layer is used as one plate of the storage capacitor, and at least a portion of the second gate metal layer is used as another plate of the storage capacitor; The second gate metal layer is located on a side of the first gate metal layer away from the base substrate, and the second metal layer of the isolation column is made of the same material as the second gate metal layer.

15. The display substrate according to claim 13, wherein: The pixel circuit further includes a second gate metal layer and a third gate metal layer provided in the display area; The second gate metal layer is located on the side of the first gate metal layer away from the substrate, the third gate metal layer is located on the side of the second gate metal layer away from the first gate metal layer, and the second metal layer of the isolation column is made of the same material as the third gate metal layer.

16. The display substrate according to any one of claims 1 to 15, wherein: The isolation column further includes a fourth insulating layer; The fourth insulating layer is located on a side of the second insulating layer away from the first metal layer, and a material of the fourth insulating layer includes an organic material.

17. The display substrate according to any one of claims 1 to 16, wherein: The isolation column also includes an electrostatic shielding layer; The electrostatic shielding layer is located between the bottom isolation layer and the base substrate, and an edge of the electrostatic shielding layer does not exceed an edge of the bottom isolation layer.

18. The display substrate according to claim 17, further comprising a light shielding layer, wherein the light shielding layer overlaps with an active layer pattern of the thin film transistor disposed in the display area; The electrostatic shielding layer and the light shielding layer are made of the same material.

19. A method for manufacturing a display substrate, wherein: The display substrate includes a display area, a hole area, and an isolation area, wherein the isolation area separates the display area and the hole area; the method includes: forming a semiconductor layer on the base substrate, wherein the semiconductor layer includes an active layer pattern of the thin film transistor located in the display area and a bottom isolation layer located in the isolation area; forming a first gate dielectric layer on a side of the active layer pattern away from the base substrate, and forming a first insulating layer on a side of the bottom isolation layer away from the base substrate; forming a first gate metal layer on a side of the first gate dielectric layer away from the active layer pattern, and forming a first metal layer on a side of the first insulating layer away from the bottom isolation layer; the first gate metal layer includes a gate electrode of the thin film transistor; A second gate dielectric layer is formed on a side of the first gate metal layer away from the first gate dielectric layer, and a second insulating layer is formed on a side of the first metal layer away from the first insulating layer.

20. The method for manufacturing a display substrate according to claim 19, wherein: After forming a second gate dielectric layer on a side of the first gate metal layer away from the first gate dielectric layer and forming a second insulating layer on a side of the first metal layer away from the first insulating layer, the method further includes: Etching an opening in the second gate dielectric layer along the thickness direction of the display substrate, and etching the side of the first insulating layer facing the display area so that the edges of the bottom isolation layer and the second insulating layer facing the display area protrude relative to the edge of the first insulating layer; and / or, An opening is etched in the second gate dielectric layer along the thickness direction of the display substrate, and the side of the first insulating layer facing the hole area is etched so that the edges of the bottom isolation layer and the second insulating layer facing the hole area protrude relative to the edge of the first insulating layer.

21. A display device comprising: The display substrate according to any one of claims 1 to 18; A driving circuit board is electrically connected to the display substrate.

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