Data driving circuit, display device and display driving method

Abstract

The invention belongs to the field of display, and particularly relates to a data driving circuit, a display device and a display driving method.The data driving circuit comprises a data driving module, a power module, an output control module and a selection module, and the power module comprises a plurality of gamma voltage output ends; the gamma voltage output ends comprise M dark-state voltage output ends and N bright-state voltage output ends, at least one of M and N is larger than 1, the output control module is at least connected with the data driving module and one of the M dark-state voltage output ends and the N bright-state voltage output ends, and the selection module is connected with the output control module and used for controlling the output control module to work. The gamma voltage of the dark state voltage output end and the gamma voltage of the bright state voltage output end are output to the data driving module. When the display panel is driven to display a picture, the selection module distributes different gamma voltages for the normal display area and the abnormal display area, the problem of uneven display can be improved or eliminated, and the display picture quality of the display panel is improved.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a data driving circuit, a display device and a display driving method. Background Art

[0002] Displays include liquid crystal displays (LCDs), electronic paper (e-Paper) displays, and organic light-emitting diode (OLED) displays. Each of these displays includes a display panel, a scan drive circuit, and a data drive circuit.

[0003] When the monitor displays an image, the gate drive circuit provides a scan drive signal to control the drive transistors of all sub-pixels in a row of the display panel to turn on, so that the drive transistor of each sub-pixel in the row receives a data voltage signal from the data line of its respective column. The data voltage signal controls the brightness of the sub-pixel, realizing the display of a row of pixels. Row-by-row scanning can realize the display of a frame of image.

[0004] In the data drive circuit, the data drive module provides data voltages based on a gamma curve determined by dark-state voltage and bright-state voltage. This gamma curve is identical for all sub-pixels in the display. However, during the display panel manufacturing process, achieving high uniformity across sub-pixels in different regions is difficult. This means that even if the data voltages for sub-pixels in different regions are the same, the brightness of the sub-pixels may vary, leading to uneven display (mura). Summary of the Invention

[0005] The purpose of the present application is to provide a data driving circuit, a display device and a display driving method to improve or eliminate the problem of uneven display and enhance the display quality of the display.

[0006] To achieve the above-mentioned object, the present application provides a data driving circuit, including a data driving module for connecting to a display panel, and the data driving circuit further includes:

[0007] A power supply module, comprising a plurality of gamma voltage output terminals, wherein the plurality of gamma voltage output terminals include M dark-state voltage output terminals and N bright-state voltage output terminals, where M and N are both positive integers, and at least one of M and N is greater than 1;

[0008] an output control module, connected to at least the data driving module and one of the M dark-state voltage output terminals and the N bright-state voltage output terminals;

[0009] A selection module is connected to the output control module, and the selection module is used to control the operation of the output control module so that the gamma voltages of one of the dark state voltage output terminals and one of the bright state voltage output terminals are output to the data driving module. The data driving module can provide different data voltages for the display panel according to different dark state voltages and bright state voltages.

[0010] Optionally, M is greater than 1 and N is equal to 1.

[0011] Optionally, the output control module includes M output control units, and each of the dark-state voltage output terminals is connected to the data driving module via one of the output control units.

[0012] Optionally, M is equal to 4, the selection module includes 2 control signal output terminals, each of the output control units includes 2 control signal input terminals, and the control signal input terminal of each output control unit is connected to the control signal output terminal in a one-to-one correspondence.

[0013] Optionally, the four output control units include a first output control unit, a second output control unit, a third output control unit, and a fourth output control unit; the four dark-state voltage output terminals are respectively a first dark-state voltage output terminal, a second dark-state voltage output terminal, a third dark-state voltage output terminal, and a fourth dark-state voltage output terminal; and the two control signal output terminals are respectively a first control signal output terminal and a second control signal output terminal;

[0014] The first output control unit includes a 1-1 transistor, a 1-2 transistor, a 1-3 transistor, a 1-4 transistor, a 1-5 transistor, a 1-6 transistor, a 1-7 transistor, a 1-8 transistor, a 1-9 transistor, a 1-10 transistor, a 1-11 transistor and a 1-12 transistor, wherein the 1-1 transistor, the 1-3 transistor, the 1-4 transistor, the 1-5 transistor, the 1-7 transistor, the 1-8 transistor and the 1-10 transistor are P-type transistors, the 1-2 transistor, the 1-6 transistor, the 1-9 transistor, the 1-11 transistor and the 1-12 transistor are N-type transistors, and the 1-1 transistors are N-type transistors. The control end of the 1-1 transistor and the control end of the 1-2 transistor are both connected to the second control signal output end, the high level signal end, the first end of the 1-1 transistor, the second end of the 1-1 transistor, the A1 node, the first end of the 1-2 transistor, the second end of the 1-2 transistor and the ground end are connected in sequence, the control end of the 1-3 transistor is connected to the second control signal output end, the control end of the 1-4 transistor is connected to the first control signal output end, the high level signal end, the first end of the 1-4 transistor, the second end of the 1-4 transistor, the first end of the 1-3 transistor, the second end of the 1-3 transistor and the 1-9 transistor are connected in sequence. The control ends of the transistors are connected in sequence, the control ends of the 1-5 transistors and the control ends of the 1-6 transistors are both connected to the first control signal output end, the high level signal end, the first ends of the 1-5 transistors, the second ends of the 1-5 transistors, the A2 node, the first ends of the 1-6 transistors, the second ends of the 1-6 transistors and the ground end are connected in sequence, the control ends of the 1-7 transistors are connected to the A2 node, the control ends of the 1-8 transistors are connected to the A1 node, the high level signal end, the first ends of the 1-7 transistors, the second ends of the 1-7 transistors, the first ends of the 1-8 transistors, the second ends of the 1-8 transistors, the A A3 node, the first end of the 1-9 transistor, the second end of the 1-9 transistor, and the ground end are connected in sequence, the control end of the 1-10 transistor and the control end of the 1-11 transistor are both connected to the A3 node, the high-level signal end, the first end of the 1-10 transistor, the second end of the 1-10 transistor, the A4 node, the first end of the 1-11 transistor, the second end of the 1-11 transistor, and the ground end are connected in sequence, the control end of the 1-12 transistor is connected to the A4 node, the first end of the 1-12 transistor is connected to the first dark-state voltage output end, and the second end of the 1-12 transistor is connected to the data driving module;

[0015] The second output control unit includes a 2-1 transistor, a 2-2 transistor, a 2-3 transistor, a 2-4 transistor, a 2-5 transistor, a 2-6 transistor, a 2-7 transistor, a 2-8 transistor, a 2-9 transistor, a 2-10 transistor, a 2-11 transistor and a 2-12 transistor, wherein the 2-1 transistor, the 2-3 transistor, the 2-4 transistor, the 2-5 transistor, the 2-7 transistor, the 2-8 transistor and the 2-10 transistor are P-type transistors, the 2-2 transistor, the 2-6 transistor, the 2-9 transistor, the 2-11 transistor and the 2-12 transistor are N-type transistors, and the 2-1 transistors are N-type transistors. The control end of the 2-1 transistor and the control end of the 2-2 transistor are both connected to the second control signal output end, the high-level signal end, the first end of the 2-1 transistor, the second end of the 2-1 transistor, the B1 node, the first end of the 2-2 transistor, the second end of the 2-2 transistor and the ground end are connected in sequence, the control end of the 2-3 transistor is connected to the B1 node, the control end of the 2-4 transistor is connected to the first control signal output end, the high-level signal end, the first end of the 2-4 transistor, the second end of the 2-4 transistor, the first end of the 2-3 transistor, the second end of the 2-3 transistor and the 2-9 transistor are connected in sequence. The control ends of the transistors are connected in sequence, the control ends of the 2-5 transistors and the control ends of the 2-6 transistors are both connected to the first control signal output end, the high level signal end, the first end of the 2-5 transistors, the second end of the 2-5 transistors, the B2 node, the first end of the 2-6 transistors, the second end of the 2-6 transistors and the ground end are connected in sequence, the control end of the 2-7 transistors is connected to the B2 node, the control end of the 2-8 transistors is connected to the B1 node, the high level signal end, the first end of the 2-7 transistors, the second end of the 2-7 transistors, the first end of the 2-8 transistors, the second end of the 2-8 transistors, the B 3 node, the first end of the 2-9 transistor, the second end of the 2-9 transistor, and the ground end are connected in sequence, the control end of the 2-10 transistor and the control end of the 2-11 transistor are both connected to the B3 node, the high-level signal end, the first end of the 2-10 transistor, the second end of the 2-10 transistor, the B4 node, the first end of the 2-11 transistor, the second end of the 2-11 transistor, and the ground end are connected in sequence, the control end of the 2-12 transistor is connected to the B4 node, the first end of the 2-12 transistor is connected to the second dark-state voltage output end, and the second end of the 2-12 transistor is connected to the data driving module;

[0016] The third output control unit includes a 3-1 transistor, a 3-2 transistor, a 3-3 transistor, a 3-4 transistor, a 3-5 transistor, a 3-6 transistor, a 3-7 transistor, a 3-8 transistor, a 3-9 transistor, a 3-10 transistor, a 3-11 transistor and a 3-12 transistor, wherein the 3-1 transistor, the 3-3 transistor, the 3-4 transistor, the 3-5 transistor, the 3-7 transistor, the 3-8 transistor and the 3-10 transistor are P-type transistors, the 3-2 transistor, the 3-6 transistor, the 3-9 transistor, the 3-11 transistor and the 3-12 transistor are N-type transistors, and the 3-1 transistor is a 3-2 transistor. The control end of the 3-1 transistor and the control end of the 3-2 transistor are both connected to the second control signal output end, the high-level signal end, the first end of the 3-1 transistor, the second end of the 3-1 transistor, the C1 node, the first end of the 3-2 transistor, the second end of the 3-2 transistor, and the ground end are connected in sequence, the control end of the 3-5 transistor and the control end of the 3-6 transistor are both connected to the first control signal output end, the high-level signal end, the first end of the 3-5 transistor, the second end of the 3-5 transistor, the C2 node, the first end of the 3-6 transistor, the second end of the 3-6 transistor, and the ground end are connected in sequence, The control terminal of the 3-3 transistor is connected to the first control signal output terminal, the control terminal of the 3-4 transistor is connected to the C2 node, the high level signal terminal, the first terminal of the 3-4 transistor, the second terminal of the 3-4 transistor, the first terminal of the 3-3 transistor, the second terminal of the 3-3 transistor and the control terminal of the 3-9 transistor are connected in sequence, the control terminal of the 3-7 transistor is connected to the C2 node, the control terminal of the 3-8 transistor is connected to the C1 node, the high level signal terminal, the first terminal of the 3-7 transistor, the second terminal of the 3-7 transistor, the first terminal of the 3-8 transistor, the second terminal of the 3-8 transistor, C 3 node, the first end of the 3-9 transistor, the second end of the 3-9 transistor and the ground terminal are connected in sequence, the control end of the 3-10 transistor and the control end of the 3-11 transistor are both connected to the C3 node, the high-level signal end, the first end of the 3-10 transistor, the second end of the 3-10 transistor, the C4 node, the first end of the 3-11 transistor, the second end of the 3-11 transistor and the ground terminal are connected in sequence, the control end of the 3-12 transistor is connected to the C4 node, the first end of the 3-12 transistor is connected to the third dark-state voltage output terminal, and the second end of the 3-12 transistor is connected to the data driving module;

[0017] The fourth output control unit includes a 4-1 transistor, a 4-2 transistor, a 4-3 transistor, a 4-4 transistor, a 4-5 transistor, a 4-6 transistor, a 4-7 transistor, a 4-8 transistor and a 4-9 transistor, wherein the 4-2 transistor, the 4-4 transistor, the 4-6 transistor and the 4-7 transistor are P-type transistors, the 4-1 transistor, the 4-3 transistor, the 4-5 transistor, the 4-8 transistor and the 4-9 transistor are N-type transistors, and the The control end of the 4-2 transistor and the control end of the 4-3 transistor are both connected to the first control signal output end, the high level signal end, the first end of the 4-2 transistor, the second end of the 4-2 transistor, the D1 node, the first end of the 4-3 transistor, the second end of the 4-3 transistor and the ground end are connected in sequence, the control end of the 4-4 transistor and the control end of the 4-5 transistor are both connected to the second control signal output end, the high level signal end, the first end of the 4-4 transistor , the second end of the 4-4 transistor, the D2 node, the first end of the 4-5 transistor, the second end of the 4-5 transistor and the ground terminal are connected in sequence, the control end of the 4-6 transistor is connected to the D1 node, the control end of the 4-7 transistor and the control end of the 4-9 transistor are both connected to the D2 node, the high-level signal end, the first end of the 4-6 transistor, the second end of the 4-6 transistor, the first end of the 4-7 transistor, the second end of the 4-7 transistor, the D3 node, the first end of the 4-9 transistor, the second end of the 4-9 transistor and the ground terminal are connected in sequence, the control end of the 4-8 transistor is connected to the D1 node, the first end of the 4-8 transistor is connected to the ground terminal, the second end of the 4-8 transistor is connected to the D3 node, the control end of the 4-1 transistor is connected to the D3 node, the first end of the 4-1 transistor is connected to the fourth dark state voltage output terminal, and the second end of the 4-1 transistor is connected to the data driving module.

[0018] The present application also provides a display device, comprising:

[0019] Display panel;

[0020] The data driving circuit is connected to the data line of the display panel.

[0021] Optionally, the display panel includes a normal display area and at least one abnormal display area. Under the same data voltage, the brightness difference between the sub-pixels in the abnormal display area and the sub-pixels in the normal display area is greater than a preset brightness deviation, the preset brightness deviation is greater than or equal to 0 nits, and the dark state voltage corresponding to the abnormal display area is greater than or less than the dark state voltage corresponding to the normal display area.

[0022] Optionally, the display panel is a liquid crystal display panel, the data driving module is bound to the display panel, and the abnormal display area is an area around the data driving module.

[0023] The present application also provides a display driving method, comprising:

[0024] Providing the data driving circuit;

[0025] Under the same data voltage, detecting brightness differences between different areas of the display panel, and dividing the display panel into a normal display area and at least one abnormal display area based on the detection result, wherein the brightness difference between sub-pixels in the abnormal display area and sub-pixels in the normal display area is greater than a preset brightness deviation, and the preset brightness deviation is greater than or equal to 0 nit;

[0026] During line-by-line scanning, the selection module is controlled to assign different gamma voltages to the normal display area and the abnormal display area according to the brightness difference between the abnormal display area and the normal display area, so that the gamma voltages of the normal display area and the abnormal display area are negatively correlated with the brightness measured under the same data voltage.

[0027] Optionally, the display panel is a liquid crystal display panel, the data driving module is bound to the display panel, the abnormal display area is the area around the data driving module, and among the multiple abnormal display areas: adjacent abnormal display areas include sub-pixels located in the same row and / or the same column.

[0028] The data driving circuit, display device, and display driving method disclosed in this application have the following beneficial effects:

[0029] In the present application, a data driving circuit includes a data driving module, a power module, an output control module, and a selection module. The data driving module is connected to a display panel. The power module includes multiple gamma voltage output terminals, including M dark-state voltage output terminals and N bright-state voltage output terminals, where at least one of M and N is greater than 1. The output control module is connected to at least the data driving module and one of the M dark-state voltage output terminals and the N bright-state voltage output terminals. The selection module is connected to the output control module and is configured to control the output control module so that the gamma voltages from one dark-state voltage output terminal and one bright-state voltage output terminal are output to the data driving module. The data driving module is capable of providing different data voltages to the display panel based on different dark-state voltages and bright-state voltages. When driving the display panel to display an image, the selection module assigns different gamma voltages to the normal display area and the abnormal display area, so that the gamma voltages in the normal display area and the abnormal display area are negatively correlated with the brightness measured under the same data voltage. This can improve or eliminate the display unevenness problem and enhance the display quality of the display panel.

[0030] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0033] Figure 1 Schematic diagram of the structure of the data driving circuit in the first embodiment of the present application.

[0034] Figure 2 It is a structural diagram of the display panel in Example 1 of the present application.

[0035] Figure 3 This is a schematic diagram of the first output control unit under the LL signal in Example 1 of the present application.

[0036] Figure 4 This is a schematic diagram of the first output control unit under the LH signal in Example 1 of the present application.

[0037] Figure 5 This is a schematic diagram of the first output control unit under the HL signal in Example 1 of the present application.

[0038] Figure 6 This is a schematic diagram of the first output control unit under the HH signal in Example 1 of the present application.

[0039] Figure 7 This is a schematic diagram of the second output control unit under the LL signal in Example 1 of the present application.

[0040] Figure 8 This is a schematic diagram of the second output control unit under the LH signal in Example 1 of the present application.

[0041] Figure 9 This is a schematic diagram of the second output control unit under the HL signal in Example 1 of the present application.

[0042] Figure 10 This is a schematic diagram of the second output control unit under the HH signal in Example 1 of the present application.

[0043] Figure 11 This is a schematic diagram of the third output control unit under the LL signal in Example 1 of the present application.

[0044] Figure 12 This is a schematic diagram of the third output control unit under the LH signal in Example 1 of the present application.

[0045] Figure 13 This is a schematic diagram of the third output control unit under the HL signal in Example 1 of the present application.

[0046] Figure 14 This is a schematic diagram of the third output control unit under the HH signal in Example 1 of the present application.

[0047] Figure 15 This is a schematic diagram of the fourth output control unit under the LL signal in Example 1 of the present application.

[0048] Figure 16 This is a schematic diagram of the fourth output control unit under the LH signal in Example 1 of the present application.

[0049] Figure 17 This is a schematic diagram of the fourth output control unit under the HL signal in Example 1 of the present application.

[0050] Figure 18 This is a schematic diagram of the fourth output control unit under the HH signal in Example 1 of the present application.

[0051] Figure 19 It is a structural diagram of the display device in Example 2 of the present application.

[0052] Figure 20 It is a structural diagram of the liquid crystal display panel in the second embodiment of the present application.

[0053] Figure 21 It is a flow chart of the display driving method in the third embodiment of the present application.

[0054] Figure 22 This is a schematic diagram of the array distribution of abnormal display areas in Example 3 of the present application.

[0055] Figure 23 This is a schematic diagram of the misaligned setting of the abnormal display area in Example 3 of the present application.

[0056] Figure 24 This is a schematic diagram of the cross setting of abnormal display areas in Example 3 of the present application.

[0057] Description of reference numerals:

[0058] 100, data drive circuit; 110, data drive module; 120, power supply module; 121, first dark-state voltage output terminal; 122, second dark-state voltage output terminal; 123, third dark-state voltage output terminal; 124, fourth dark-state voltage output terminal; 130, output control module; 131, first output control unit; 132, second output control unit; 133, third output control unit; 134, fourth output control unit; 135, high-level signal terminal; 136, ground terminal; 140, selection module;

[0059] 200, display panel; 210, sub-pixel; 201, normal display area; 202, abnormal display area. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0061] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0062] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0063] Example 1

[0064] See also Figure 1 and Figure 2 As shown, the data driving circuit 100 in this embodiment includes a data driving module 110, a power module 120, an output control module 130 and a selection module 140. The data driving module 110 is used to connect to the display panel 200 to provide data voltages for the data lines of the display panel 200.

[0065] The power module 120 includes multiple gamma voltage output terminals, each of which outputs a gamma voltage. The multiple gamma voltage output terminals include M dark-state voltage output terminals and N bright-state voltage output terminals. The dark-state voltage output terminals output a dark-state voltage, and the bright-state voltage output terminals output a bright-state voltage. M and N are both positive integers, and at least one of M and N is greater than 1. It should be noted that different dark-state voltage output terminals output different dark-state voltages, and different bright-state voltage output terminals output different bright-state voltages. The data driver module 110 can set the data voltage corresponding to each grayscale according to a gamma curve determined by the dark-state voltage and the bright-state voltage.

[0066] In other embodiments, the gamma voltage may also include multiple gamma tie-point voltages, where the gamma tie-point voltage is greater than the dark state voltage and less than the bright state voltage. The data driving module 110 may set the data voltage corresponding to each grayscale according to a gamma curve determined by the dark state voltage, the bright state voltage, and the gamma tie-point voltage.

[0067] The output control module 130 is connected to at least the data driver module 110 and one of the M dark-state voltage output terminals and the N bright-state voltage output terminals. If the power module 120 includes two or more dark-state voltage output terminals, all dark-state voltage output terminals are connected to the data driver module 110 through the output control module 130. If the power module 120 includes two or more bright-state voltage output terminals, all bright-state voltage output terminals are connected to the data driver module 110 through the output control module 130. If there is only one bright-state voltage output terminal, the bright-state voltage output terminal can be directly connected to the data driver module 110. If there is only one dark-state voltage output terminal, the dark-state voltage output terminal can be directly connected to the data driver module 110.

[0068] The selection module 140 is connected to the output control module 130 and is used to control the output control module 130 so that the gamma voltages at one dark-state voltage output terminal and one bright-state voltage output terminal are output to the data driving module 110. The data driving module 110 can provide different data voltages to the display panel 200 according to different dark-state voltages and bright-state voltages.

[0069] During the manufacturing process of the display panel 200, the sub-pixels 210 ( Figure 2The consistency of the sub-pixels 210 (only a portion is shown schematically) is difficult to achieve high uniformity. That is, when the data voltages of the sub-pixels 210 in different areas are the same, the brightness of the sub-pixels 210 may vary, which in turn causes uneven display on the display panel 200. To improve or eliminate the uneven display, the display panel 200 can be divided into a normal display area 201 and at least one abnormal display area 202. Under the same data voltage, the brightness difference between the sub-pixels 210 in the abnormal display area 202 and the sub-pixels 210 in the normal display area 201 is greater than a preset brightness deviation, and the preset brightness deviation is greater than or equal to 0 nits.

[0070] In this embodiment, the data driving circuit 100 includes a data driving module 110, a power module 120, an output control module 130, and a selection module 140. The data driving module 110 is used to connect to the display panel 200. The power module 120 includes multiple gamma voltage output terminals, and the multiple gamma voltage output terminals include M dark-state voltage output terminals and N bright-state voltage output terminals, where at least one of M and N is greater than 1. The output control module 130 is connected to at least the data driving module 110 and one of the M dark-state voltage output terminals and the N bright-state voltage output terminals. The selection module 140 is connected to the output control module 130 and is used to control the output control module 130 to output the gamma voltages of one dark-state voltage output terminal and one bright-state voltage output terminal to the data driving module 110. The data driving module 110 can provide different data voltages to the display panel 200 according to different dark-state voltages and bright-state voltages. When driving the display panel 200 to display an image, the selection module 140 assigns different gamma voltages to the normal display area 201 and the abnormal display area 202, so that the gamma voltages of the normal display area 201 and the abnormal display area 202 are negatively correlated with the brightness measured under the same data voltage, thereby improving or eliminating the display unevenness problem and enhancing the display quality of the display panel 200.

[0071] In some embodiments, M is greater than 1, and N is equal to 1. That is, the power module 120 includes two or more dark-state voltage output terminals and one bright-state voltage output terminal.

[0072] The dark-state voltage of the normal display area 201 of the display panel 200 is typically around 0.3V, while the bright-state voltage is typically around 6V. The dark-state voltage is much lower than the bright-state voltage. By adjusting the dark-state voltage in different display areas, the brightness of the sub-pixels 210 in different display areas can be adjusted with a small adjustment range and significant effect. Furthermore, at lower brightness levels, the display panel 200 exhibits more pronounced display unevenness. Adjusting the dark-state voltage in different display areas to adjust the brightness of the sub-pixels 210 in different display areas is particularly beneficial in improving display unevenness at low brightness levels.

[0073] In some embodiments, the output control module 130 includes M output control units, and each dark-state voltage output terminal is connected to the data driving module 110 via one output control unit.

[0074] The dark state voltage output terminals are connected to the output control units in a one-to-one correspondence. Each dark state voltage output terminal and the data driving module 110 are independently controlled to be turned on or off by an output control unit, which can reduce the control difficulty of the selection module 140.

[0075] In some embodiments, M is equal to 4, that is, the power module 120 includes four dark-state voltage output terminals. The selection module 140 includes two control signal output terminals, namely a first control signal output terminal (bit: 1) and a second control signal output terminal (bit: 0). Each control signal output terminal can output a high-level signal H and a low-level signal L. Each output control unit includes two control signal input terminals, and the control signal input terminals of each output control unit are connected to the control signal output terminals in a one-to-one correspondence.

[0076] The selection module 140 outputs two control signals to control four output control units. The selection module 140 has a simple structure, which can reduce the manufacturing cost of the data driving circuit 100.

[0077] In some embodiments, the four output control units include a first output control unit 131, a second output control unit 132, a third output control unit 133, and a fourth output control unit 134. The four dark-state voltage output terminals are a first dark-state voltage output terminal 121 (Level 1), a second dark-state voltage output terminal 122 (Level 2), a third dark-state voltage output terminal 123 (Level 3), and a fourth dark-state voltage output terminal 124 (Level 4). For example, the dark-state voltages output by the first dark-state voltage output terminal 121, the second dark-state voltage output terminal 122, the third dark-state voltage output terminal 123, and the fourth dark-state voltage output terminal 124 are 0.24V, 0.26V, 0.28V, and 0.3V, respectively.

[0078] See also Figures 3 to 6 As shown, the first output control unit 131 includes a 1-1 transistor, a 1-2 transistor, a 1-3 transistor, a 1-4 transistor, a 1-5 transistor, a 1-6 transistor, a 1-7 transistor, a 1-8 transistor, a 1-9 transistor, a 1-10 transistor, a 1-11 transistor and a 1-12 transistor, wherein the 1-1 transistor, the 1-3 transistor, the 1-4 transistor, the 1-5 transistor, the 1-7 transistor, the 1-8 transistor and the 1-10 transistor are P-type transistors, and the 1-2 transistor, the 1-6 transistor, the 1-9 transistor, the 1-11 transistor and the 1-12 transistor are N-type transistors.

[0079] The control terminals of transistors 1-1 and 1-2 are both connected to the second control signal output terminal, and the high-level signal terminal 135, the first terminal of transistor 1-1, the second terminal of transistor 1-1, node A1, the first terminal of transistor 1-2, the second terminal of transistor 1-2, and the ground terminal 136 are sequentially connected. The control terminal of transistor 1-3 is connected to the second control signal output terminal, and the control terminal of transistor 1-4 is connected to the first control signal output terminal. The high-level signal terminal 135, the first terminal of transistor 1-4, the second terminal of transistor 1-4, the first terminal of transistor 1-3, the second terminal of transistor 1-3, and the control terminal of transistor 1-9 are sequentially connected.

[0080] The control terminals of transistors 1-5 and 1-6 are both connected to the first control signal output terminal, and the high-level signal terminal 135, the first terminals of transistors 1-5, the second terminals of transistors 1-5, the A2 node, the first terminals of transistors 1-6, the second terminals of transistors 1-6, and the ground terminal 136 are sequentially connected. The control terminals of transistors 1-7 are connected to the A2 node, and the control terminals of transistors 1-8 are connected to the A1 node. The high-level signal terminal 135, the first terminals of transistors 1-7, the second terminals of transistors 1-7, the first terminals of transistors 1-8, the second terminals of transistors 1-8, the A3 node, the first terminals of transistors 1-9, the second terminals of transistors 1-9, and the ground terminal 136 are sequentially connected.

[0081] The control end of the 1-10 transistor and the control end of the 1-11 transistor are both connected to the A3 node, the high-level signal end 135, the first end of the 1-10 transistor, the second end of the 1-10 transistor, the A4 node, the first end of the 1-11 transistor, the second end of the 1-11 transistor and the ground end 136 are connected in sequence, the control end of the 1-12 transistor is connected to the A4 node, the first end of the 1-12 transistor is connected to the first dark state voltage output end 121, and the second end of the 1-12 transistor is connected to the data driving module 110.

[0082] See also Figure 3 As shown, when the control signal of the selection module 140 is LL, that is, when the first control signal output terminal outputs a low level signal L and the second control signal output terminal outputs a low level signal L:

[0083] The 1-5 transistor is turned on and the 1-6 transistor is turned off, the high-level signal H of the high-level signal terminal 135 is written to the A2 node, and the 1-7 transistor is turned off; the 1-1 transistor is turned on and the 1-2 transistor is turned off, the high-level signal H is written to the A1 node, and the 1-8 transistor is turned off; the 1-3 transistor and the 1-4 transistor are turned on, the high-level signal H is written to the gate of the 1-9 transistor, the 1-9 transistor is turned on, and the low-level signal L of the ground terminal 136 is written to the A3 node; the 1-10 transistor is turned on and the 1-11 transistor is turned off, the high-level signal H is written to the A4 node, and the 1-12 transistor is turned on, so that the dark state voltage of the first dark state voltage output terminal 121 can be output to the data driving module 110.

[0084] See also Figure 4 As shown, when the control signal of the selection module 140 is LH, that is, when the first control signal output terminal outputs a low level signal L and the second control signal output terminal outputs a high level signal H:

[0085] The 1-5 transistor is turned on and the 1-6 transistor is turned off, a high-level signal H is written to the A2 node, and the 1-7 transistor is turned off; the 1-1 transistor is turned off and the 1-2 transistor is turned on, a low-level signal L is written to the A1 node, and the 1-8 transistor is turned on; the 1-3 transistor is turned off and the 1-4 transistor is turned on, the high-level signal H cannot be written to the gate of the 1-9 transistor, the 1-9 transistor is turned off, and no signal is written to the A3 node; the 1-10 transistor and the 1-11 transistor are both turned off, no signal is written to the A4 node, and the 1-12 transistor is turned off, so that the dark state voltage of the first dark state voltage output terminal 121 cannot be output to the data driving module 110.

[0086] See also Figure 5 As shown, when the control signal of the selection module 140 is HL, that is, when the first control signal output terminal outputs a high level signal H and the second control signal output terminal outputs a low level signal L:

[0087] The 1-5 transistor is turned off and the 1-6 transistor is turned on, the low-level signal L is written to the A2 node, and the 1-7 transistor is turned on; the 1-1 transistor is turned on and the 1-2 transistor is turned off, the high-level signal H is written to the A1 node, and the 1-8 transistor is turned off; the 1-3 transistor is turned on and the 1-4 transistor is turned off, the high-level signal H cannot be written to the gate of the 1-9 transistor, the 1-9 transistor is turned off, and no signal is written to the A3 node; the 1-10 transistor and the 1-11 transistor are both turned off, no signal is written to the A4 node, and the 1-12 transistor is turned off, so that the dark state voltage of the first dark state voltage output terminal 121 cannot be output to the data driving module 110.

[0088] See also Figure 6As shown, when the control signal of the selection module 140 is HH, that is, when the first control signal output terminal outputs a high level signal H and the second control signal output terminal outputs a high level signal H:

[0089] The 1-5 transistor is turned off and the 1-6 transistor is turned on, the low-level signal L is written to the A2 node, and the 1-7 transistor is turned on; the 1-1 transistor is turned off and the 1-2 transistor is turned on, the low-level signal L is written to the A1 node, and the 1-8 transistor is turned on; the 1-3 transistor and the 1-4 transistor are turned off, the high-level signal H cannot be written to the gate of the 1-9 transistor, the 1-9 transistor is turned off, and the high-level signal H is written to the A3 node; the 1-10 transistor is turned off and the 1-11 transistor is turned on, the low-level signal L is written to the A4 node, and the 1-12 transistor is turned off, so that the dark state voltage of the first dark state voltage output terminal 121 cannot be output to the data driving module 110.

[0090] See also Figures 7 to 10 As shown, the second output control unit 132 includes a 2-1 transistor, a 2-2 transistor, a 2-3 transistor, a 2-4 transistor, a 2-5 transistor, a 2-6 transistor, a 2-7 transistor, a 2-8 transistor, a 2-9 transistor, a 2-10 transistor, a 2-11 transistor and a 2-12 transistor, wherein the 2-1 transistor, the 2-3 transistor, the 2-4 transistor, the 2-5 transistor, the 2-7 transistor, the 2-8 transistor and the 2-10 transistor are P-type transistors, and the 2-2 transistor, the 2-6 transistor, the 2-9 transistor, the 2-11 transistor and the 2-12 transistor are N-type transistors.

[0091] The control end of the 2-1 transistor and the control end of the 2-2 transistor are both connected to the second control signal output end, the high-level signal end 135, the first end of the 2-1 transistor, the second end of the 2-1 transistor, the B1 node, the first end of the 2-2 transistor, the second end of the 2-2 transistor and the ground end 136 are connected in sequence, the control end of the 2-3 transistor is connected to the B1 node, the control end of the 2-4 transistor is connected to the first control signal output end, the high-level signal end 135, the first end of the 2-4 transistor, the second end of the 2-4 transistor, the first end of the 2-3 transistor, the second end of the 2-3 transistor and the control end of the 2-9 transistor are connected in sequence.

[0092] The control end of the 2-5 transistor and the control end of the 2-6 transistor are both connected to the first control signal output end, the high-level signal end 135, the first end of the 2-5 transistor, the second end of the 2-5 transistor, the B2 node, the first end of the 2-6 transistor, the second end of the 2-6 transistor, and the ground end 136 are connected in sequence, the control end of the 2-7 transistor is connected to the B2 node, the control end of the 2-8 transistor is connected to the B1 node, the high-level signal end 135, the first end of the 2-7 transistor, the second end of the 2-7 transistor, the first end of the 2-8 transistor, the second end of the 2-8 transistor, the B3 node, the first end of the 2-9 transistor, the second end of the 2-9 transistor, and the ground end 136 are connected in sequence.

[0093] The control end of the 2-10 transistor and the control end of the 2-11 transistor are both connected to the B3 node, the high-level signal end 135, the first end of the 2-10 transistor, the second end of the 2-10 transistor, the B4 node, the first end of the 2-11 transistor, the second end of the 2-11 transistor and the ground end 136 are connected in sequence, the control end of the 2-12 transistor is connected to the B4 node, the first end of the 2-12 transistor is connected to the second dark state voltage output end 122, and the second end of the 2-12 transistor is connected to the data driving module 110.

[0094] See also Figure 7 As shown, when the control signal of the selection module 140 is LL:

[0095] The 2-5 transistor is turned on and the 2-6 transistor is turned off, a high-level signal H is written to the B2 node, and the 2-7 transistor is turned off; the 2-1 transistor is turned on and the 2-2 transistor is turned off, a high-level signal H is written to the B1 node, and the 2-8 transistor is turned off; the 2-3 transistor is turned off and the 2-4 transistor is turned on, no signal is written to the gate of the 2-9 transistor, the 2-9 transistor is turned off, and no signal is written to the B3 node; the 2-10 transistor and the 2-11 transistor are turned off, no signal is written to the B4 node, and the 2-12 transistor is turned off, so that the dark state voltage of the second dark state voltage output terminal 122 cannot be output to the data driving module 110.

[0096] See also Figure 8 As shown, when the control signal of the selection module 140 is LH:

[0097] The 2-5 transistor is turned on and the 2-6 transistor is turned off, a high-level signal H is written to the B2 node, and the 2-7 transistor is turned off; the 2-1 transistor is turned off and the 2-2 transistor is turned on, a low-level signal L is written to the B1 node, and the 2-8 transistor is turned on; the 2-3 transistor and the 2-4 transistor are turned on, a high-level signal H is written to the gate of the 2-9 transistor, the 2-9 transistor is turned on, and a low-level signal L is written to the B3 node; the 2-10 transistor is turned on and the 2-11 transistor is turned off, a high-level signal H is written to the B4 node, and the 2-12 transistor is turned on, so that the dark state voltage of the second dark state voltage output terminal 122 can be output to the data driving module 110.

[0098] See also Figure 9 As shown, when the control signal of the selection module 140 is HL:

[0099] The 2-5 transistor is turned off and the 2-6 transistor is turned on, a low-level signal L is written to the B2 node, and the 2-7 transistor is turned on; the 2-1 transistor is turned on and the 2-2 transistor is turned off, a high-level signal H is written to the B1 node, and the 2-8 transistor is turned off; the 2-3 transistor and the 2-4 transistor are turned off, no signal is written to the gate of the 2-9 transistor, the 2-9 transistor is turned off, and no signal is written to the B3 node; the 2-10 transistor and the 2-11 transistor are both turned off, no signal is written to the B4 node, and the 2-12 transistor is turned off, so that the dark state voltage of the second dark state voltage output terminal 122 cannot be output to the data driving module 110.

[0100] See also Figure 10 As shown, when the control signal of the selection module 140 is HH:

[0101] The 2-5 transistor is turned off and the 2-6 transistor is turned on, the low-level signal L is written to the B2 node, and the 2-7 transistor is turned on; the 2-1 transistor is turned off and the 2-2 transistor is turned on, the low-level signal L is written to the B1 node, and the 2-8 transistor is turned on; the 2-3 transistor and the 2-4 transistor are turned off, the high-level signal H cannot be written to the gate of the 2-9 transistor, the 2-9 transistor is turned off, and the high-level signal H is written to the B3 node; the 2-10 transistor is turned off and the 2-11 transistor is turned on, the low-level signal L is written to the B4 node, and the 2-12 transistor is turned off, so that the dark state voltage of the second dark state voltage output terminal 122 cannot be output to the data driving module 110.

[0102] See also Figures 11 to 14As shown, the third output control unit 133 includes a 3-1 transistor, a 3-2 transistor, a 3-3 transistor, a 3-4 transistor, a 3-5 transistor, a 3-6 transistor, a 3-7 transistor, a 3-8 transistor, a 3-9 transistor, a 3-10 transistor, a 3-11 transistor and a 3-12 transistor, wherein the 3-1 transistor, the 3-3 transistor, the 3-4 transistor, the 3-5 transistor, the 3-7 transistor, the 3-8 transistor and the 3-10 transistor are P-type transistors, and the 3-2 transistor, the 3-6 transistor, the 3-9 transistor, the 3-11 transistor and the 3-12 transistor are N-type transistors.

[0103] The control end of the 3-1 transistor and the control end of the 3-2 transistor are both connected to the second control signal output end, the high-level signal end 135, the first end of the 3-1 transistor, the second end of the 3-1 transistor, the C1 node, the first end of the 3-2 transistor, the second end of the 3-2 transistor and the ground end 136 are connected in sequence, the control end of the 3-5 transistor and the control end of the 3-6 transistor are both connected to the first control signal output end, the high-level signal end 135, the first end of the 3-5 transistor, the second end of the 3-5 transistor, the C2 node, the first end of the 3-6 transistor, the second end of the 3-6 transistor and the ground end 136 are connected in sequence.

[0104] The control terminal of transistor 3-3 is connected to the first control signal output terminal, the control terminal of transistor 3-4 is connected to node C2, the high-level signal terminal 135, the first terminal of transistor 3-4, the second terminal of transistor 3-4, the first terminal of transistor 3-3, the second terminal of transistor 3-3, and the control terminal of transistor 3-9 are connected in sequence. The control terminal of transistor 3-7 is connected to node C2, the control terminal of transistor 3-8 is connected to node C1, the high-level signal terminal 135, the first terminal of transistor 3-7, the second terminal of transistor 3-7, the first terminal of transistor 3-8, the second terminal of transistor 3-8, node C3, the first terminal of transistor 3-9, the second terminal of transistor 3-9, and ground terminal 136 are connected in sequence.

[0105] The control terminals of the 3-10 transistor and the 3-11 transistor are both connected to the C3 node. The high-level signal terminal 135, the first terminal of the 3-10 transistor, the second terminal of the 3-10 transistor, the C4 node, the first terminal of the 3-11 transistor, the second terminal of the 3-11 transistor, and the ground terminal 136 are sequentially connected. The control terminal of the 3-12 transistor is connected to the C4 node. The first terminal of the 3-12 transistor is connected to the third dark-state voltage output terminal 123, and the second terminal of the 3-12 transistor is connected to the data driving module 110.

[0106] See also Figure 11 As shown, when the control signal of the selection module 140 is LL:

[0107] The 3-5th transistor is turned on and the 3-6th transistor is turned off, a high-level signal H is written to the C2 node, and the 3-7th transistor is turned off; the 3-1st transistor is turned on and the 3-2nd transistor is turned off, a high-level signal H is written to the C1 node, and the 3-8th transistor is turned off; the 3-3rd transistor is turned on and the 3-4th transistor is turned off, no signal is written to the gate of the 3-9th transistor, the 3-9th transistor is turned off, and no signal is written to the C3 node; the 3-10th transistor and the 3-11th transistor are turned off, no signal is written to the C4 node, and the 3-12th transistor is turned off, so that the dark state voltage of the third dark state voltage output terminal 123 cannot be output to the data driving module 110.

[0108] See also Figure 12 As shown, when the control signal of the selection module 140 is LH:

[0109] The 3-5th transistor is turned on and the 3-6th transistor is turned off, a high-level signal H is written to the C2 node, and the 3-7th transistor is turned off; the 3-1st transistor is turned off and the 3-2nd transistor is turned on, a low-level signal L is written to the C1 node, and the 3-8th transistor is turned on; the 3-3rd transistor and the 3-4th transistor are turned off, no signal is written to the gate of the 3-9th transistor, the 3-9th transistor is turned off, and no signal is written to the C3 node; the 3-10th transistor and the 3-11th transistor are turned off, no signal is written to the C4 node, and the 3-12th transistor is turned off, so that the dark state voltage of the third dark state voltage output terminal 123 cannot be output to the data driving module 110.

[0110] See also Figure 13 As shown, when the control signal of the selection module 140 is HL:

[0111] The 3-5 transistor is turned off and the 3-6 transistor is turned on, a low-level signal L is written to the C2 node, and the 3-7 transistor is turned on; the 3-1 transistor is turned on and the 3-2 transistor is turned off, a high-level signal H is written to the C1 node, and the 3-8 transistor is turned off; the 3-3 transistor and the 3-4 transistor are turned on, a high-level signal H is written to the gate of the 3-9 transistor, the 3-9 transistor is turned on, and a low-level signal L is written to the C3 node; the 3-10 transistor is turned on and the 3-11 transistor is turned off, a high-level signal H is written to the C4 node, and the 3-12 transistor is turned on, so that the dark state voltage of the third dark state voltage output terminal 123 can be output to the data driving module 110.

[0112] See also Figure 14 As shown, when the control signal of the selection module 140 is HH:

[0113] The 3-5 transistor is turned off and the 3-6 transistor is turned on, a low-level signal L is written to the C2 node, and the 3-7 transistor is turned on; the 3-1 transistor is turned off and the 3-2 transistor is turned on, a low-level signal L is written to the C1 node, and the 3-8 transistor is turned on; the 3-3 transistor is turned off and the 3-4 transistor is turned on, no signal is written to the gate of the 3-9 transistor, the 3-9 transistor is turned off, and a high-level signal H is written to the C3 node; the 3-10 transistor is turned off and the 3-11 transistor is turned on, a low-level signal L is written to the C4 node, and the 3-12 transistor is turned off, so that the dark state voltage of the third dark state voltage output terminal 123 cannot be output to the data driving module 110.

[0114] See also Figures 15 to 18 As shown, the fourth output control unit 134 includes a 4-1 transistor, a 4-2 transistor, a 4-3 transistor, a 4-4 transistor, a 4-5 transistor, a 4-6 transistor, a 4-7 transistor, a 4-8 transistor and a 4-9 transistor, the 4-2 transistor, the 4-4 transistor, the 4-6 transistor and the 4-7 transistor are P-type transistors, and the 4-1 transistor, the 4-3 transistor, the 4-5 transistor, the 4-8 transistor and the 4-9 transistor are N-type transistors.

[0115] The control terminals of the 4-2 transistor and the 4-3 transistor are both connected to the first control signal output terminal, and the high-level signal terminal 135, the first terminal of the 4-2 transistor, the second terminal of the 4-2 transistor, the D1 node, the first terminal of the 4-3 transistor, the second terminal of the 4-3 transistor, and the ground terminal 136 are connected in sequence. The control terminals of the 4-4 transistor and the 4-5 transistor are both connected to the second control signal output terminal, and the high-level signal terminal 135, the first terminal of the 4-4 transistor, the second terminal of the 4-4 transistor, the D2 node, the first terminal of the 4-5 transistor, the second terminal of the 4-5 transistor, and the ground terminal 136 are connected in sequence.

[0116] The control terminal of the 4-6 transistor is connected to the D1 node, the control terminal of the 4-7 transistor and the control terminal of the 4-9 transistor are both connected to the D2 node, and the high-level signal terminal 135, the first terminal of the 4-6 transistor, the second terminal of the 4-6 transistor, the first terminal of the 4-7 transistor, the second terminal of the 4-7 transistor, the D3 node, the first terminal of the 4-9 transistor, the second terminal of the 4-9 transistor, and the ground terminal 136 are connected in sequence. The control terminal of the 4-8 transistor is connected to the D1 node, the first terminal of the 4-8 transistor is connected to the ground terminal 136, and the second terminal of the 4-8 transistor is connected to the D3 node. The control terminal of the 4-1 transistor is connected to the D3 node, the first terminal of the 4-1 transistor is connected to the fourth dark-state voltage output terminal 124, and the second terminal of the 4-1 transistor is connected to the data driver module 110.

[0117] See also Figure 15 As shown, when the control signal of the selection module 140 is LL:

[0118] The 4-2 transistor is turned on and the 4-3 transistor is turned off, a high-level signal H is written to the D1 node, the 4-6 transistor is turned off and the 4-8 transistor is turned on; the 4-4 transistor is turned on and the 4-5 transistor is turned off, a high-level signal H is written to the D2 node, the 4-7 transistor is turned off and the 4-9 transistor is turned on; a low-level signal L is written to the D3 node, and the 4-1 transistor is turned off, so that the dark state voltage of the fourth dark state voltage output terminal 124 cannot be output to the data driving module 110.

[0119] See also Figure 16 As shown, when the control signal of the selection module 140 is LH:

[0120] The 4-2 transistor is turned on and the 4-3 transistor is turned off, a high-level signal H is written to the D1 node, the 4-6 transistor is turned off and the 4-8 transistor is turned on; the 4-4 transistor is turned off and the 4-5 transistor is turned on, a low-level signal L is written to the D2 node, the 4-7 transistor is turned on and the 4-9 transistor is turned off; a low-level signal L is written to the D3 node, and the 4-1 transistor is turned off, so that the dark state voltage of the fourth dark state voltage output terminal 124 cannot be output to the data driving module 110.

[0121] See also Figure 17 As shown, when the control signal of the selection module 140 is HL:

[0122] The 4-2 transistor is turned off and the 4-3 transistor is turned on, a low-level signal L is written to the D1 node, the 4-6 transistor is turned on and the 4-8 transistor is turned off; the 4-4 transistor is turned on and the 4-5 transistor is turned off, a high-level signal H is written to the D2 node, the 4-7 transistor is turned off and the 4-9 transistor is turned on; a low-level signal L is written to the D3 node, and the 4-1 transistor is turned off, so that the dark state voltage of the fourth dark state voltage output terminal 124 cannot be output to the data driving module 110.

[0123] See also Figure 18 As shown, when the control signal of the selection module 140 is HH:

[0124] The 4-2 transistor is turned off and the 4-3 transistor is turned on, a low-level signal L is written to the D1 node, the 4-6 transistor is turned on and the 4-8 transistor is turned off; the 4-4 transistor is turned off and the 4-5 transistor is turned on, a low-level signal L is written to the D2 node, the 4-7 transistor is turned on and the 4-9 transistor is turned off; a high-level signal H is written to the D3 node, the 4-1 transistor is turned on, so that the dark state voltage of the fourth dark state voltage output terminal 124 can be output to the data driving module 110.

[0125] Four output control units with different structures are provided. The selection module 140 outputs two control signals to control one dark-state voltage output terminal and one bright-state voltage output terminal to output gamma voltage. The structure of the selection module 140 is simple, which can reduce the manufacturing cost of the data driving circuit 100.

[0126] Example 2

[0127] See also Figure 19 As shown, the display device in this embodiment includes a display panel 200 and the data driving circuit 100 disclosed in the first embodiment. The data driving module 110 of the data driving circuit 100 is connected to the data line of the display panel 200 .

[0128] The display panel 200 can be divided into a normal display area 201 and at least one abnormal display area 202. Under the same data voltage, the brightness difference between the sub-pixel 210 in the abnormal display area 202 and the sub-pixel 210 in the normal display area 201 is greater than a preset brightness deviation, and the preset brightness deviation is greater than or equal to 0 nits.

[0129] The display device includes a display panel 200 and a data driving circuit 100. When driving the display panel 200 to display an image, the selection module 140 assigns different gamma voltages to the normal display area 201 and the abnormal display area 202, so that the gamma voltages of the normal display area 201 and the abnormal display area 202 are negatively correlated with the brightness measured under the same data voltage. This can improve or eliminate the display unevenness problem and enhance the display quality of the display panel 200 and the display device.

[0130] In some embodiments, the dark state voltage corresponding to the abnormal display area 202 is greater than or less than the dark state voltage corresponding to the normal display area 201. For example, the dark state voltage corresponding to the normal display area 201 may be 0.3V, and the dark state voltage corresponding to the abnormal display area 202 is greater than or less than 0.3V.

[0131] The area of ​​the abnormal display area 202 is smaller than the normal display area 201, and the dark state voltage of the normal display area 201 remains unchanged. According to the brightness difference between the abnormal display area 202 and the normal display area 201, the dark state voltage of the abnormal display area 202 is increased or decreased to better improve or eliminate the display unevenness problem.

[0132] In some embodiments, see Figure 20 As shown, the display panel 200 is a liquid crystal display panel, and the data driving module 110 is bonded to the display panel 200 , that is, a COG (Chip On Glass) package is used. The abnormal display area 202 is the area around the data driving module 110 .

[0133] The display panel 200 uses COG packaging, which can reduce the manufacturing cost of the display panel 200 and the display device, and improve the reliability and lifespan of the display panel 200 and the display device. However, the data driver module 110 is bonded to the display panel 200. Improving the bonding conditions improves electrical conductivity, but it can easily cause uneven thickness of the liquid crystal layer, which in turn leads to uneven display on the display panel 200. The uneven display area is the area around the data driver module 110.

[0134] This application divides the display panel 200 into a normal display area 201 and at least one abnormal display area 202. By assigning different gamma voltages to the normal display area 201 and the abnormal display area 202 through the selection module 140, the gamma voltages of the normal display area 201 and the abnormal display area 202 are negatively correlated with the brightness measured at the same data voltage, thereby improving or eliminating the display unevenness problem. Therefore, the binding conditions can be appropriately improved, thereby improving electrical conductivity.

[0135] Example 3

[0136] See also Figure 21 As shown, the display driving method in this embodiment includes:

[0137] S100: providing a data driving circuit 100;

[0138] S200: Under the same data voltage, detecting brightness differences between different areas of the display panel 200, and dividing the display panel 200 into a normal display area 201 and at least one abnormal display area 202 according to the detection results, wherein a brightness difference between a sub-pixel 210 in the abnormal display area 202 and a sub-pixel 210 in the normal display area 201 is greater than a preset brightness deviation, and the preset brightness deviation is greater than or equal to 0 nit;

[0139] S300: During line-by-line scanning, the control selection module 140 allocates different gamma voltages to the normal display area 201 and the abnormal display area 202 according to the brightness difference between the abnormal display area 202 and the normal display area 201, so that the gamma voltages of the normal display area 201 and the abnormal display area 202 are negatively correlated with the brightness measured under the same data voltage.

[0140] In step S200, the brightness difference between different areas of the display panel 200 is detected by a detection device, or a structure for detecting the brightness of different areas is set on the display panel 200. The data driving circuit 100 divides the display into a normal display area 201 and an abnormal display area 202 in real time according to the detection structure. The gamma voltages of different abnormal display areas 202 can be the same or different.

[0141] For example, the abnormal display area 202 is divided into three levels according to its brightness, namely, a highlighted abnormal display area 202, a medium-bright abnormal display area 202, and a low-bright abnormal display area 202. The dark state voltages output by the first dark state voltage output terminal 121, the second dark state voltage output terminal 122, the third dark state voltage output terminal 123, and the fourth dark state voltage output terminal 124 are 0.24V, 0.26V, 0.28V, and 0.3V, respectively. The dark state voltage of the first dark state voltage output terminal 121 can be allocated to the highlighted abnormal display area 202, the dark state voltage of the second dark state voltage output terminal 122 can be allocated to the medium-bright abnormal display area 202, the dark state voltage of the third dark state voltage output terminal 123 can be allocated to the low-bright abnormal display area 202, and the dark state voltage of the fourth dark state voltage output terminal 124 can be allocated to the normal display area 201.

[0142] The gamma voltages of the normal display area 201 and the abnormal display area 202 are negatively correlated with the brightness measured under the same data voltage, which can improve or eliminate the display unevenness problem.

[0143] In some embodiments, the display panel 200 is a liquid crystal display panel, the data driving module 110 is bound to the display panel 200, the abnormal display area 202 is the area around the data driving module 110, and among the multiple abnormal display areas 202: adjacent abnormal display areas 202 include sub-pixels 210 located in the same row and / or the same column. For example, the abnormal display area 202 is a rectangular area, and the abnormal display areas 202 adjacent in the column direction are staggered in the row direction, such as Figure 23 or the abnormal display area 202 is a non-rectangular area, and the adjacent sides of some adjacent abnormal display areas 202 are curved, such as Figure 24 shown.

[0144] It should be noted that adjacent abnormal display areas 202 include sub-pixels 210 located in the same row and / or the same column, but are not limited thereto. The abnormal display area 202 may also be a rectangular area arranged in an array, such as Figure 22 As shown, it depends on the specific situation.

[0145] Adjacent abnormal display areas 202 include sub-pixels 210 located in the same row and / or the same column, that is, irregularly dividing the abnormal display area 202 can further improve or eliminate the display unevenness problem.

[0146] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0147] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0148] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0149] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A data driving circuit, comprising a data driving module, for connecting to a display panel, characterized in that: The data driving circuit further includes: A power supply module, comprising a plurality of gamma voltage output terminals, wherein the plurality of gamma voltage output terminals include M dark-state voltage output terminals and N bright-state voltage output terminals, where M and N are both positive integers, and at least one of M and N is greater than 1; an output control module, connected to at least the data driving module and one of the M dark-state voltage output terminals and the N bright-state voltage output terminals; A selection module is connected to the output control module, and the selection module is used to control the operation of the output control module so that the gamma voltages of one of the dark state voltage output terminals and one of the bright state voltage output terminals are output to the data driving module. The data driving module can provide different data voltages for the display panel according to different dark state voltages and bright state voltages.

2. The data driving circuit according to claim 1, wherein: M is greater than 1 and N is equal to 1.

3. The data driving circuit according to claim 2, wherein: The output control module includes M output control units, and each of the dark-state voltage output terminals is connected to the data driving module via one of the output control units.

4. The data driving circuit according to claim 3, wherein: M is equal to 4, the selection module includes 2 control signal output terminals, each of the output control units includes 2 control signal input terminals, and the control signal input terminal of each output control unit is connected to the control signal output terminal in a one-to-one correspondence.

5. The data driving circuit according to claim 4, wherein: The four output control units include a first output control unit, a second output control unit, a third output control unit, and a fourth output control unit; the four dark-state voltage output terminals are respectively a first dark-state voltage output terminal, a second dark-state voltage output terminal, a third dark-state voltage output terminal, and a fourth dark-state voltage output terminal; and the two control signal output terminals are respectively a first control signal output terminal and a second control signal output terminal; The first output control unit includes a 1-1 transistor, a 1-2 transistor, a 1-3 transistor, a 1-4 transistor, a 1-5 transistor, a 1-6 transistor, a 1-7 transistor, a 1-8 transistor, a 1-9 transistor, a 1-10 transistor, a 1-11 transistor and a 1-12 transistor, wherein the 1-1 transistor, the 1-3 transistor, the 1-4 transistor, the 1-5 transistor, the 1-7 transistor, the 1-8 transistor and the 1-10 transistor are P-type transistors, the 1-2 transistor, the 1-6 transistor, the 1-9 transistor, the 1-11 transistor and the 1-12 transistor are N-type transistors, and the 1-1 transistors are N-type transistors. The control end of the 1-1 transistor and the control end of the 1-2 transistor are both connected to the second control signal output end, the high level signal end, the first end of the 1-1 transistor, the second end of the 1-1 transistor, the A1 node, the first end of the 1-2 transistor, the second end of the 1-2 transistor and the ground end are connected in sequence, the control end of the 1-3 transistor is connected to the second control signal output end, the control end of the 1-4 transistor is connected to the first control signal output end, the high level signal end, the first end of the 1-4 transistor, the second end of the 1-4 transistor, the first end of the 1-3 transistor, the second end of the 1-3 transistor and the 1-9 transistor are connected in sequence. The control ends of the transistors are connected in sequence, the control ends of the 1-5 transistors and the control ends of the 1-6 transistors are both connected to the first control signal output end, the high level signal end, the first ends of the 1-5 transistors, the second ends of the 1-5 transistors, the A2 node, the first ends of the 1-6 transistors, the second ends of the 1-6 transistors and the ground end are connected in sequence, the control ends of the 1-7 transistors are connected to the A2 node, the control ends of the 1-8 transistors are connected to the A1 node, the high level signal end, the first ends of the 1-7 transistors, the second ends of the 1-7 transistors, the first ends of the 1-8 transistors, the second ends of the 1-8 transistors, the A A3 node, the first end of the 1-9 transistor, the second end of the 1-9 transistor, and the ground end are connected in sequence, the control end of the 1-10 transistor and the control end of the 1-11 transistor are both connected to the A3 node, the high-level signal end, the first end of the 1-10 transistor, the second end of the 1-10 transistor, the A4 node, the first end of the 1-11 transistor, the second end of the 1-11 transistor, and the ground end are connected in sequence, the control end of the 1-12 transistor is connected to the A4 node, the first end of the 1-12 transistor is connected to the first dark-state voltage output end, and the second end of the 1-12 transistor is connected to the data driving module; The second output control unit includes a 2-1 transistor, a 2-2 transistor, a 2-3 transistor, a 2-4 transistor, a 2-5 transistor, a 2-6 transistor, a 2-7 transistor, a 2-8 transistor, a 2-9 transistor, a 2-10 transistor, a 2-11 transistor and a 2-12 transistor, wherein the 2-1 transistor, the 2-3 transistor, the 2-4 transistor, the 2-5 transistor, the 2-7 transistor, the 2-8 transistor and the 2-10 transistor are P-type transistors, the 2-2 transistor, the 2-6 transistor, the 2-9 transistor, the 2-11 transistor and the 2-12 transistor are N-type transistors, and the 2-1 transistors are N-type transistors. The control end of the 2-1 transistor and the control end of the 2-2 transistor are both connected to the second control signal output end, the high-level signal end, the first end of the 2-1 transistor, the second end of the 2-1 transistor, the B1 node, the first end of the 2-2 transistor, the second end of the 2-2 transistor and the ground end are connected in sequence, the control end of the 2-3 transistor is connected to the B1 node, the control end of the 2-4 transistor is connected to the first control signal output end, the high-level signal end, the first end of the 2-4 transistor, the second end of the 2-4 transistor, the first end of the 2-3 transistor, the second end of the 2-3 transistor and the 2-9 transistor are connected in sequence. The control ends of the transistors are connected in sequence, the control ends of the 2-5 transistors and the control ends of the 2-6 transistors are both connected to the first control signal output end, the high level signal end, the first end of the 2-5 transistors, the second end of the 2-5 transistors, the B2 node, the first end of the 2-6 transistors, the second end of the 2-6 transistors and the ground end are connected in sequence, the control end of the 2-7 transistors is connected to the B2 node, the control end of the 2-8 transistors is connected to the B1 node, the high level signal end, the first end of the 2-7 transistors, the second end of the 2-7 transistors, the first end of the 2-8 transistors, the second end of the 2-8 transistors, the B 3 node, the first end of the 2-9 transistor, the second end of the 2-9 transistor, and the ground end are connected in sequence, the control end of the 2-10 transistor and the control end of the 2-11 transistor are both connected to the B3 node, the high-level signal end, the first end of the 2-10 transistor, the second end of the 2-10 transistor, the B4 node, the first end of the 2-11 transistor, the second end of the 2-11 transistor, and the ground end are connected in sequence, the control end of the 2-12 transistor is connected to the B4 node, the first end of the 2-12 transistor is connected to the second dark-state voltage output end, and the second end of the 2-12 transistor is connected to the data driving module; The third output control unit includes a 3-1 transistor, a 3-2 transistor, a 3-3 transistor, a 3-4 transistor, a 3-5 transistor, a 3-6 transistor, a 3-7 transistor, a 3-8 transistor, a 3-9 transistor, a 3-10 transistor, a 3-11 transistor and a 3-12 transistor, wherein the 3-1 transistor, the 3-3 transistor, the 3-4 transistor, the 3-5 transistor, the 3-7 transistor, the 3-8 transistor and the 3-10 transistor are P-type transistors, the 3-2 transistor, the 3-6 transistor, the 3-9 transistor, the 3-11 transistor and the 3-12 transistor are N-type transistors, and the 3-1 transistor is a 3-2 transistor. The control end of the 3-1 transistor and the control end of the 3-2 transistor are both connected to the second control signal output end, the high-level signal end, the first end of the 3-1 transistor, the second end of the 3-1 transistor, the C1 node, the first end of the 3-2 transistor, the second end of the 3-2 transistor, and the ground end are connected in sequence, the control end of the 3-5 transistor and the control end of the 3-6 transistor are both connected to the first control signal output end, the high-level signal end, the first end of the 3-5 transistor, the second end of the 3-5 transistor, the C2 node, the first end of the 3-6 transistor, the second end of the 3-6 transistor, and the ground end are connected in sequence, The control terminal of the 3-3 transistor is connected to the first control signal output terminal, the control terminal of the 3-4 transistor is connected to the C2 node, the high level signal terminal, the first terminal of the 3-4 transistor, the second terminal of the 3-4 transistor, the first terminal of the 3-3 transistor, the second terminal of the 3-3 transistor and the control terminal of the 3-9 transistor are connected in sequence, the control terminal of the 3-7 transistor is connected to the C2 node, the control terminal of the 3-8 transistor is connected to the C1 node, the high level signal terminal, the first terminal of the 3-7 transistor, the second terminal of the 3-7 transistor, the first terminal of the 3-8 transistor, the second terminal of the 3-8 transistor, C 3 node, the first end of the 3-9 transistor, the second end of the 3-9 transistor and the ground terminal are connected in sequence, the control end of the 3-10 transistor and the control end of the 3-11 transistor are both connected to the C3 node, the high-level signal end, the first end of the 3-10 transistor, the second end of the 3-10 transistor, the C4 node, the first end of the 3-11 transistor, the second end of the 3-11 transistor and the ground terminal are connected in sequence, the control end of the 3-12 transistor is connected to the C4 node, the first end of the 3-12 transistor is connected to the third dark-state voltage output terminal, and the second end of the 3-12 transistor is connected to the data driving module; The fourth output control unit includes a 4-1 transistor, a 4-2 transistor, a 4-3 transistor, a 4-4 transistor, a 4-5 transistor, a 4-6 transistor, a 4-7 transistor, a 4-8 transistor and a 4-9 transistor, wherein the 4-2 transistor, the 4-4 transistor, the 4-6 transistor and the 4-7 transistor are P-type transistors, the 4-1 transistor, the 4-3 transistor, the 4-5 transistor, the 4-8 transistor and the 4-9 transistor are N-type transistors, and the The control end of the 4-2 transistor and the control end of the 4-3 transistor are both connected to the first control signal output end, the high level signal end, the first end of the 4-2 transistor, the second end of the 4-2 transistor, the D1 node, the first end of the 4-3 transistor, the second end of the 4-3 transistor and the ground end are connected in sequence, the control end of the 4-4 transistor and the control end of the 4-5 transistor are both connected to the second control signal output end, the high level signal end, the first end of the 4-4 transistor , the second end of the 4-4 transistor, the D2 node, the first end of the 4-5 transistor, the second end of the 4-5 transistor and the ground terminal are connected in sequence, the control end of the 4-6 transistor is connected to the D1 node, the control end of the 4-7 transistor and the control end of the 4-9 transistor are both connected to the D2 node, the high-level signal end, the first end of the 4-6 transistor, the second end of the 4-6 transistor, the first end of the 4-7 transistor, the second end of the 4-7 transistor, the D3 node, the first end of the 4-9 transistor, the second end of the 4-9 transistor and the ground terminal are connected in sequence, the control end of the 4-8 transistor is connected to the D1 node, the first end of the 4-8 transistor is connected to the ground terminal, the second end of the 4-8 transistor is connected to the D3 node, the control end of the 4-1 transistor is connected to the D3 node, the first end of the 4-1 transistor is connected to the fourth dark state voltage output terminal, and the second end of the 4-1 transistor is connected to the data driving module.

6. A display device, characterized in that: include: Display panel; The data driving circuit according to any one of claims 1 to 5, connected to the data line of the display panel.

7. The display device according to claim 6, wherein: The display panel includes a normal display area and at least one abnormal display area. Under the same data voltage, the brightness difference between the sub-pixels in the abnormal display area and the sub-pixels in the normal display area is greater than a preset brightness deviation, the preset brightness deviation is greater than or equal to 0 nit, and the dark state voltage corresponding to the abnormal display area is greater than or less than the dark state voltage corresponding to the normal display area.

8. The display device according to claim 7, wherein: The display panel is a liquid crystal display panel, the data driving module is bound to the display panel, and the abnormal display area is an area around the data driving module.

9. A display driving method, characterized in that: include: Providing a data driving circuit according to any one of claims 1 to 5; Under the same data voltage, detecting brightness differences between different areas of the display panel, and dividing the display panel into a normal display area and at least one abnormal display area based on the detection result, wherein the brightness difference between sub-pixels in the abnormal display area and sub-pixels in the normal display area is greater than a preset brightness deviation, and the preset brightness deviation is greater than or equal to 0 nit; During line-by-line scanning, the selection module is controlled to assign different gamma voltages to the normal display area and the abnormal display area according to the brightness difference between the abnormal display area and the normal display area, so that the gamma voltages of the normal display area and the abnormal display area are negatively correlated with the brightness measured under the same data voltage.

10. The display driving method according to claim 9, wherein: The display panel is a liquid crystal display panel, the data driving module is bound to the display panel, the abnormal display area is the area around the data driving module, and among the multiple abnormal display areas: adjacent abnormal display areas include sub-pixels located in the same row and / or the same column.

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