Self-adaptive time sequence control circuit and method applied to SRAM (Static Random Access Memory)

Abstract

The invention discloses a self-adaptive time sequence control circuit and method applied to an SRAM (Static Random Access Memory), relates to the technical field of integrated circuits, and aims to solve the problem that the traditional SRAM time sequence control circuit easily causes unstable performance of the SRAM under different temperature conditions. The adaptive time sequence control circuit comprises a temperature compensation code generation circuit and a time sequence compensation circuit. The time sequence compensation circuit at least comprises a delay chain circuit, a first AND gate and a second AND gate; the output end of the first AND gate is connected with the data input end of the delay chain circuit and the first input end of the second AND gate, the data selection end of the delay chain circuit is connected with the output end of the temperature compensation code generation circuit, the output end of the delay chain circuit is connected with the second input end of the second AND gate, and the output end of the second AND gate is connected with the SRAM. The self-adaptive time sequence control circuit applied to the SRAM is used for improving the performance stability of the SRAM under different working temperature conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an adaptive timing control circuit and method applied to an SRAM memory. Background Art

[0002] SRAM (Static Random Access Memory) is a type of memory based on a trigger structure that can retain data without refreshing. It has characteristics such as high-speed reading and writing and static storage, but has limitations such as low integration and high power consumption. It is widely used in scenarios with high speed requirements, such as CPU cache and embedded systems. SRAM timing control is crucial to ensure the correct reading and writing of data. Traditional SRAM timing control circuits often use fixed delay chains for timing control. Fixed delay chains use a series of logic gates to achieve a fixed time delay. This structure is easy to implement, has a simple algorithm, and can meet basic accuracy requirements. The performance of SRAM is greatly affected by temperature changes. In systems that require fast response, the non-adjustability of the fixed delay chain limits the flexibility and response speed of the system, resulting in unstable SRAM performance under different temperature conditions, affecting data reliability and system efficiency.

[0003] Therefore, there is an urgent need for an adaptive timing control circuit and method for SRAM memory. Summary of the Invention

[0004] The purpose of the present invention is to provide an adaptive timing control circuit and method for SRAM memory. By directly generating a timing signal for temperature adaptive compensation, the timing of the circuit can be dynamically adjusted in a timely manner when the operating temperature of the SRAM memory changes, thereby improving the performance and stability of the SRAM.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides an adaptive timing control circuit applied to an SRAM memory, comprising:

[0007] Temperature compensation code generation circuit and timing compensation circuit;

[0008] The timing compensation circuit at least includes a delay chain circuit, a first AND gate, and a second AND gate; the output end of the first AND gate is connected to the data input end of the delay chain circuit and the first input end of the second AND gate, the data selection end of the delay chain circuit is connected to the output end of the temperature compensation code generation circuit, the output end of the delay chain circuit is connected to the second input end of the second AND gate, and the output end of the second AND gate is connected to the SRAM memory;

[0009] The temperature compensation code generating circuit is used to detect the temperature of the SRAM memory and generate a temperature compensation code; the first AND gate is used to perform an AND operation on the read / write signal and the clock signal to generate a read / write control signal; the delay chain circuit is used to delay the read / write control signal.

[0010] Optionally, the timing compensation circuit also includes an inverter and a third AND gate, the input end of the inverter is connected to the output end of the second AND gate, the output end of the second AND gate is connected to the word line of the SRAM memory, the output end of the inverter is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the output end of the first AND gate, and the output end of the third AND gate is connected to the bit line and complementary bit line of the SRAM memory.

[0011] Optionally, the delay chain circuit includes a multiple-selector and multiple delay units connected in series, the output ends of the multiple delay units are connected to the data input ends of the multiple-selector, and the data selection end of the multiple-selector is connected to the output end of the temperature compensation code generating circuit.

[0012] Optionally, the delay unit includes two standard inverters and two delayed inverters, the two delayed inverters are connected and arranged between the two standard inverters; the delay inverter includes a first transistor and a second transistor, the gate of the first transistor is coupled to the input signal, the source of the first transistor is coupled to the power supply, the drain of the first transistor is coupled to the drain of the second transistor, the gate of the second transistor is coupled to the input signal, and the source of the second transistor is coupled to the ground.

[0013] Optionally, the temperature compensation code generating circuit includes a temperature detection circuit, a multi-channel compensation code generating circuit and a reference source, the temperature detection circuit and the reference source are connected to the multi-channel compensation code generating circuit, the temperature detection circuit is used to detect the temperature of the SRAM memory and output the detection voltage; the reference source is used to provide a reference voltage; the multi-channel compensation code generating circuit is used to compare the reference voltage with the detection voltage and generate a temperature compensation code.

[0014] Optionally, the multiple-choice selector is a four-choice selector, a six-choice selector, or an eight-choice selector.

[0015] Optionally, when the multi-select selector is the four-select selector, the delay unit includes a first delay unit, a second delay unit, a third delay unit and a fourth delay unit, and the first delay unit, the second delay unit, the third delay unit and the fourth delay unit are connected in series, the input end of the first delay unit is connected to the output end of the first AND gate, the output end of the first delay unit is connected to the first data input end of the four-select selector, the output end of the second delay unit is connected to the second data input end of the four-select selector, the output end of the third delay unit is connected to the third data input end of the four-select selector, and the output end of the fourth delay unit is connected to the fourth data input end of the four-select selector.

[0016] Optionally, when the multi-select selector is the four-select selector, when the temperature compensation code is "00", the four-select selector selects the output of the first delay unit for output; when the temperature compensation code is "01", the four-select selector selects the output of the second delay unit for output; when the temperature compensation code is "10", the four-select selector selects the output of the third delay unit for output; when the temperature compensation code is "11", the four-select selector selects the output of the fourth delay unit for output.

[0017] Compared with the prior art, the present invention provides an adaptive timing control circuit for an SRAM memory, including a temperature compensation code generating circuit and a timing compensation circuit; the timing compensation circuit includes at least a delay chain circuit, a first AND gate, and a second AND gate; the output end of the first AND gate is connected to the data input end of the delay chain circuit and the first input end of the second AND gate, the data selection end of the delay chain circuit is connected to the output end of the temperature compensation code generating circuit, the output end of the delay chain circuit is connected to the second input end of the second AND gate, and the output end of the second AND gate is connected to the SRAM memory; the temperature compensation code generating circuit is used to detect the temperature of the SRAM memory and generate a temperature compensation code; the first AND gate is used to perform an AND operation on a read / write signal and a clock signal to generate a read / write control signal; and the delay chain circuit is used to delay the read / write control signal. The present application couples the clock signal and the read / write signal through a first AND gate, delays the coupled signal through a delay chain circuit, and then directly generates a timing signal, i.e., a word line control signal, through a second AND gate to achieve timing control of the SRAM. Moreover, the temperature compensation code generation circuit of the present application can generate different temperature compensation codes at different temperatures, and the delay chain circuit can adjust the delay length according to the temperature compensation code, thereby enabling different delay lengths to be selected to adjust the read / write control signal at different temperatures, so that when the operating temperature of the SRAM memory changes, the timing of the circuit is dynamically adjusted in a timely manner, thereby improving the performance and stability of the SRAM. In addition, the adaptive timing control circuit of the present application has a simple structure and fewer components, which reduces the impact of temperature on device performance, and further reduces the impact of temperature on the performance of the SRAM memory. The adaptive timing control circuit can be quickly adjusted according to system requirements, thereby improving the flexibility and response speed of the system.

[0018] In a second aspect, the present invention further provides an adaptive timing control method applied to an SRAM memory, applying the adaptive timing control circuit applied to the SRAM memory, and the adaptive timing control method applied to the SRAM memory includes:

[0019] Acquire the read / write signal, the clock signal, and the temperature of the SRAM memory, and generate a temperature compensation code according to the temperature;

[0020] Performing an AND operation on the read / write signal and the clock signal to obtain a read / write control signal;

[0021] Determine a target delay unit according to the temperature compensation code, and output a signal output by the target delay unit to obtain a delay control signal; the target delay unit is used to delay the read / write control signal;

[0022] An AND operation is performed on the delay control signal and the read / write control signal to obtain a word line control signal, and the word line control signal is used to perform read / write control on the SRAM memory.

[0023] Optionally, when the read / write signal is a read signal, the read / write control signal is a read enable signal, and after performing an AND operation on the delay control signal and the read / write control signal to obtain a word line control signal, the method further includes:

[0024] Using an inverter to process the word line control signal to obtain an inverted control signal;

[0025] An AND operation is performed on the inverted control signal and the read enable signal to obtain a precharge control signal; the precharge control signal is used to control the charging time of the bit line and the complementary bit line of the SRAM memory.

[0026] Compared with the prior art, the beneficial effects of the adaptive timing control method applied to SRAM memory provided by the present invention are the same as the beneficial effects of the adaptive timing control circuit applied to SRAM memory described in the above technical solution, and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0028] Figure 1 A schematic structural diagram of an adaptive timing control circuit applied to an SRAM memory provided by the present invention;

[0029] Figure 2 A schematic diagram of signal delay provided by the present invention;

[0030] Figure 3 A schematic structural diagram of a temperature compensation code generating circuit provided by the present invention;

[0031] Figure 4 A schematic structural diagram of the delay unit provided by the present invention;

[0032] Figure 5 A schematic structural diagram of a time-delay inverter provided by the present invention;

[0033] Figure 6 A schematic diagram of the delay chain circuit structure corresponding to the four-to-one selector provided by the present invention;

[0034] Figure 7 The present invention provides a flow chart of an adaptive timing control method applied to an SRAM memory.

[0035] Reference numerals:

[0036] 1-temperature compensation code generation circuit, 11-temperature detection circuit, 12-reference source, 13-multi-path compensation code generation circuit, 2-timing compensation circuit, 21-first AND gate, 22-delay chain circuit, 23-second AND gate, 24-inverter, 25-third AND gate, 221-four-to-one selector, 222-first delay unit, 223-second delay unit, 224-third delay unit, 225-fourth delay unit, 31-first standard inverter, 32-first delayed inverter, 33-second delayed inverter, 34-second standard inverter, M1-first transistor, M2-second transistor. DETAILED DESCRIPTION

[0037] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0038] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0039] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0040] Traditional SRAM timing control circuits often use fixed delay chains. When the operating temperature of the SRAM chip changes, in systems that require fast response, the non-adjustability of the fixed delay chain limits the system's flexibility and response speed, resulting in unstable SRAM performance under different operating conditions, affecting data reliability and system efficiency.

[0041] To solve the above problems, the present invention provides an adaptive timing control circuit and method for SRAM memory, which will be described below with reference to the accompanying drawings.

[0042] See also Figure 1 , the present invention provides an adaptive timing control circuit for SRAM memory, comprising: a temperature compensation code generating circuit 1 and a timing compensation circuit 2;

[0043] The timing compensation circuit 2 includes at least a first AND gate 21, a delay chain circuit 22 and a second AND gate 23; the output end of the first AND gate 21 is connected to the data input end of the delay chain circuit 22 and the first input end of the second AND gate 23, the data selection end of the delay chain circuit 22 is connected to the output end of the temperature compensation code generation circuit 1, the output end of the delay chain circuit 22 is connected to the second input end of the second AND gate 23, and the output end of the second AND gate 23 is connected to the SRAM memory. Optionally, the output end of the second AND gate 23 can be directly connected to the word line of the SRAM memory.

[0044] The temperature compensation code generation circuit is used to detect the temperature of the SRAM memory and generate a temperature compensation code; the first AND gate is used to perform an AND operation on the read / write signal and the clock signal to generate a read / write control signal; the delay chain circuit is used to delay the read / write control signal. The higher the temperature, the longer the delay time, and vice versa. The second AND gate is used to perform an AND operation on the delayed signal and the read / write control signal to generate a word line control signal. The word line control signal is used to perform read and write control on the SRAM memory.

[0045] During the read operation, the opening and closing timing of the word line directly affects the reliability and speed of the read. At the same time, since temperature changes can affect circuit performance, the precharge time, that is, the PC time, also needs to be adjusted accordingly. The word line must be turned on after the precharge is completed, otherwise it will cause read failure. For example, at high temperatures, the PMOS charging time slows down, so the PC time needs to be extended. Otherwise, the BL / BLB will not be charged enough, affecting the read stability. In order to make the precharge time adaptively adjusted according to the temperature, such as Figure 1As shown, the timing compensation circuit 2 may further include an inverter 24 and a third AND gate 25. The input of the inverter 24 is connected to the output of the second AND gate 23, the output of the inverter 24 is connected to the first input of the third AND gate 25, the second input of the third AND gate 25 is connected to the output of the first AND gate 21, and the output of the third AND gate 25 may be directly connected to the bit line and complementary bit line of the SRAM memory, or indirectly connected through other logic circuits. The arrangement of the inverter and the third AND gate ensures that the precharge time is determined by the delay length of the delay chain circuit. The circuit composed of the inverter and the third AND gate is used to generate a precharge control signal, which is used to control the charging time of the bit line and complementary bit line of the SRAM memory, so that the word line WL is turned on after the precharge of the SRAM memory is completed.

[0046] In a specific implementation, the first AND gate performs an AND operation on the clock signal and the read / write signal to obtain a read / write control signal. The temperature compensation code generation circuit generates a temperature compensation code according to the operating temperature of the SRAM memory. The delay chain circuit delays the read / write control signal according to the temperature compensation code. The third AND gate performs an AND operation on the delayed signal and the read / write control signal to output a word line control signal. The word line control signal controls the opening and closing of the word line of the SRAM memory, thereby controlling the SRAM memory to perform read and write operations. Specifically, Figure 2 As shown, when the read / write signal is a read signal READ, the first AND gate outputs a read enable signal READ_EN. The delay chain circuit delays READ_EN according to the temperature compensation code. The delayed signal passes through the second AND gate to output the word line control signal WL. The signal output by the second AND gate passes through an inverter and a third AND gate. The third AND gate outputs the precharge control signal PC. The charging time td of the PC signal is the same as the delay time of the READ_EN signal. When the read / write signal is a write signal, the first AND gate outputs a write enable signal. The delay chain circuit delays the write enable signal according to the temperature compensation code. The second AND gate outputs the word line control signal corresponding to the write operation to control the write operation of the SRAM memory. When the read / write signal is a write signal, no signal passes through the inverter and the third AND gate.

[0047] Based on the above circuit structure and specific implementation methods, the present invention provides an adaptive timing control circuit for an SRAM memory that combines a clock signal and a read / write signal through a first AND gate, delays the combined signal through a delay chain circuit, and then directly generates a timing signal, namely a word line control signal, through a second AND gate to achieve timing control of the SRAM. Furthermore, a temperature compensation code generation circuit can dynamically adjust timing control parameters according to temperature changes, thereby improving the reliability of the SRAM under different operating conditions, including extreme temperatures. A delay chain circuit with a configurable delay length can adjust the delay length according to the temperature compensation code, optimize the timing of read and write operations, improve the read and write speed of the SRAM memory, and reduce unnecessary power consumption, especially in low-power mode, while ensuring operational correctness. In addition, the adaptive timing control circuit of the present application has a simple structure and fewer components, which reduces the impact of temperature on device performance, further reducing the impact of temperature on the performance of the SRAM memory. The configuration of the inverter and the third AND gate can ensure that the word line is turned on after precharging is completed, thereby improving the stability of the SRAM memory read operation.

[0048] See also Figure 3 The temperature compensation code generation circuit 1 may include a temperature detection circuit 11, a multi-channel compensation code generation circuit 13, and a reference source 12. The temperature detection circuit 11 and the reference source 12 are connected to the multi-channel compensation code generation circuit 13. The temperature detection circuit 11 is used to detect the temperature of the SRAM memory and output a detection voltage; the reference source 12 is used to provide a reference voltage; and the multi-channel compensation code generation circuit 13 is used to compare the reference voltage with the detection voltage and generate a temperature compensation code. The temperature detection circuit 11 may be a temperature sensor or other circuit that can be used to detect the operating temperature of the SRAM memory, and the multi-channel compensation code generation circuit 13 may be a comparator or other circuit that can be used to compare the detection voltage with the reference voltage and output a temperature compensation code.

[0049] As an optional approach, a delay chain circuit includes a multiple-choice selector and multiple delay units connected in series. The outputs of the multiple delay units are connected to the data input of the multiple-choice selector, and the data selection terminal of the multiple-choice selector is connected to the output of the temperature compensation code generation circuit. Different delay units provide different delay lengths. The more delay units there are, the more selectable delay lengths there are. The advantage of the delay chain circuit lies in its flexibility and scalability. The length and delay range of the delay chain can be increased by adding more delay units and the number of data inputs of the multiple-choice selector.

[0050] The delay unit includes two standard inverters and two delayed inverters, the two delayed inverters are connected and arranged between the two standard inverters; the two standard inverters are as follows: Figure 4The first standard inverter 31 and the second standard inverter 34 are shown, and the two delayed inverters are as shown in FIG. Figure 4 In the first delayed inverter 32 and the second delayed inverter 33, the width-to-length ratio of the components in the standard inverter is inversely proportional to the width-to-length ratio of the components in the delayed inverter. The delay duration of the delayed inverter is longer than that of the standard inverter, and fewer inverters can be used to provide a more stable delay duration.

[0051] See also Figure 5 The delay inverter includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is coupled to an input signal A, the source of the first transistor M1 is coupled to a power supply, the drain of the first transistor M1 and the drain of the second transistor M2 are coupled to an output signal X, the gate of the second transistor M2 is coupled to the input signal A, and the source of the second transistor M2 is coupled to ground. It should be noted that the input signal A and the output signal X are the signals corresponding to the current delay inverter, and different delay inverters correspond to different input signals and output signals.

[0052] The above-mentioned multiple-choice selector can be a four-choice selector, a six-choice selector, or an eight-choice selector. The number of delay units is related to the type of the multiple-choice selector.

[0053] See also Figure 6 When the multi-select selector is a four-select selector 221, the delay unit includes a first delay unit 222, a second delay unit 223, a third delay unit 224, and a fourth delay unit 225. The first delay unit 222, the second delay unit 223, and the third delay unit 224 are connected in series. The input of the first delay unit 222 is connected to the output of the first AND gate. The output of the first delay unit 222 is connected to the first data input D0 of the four-select selector. The output of the second delay unit 223 is connected to the second data input D1 of the four-select selector. The output of the third delay unit 224 is connected to the third data input D2 of the four-select selector. The output of the fourth delay unit 225 is connected to the fourth data input D3 of the four-select selector. The data selection terminals S0 and S1 of the four-select selector are connected to the output of the multi-path compensation code generation circuit. Optionally, the selection signal of the four-select selector can also be manually controlled.

[0054] In actual applications, by changing the control signal received by the data selection end of the multi-selector, the multi-selector can select the signal output of different data input ends, thereby realizing the control of the output signal delay. For example, when the multi-selector is a four-selector, when the temperature compensation code is "00", the four-selector selects the output of the first delay unit for output, when the temperature compensation code is "01", the four-selector selects the output of the second delay unit for output, when the temperature compensation code is "10", the four-selector selects the output of the third delay unit for output, and when the temperature compensation code is "11", the four-selector selects the output of the fourth delay unit for output.

[0055] Based on the above structure, the present invention further provides an adaptive timing control method applied to an SRAM memory, which is applied to the adaptive timing control circuit applied to the SRAM memory.

[0056] See also Figure 7 , the adaptive timing control method applied to SRAM memory includes the following steps:

[0057] Step 701: Acquire a read / write signal, a clock signal, and the temperature of the SRAM memory, and generate a temperature compensation code according to the temperature;

[0058] Step 702: performing an AND operation on the read / write signal and the clock signal to obtain a read / write control signal;

[0059] Step 703: determining a target delay unit according to the temperature compensation code, and outputting a signal output by the target delay unit to obtain a delay control signal; the target delay unit is used to delay the read / write control signal;

[0060] Step 704: performing an AND operation on the delay control signal and the read / write control signal to obtain a word line control signal, wherein the word line control signal is used to perform read / write control on the SRAM memory.

[0061] As an optional manner, when the read / write signal is a read signal, the read / write control signal is a read enable signal, and after performing an AND operation on the delay control signal and the read / write control signal to obtain a word line control signal, the method further includes:

[0062] Using an inverter to process the word line control signal to obtain an inverted control signal;

[0063] An AND operation is performed on the inverted control signal and the read enable signal to obtain a precharge control signal; the precharge control signal is used to control the charging time of the bit line and the complementary bit line of the SRAM memory.

[0064] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0065] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. An adaptive timing control circuit applied to an SRAM memory, characterized in that: include: Temperature compensation code generation circuit and timing compensation circuit; The timing compensation circuit at least includes a delay chain circuit, a first AND gate, and a second AND gate; the output end of the first AND gate is connected to the data input end of the delay chain circuit and the first input end of the second AND gate, the data selection end of the delay chain circuit is connected to the output end of the temperature compensation code generation circuit, the output end of the delay chain circuit is connected to the second input end of the second AND gate, and the output end of the second AND gate is connected to the SRAM memory; The temperature compensation code generating circuit is used to detect the temperature of the SRAM memory and generate a temperature compensation code; the first AND gate is used to perform an AND operation on the read / write signal and the clock signal to generate a read / write control signal; the delay chain circuit is used to delay the read / write control signal.

2. The adaptive timing control circuit for SRAM memory according to claim 1, characterized in that: The timing compensation circuit also includes an inverter and a third AND gate, wherein the input end of the inverter is connected to the output end of the second AND gate, the output end of the second AND gate is connected to the word line of the SRAM memory, the output end of the inverter is connected to the first input end of the third AND gate, the second input end of the third AND gate is connected to the output end of the first AND gate, and the output end of the third AND gate is connected to the bit line and the complementary bit line of the SRAM memory.

3. The adaptive timing control circuit for SRAM memory according to claim 1, characterized in that: The delay chain circuit includes a multiple-selector and multiple delay units connected in series, the output ends of the multiple delay units are connected to the data input end of the multiple-selector, and the data selection end of the multiple-selector is connected to the output end of the temperature compensation code generating circuit.

4. The adaptive timing control circuit for SRAM memory according to claim 1, characterized in that: The delay unit includes two standard inverters and two delayed inverters, the two delayed inverters are connected and arranged between the two standard inverters; the delayed inverter includes a first transistor and a second transistor, the gate of the first transistor is coupled to the input signal, the source of the first transistor is coupled to the power supply, the drain of the first transistor is coupled to the drain of the second transistor, the gate of the second transistor is coupled to the input signal, and the source of the second transistor is coupled to the ground.

5. The adaptive timing control circuit for SRAM memory according to claim 1, characterized in that: The temperature compensation code generating circuit includes a temperature detection circuit, a multi-channel compensation code generating circuit and a reference source. The temperature detection circuit and the reference source are connected to the multi-channel compensation code generating circuit. The temperature detection circuit is used to detect the temperature of the SRAM memory and output a detection voltage. The reference source is used to provide a reference voltage. The multi-path compensation code generating circuit is used for comparing the reference voltage with the detection voltage and generating a temperature compensation code.

6. The adaptive timing control circuit for SRAM memory according to claim 3, characterized in that: The multiple-choice selector is a four-choice selector, a six-choice selector, or an eight-choice selector.

7. The adaptive timing control circuit for SRAM memory according to claim 6, characterized in that: When the multi-select selector is the four-select selector, the delay unit includes a first delay unit, a second delay unit, a third delay unit and a fourth delay unit. The first delay unit, the second delay unit, the third delay unit and the fourth delay unit are connected in series, the input end of the first delay unit is connected to the output end of the first AND gate, the output end of the first delay unit is connected to the first data input end of the four-select selector, the output end of the second delay unit is connected to the second data input end of the four-select selector, the output end of the third delay unit is connected to the third data input end of the four-select selector, and the output end of the fourth delay unit is connected to the fourth data input end of the four-select selector.

8. The adaptive timing control circuit for SRAM memory according to claim 7, characterized in that: When the multi-select selector is the four-select selector, when the temperature compensation code is "00", the four-select selector selects the output of the first delay unit for output; when the temperature compensation code is "01", the four-select selector selects the output of the second delay unit for output; when the temperature compensation code is "10", the four-select selector selects the output of the third delay unit for output; when the temperature compensation code is "11", the four-select selector selects the output of the fourth delay unit for output.

9. An adaptive timing control method applied to SRAM memory, characterized in that: The adaptive timing control circuit applied to an SRAM memory according to any one of claims 1 to 8 is applied, and the adaptive timing control method applied to the SRAM memory comprises: Acquire the read / write signal, the clock signal, and the temperature of the SRAM memory, and generate a temperature compensation code according to the temperature; Performing an AND operation on the read / write signal and the clock signal to obtain a read / write control signal; Determine a target delay unit according to the temperature compensation code, and output a signal output by the target delay unit to obtain a delay control signal; the target delay unit is used to delay the read / write control signal; An AND operation is performed on the delay control signal and the read / write control signal to obtain a word line control signal, and the word line control signal is used to perform read / write control on the SRAM memory.

10. The adaptive timing control method applied to SRAM memory according to claim 9, characterized in that: When the read / write signal is a read signal, the read / write control signal is a read enable signal, and after performing an AND operation on the delay control signal and the read / write control signal to obtain a word line control signal, the method further includes: Using an inverter to process the word line control signal to obtain an inverted control signal; An AND operation is performed on the inverted control signal and the read enable signal to obtain a precharge control signal; the precharge control signal is used to control the charging time of the bit line and the complementary bit line of the SRAM memory.

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