SRAM memory unit
By setting independent write operation lines and read operation lines in the SRAM memory cell, the problem of poor read data stability of traditional 6T-SRAM is solved, and higher read data stability and noise resistance are achieved.
Patent Information
- Application Number
- CN202510705993.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-09-12
AI Technical Summary
Traditional 6T-SRAM memory cells use the same set of operating lines for read and write operations, resulting in the storage node voltage being partially pulled down during reading, causing destructive reading, reducing data stability, and having a low read static noise margin, making it susceptible to noise and causing unexpected data flipping.
Independent write and read lines are set in the memory cell to control data writing and reading operations respectively, avoiding interference of read data operations on storage nodes and improving read stability.
By separately controlling the read and write operation lines, the stability and noise resistance of the read data are improved, accidental data flipping is avoided, and the stability of the read data is improved.
Smart Images
Figure CN120636498A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of static random access memory (SRAM), in particular to an SRAM memory unit. Background Art
[0002] SRAM (Static Random Access Memory) is a volatile memory whose basic structure stores data using a bistable flip-flop circuit composed of six transistors. As long as the power is maintained, the data is stably stored, without the need for periodic refreshes like DRAM (Dynamic Random Access Memory). Its operating principle is to use the two stable states (0 or 1) of the flip-flop to store data. Read and write operations select the corresponding cell through an address decoder, and data is directly accessed. However, traditional 6T-SRAM uses the same set of operating lines (WL) for read and write operations, resulting in the storage node voltage being partially pulled down during reads, causing destructive reads, reducing data stability, and increasing the risk of noise interference, especially in nanometer processes. Furthermore, the read static noise margin (SNM) of 6T-SRAM is low, making it more susceptible to noise during the data read process, resulting in unexpected data flips. This results in poor read data stability in existing 6T-SRAM memory cells.
[0003] In view of this, there is an urgent need to design a more advanced memory cell to solve the problem of poor data reading stability of the 6T-SRAM memory cell in the prior art. Summary of the Invention
[0004] The object of the present invention is to provide an SRAM memory cell, in which a write operation line for controlling a write data module to write data and a read operation line for controlling a read data module to read data are set. This realizes separate control of the read and write operation lines of the memory cell, thereby avoiding interference of the read data operation on the storage node and improving the reading stability; at the same time, it also improves the ability to resist noise influence during the data reading process, avoiding accidental data flipping and affecting the stability of the read data.
[0005] In order to achieve the above object, the present invention provides the following technical solutions:
[0006] The present invention provides an SRAM memory cell, which may at least include:
[0007] Data storage module, data writing module and data reading module;
[0008] The data storage module is connected to the data writing module and the data reading module respectively;
[0009] The data writing module is connected to the write operation line and the bit line respectively; the write operation line is used to control the data writing module to write data;
[0010] The data reading module is connected to the bit line and the read operation line respectively; the read operation line is used to control the data reading module to read data.
[0011] Preferably, the data storage module may include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor;
[0012] The source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, and the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor; the source of the first NMOS transistor is grounded;
[0013] The source of the second PMOS transistor is connected to the power supply terminal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor; the source of the second NMOS transistor is grounded.
[0014] Preferably, the data writing module may include a third NMOS transistor;
[0015] The gate of the third NMOS transistor is connected to the write operation line, the drain of the third NMOS transistor is connected to the gate of the first PMOS transistor, and the source of the third NMOS transistor is connected to the bit line.
[0016] Preferably, the data reading module may include a fourth NMOS transistor and a fifth NMOS transistor;
[0017] The gate of the fourth NMOS transistor is connected to the drain of the first PMOS transistor, the drain of the fourth NMOS transistor is connected to the bit line, and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor;
[0018] The gate of the fifth NMOS transistor is connected to the read operation line, and the source of the fifth NMOS transistor is grounded.
[0019] Preferably, when the memory unit is in a hold state, the levels corresponding to the write operation line and the read operation line are low levels, and the third NMOS transistor and the fifth NMOS transistor are turned off.
[0020] Preferably, when the memory unit is in a write operation state, the level corresponding to the write operation line is a high level, and the third NMOS tube is turned on; when the read operation of the memory unit is completed, the level corresponding to the write operation line is a low level.
[0021] Preferably, when the memory unit is in a read operation state, the bit line is precharged, the voltage corresponding to the read operation line is high, and the fifth NMOS transistor is turned on.
[0022] Preferably, when the data of the first storage node is 1, the data of the second storage node is 0, and the fourth NMOS transistor is turned off.
[0023] Preferably, when the data of the first storage node is 0, the data of the second storage node is 1, and the fourth NMOS transistor and the fifth NMOS transistor are turned on.
[0024] Compared with the prior art, the memory unit provided by the present invention is provided with a data storage module, a write data module and a read data module; the data storage module is connected to the write data module and the read data module respectively; and the write data module is connected to the write operation line and the bit line respectively, and the read data module is connected to the bit line and the read operation line respectively, wherein the write operation line is used to control the write data module to write data, and the read operation line is used to control the read data module to read data; based on this, the write operation line can be used to control the write data module to write data, and the read operation line can be used to control the read data module to read data, thereby realizing separate control of the read and write operation lines of the memory unit, thereby avoiding interference of the read data operation on the storage node and improving the reading stability; at the same time, the anti-noise effect capability during the data reading process is also improved, avoiding accidental data flipping and affecting the stability of the read data; and solving the problem of poor read data stability of the 6T-SRAM memory unit in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0026] Figure 1 Schematic diagram of the 6T-SRAM structure in the prior art;
[0027] Figure 2 This is a structural schematic diagram of an SRAM memory unit provided by the present invention.
[0028] Reference numerals: 210 - data storage module, 220 - write data module, 230 - read data module, WL - write operation line, BL - bit line, RL - read operation line, Q - first storage node, QB - second storage node. DETAILED DESCRIPTION
[0029] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the embodiments of the present invention use terms such as "first" and "second" to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order of precedence. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily define differences.
[0030] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0031] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the preceding time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.
[0032] Among existing technologies, 6T-SRAM has significant advantages over DRAM. 6T-SRAM uses a six-transistor bistable trigger structure, which does not require periodic refresh like DRAM, resulting in greater data stability and simpler circuit design. Secondly, its access speed is faster, with typical latency as low as below 20ns, far exceeding the tens to hundreds of nanoseconds of DRAM, making it particularly suitable for scenarios with stringent speed requirements. Its static power consumption is extremely low, consuming almost no energy in the non-reading or writing state, while DRAM requires continuous refresh even in standby mode, consuming higher power. In addition, SRAM's bistable characteristics make it more resistant to interference and more reliable in data storage. Based on these advantages, SRAM is widely used in CPU caches, embedded systems, and high-performance devices. Despite its high cost and limited capacity, its outstanding performance in speed, stability, and energy efficiency make it an indispensable memory type in high-speed data processing scenarios.
[0033] However, traditional 6T-SRAM uses the same set of operating lines WL for both read and write operations, which results in the storage node voltage being partially pulled down during reading, causing destructive reading, reducing data stability, and increasing the risk of noise interference, which is particularly significant in nanometer processes. For details, please refer to Figure 1 , Figure 1 Schematic diagram of the 6T-SRAM structure in the prior art; Figure 1 In the data storage structure, transistors P1, P2, N1, and N2 form the read and write operation lines. This will cause the storage node voltage to be partially pulled down during reading, causing destructive reading and reducing the stability of read data. In addition, the 6T-SRAM has a low read static noise margin (SNM), which is more susceptible to noise during the data reading process, resulting in unexpected data flipping, further affecting the stability of read data.
[0034] In view of this, the present invention provides an SRAM memory cell, in which a write operation line for controlling a write data module to write data, and a read operation line for controlling a read data module to read data are set. This realizes separate control of the read and write operation lines of the memory cell, thereby avoiding interference of the read data operation on the storage node and improving the stability of the read data; at the same time, it can avoid accidental data flipping, further improving the stability of the read data.
[0035] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:
[0036] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of an SRAM memory cell provided by the present invention. It should be noted that, Figure 2 For a memory cell based on 7T-SRAM, in actual applications, more transistors can also be used to form an SRAM structure, such as an SRAM structure composed of eight transistors or ten transistors. As long as the read and write operation lines of the memory cell are controlled separately, interference with the storage node during the data read operation can be avoided, thereby improving the stability of the memory cell reading data.
[0037] exist Figure 2 In the embodiment, the memory unit may include at least: a data storage module 210 , a data writing module 220 and a data reading module 230 .
[0038] The data storage module 210 is connected to the data writing module 220 and the data reading module 230 respectively.
[0039] The data writing module 220 is connected to the write operation line WL and the bit line BL respectively; the write operation line WL is used to control the data writing module 220 to write data.
[0040] The data reading module 230 is connected to the bit line BL and the read operation line RL respectively; the read operation line RL is used to control the data reading module 230 to read data.
[0041] Based on this, the memory unit provided by the present invention can use the write operation line to control the write data module to write data, and use the read operation line to control the read data module to read data, thereby realizing separate control of the read and write operation lines of the memory unit, thereby avoiding interference of the read data operation on the storage node and improving the reading stability; at the same time, it also improves the ability to resist noise influence during the data reading process, avoiding accidental data flipping and affecting the stability of the read data; and solves the problem of poor read data stability of the 6T-SRAM memory unit in the prior art.
[0042] Preferably, the data storage module 210 may include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor.
[0043] Specifically, the source of the first PMOS tube can be connected to the power supply terminal V DD The drain of the first PMOS tube is connected to the drain of the first NMOS tube, the gate of the first PMOS tube is connected to the gate of the first NMOS tube, and the gate of the first PMOS tube is connected to the drain of the second PMOS tube; the source of the first NMOS tube is grounded.
[0044] Furthermore, the source of the second PMOS tube is connected to the power supply terminal V DD The drain of the second PMOS tube is connected to the drain of the second NMOS tube, the gate of the second PMOS tube is connected to the gate of the second NMOS tube, and the gate of the second PMOS tube is connected to the drain of the first PMOS tube; the source of the second NMOS tube is grounded.
[0045] Based on this, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are used to form two cross-coupled inverters as a data storage module, forming the following Figure 2 The first storage node Q and the second storage node QB are shown in , so that data can be maintained through positive feedback using the first storage node Q and the second storage node QB.
[0046] Preferably, the data writing module 220 may include a third NMOS transistor.
[0047] Specifically, the gate of the third NMOS transistor can be connected to the write operation line WL, the drain of the third NMOS transistor can be connected to the gate of the first PMOS transistor, and the source of the third NMOS transistor can be connected to the bit line BL. Figure 2 The write data path of the write data module 220 is shown to implement data writing to the memory cell.
[0048] Preferably, the data reading module 230 may include a fourth NMOS transistor and a fifth NMOS transistor.
[0049] Specifically, the gate of the fourth NMOS transistor can be connected to the drain of the first PMOS transistor, the drain of the fourth NMOS transistor can be connected to the bit line BL, and the source of the fourth NMOS transistor can be connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor can be connected to the read operation line RL, and the source of the fifth NMOS transistor can be grounded. The control signals corresponding to the read operation line RL and the write operation line WL are different dynamic control signals. Based on this, the following is constructed: Figure 2 The read data path of the read data module 230 shown is composed of a fourth NMOS transistor and a fifth NMOS transistor connected in series. The source end of the fourth NMOS transistor is connected to the bit line BL, and the gate end of the fourth NMOS transistor is also connected to the second storage node QB, so that the read operation line RL can be used to control the on and off of the read circuit based on the internal data in the memory cell.
[0050] In summary, the circuit structure corresponding to the 7T-SRAM memory cell provided by the present invention has lower static power consumption, dynamic control signals reduce redundant current, and independent read paths reduce standby power consumption. In addition, the use of optimized transmission gates and auxiliary circuits can shorten read and write delays. In addition, the separation of read and write paths can effectively avoid read-destructive effects and have higher stability.
[0051] It should be noted that in practical applications, the aspect ratio or number of transistors can be changed, or SRAM prepared by a more advanced process can be used to replace Figure 2 The transistor shown in ; thereby, the stability of reading data can be further improved.
[0052] Furthermore, the improved 7T-SRAM memory cell provided by the present invention has the following three working states:
[0053] 1. Maintain status
[0054] When the memory unit is in the hold state, the levels corresponding to the write operation line and the read operation line are low, and the third NMOS transistor and the fifth NMOS transistor are turned off.
[0055] Specifically, in the hold state, the write operation line WL and the read operation line RL are both pulled down to a low level 0, the third NMOS transistor and the fifth NMOS transistor are turned off, the read and write paths are both disconnected, and the internal data in the memory cell is held; thereby achieving data retention in the memory cell.
[0056] 2. Write operation status
[0057] When the memory cell is in a write operation state, the level corresponding to the write operation line is high, and the third NMOS tube is turned on; when the read operation of the memory cell is completed, the level corresponding to the write operation line is low.
[0058] Specifically, when performing a write operation, the potential of the write operation line WL is pulled up to V DD At this time, the third NMOS tube is turned on, and data is written through the bit line BL, changing the internal node state. After the write operation is completed, the write operation line WL returns to the low level state; thereby realizing the writing of data into the memory cell.
[0059] 3. Read operation status
[0060] When the memory cell is in a read operation state, the bit line is precharged, the voltage corresponding to the read operation line is high, and the fifth NMOS transistor is turned on. When the data of the first storage node is 1, the data of the second storage node is 0, and the fourth NMOS transistor is turned off. When the data of the first storage node is 0, the data of the second storage node is 1, and the fourth and fifth NMOS transistors are turned on.
[0061] Specifically, during a read operation, the bit line BL is first precharged, and then the read operation line RL is turned on. At this point, the fifth NMOS transistor is turned on. If the data at the first storage node Q is "1," the data at the second storage node QB is "0," and the fourth NMOS transistor, controlled by the second storage node QB, is turned off. At this point, because there is no discharge path from the bit line BL to ground, the bit line BL remains at a high level, VDD. If the data at the first storage node Q is "0," the data at the second storage node QB is "1," and the fourth NMOS transistor, controlled by the second storage node QB, is turned on. That is, the fourth and fifth NMOS transistors are turned on, forming a discharge path, pulling the bit line BL down to a low level, "0."
[0062] Based on this, the present invention provides an SRAM memory cell that realizes separate control of the read and write lines, thereby avoiding interference of the read operation on the storage node and improving the stability of the read data.
[0063] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0064] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.
Claims
1. An SRAM memory cell, characterized in that At least: Data storage module, data writing module and data reading module; The data storage module is connected to the data writing module and the data reading module respectively; The data writing module is connected to the write operation line and the bit line respectively; the write operation line is used to control the data writing module to write data; The data reading module is connected to the bit line and the read operation line respectively; the read operation line is used to control the data reading module to read data.
2. The memory cell according to claim 1, wherein The data storage module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor; The source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, and the gate of the first PMOS transistor is connected to the drain of the second PMOS transistor; the source of the first NMOS transistor is grounded; The source of the second PMOS transistor is connected to the power supply terminal, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor; the source of the second NMOS transistor is grounded.
3. The memory cell according to claim 2, wherein The data writing module includes a third NMOS tube; The gate of the third NMOS transistor is connected to the write operation line, the drain of the third NMOS transistor is connected to the gate of the first PMOS transistor, and the source of the third NMOS transistor is connected to the bit line.
4. The memory cell according to claim 2, wherein The data reading module includes a fourth NMOS transistor and a fifth NMOS transistor; The gate of the fourth NMOS transistor is connected to the drain of the first PMOS transistor, the drain of the fourth NMOS transistor is connected to the bit line, and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor; The gate of the fifth NMOS transistor is connected to the read operation line, and the source of the fifth NMOS transistor is grounded.
5. The memory cell according to claim 4, wherein When the memory unit is in the hold state, the levels corresponding to the write operation line and the read operation line are low, and the third NMOS transistor and the fifth NMOS transistor are turned off.
6. The memory cell according to claim 4, wherein When the memory unit is in a write operation state, the level corresponding to the write operation line is a high level, and the third NMOS transistor is turned on; when the read operation of the memory unit is completed, the level corresponding to the write operation line is a low level.
7. The memory cell according to claim 4, wherein When the memory cell is in a read operation state, the bit line is precharged, the voltage corresponding to the read operation line is high, and the fifth NMOS transistor is turned on.
8. The memory cell according to claim 7, wherein When the data of the first storage node is 1, the data of the second storage node is 0, and the fourth NMOS transistor is turned off.
9. The memory cell according to claim 7, wherein When the data of the first storage node is 0, the data of the second storage node is 1, and the fourth NMOS transistor and the fifth NMOS transistor are turned on.