Electrical device for high voltage applications

Abstract

The invention provides an electrical device for high voltage applications. The present invention relates to an electrical device (100) comprising a capacitor, comprising: a bottom electrode (110) comprising a conductive structure having a base surface (BS) and a protruding wall (111), in which the base surface (BS) of the conductive structure of the bottom electrode (110) is lower than a top surface of the protruding wall (111), and the base surface (BS) surrounds the protruding wall (111); a dielectric structure (120), the dielectric structure (120) extending conformally over the bottom electrode (110); a top electrode (130) extending conformally over the dielectric structure (120) and comprising a stack of layers comprising a first conductive layer (131) and a second conductive layer (132), where the second conductive layer (132) has an opposite mechanical stress compared to the mechanical stress caused by the first conductive layer (131) and the dielectric structure (120).

Description

Technical Field

[0001] The present invention relates to the field of electrical devices, and more particularly to capacitive devices for use in high voltage applications. Background Art

[0002] In order to provide high energy storage density, capacitors with three-dimensional (3D) capacitor structures have been developed. Typically, such 3D capacitor structures are conformally formed on reliefs (e.g., holes, cavities, trenches, or pillars) and provide a large specific surface area for a given component size.

[0003] Using electrical components with 3D capacitor structures for high voltage applications (e.g., exceeding 400 V, 600 V, 900 V, or 1200 V) requires adapting them to the specific characteristics and limitations of these applications. In particular, 3D capacitor structures with significantly thicker dielectric layers are required to withstand high voltages.

[0004] However, when using semiconductor wafers to manufacture electrical components with 3D capacitor structures for high-voltage applications, significant wafer bow has been observed. That is, a significant vertical deviation is observed between the center of the wafer and the edge of the wafer. Such wafer bow has several negative consequences. In particular, the wafer can bend to the point where it can no longer be manipulated by robotic tools (the robotic handling limit is typically around ±150 μm of bow), which can lead to manufacturing interruptions.

[0005] Wafer bowing and its negative consequences have long been an obstacle to manufacturing electronic components with high energy storage density for high-voltage applications. One solution envisioned in the current state of the art to reduce wafer bowing is to use a larger distance between the reliefs of the 3D capacitor structure. However, this solution inevitably leads to a reduction in energy storage density.

[0006] Therefore, there is a need for a solution that enables the fabrication of electrical devices having high energy storage density and suitable for high voltage applications while limiting wafer bowing. Summary of the Invention

[0007] The present invention has been made in view of the above problems.

[0008] According to one aspect The present invention provides an electrical device including a capacitor, the electrical device comprising:

[0009] a bottom electrode, the bottom electrode comprising a conductive structure having a base surface and a protruding wall extending upward from the base surface, wherein the base surface of the conductive structure of the bottom electrode is lower than a top surface of the protruding wall and the base surface surrounds the protruding wall;

[0010] a dielectric structure extending conformally over the bottom electrode (which conforms to the protruding wall);

[0011] - a top electrode that extends conformally above the dielectric structure (it is conformal to the protruding wall covered by the dielectric structure) and comprises a stack of layers including a first conductive layer and a second conductive layer (i.e., the first conductive layer is above the second conductive layer in the stack, or the second conductive layer is above the first conductive layer in the stack), wherein the second conductive layer has an intrinsic mechanical stress that is opposite to the intrinsic mechanical stress caused by the first conductive layer and the dielectric structure.

[0012] The present invention proposes combining an open 3D structure and a multi-layer composite top electrode in order to limit wafer bowing during the fabrication of electrical devices.

[0013] In one aspect, the proposed electrical device utilizes an open 3D structure. To illustrate this structure, we consider an example in which the conductive structure of the bottom electrode is formed by a semiconductor substrate having a base surface and a protruding wall extending above the base surface of the substrate. Specifically, the base surface of the substrate is lower than the top surface of the protruding wall and surrounds the protruding wall. Thus, the protruding wall forms a protruding structure relative to the base surface of the substrate. The 3D capacitive structure of the electrical device is thus conformally formed on the protruding wall.

[0014] The 3D structure used in the proposed solution is called an open 3D structure. It differs from a 3D structure formed by recesses extending downward from the top surface of the substrate, which can be called a closed 3D structure. In contrast to a closed 3D structure, in which the substrate is generally thicker (except at the level of the recesses), an open 3D structure is generally thinner (except at the level of the protruding walls) and is therefore significantly less rigid.

[0015] In another aspect, the proposed electrical device utilizes a multilayer composite top electrode. More specifically, the second conductive layer exhibits an opposite mechanical tension compared to the mechanical tension induced by the first conductive layer and the dielectric structure. In other words, the second conductive layer counteracts the deformation induced by the first conductive layer and the dielectric structure.

[0016] The combination of an open 3D structure and a multilayer composite top electrode is particularly advantageous. Since the side with the open 3D structure is significantly less rigid, this allows the multilayer composite top electrode to control the deformation of the wafer.

[0017] The inventors have observed that the proposed solution leads to a significant reduction in wafer bow during the manufacture of the proposed electrical device, in particular after the electrode deposition step, which almost completely fills the open structure. By limiting the wafer bow, the proposed solution also ensures that the wafer can be handled by robotic tools (i.e., the wafer bow remains below the robotic handling limit).

[0018] For these reasons, the proposed solution allows the use of 3D capacitor structures with a large specific surface area (i.e., a dense 3D structure that yields high capacitance) and thick dielectrics, while ensuring that wafer bowing remains limited. Thus, the present invention provides an electrical device with a high energy storage density suitable for high voltage applications, while limiting wafer bowing during its manufacture.

[0019] In certain embodiments , a base surface of the conductive structure of the bottom electrode forms a continuous groove extending between and surrounding the protruding walls of the conductive structure.

[0020] In this embodiment, the base surface of the conductive structure forms a single continuous groove that not only separates the protruding walls of the conductive structure from each other but also surrounds the protruding walls. In other words, the single continuous groove extends between each pair of adjacent protruding walls and surrounds the protruding walls.

[0021] This embodiment proposes using an open 3D structure defined by continuous trenches to form a capacitor of an electrical device.Using such an open 3D structure formed by continuous trenches provides many electrical and mechanical improvements.

[0022] In particular, this embodiment provides a 3D structure with a large specific surface area and, therefore, an electrical device with a high energy storage density. The 3D structure proposed in this embodiment also exhibits low rigidity, which helps reduce mechanical stress within the structure and helps control wafer bowing.

[0023] In certain embodiments , the second conductive layer of the top electrode extends over the first conductive layer of the top electrode and seals the region (eg, trench) between the protruding walls.

[0024] In this embodiment, the second conductive layer of the top electrode seals the 3D structure. That is, the top surface of the second conductive layer is above the top surface of the protruding wall.

[0025] This embodiment is particularly advantageous from a manufacturing and electrical performance perspective. Specifically, by sealing the 3D structure, the second conductive layer protects the 3D structure and prevents it from being exposed to potentially damaging chemicals during subsequent manufacturing steps. It also advantageously provides a substantially flat surface on which additional layers can be easily deposited.

[0026] It should be noted that the areas (e.g., trenches) between the protruding walls can be completely or partially filled, both configurations being possible. These areas can be filled by the first conductive layer, with the second conductive layer extending above the first conductive layer. Alternatively, the first conductive layer can only partially fill the areas between the protruding walls, and the second conductive layer can fill these areas and seal the 3D structure. Finally, the second conductive layer can also seal the 3D structure while leaving unfilled spaces, i.e., gaps, between the protruding walls.

[0027] In certain embodiments , the second conductive layer of the top electrode seals the regions (eg, trenches) between the protruding walls, such that one or more spaces between the protruding walls remain unfilled.

[0028] In this embodiment, the first conductive layer only partially fills the areas (e.g., trenches) between the protruding walls. The second conductive layer extends over the first conductive layer to seal the 3D structure without filling the areas between the protruding walls. In other words, the second conductive layer seals the 3D structure while leaving unfilled spaces (i.e., gaps) between the protruding walls.

[0029] An advantage of this embodiment is that it prevents mechanical stress buildup within the 3D structure while sealing it for manufacturability and electrical performance considerations.

[0030] In certain embodiments , the first conductive layer of the top electrode includes polysilicon, and the second conductive layer of the top electrode includes tungsten and extends on the first conductive layer.

[0031] An advantage of this embodiment is that the proposed electrical device can be easily obtained using conventional manufacturing techniques. The use of a polysilicon layer (e.g., a low-stress polysilicon layer) is particularly advantageous because it can be easily deposited within the 3D structure using low-pressure chemical vapor deposition (LPCVD) and allows (completely or partially) filling the 3D structure. In addition, a tungsten layer (e.g., a tensile tungsten layer) can be easily deposited by chemical vapor deposition (CVD) and allows controlling mechanical stresses in the 3D structure and limiting wafer bowing. This embodiment allows significantly reducing wafer bowing while using conventional manufacturing techniques.

[0032] In certain embodiments , the second conductive layer of the top electrode is thinner than the first conductive layer of the top electrode.

[0033] This embodiment allows for the deposition of a first conductive layer conformal to the 3D structure to form the bulk of the top electrode, and then deposition of a thin second conductive layer to reduce wafer bow. This thin second conductive layer deposition is advantageous because it can be performed quickly and enables wafer bow to be significantly reduced.

[0034] In certain embodiments, the thickness of the second conductive layer of the top electrode is included between 50 nm and 1000 nm.

[0035] The inventors have observed that such an embodiment enables effective control of wafer bowing by using a second conductive layer of relatively small thickness. In other words, this embodiment allows a single deposition step (ie, rapid deposition) of a thin conductive layer to significantly reduce wafer bowing.

[0036] In certain embodiments , the conductive structure of the bottom electrode is (or includes) a silicon substrate. Alternatively, other embodiments can be envisioned in which other types of substrates or structures are used to form the bottom electrode.

[0037] In certain embodiments The electrical device is configured to be used with an operating voltage measured between the bottom electrode and the top electrode exceeding 400 V, 600 V, 900 V or 1200 V. For example, the proposed electrical device can be used as a decoupling or buffering capacitive element of a power electrical device.

[0038] According to another aspect , the present invention provides a method for manufacturing an electrical device including a capacitor, the method comprising:

[0039] - forming a bottom electrode including a conductive structure having a base surface and a protruding wall extending upward from the base surface, wherein the base surface of the conductive structure is lower than a top surface of the protruding wall and the base surface surrounds the protruding wall;

[0040] - conformally forming a dielectric structure over the bottom electrode; and

[0041] - conformally forming a top electrode over the dielectric structure, the top electrode comprising a stack of layers including a first conductive layer and a second conductive layer, wherein the second conductive layer has an intrinsic mechanical stress opposite to that of the first conductive layer and the dielectric structure.

[0042] The proposed manufacturing method may be adapted to obtain any of the electrical devices defined in the present disclosure.Furthermore, it should be noted that embodiments of the proposed method for manufacturing an electrical device present the advantages described with respect to embodiments of the proposed electrical device.

[0043] In certain embodiments , the proposed manufacturing method comprises a preliminary step of selecting the second conductive layer of the top electrode based on the following mechanical stresses: the intrinsic mechanical stress of the dielectric structure; and the intrinsic mechanical stress of the first conductive layer of the top electrode.

[0044] In certain embodiments The step of forming the bottom electrode includes etching a continuous trench extending between and surrounding the protruding walls.

[0045] In certain embodiments , the second conductive layer of the top electrode extends over the first conductive layer of the top electrode and seals the region between the protruding walls.

[0046] In certain embodiments , the first conductive layer of the top electrode includes polysilicon, and the second conductive layer of the top electrode includes tungsten and extends on the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Further features and advantages of the invention will become apparent from the following description of certain embodiments of the invention, given by way of example only and not by way of limitation, with reference to the accompanying drawings, in which:

[0048] Figures 1A to 1C An electrical device according to an embodiment outside the scope of the present invention and the evolution of wafer bow during the manufacture of the electrical device are shown;

[0049] Figures 2A to 2C An electrical device according to an embodiment of the present invention and the evolution of wafer bow during the manufacture of the electrical device are shown;

[0050] Figures 3A to 3E The steps of a method for manufacturing an electrical device according to an embodiment of the present invention are shown;

[0051] Figures 4A to 4C is a SEM image of a cross-sectional view of an electrical device according to an embodiment of the present invention; and

[0052] Figure 5 is a SEM image of the 3D structure of an electric device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] Embodiments of the present invention provide electrical devices suitable for high voltage applications and having high energy storage density. More specifically, embodiments of the present invention seek to limit wafer bowing when manufacturing such electrical devices.

[0054] The present invention is particularly applicable to electrical devices utilizing 3D capacitor structures formed using trenches. The following description of the present invention will relate to this specific application, which is given as an illustrative example only. The present invention is also applicable to 3D capacitor structures based on pillars.

[0055] Figures 1A to 1C An electrical device according to an embodiment outside the scope of the present invention and the evolution of the wafer bow during its manufacture are shown.These figures are described below to present the experiments and observations of the inventors on which the present invention relies.

[0056] Hereinafter, wafer bow is defined as the vertical deviation between the center of the wafer and the edge of the wafer. It characterizes the flatness of the wafer.

[0057] Figure 1A A side cross-sectional view of an electrical device X00 is shown according to an embodiment outside the scope of the present invention.

[0058] Figure 1A The electrical device X00 shown in FIG. 1 comprises a capacitor formed by a bottom electrode X10 and a top electrode X30 , which are separated by a dielectric structure X20 .

[0059] More specifically, the bottom electrode X10 includes a conductive structure having a base surface BS and a protruding wall X11 extending upward from the base surface BS. For example, the bottom electrode X10 may be formed by etching one or more trenches in a doped silicon substrate.

[0060] It should be emphasized that the base surface BS of the conductive structure of the bottom electrode X10 is lower than the top surface of the protruding wall X11 and the base surface BS surrounds the protruding wall X11. This conductive structure defines an open 3D structure with reduced rigidity. Such an open 3D structure is formed by Figure 5 is shown and described in further detail with reference to this figure.

[0061] The dielectric structure X20 shown in the figure conformally extends above the bottom electrode X10. It includes a first dielectric layer X21 (e.g., a SiO2 layer) and a second dielectric layer X22 (e.g., a Si3N4 layer). For high-voltage applications, the thickness of the dielectric structure X20 is typically better than 1 μm or 2 μm. Such a multilayer dielectric structure X20 can be advantageously adjusted for its dielectric strength and adhesion to the bottom electrode X10.

[0062] As for the top electrode X30 , it is here composed of a single conductive layer X31 (for example, a polysilicon layer) This layer X31 fills the area between the protruding walls X11 .

[0063] The structure shown here provides an electrical device X00 having a high energy storage density and suitable for high voltage applications. However, as shown in the following figures, the manufacture of this electrical device X00 results in significant wafer bowing.

[0064] Figure 1B The evolution of wafer bow during the manufacture of an electrical device X00 according to an embodiment outside the scope of the present invention is shown.

[0065] The figure shows the evolution of the wafer bow at the end of the different manufacturing steps of an electrical device X00. Step DIEL corresponds to the deposition of a dielectric structure X20, and steps PS1 to PS6 correspond to the successive deposition of materials for forming a top electrode X30. In experiments conducted by the inventors, the top electrode X30 was formed from a layer X31 of polycrystalline silicon deposited by LPCVD at approximately 600°C.

[0066] First, it should be noted that until the deposition of the dielectric structure X20 (step DIEL), the deformation of the wafer remains low and does not hinder the automated handling of the wafer. However, as more and more material is deposited to form the top electrode X30 (steps PS1 to PS6), the wafer bow gradually increases and eventually exceeds 150 μm at the end of the manufacturing process, which prevents the automated handling of the wafer.

[0067] The inventors' experiments have shown that when the top electrode X30 is thick enough to laterally bond to the sides of the 3D structure (i.e., bond to the protruding wall X11), the deformation of the wafer increases. When the wafer is then cooled to ambient temperature, the conductive layer X31 exhibits compressive stress and deforms the wafer into a convex shape (i.e., the center of the wafer is above its edge).

[0068] In other words, the conductive layer X31 acts as a "wedge" that applies a significant mechanical stress that deforms the wafer. Figure 1C The SEM image in shows that the top electrode fills the region between the protruding walls and acts as a wedge-shaped region.

[0069] The deformation of the wafer is primarily driven by its front side (and the protruding walls). The direction and magnitude of this deformation depend on the type of 3D structure used, the thickness and type of dielectric, the deposition technique used, and the temperature. As a result, the wafer may deform beyond the limits allowed for further processing by robotic tools (typically, around ±150 μm), which can lead to manufacturing interruptions.

[0070] Below we describe how the invention allows limiting wafer bowing when manufacturing electrical devices with high energy storage density and suitable for high voltage applications.

[0071] Figures 2A to 2C An electrical device according to an embodiment of the invention and the evolution of wafer bow during the manufacture of the electrical device are shown.These figures are described to introduce the invention and to present example embodiments.

[0072] Figure 2A A side cross-sectional view of an electrical device 100 according to an embodiment of the present invention is shown.

[0073] The electrical device 100 is distinguished from the previously presented electrical device X00 by its top electrode 130. The top electrode 130 of the electrical device 100 comprises a stack of layers including a first conductive layer 131 and a second conductive layer 132.

[0074] The second conductive layer 132 has an opposite intrinsic mechanical stress in contrast to the mechanical stress caused by the first conductive layer 131 and the dielectric structure 120. The use of such a multi-layer composite top electrode 130 allows limiting wafer bowing.

[0075] The stress direction (ie, compression or tension) of the second conductive layer 132 may be adjusted with respect to the intrinsic stress of the first conductive layer 131 and the intrinsic stress of the dielectric structure 120 .

[0076] From tungsten (W) with tensile stress to titanium nitride (TiN) with compressive stress, various strategies and stackings can be used depending on the deformation direction and the remaining space between the protruding walls 111 to be filled.

[0077] Figure 2B Shown is the wafer bow evolution during the fabrication of the electrical device 100. The figure illustrates the benefit of using the proposed multi-layer composite top electrode structure 130.

[0078] With previous reference Figures 1A to 1C In contrast to the manufacturing process described herein, the manufacturing process shown here does not end by performing a step PS6 of depositing material to form the first conductive layer 131. Instead, it ends with a different deposition step, referenced W, to form the second conductive layer 132.

[0079] In the experiment shown in FIG, the second conductive layer 132 is a tungsten (W) layer with tensile stress, and is used to compensate for the compressive stress caused by the first conductive layer 131 (which is made of polysilicon) and the dielectric structure 120 .

[0080] In these experiments, the temperature for depositing the polysilicon layer 131 was between 600° C. and 900° C., and the temperature for depositing the tungsten layer 132 was between 400° C. and 500° C. The intrinsic stress of the polysilicon layer 131 was between 10 MPa and 30 MPa, while the intrinsic stress of the tungsten layer was approximately 1 GPa. Here, the thickness of the polysilicon layer 131 was approximately 1000 nm (each of the PS1 to PS5 deposition steps corresponded to the deposition of 200 nm of polysilicon), and the thickness of the tungsten layer 132 was approximately 450 nm. However, the present invention is not limited to the specific values ​​used in these experiments, which are given here only by way of example.

[0081] like Figure 2B As shown in , the inventors' experiments have shown that combining a sparse 3D structure (with reduced stiffness) with a multilayer composite top electrode has many advantages. Most importantly, this leads to a significant reduction in wafer bow: Figure 1B The proposed solution allows limiting wafer deformation.

[0082] Furthermore, the use of the second conductive layer 132 not only reduces overall wafer deformation but also seals the 3D capacitor structure. Figure 2CAs shown in the SEM image of , the 3D capacitive structure is (e.g., completely) sealed by the second conductive layer 132. Here, sealed means that the area between the facing protruding walls 111 is enclosed at the level of their top surfaces by the second conductive layer 132. By sealing the 3D structure, the second conductive layer 132 prevents it from being exposed to potentially damaging chemicals during subsequent manufacturing steps.

[0083] By limiting wafer bending, the proposed solution allows the wafer to be handled by robotic tools.

[0084] The proposed solution thus allows obtaining an electrical device 100 having a high energy storage density (ie a dense 3D structure) and suitable for high voltage applications (ie having a thick dielectric) while limiting wafer bowing during the manufacture of the electrical device.

[0085] Above, we have described the structure of the proposed electrical device 100 and how it allows limiting wafer bending. We will now describe the method for manufacturing the electrical device 100 in further detail.

[0086] Figures 3A to 3E The steps of a method for manufacturing an electrical device according to an embodiment of the present invention are shown.

[0087] The method for manufacturing the proposed electrical device 100 comprises (all or part of) the following steps described hereinafter.

[0088] exist Figure 3A middle , shows a step in which a bottom electrode 110 is formed. The bottom electrode 110 includes a conductive structure having a base surface BS and facing protruding walls 111 extending upward from the base surface BS.

[0089] Specifically, the base surface BS of the conductive structure of the bottom electrode 110 is lower than the top surface of the protruding wall 111, and the base surface BS surrounds the protruding wall 111 (eg, Figure 5 ). The conductive structure defines an open 3D structure with reduced stiffness. We also refer to Figure 5 The structure is described in further detail.

[0090] The conductive structure 110 may be formed by etching a semiconductor substrate (e.g., a doped silicon substrate). The conductive structure 110 may also be formed from an etched substrate (e.g., a substrate comprising glass or a polymer material) including protruding walls 111 and a metal layer (or conductive layer) deposited so as to conformally extend over the etched substrate.

[0091] In certain embodiments, the base surface BS of the conductive structure 110 forms a single continuous trench (eg, a zigzag trench) that not only separates the protruding walls 111 from each other but also surrounds the protruding walls 111. Figure 5 This embodiment is described in further detail.Other embodiments are also envisaged in which the protruding wall 111 forms a plurality of individual grooves.

[0092] The protruding wall 111 can extend in a (substantially) linear or curved manner. In other words, the protruding wall 111 can have: a (substantially) linear shape; a curved shape, or a combination of linear shapes with turns / curves in between. In the case of curvature, to prevent a local increase in the electrostatic field in the capacitor, the radius of curvature of the curved protruding wall 111 can be greater than twice the thickness of the dielectric structure 120 (e.g., the thickness of the dielectric between the electrodes).

[0093] The corners (eg, each corner) of the protruding wall 111 may be rounded (eg, Figure 5 This allows the electrostatic field to be kept low in magnitude within the capacitor structure. For example, an isotropic dry etch can be used to consume the sharp edges of the protruding wall 111 after the preliminary wall has been formed.

[0094] exist Figure 3B middle , showing a step in which a dielectric structure 120 is formed on the bottom electrode 110.

[0095] Here, the dielectric structure 120 includes a first dielectric layer 121 and a second dielectric layer 122 conformally extending over the protruding wall.

[0096] For example, the first dielectric layer 121 may include silicon oxide (SiO2) and may be 1 μm or 2 μm thick. The second dielectric layer 121 may include silicon nitride (Si3N4) or aluminum oxide (Al2O3) and may be 1 μm or 2 μm thick. The advantage of such a double-layer dielectric structure is that it exhibits a high dielectric constant and strong adhesion to the bottom electrode 110.

[0097] Thus, forming dielectric structure 120 may include a step in which oxide layer 121 is formed by oxidizing conductive structure 110. Forming dielectric structure 120 may also include a step in which dielectric layer 122 is formed on conductive structure 110 using LPCVD or atomic layer deposition (ALD).

[0098] Within the scope of the present invention, embodiments are also envisaged in which the dielectric structure comprises a single dielectric layer or more than two dielectric layers.

[0099] exist Figure 3C middle , shows a step in which a first conductive layer 131 is deposited so as to conformally extend over the dielectric structure 120 .

[0100] The first conductive layer 131 can be made of any conductive or semiconductive material compatible with deposition. In a specific embodiment, the first conductive layer 131 can be formed of polysilicon deposited by LPCVD. Preferably, the first conductive layer 131 is a low-stress layer. The first conductive layer can be compressible or stretchable.

[0101] The first conductive layer 131 may completely or partially (as shown here) fill the area between the protruding walls 111, but referring to Figures 4A to 4C This aspect is described in further detail.

[0102] exist Figure 3D middle , showing a step in which the second conductive layer 132 is deposited.

[0103] The second conductive layer 132 can be made of any conductive or semiconductive material that is compatible with deposition. In particular, metals can be used to form the second conductive layer because they can be easily deposited by CVD. The second conductive layer 132 can therefore be formed of tungsten (W) or titanium nitride (TiN) deposited by CVD.

[0104] It is also conceivable within the scope of the present invention that the second conductive layer 132 comprises multiple sub-layers and / or materials. For example, the second conductive layer 132 may be formed of 1 / 3 tungsten (W) and 2 / 3 titanium nitride (TiN). This allows for adjustment of the mechanical stress of the second conductive layer 132 and also allows for adjustment of its thickness to seal the 3D structure. The second conductive layer 132 may also include: a liner of titanium nitride (TiN) (for adhesion to the first conductive layer 131) and the remainder being tungsten (W).

[0105] In some embodiments, the thickness of the second conductive layer 132 is less than that of the first conductive layer 131 and can be in the range of 50 nm to 1000 nm. This allows the use of a thin conductive layer deposition step (ie, fast deposition) to significantly reduce wafer bow.

[0106] As shown here, second conductive layer 132 extends over first conductive layer 131 and seals the area between protruding walls 111. That is, the top surface of second conductive layer 132 is located above the top surface of protruding walls 111. The area between facing protruding walls 111 is sealed by second conductive layer 132 at the level of their top planes. By sealing the 3D structure, second conductive layer 132 protects it from potential exposure to damaging chemicals during subsequent manufacturing steps.

[0107] The second conductive layer 132 may be deposited down to the bottom of the 3D structure (as shown in the figure), or may be deposited only partially in the 3D structure. Figures 4A to 4C Such embodiments are described in further detail.

[0108] It should be emphasized that the second conductive layer 132 has an opposite intrinsic mechanical stress compared to the intrinsic mechanical stress caused by the dielectric structure 120 and the first conductive layer 131 (preferably a low-stress layer). In other words, the second conductive layer 132 counteracts the deformation caused by the first conductive layer 131 and the dielectric structure 120. This allows for reduced wafer bowing.

[0109] For example, the first conductive layer 131 can be a low-stress polysilicon layer, and the second conductive layer 132 can be a stretchable tungsten layer. The advantage of such a layer combination for forming the top electrode 130 is that the electrical device 100 can be easily obtained using conventional manufacturing techniques. The polysilicon layer can be easily deposited within the 3D structure using LPCVD, and allows the 3D structure to be filled (completely or partially). In addition, the tungsten layer can be easily deposited by CVD, and allows the wafer bow to be reduced.

[0110] Therefore, the multi-layer top electrode 130 combining the first conductive layer 131 and the second conductive layer 132 allows limiting wafer bending when manufacturing the electric device 100 .

[0111] Within the scope of the present invention, embodiments are also conceivable which comprise a stack of layers comprising more than two electrically conductive layers.

[0112] exist Figure 3E middle , showing the steps in which the interconnect layer 140 and the passivation layer 150 are deposited.

[0113] An interconnect layer 140 is deposited on the top electrode 130. As shown here, the top electrode 130 and the interconnect layer 140 are partially etched before the passivation layer 150 is deposited.

[0114] The present invention does not particularly limit the respective materials used to form the interconnect layer 140 and the passivation layer 150. Typically, the passivation layer 150 is made of a material that provides mechanical protection, a moisture diffusion barrier, and exhibits good electrical insulation properties, such as silicon nitride. The interconnect layer 140 is typically made of aluminum (Al) or copper (Cu), but may also be made of other materials or alloys.

[0115] The structure of the electrical device 100 and the method for manufacturing the same have been presented above. However, as mentioned above, according to different embodiments, the deposition of different layers of the top electrode 130 can be performed within a 3D structure. These embodiments are described in detail with reference to the following figures.

[0116] Figures 4A to 4C is a SEM image of a cross-sectional view of an electrical device according to an embodiment of the present invention.

[0117] In particular, these figures show different embodiments for depositing a first conductive layer 131 and a second conductive layer 132 of a top electrode 130 within the 3D structure formed by the protruding walls 111 .

[0118] Figure 4A An embodiment is shown in which the first conductive layer 131 completely fills the regions (eg, trenches) between the protruding walls 111. A second conductive layer 132 is then deposited so as to conformally extend over the first conductive layer 131.

[0119] Figure 4B An embodiment is shown in which the first conductive layer 131 partially fills the regions between the protruding walls 111. Here, the second conductive layer 132 is deposited within the unfilled regions between the protruding walls 111 (ie, within the 3D structure).

[0120] Such an embodiment provides several advantages. The second conductive layer 132 seals the 3D structure and protects the capacitor region from exposure to chemicals that may be used later in the manufacturing process (which could compromise the integrity of the dielectric). Additionally, because the second conductive layer 132 is deposited within the 3D structure, it enhances the mechanical advantage provided by the multilayer top electrode 130.

[0121] Figure 4C An embodiment is shown in which the first conductive layer 131 partially fills the areas between the protruding walls 111. In this embodiment, the second conductive layer 132 is deposited so as to seal the 3D structure while leaving the spaces between the protruding walls 111 unfilled.

[0122] An advantage of this embodiment is that it prevents mechanical stress buildup within the 3D structure while still sealing it for manufacturability and electrical performance considerations.

[0123] Here we have described how to deposit the top electrode 130 in a 3D structure defined by the protruding walls 111. We describe below particularly advantageous embodiments for the 3D structure of the electrical device 100.

[0124] Figure 5 is an SEM image of a 3D structure of an electrical device according to an embodiment of the present invention. Specifically, the figure shows an embodiment in which the protruding walls 111 are separated and surrounded by a single continuous groove.

[0125] We remind that the bottom electrode 110 of the electrical device 100 comprises a conductive structure having a base surface and facing protruding walls 111. The dielectric structure 120 and the top electrode 130 conformally extend over the bottom electrode 110. Thus, the protruding walls 111 define a 3D capacitive structure of the electrical device 100.

[0126] The protruding wall 111 forms a protrusion with respect to the base surface of the structure. As shown here, the base surface of the structure is lower than the top surface of the protruding wall 111 and surrounds the protruding wall 111. The base surface extends to the edge of the electrical device 100. The structure proposed in this embodiment can be called an open 3D structure and has the following advantages.

[0127] Such an open 3D structure facilitates gas circulation and, therefore, the deposition of layers to form the capacitor. This makes the etching and deposition processes easier (i.e., faster and more uniform).

[0128] It should also be noted that the open 3D structure exhibits a strong asymmetry between its front side (with protruding walls) and back side. Therefore, the stiffness of the structure is significantly reduced. This allows the multilayer top electrode to easily control the deformation of the wafer.

[0129] Figure 5 Also shown is an embodiment in which the conductive structure of the bottom electrode 110 may include protruding walls 111 and 111 ′ extending in different directions for reducing mechanical stress.

[0130] In this embodiment, the bottom electrode 110 includes a first protruding wall 111 extending in a first direction and a second protruding wall 111' extending in a second direction, and the first direction and the second direction form a defined angle with each other. The defined angle can be selected or adjusted to reduce mechanical stress within the structure. For example, the first direction can be substantially perpendicular to the second direction. However, the embodiment is not limited to such an implementation, and other angular relationships between the first direction and the second direction (e.g., 10 degrees, 20 degrees, 30 degrees, 60 degrees, or 120 degrees) can be used.

[0131] exist Figure 5 In the example shown in FIG. 1 , a wall region including protruding walls 111 arranged in a first direction is surrounded on its sides by a wall region including protruding walls 111′ arranged in a second direction, and vice versa. This symmetrical arrangement of the wall region including protruding walls 111 and the wall region including protruding walls 111′ helps reduce mechanical stress in the first and second directions.

[0132] Additional variations: Although the present invention has been described above with reference to certain specific embodiments, it should be understood that the present invention is not limited to the characteristics of these specific embodiments. Various changes, modifications and developments can be made to the embodiments described above within the scope of the claims.

[0133] In particular, the present invention has been described with reference to 3D capacitor structures formed using trenches. However, other embodiments of the present invention are envisioned in which other 3D capacitor structures are used, such as capacitor structures based on pillars (e.g., pillars having a cylindrical shape, a tripod shape, or even a triskel shape).

[0134] It should be understood that references to directions and positions herein, such as "top" and "bottom," "front" and "back," refer only to directions that apply when structures and components are oriented as shown in the accompanying drawings.

Claims

1. An electrical device (100) comprising a capacitor, the electrical device (100) comprising: - a bottom electrode (110), the bottom electrode (110) comprising a conductive structure having a base surface (BS) and a protruding wall (111) extending upward from the base surface (BS), wherein the base surface (BS) of the conductive structure of the bottom electrode (110) is lower than a top surface of the protruding wall (111), and the base surface (BS) surrounds the protruding wall (111); - a dielectric structure (120) extending conformally over the bottom electrode (110); - a top electrode (130) extending conformally above the dielectric structure (120) and comprising a stack of layers including a first conductive layer (131) and a second conductive layer (132), wherein the second conductive layer (132) has an intrinsic mechanical stress that is opposite to the intrinsic mechanical stress caused by the first conductive layer (131) and the dielectric structure (120).

2. The electrical device (100) according to claim 1, wherein The base surface (BS) forms a continuous groove extending between and around the protruding walls (111).

3. The electrical device (100) according to claim 1 or 2, wherein: The second conductive layer (132) of the top electrode (130) extends over the first conductive layer (131) of the top electrode (130) and seals the region between the protruding walls (111).

4. The electrical device (100) according to claim 3, wherein The second conductive layer (132) of the top electrode (130) seals the region between the protruding walls (111) such that one or more spaces between the protruding walls (111) remain unfilled.

5. The electrical device (100) according to any one of claims 1 to 4, wherein: The first conductive layer (131) of the top electrode (130) includes polysilicon, and the second conductive layer (132) of the top electrode (130) includes tungsten and extends on the first conductive layer (131).

6. The electrical device (100) according to any one of claims 1 to 5, wherein: The second conductive layer (132) of the top electrode (130) is thinner than the first conductive layer (131) of the top electrode (130).

7. The electrical device (100) according to any one of claims 1 to 6, wherein: The thickness of the second conductive layer (132) of the top electrode (130) is comprised between 50 nm and 1000 nm.

8. The electrical device (100) according to any one of claims 1 to 7, wherein: The electrical device (100) is configured for use with an operating voltage exceeding 400V, or 600V, or 900V, or 1200V measured between the bottom electrode and the top electrode.

9. A method for manufacturing an electrical device (100) comprising a capacitor, the method comprising: - forming a bottom electrode (110) comprising a conductive structure having a base surface (BS) and a protruding wall (111) extending upward from the base surface (BS), wherein the base surface (BS) of the conductive structure is lower than a top surface of the protruding wall (111) and the base surface (BS) surrounds the protruding wall (111); - conformally forming a dielectric structure (120) over the bottom electrode (110); and - conformally forming a top electrode (130) over the dielectric structure (120), the top electrode (130) comprising a stack of layers including a first conductive layer (131) and a second conductive layer (132), wherein the second conductive layer (132) has an intrinsic mechanical stress that is opposite to the mechanical stress of the first conductive layer (131) and the dielectric structure (120).

10. The method according to claim 9, comprising the preliminary step of selecting the second conductive layer (132) of the top electrode (130) based on the following mechanical stresses: the intrinsic mechanical stress of the dielectric structure (120); and the intrinsic mechanical stress of the first conductive layer (131) of the top electrode (130).

11. The method according to claim 10, wherein: The step of forming the bottom electrode (110) includes etching a continuous groove extending between and surrounding the protruding walls (111).

12. The method according to any one of claims 9 to 11, wherein: The second conductive layer (132) of the top electrode (130) extends over the first conductive layer (131) of the top electrode (130) and seals the region between the protruding walls (111).

13. The method according to any one of claims 9 to 12, wherein: The first conductive layer (131) of the top electrode (130) includes polysilicon, and the second conductive layer (132) of the top electrode (130) includes tungsten and extends on the first conductive layer (131).

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