Device based on advanced process and method for manufacturing the same

Abstract

The application relates to the field of semiconductor technology, in particular to a device based on an advanced process and a preparation method thereof, which comprises the following steps: providing an initial device structure, wherein the initial device structure comprises a substrate and at least one interconnection layer located on the substrate, functional elements of a semiconductor device are formed in the substrate, the at least one interconnection layer is located between a top metal layer and the substrate, the interconnection layer is prepared based on an advanced process and comprises a metal layer, a metal interconnection structure and a dielectric layer; forming a deep trench in the initial device structure, the deep trench penetrates through the at least one interconnection layer and then penetrates into the substrate; and filling the deep trench with an isolation material to form a filling material layer which fills the deep trench and is stacked on the at least one interconnection layer, and the area of the filling material layer which is stacked on the at least one interconnection layer is reused by the next interconnection layer adjacent to the at least one interconnection layer. The application can integrate the preparation process of the DTI into the preparation process of the interconnection layer of the BCD device and simplify the integrated process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a device based on an advanced process and a preparation method thereof. BACKGROUND

[0002] With the improvement of process and the reduction of feature size of semiconductor devices, the integration of deep trench isolation (DTI) structure in semiconductor devices faces many challenges, such as semiconductor structure warping and trench cracking caused by high-temperature process of DTI, and the current DTI integration process has low compatibility with the original machine, which requires the addition of new equipment or the increase of complex equipment process, reduces the production yield and increases the cost of device preparation. SUMMARY

[0003] To solve the above technical problems, in one aspect, the present application discloses a device preparation method based on an advanced process, which comprises: providing an initial device structure, the initial device structure comprising a substrate and at least one interconnection layer located on the substrate, the substrate forming a functional element of a semiconductor device, the at least one interconnection layer being located between a top metal layer and the substrate, the interconnection layer being prepared based on an advanced process, comprising a metal layer, a metal interconnection structure and a dielectric layer, the metal interconnection structure longitudinally penetrating the dielectric layer and being electrically connected with the metal layer;

[0004] forming a deep trench in the initial device structure, the deep trench penetrating the at least one interconnection layer and then extending into the substrate;

[0005] filling the deep trench with isolation material to form a filling material layer filling the deep trench and stacked on the at least one interconnection layer, the region of the filling material layer stacked on the at least one interconnection layer being reused by the next interconnection layer adjacent to the at least one interconnection layer.

[0006] In a possible implementation, the top interconnection layer of the at least one interconnection layer exposes the surface of the metal layer, and before the deep trench is formed in the initial device structure, the method further comprises:

[0007] forming a first protective layer covering the metal layer of the top interconnection layer of the at least one interconnection layer, the deep trench penetrating the first protective layer and the at least one interconnection layer and then extending into the substrate.

[0008] In a possible implementation, the substrate comprises a substrate layer, an epitaxial layer, and a doped buried layer spanning the substrate layer and the epitaxial layer, the deep trench penetrating the at least one interconnection layer and the epitaxial layer and then extending into the substrate layer;

[0009] The deep trench and the doped buried layer are connected for isolating adjacent device modules.

[0010] In a possible implementation, a shallow trench isolation structure is formed in the epitaxial layer, and the deep trench extends into the substrate layer after sequentially penetrating the at least one interconnection layer, the shallow trench isolation structure, and the epitaxial layer.

[0011] In a possible implementation, a part of the filling material layer filling the deep trench forms a deep trench isolation structure, and the deep trench isolation structure has a closed air gap, which is located at least in the substrate.

[0012] In a possible implementation, the filling material layer includes a dielectric filling layer covering at least the sidewall of the deep trench and stacked on the at least one interconnection layer.

[0013] An area of the dielectric filling layer stacked on the at least one interconnection layer is reused as a dielectric layer of the next interconnection layer.

[0014] In a possible implementation, an area of the dielectric filling layer filling the deep trench forms a deep trench isolation structure, and the deep trench isolation structure has a closed air gap enclosed by the dielectric filling layer, and the dielectric filling layer is formed based on a high-density plasma deposition process.

[0015] In a possible implementation, the filling material layer further includes a metal filling layer, a part of the metal filling layer is a metal plug structure filling the deep trench, and a part of the metal filling layer is located in an area of the dielectric filling layer stacked on the at least one interconnection layer, to be reused as a metal layer and a metal interconnection structure of the next interconnection layer.

[0016] In a possible implementation, the method of filling the deep trench with an isolation material to form a filling material layer filling the deep trench and stacked on the at least one interconnection layer includes:

[0017] depositing a dielectric material to form an initial dielectric filling layer filling the deep trench and stacked on the at least one interconnection layer, an area of the initial dielectric filling layer filling the deep trench forms a deep trench isolation structure and has a closed air gap;

[0018] performing a surface polishing process on the initial dielectric filling layer to form a dielectric filling layer as the filling material layer.

[0019] In a possible implementation, after the surface polishing process on the initial dielectric filling layer to form a dielectric filling layer as the filling material layer, the method further includes:

[0020] patterning and etching the dielectric fill layer to form interconnection via holes corresponding to the metal interconnection structure of the next interconnection layer and openings corresponding to the metal layer of the next interconnection layer;

[0021] filling the interconnection via holes and the openings based on a metal deposition process to form the metal interconnection structure and the metal layer of the next interconnection layer.

[0022] In a possible implementation, the filling the deep trench with an isolation material to form a fill material layer filling the deep trench and stacked on the at least one interconnection layer comprises:

[0023] depositing a dielectric material to form a dielectric fill layer covering the sidewall of the deep trench and stacked on the at least one interconnection layer, the dielectric fill layer exposing the bottom of the deep trench and having interconnection via holes corresponding to the metal interconnection structure of the next interconnection layer and openings corresponding to the metal layer of the next interconnection layer;

[0024] depositing a metal material to fill the deep trench, the interconnection via holes corresponding to the metal interconnection structure of the next interconnection layer and the openings corresponding to the metal layer of the next interconnection layer, to obtain a metal fill layer, the region of the dielectric fill layer covering the sidewall of the deep trench and the metal plug structure of the metal fill layer filling the deep trench forming a deep trench isolation structure, the region of the dielectric fill layer stacked on the at least one interconnection layer being reused as a dielectric layer of the next interconnection layer, the region of the metal fill layer filling the interconnection via holes being the metal interconnection structure of the next interconnection layer, and the region of the metal fill layer filling the openings being the metal layer of the next interconnection layer.

[0025] In a possible implementation, before the depositing a metal material to fill the deep trench, the interconnection via holes corresponding to the metal interconnection structure of the next interconnection layer and the openings corresponding to the metal layer of the next interconnection layer to obtain a metal fill layer, the method further comprises:

[0026] performing ion implantation on the bottom of the deep trench to form a doped structure at the bottom of the deep trench, the metal plug structure being connected with the doped structure.

[0027] In a possible implementation, the depositing a dielectric material to form a dielectric fill layer covering the sidewall of the deep trench and stacked on the at least one interconnection layer comprises:

[0028] depositing an initial dielectric fill layer covering the sidewall of the deep trench and stacked on the at least one interconnection layer, and having a cavity at the deep trench, the cavity being enclosed by the initial dielectric fill layer;

[0029] The initial dielectric filling layer is patterned and etched to form an opening corresponding to the metal layer of the next interconnection layer, the opening corresponding to the metal layer of the next interconnection layer including a first opening and a second opening, the first opening being located above the deep trench;

[0030] The metal interconnection structure of the next interconnection layer is formed based on the patterned and etched interconnection via to expose the bottom of the deep trench, and the dielectric filling layer is obtained, the cavity being in communication with the first opening.

[0031] In a possible implementation, the metal filling layer further includes a region stacked on the dielectric filling layer, after the metal material is deposited to fill the deep trench, the interconnection via corresponding to the metal interconnection structure of the next interconnection layer, and the opening corresponding to the metal layer of the next interconnection layer, the method further includes:

[0032] The metal filling layer is polished with the dielectric filling layer as a stop layer to remove the region of the metal filling layer stacked on the dielectric filling layer.

[0033] In a possible implementation, the metal plug structure has an air gap formed therein.

[0034] In another aspect, the application discloses a device based on an advanced process, including:

[0035] A substrate on which functional elements of a semiconductor device are formed;

[0036] At least one interconnection layer on the substrate, prepared based on an advanced process, between a top metal layer and the substrate, the interconnection layer including a metal layer, a metal interconnection structure, and a dielectric layer, the metal interconnection structure longitudinally penetrating the dielectric layer and electrically connected to the metal layer;

[0037] A deep trench penetrating the at least one interconnection layer and extending into the substrate;

[0038] A filling material layer filling the deep trench and stacked on the at least one interconnection layer, a material region of the filling material layer stacked on the at least one interconnection layer being reused by a next interconnection layer adjacent to the at least one interconnection layer

[0039] In a possible implementation, the at least one interconnection layer has a top interconnection layer exposing a surface of a metal layer, and the device further includes a first protective layer covering the metal layer of the top interconnection layer of the at least one interconnection layer, the deep trench penetrating the first protective layer and the at least one interconnection layer and extending into the substrate.

[0040] In a possible implementation, the substrate includes a substrate layer, an epitaxial layer, and a doped buried layer across the substrate layer and the epitaxial layer, the deep trench extends into the substrate layer through the at least one interconnect layer and the epitaxial layer;

[0041] The deep trench and the doped buried layer are connected for isolating adjacent device modules.

[0042] In a possible implementation, a shallow trench isolation structure is formed in the epitaxial layer, and the deep trench extends into the substrate layer through the at least one interconnect layer, the shallow trench isolation structure, and the epitaxial layer in sequence.

[0043] In a possible implementation, a portion of the filling material layer filling the deep trench forms a deep trench isolation structure, and the deep trench isolation structure has an enclosed air gap, which is located at least in the substrate.

[0044] In a possible implementation, the filling material layer includes a dielectric filling layer covering at least the sidewall of the deep trench and stacked on the at least one interconnect layer.

[0045] An area of the dielectric filling layer stacked on the at least one interconnect layer is reused as a dielectric layer of the next interconnect layer.

[0046] In a possible implementation, an area of the dielectric filling layer filling the deep trench forms a deep trench isolation structure, and the deep trench isolation structure has an enclosed air gap enclosed by the dielectric filling layer, and the dielectric filling layer is formed based on a high-density plasma deposition process.

[0047] In a possible implementation, the filling material layer further includes a metal filling layer, a portion of the metal filling layer is a metal plug structure filling the deep trench, and a portion of the metal filling layer is located in an area of the dielectric filling layer stacked on the at least one interconnect layer, to be reused as a metal layer and a metal interconnect structure of the next interconnect layer.

[0048] In a possible implementation, the device further includes a doped structure at the bottom of the deep trench, and the metal plug structure is connected to the doped structure.

[0049] In a possible implementation, the metal plug structure has an air gap.

[0050] In another aspect, the present application also discloses an integrated circuit including the device based on an advanced process mentioned above.

[0051] In another aspect, the present application also discloses an electronic device including the device based on an advanced process mentioned above.

[0052] Based on the above technical solution, the present application has the following beneficial effects:

[0053] In the preparation process of the metal interconnection layer, the DTI process is integrated to prepare the DTI structure after forming at least one interconnection layer of the metal interconnection layer and before forming the top metal (TM) layer of the metal interconnection layer, so that the isolation material prepared by the DTI is integrated with the process of the next interconnection layer, thereby sharing the filling material layer with the next interconnection layer. Not only is it highly adaptable to the equipment process of the machine, but also simplifies the integration process steps of the DTI and reduces the preparation cost. Moreover, the DTI is integrated in the back-end process of the device, and the DTI structure preparation can be realized by filling the isolation material at a lower temperature in this stage, avoiding device damage caused by high-temperature processes and improving product yield. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating laborious work.

[0055] Figure 1 A flowchart of a device preparation method based on an advanced process is provided for the embodiments of the present application.

[0056] Figures 2-16 A cross-sectional view of a device based on an advanced process during preparation is provided for the embodiments of the present application.

[0057] The following is a supplementary description of the drawings:

[0058] 1-initial device structure, 10-substrate, 101-substrate layer, 102-epitaxial layer, 103-doped buried layer, 104-shallow trench isolation structure, 105-gate structure, 106-deep trench, 107-isolation layer, 108-first shielding layer, 109-second shielding layer, 110-third shielding layer, 20-interconnection layer, 201-metal layer, 202-metal interconnection structure, 203-dielectric layer, 204-interlayer dielectric layer, 205-intermetal dielectric layer, 30-filling material layer, 301-deep trench isolation structure, 301a-metal plug structure, 301b-air gap, 302-dielectric filling layer, 303-metal filling layer, 304-opening, 304a-first opening, 304b-second opening, 305-interconnection via, 306-doped structure, 40-first protective layer, 50-initial dielectric filling layer, 501-cavity. DETAILED DESCRIPTION

[0059] With reference to the drawings and the embodiments described herein, it should be understood that the drawings and detailed description are to be considered only illustrative of the principles of the application. The application can be implemented in various ways, some of which will be described herein. The embodiments described herein should be understood not to limit the application, but rather to provide examples of how the application can be implemented. The embodiments described herein are not intended to be exhaustive or to be limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings.

[0060] As used in this application, the terms "one embodiment", "an embodiment”, or "embodiments” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the application. The appearances of the phrase "in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, and some embodiments can be understood as alternative specific implementations of the application. In this specification and in the claims, the term "when” can be used to indicate not only "if’ or "when” but also "every time” or "each time” that a condition precedent is met. Further, the terms "comprise”, "comprising”, "comprises” and "comprising” when used in this specification and in the claims are used to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

[0061] When a range of values is disclosed, unless otherwise stated, the endpoints of the ranges are not included. However, the scope of the ranges and the numbers are intended to include any and all sub-ranges therebetween, and are intended to include the number in the range. For example, a range of "1 to 10” is intended to include any and all sub-ranges between (and including) the recited minimum value of 1 and the recited maximum value of 10, that is, any and all sub-ranges between (and including) the minimum of 1 and the maximum of 10, for example, 5 to 6, 8 to 9, 3 to 7, 5 to 9, 1 to 6, 1 to 9, 3 to 10, 5 to 10, 10 to 10, 1 to 10, etc. Further, a range including integers between (and including) the recited minimum and maximum, for example, - 1 to 10, is intended to include any and all sub-ranges between (and including) the recited minimum value of -1 and the recited maximum value of 10, that is, any and all sub-ranges between (and including) the minimum of -1 and the maximum of 10, for example, -1 to 6, 5 to 9, 3 to 7, 5 to 6, 1 to 6, 1 to 9, 3 to 10, 5 to 10, 10 to 10, 1 to 10, etc.

[0062] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can extend part way over a underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes within the same. A layer can extend horizontally, vertically, and / or along a contoured surface. A layer can include multiple layers. For example, the substrate 10 can include multiple sub-layers, etc., and can have the same or different materials.

[0063] It should be appreciated that the terms "substantially uniform", "substantially vertical", etc. as used herein refer to a substantially uniform or substantially vertical, etc. within process error, and do not refer to absolute uniformity or absolute verticality in a physical sense.

[0064] It should be appreciated that the terms "surface", such as "first surface", "second surface", etc. as used herein refer to an XY plane of the substrate 10 or substrate structure, etc. corresponding to the device XY plane based on the advanced process, and "in-plane direction", "lateral direction" refer to a direction parallel to the XY plane, and "thickness direction", "trench depth direction" or "longitudinal direction" refer to a Z direction relative to the XY plane.

[0065] The following describes the device preparation method based on the advanced process provided by the embodiments of the present application, Figures 1-16 The device preparation method based on the advanced process provided by the embodiments of the present application is described below, Figure 1 The flowchart of the device preparation method based on the advanced process is shown in FIG. 1. The present specification provides method operation steps such as embodiments or flowcharts, but more or fewer operation steps can be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one of the many execution orders, and does not represent the only execution order. In actual preparation method execution, the method order shown in the embodiments or the drawings can be executed or executed in parallel. The preparation method can include S11-S13:

[0066] S11: providing an initial device structure 1.

[0067] Specifically, the initial device structure 1 includes a substrate 10 and at least one interconnection layer 20 located on the substrate 10, the substrate 10 has functional elements of a semiconductor device formed therein, and the at least one interconnection layer 20 is located between a top metal layer and the substrate 10. The interconnection layer 20 is prepared based on the advanced process, and includes a metal layer 201, a metal interconnection structure 202, and a dielectric layer 203. The metal interconnection structure 202 longitudinally penetrates the dielectric layer 203 and is electrically connected to the metal layer 201.

[0068] In particular, the substrate 10 can be a semiconductor substrate capable of being processed for semiconductor devices based on advanced processes. Optionally, the substrate 10 can be made of at least one of silicon, a material containing silicon (e.g., a III-V compound semiconductor material such as gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials capable of forming the substrate 10.

[0069] In some embodiments, the substrate 10 can be a continuous structure such as a wafer substrate, or can include a substrate layer 101 and an epitaxial layer 102 (see Figure 2 ). Optionally, the epitaxial layer 102 can be formed by an epitaxial growth process, and can be a homo-epitaxial layer 102 that can continue to grow along the lattice direction of the substrate layer 101, or can be a hetero-epitaxial layer 102. The process conditions such as the growth temperature can be the same as existing processes or can be adjusted as appropriate. Optionally, the epitaxial layer 102 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic vapor deposition (ALD), or other methods. For example, the material of the epitaxial layer 102 can include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), or other materials that can be epitaxially grown or deposited on the substrate layer 101 and capable of being processed for device regions. Figure 2 In some embodiments, the functional elements of the semiconductor devices in the substrate 10 can be located in the epitaxial layer 102.

[0070] In particular, the functional elements (not shown) in the substrate 10 can be prepared and arranged based on the requirements of the semiconductor devices, such as MOS transistor units of BCD (Bipolar CMOS DMOS) devices, or active regions of power transistor devices (e.g., SGT MOSFET (Shielded Gate Trench MOSFET)). It can be understood that the semiconductor devices can also be RF (Radio Frequency) devices, etc. The functional elements can be prepared in the front-end process of the semiconductor devices.

[0071] In some embodiments, the substrate 10 can be a continuous structure such as a wafer substrate, or can include a substrate layer 101 and an epitaxial layer 102 (see Figure 2The initial device structure 1 can further include a gate structure 105 formed by a gate material deposition and patterning etching process, and an isolation layer 107 covering the substrate 10 and the gate structure 105. The material of the gate structure 105 can include, but is not limited to, polysilicon, etc. The isolation layer 107 is used to protect the substrate 10 and the gate structure 105, and can be formed by a deposition process. The material of the isolation layer 107 can include, but is not limited to, at least one of silicon nitride, titanium nitride, silicon oxynitride, silicon dioxide, etc., or other materials capable of achieving the structure protection effect. Optionally, the deposition process in the present application can be implemented by a chemical vapor deposition (CVD) process, such as a plasma enhanced chemical vapor deposition (PECVD), a high density plasma chemical vapor deposition (HDPECVD), a sub atmospheric chemical vapor deposition (SACVD), a low pressure chemical vapor deposition (LPCVD), an atomic layer deposition (ALD), a plasma enhanced atomic layer deposition (PEALD), or other kinds of chemical vapor deposition processes.

[0072] In particular, the metal interconnection layer is a conductive network in the semiconductor device for connecting functional elements and other elements, responsible for signal transmission and power distribution. The metal interconnection layer is prepared in the back-end-of-line process of the semiconductor device. The metal interconnection layer is located on one side surface of the substrate 10, and can include two or more interconnection layers 20 for electrical extension and signal transmission in the XY plane, where the XY plane refers to the XY plane of the device or the substrate 10. The interconnection layer 20 can be formed by at least photolithography, metal layer 201 deposition, and dielectric layer 203 deposition processes, and metal wires are formed in the metal layer 201 to achieve the redistribution of IO ports, and to redistribute electrical signals, power signals, or ground signals. The dielectric layer 203 is used to isolate adjacent metal layers 201 and metal interconnection structures 202, and the metal wires of the same layer metal layer 201 and the metal wires of the adjacent metal layer 201 are electrically isolated by the dielectric layer 203, and the metal interconnection structure 202 is provided in the dielectric layer 203 to electrically connect the metal layers 201 of the two adjacent layers. In particular, the metal layer 201 of the current interconnection layer 20 is electrically connected to the metal layer 201 of the previous layer interconnection layer 20 in the process by the metal interconnection structure 202 in the current layer. Among them, the interconnection layer 20 closest to the substrate 10 is the first interconnection layer, and the metal layer 201 in the first interconnection layer is the first metal layer 201 (M1), and the metal layer 201 in the uppermost interconnection layer 20 in the metal interconnection layer is the top metal layer (TM). The at least one interconnection layer 20 can include one or more interconnection layers 20 below the top metal layer, which can be the first interconnection layer, and can also include other intermediate interconnection layers. For example, referring to Figure 3 , the at least one interconnection layer 20 is the first interconnection layer, or can also include the first interconnection layer and the second interconnection layer (not shown).

[0073] In particular, referring to Figure 3 , the dielectric layer 203 of the first interconnection layer includes an interlayer dielectric layer 204 (ILD) covering the substrate 10, located between the first metal layer and the substrate 10, and specifically can be located between the first metal layer of the metal interconnection layer and the isolation layer 107, used to realize resistive connection and form an interconnection via hole 305, so as to fill the metal material in the interconnection via hole 305 to form the metal interconnection structure 202 electrically connecting the substrate 10 and the first metal layer, and the gate structure 105 and the first metal layer. The metal layer 201 is electrically connected to at least part of the functional elements in the semiconductor device through the metal interconnection structure 202.

[0074] In particular, referring to Figure 4The interconnection layer 20 can further include an inter-metal dielectric layer 205 (IMD) covering the first metal layer 201, and the inter-metal dielectric layer 205 is used to isolate the adjacent metal layers 201 and form the interconnection via 305 of the interconnection structure 202 between the adjacent metal layers 201. The inter-metal dielectric layer 205 of the first interconnection layer 20 and the inter-layer dielectric layer 204 can further form a second protective layer. The second protective layer can be formed by a deposition process, and the material can include, but is not limited to, at least one of silicon nitride, titanium nitride, silicon oxynitride, silicon dioxide, etc., or other materials capable of achieving the structure protection effect.

[0075] Optionally, the interconnection layer 20 can be formed by depositing a non-conductive material, and the material of the metal layer 201 can include, but is not limited to, one or more of copper, titanium, tungsten, gold, nickel, tantalum, titanium nitride, tantalum nitride, etc., or other alternative conductive materials. The advanced process used by the interconnection layer 20 can be formed based on an advanced process such as the damascene process.

[0076] In some embodiments, referring to Figures 2-4 The preparation process of the first interconnection layer can include: depositing the inter-layer dielectric layer 204 on the substrate 10, and the inter-layer dielectric layer 204 is stacked on the isolation layer 107; performing patterned etching on the inter-layer dielectric layer 204 to form the interconnection via 305, and filling the interconnection via 305 based on the metal material deposition to form the metal interconnection structure 202 of the first interconnection layer 20; forming a second protective layer stacked on the inter-layer dielectric layer 204, and further depositing the inter-metal dielectric layer 205; performing patterned etching on the inter-metal dielectric layer 205 to form the opening 304 corresponding to the first metal layer, the opening 304 penetrates the second protective layer, and at least part of the opening 304 exposes the metal interconnection structure 202; depositing the metal material to fill the opening 304 corresponding to the first metal layer to form the first metal layer, thereby obtaining the first interconnection layer.

[0077] S12: forming the deep trench 106 in the initial device structure 1.

[0078] Specifically, the deep trench 106 is etched after any interconnect layer is prepared before the top metal layer is prepared in the back-end-of-line process, and the top end of the deep trench 106 is located in the dielectric layer 203 of the top interconnect layer 20 of the at least one interconnect layer 20, and the deep trench 106 extends into the substrate 10 after extending through the dielectric layers 203 of the interconnect layers 20 in sequence, for isolating a device module of the semiconductor device, which can include a partial functional module of the semiconductor device, or can be a complete semiconductor device. The initial device structure 1 can include one or more semiconductor devices.

[0079] Specifically, referring to Figure 5 , the deep trench 106 can be formed based on a patterned etching process. In a possible implementation, S12: forming the deep trench 106 in the initial device structure 1 can include S121-S123:

[0080] S121: forming a first shielding layer 108, the first shielding layer 108 covering the top interconnect layer 20 of the at least one interconnect layer 20;

[0081] S122: performing a patterned process on the first shielding layer 108 to expose a corresponding interconnect layer region of the deep trench 106, the exposed interconnect layer region being located in the dielectric layer 203;

[0082] S123: etching the exposed interconnect layer region and etching to a depth of the substrate 10 to form the deep trench 106.

[0083] Specifically, the first shielding layer 108 can be formed by coating photoresist, and the first shielding layer 108 is subjected to a patterned exposure process to expose the region to be etched by the patterned first shielding layer 108, to form an etching window, and then the interconnect layer 20 and the substrate 10 thereunder exposed by the etching window are etched to obtain the deep trench 106. The deep trench 106 etching can adopt a wet etching process, such as using phosphoric acid as an etching solution for wet etching, or can adopt a dry etching process, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation, such as plasma etching by a mixed gas of C4F8 and O2.

[0084] In some embodiments, referring to Figure 4 and Figure 5 , the top interconnect layer 20 of the at least one interconnect layer 20 exposes the surface of the metal layer 201, and accordingly, before S12: forming the deep trench 106 in the initial device structure 1, the method further includes: forming a first protective layer 40, the first protective layer 40 covering the metal layer 201 of the top interconnect layer 20 of the at least one interconnect layer 20, and the deep trench 106 extends through the first protective layer 40 and the at least one interconnect layer 20 and extends into the substrate 10.

[0085] Specifically, the first protective layer 40 covers at least the metal layer 201 of the at least one interconnect layer 20 located at the top layer, and can also cover the dielectric layer 203 of the at least one interconnect layer 20 located at the top layer, and the first shielding layer 108 is laminated on the first protective layer 40. The metal layer 201 of the at least one interconnect layer 20 can be protected by the first protective layer 40, and the dielectric layer 203 thereof can also be protected, so as to avoid damage to the at least one interconnect layer 20 caused by etching of the deep trench 106.

[0086] Optionally, the material of the first protective layer 40 can include at least one of silicon nitride, titanium nitride, silicon oxynitride, silicon dioxide, etc., or can also be other materials capable of achieving etching blocking protection. The first protective layer 40 can be formed based on a deposition process. In an embodiment, the material of the first protective layer 40 is consistent with the material of the dielectric layer 203 of the next interconnect layer 20. The next interconnect layer 20 refers to the interconnect layer 20 located after the at least one interconnect layer 20 in the initial device structure 1 in the preparation process. It can be understood that the first protective layer 40 is a thin layer covering the at least one interconnect layer 20 currently located at the top layer, and the filling material layer 30 formed by filling the isolation material in the deep trench 106 is laminated on the first protective layer 40, which can be reused as the dielectric layer 203 of the next interconnect layer 20, avoiding thickening the thickness of the intermetallic dielectric layer 205 and introducing additional complex deposition and cleaning processes. Preferably, the deposition process of the first protective layer 40, the deposition process of the filling material layer 30, and the deposition process of the intermetallic dielectric layer 205 are consistent.

[0087] S13: filling the deep trench 106 with an isolation material to form a filling material layer 30 filling the deep trench 106 and laminated on the at least one interconnect layer 20.

[0088] Specifically, the next interconnect layer 20 adjacent to the at least one interconnect layer 20 reuses the area of the filling material layer 30 laminated on the at least one interconnect layer 20. Specifically, the area of the filling material layer 30 filling the deep trench 106 forms a deep trench isolation structure 301, and the area of the filling material layer 30 laminated on the current interconnect layer 20 can be reused as the material of the next interconnect layer 20. Specifically, the deep trench isolation structure 301 can improve the breakdown voltage of the device and prevent the crosstalk problem between device modules.

[0089] Specifically, the isolation material can be deposited to form the fill material layer 30, the isolation material deposited in S13 includes the material required for depositing the dielectric layer 203 between the metal layers 201, so that a new sputtering or deposition material does not need to be introduced in the back-end process to prepare the original dielectric layer 203 in cooperation with filling the deep trench 106. Alternatively, the dielectric material of the fill material layer 30 can include but is not limited to one or more of silicon glass (such as fluorinated silicate glass (FSG) and the like), sub-atmospheric tetra-ethyl ortho silicate (SATEOS), carbon-doped oxide, silicon nitride, and silicon dioxide, etc. to achieve isolation and protection.

[0090] In summary, the present application integrates the DTI process in the preparation process of the metal interconnection layer to prepare the DTI structure after forming at least one interconnection layer 20 of the metal interconnection layer and before forming the top metal (TM) layer of the metal interconnection layer, so that the isolation material prepared by the DTI fills the process of the next interconnection layer 20, thereby sharing the fill material layer 30 with the next interconnection layer 20, which not only highly adapts to the equipment process of the machine, but also simplifies the integration process step of the DTI and reduces the preparation cost. Moreover, the DTI is integrated in the back-end process of the device, and the DTI structure preparation can be achieved by filling the isolation material with a lower temperature in this stage, which avoids the damage to the device caused by high-temperature processes and improves the product yield.

[0091] In a possible implementation, referring to Figures 3-5 The substrate 10 includes a substrate layer 101, an epitaxial layer 102, and a doped buried layer 103 across the substrate layer 101 and the epitaxial layer 102, and the deep trench 106 extends into the substrate layer 101 after penetrating at least one interconnection layer 20 and the epitaxial layer 102; the deep trench 106 and the doped buried layer 103 are connected to isolate adjacent device modules, thereby avoiding the crosstalk problem of adjacent functional modules or adjacent semiconductor devices.

[0092] Specifically, based on the device requirements, the doped buried layer 103 can be an NBL (N-type buried layer) or a PBL (P-type buried layer) for reducing the N region resistance, longitudinal isolation, or for reducing the P region resistance and optimizing the substrate bias. The doped buried layer 103 is located between the substrate layer 101 and the epitaxial layer 102 and can be formed by ion implantation and high-temperature annealing. In some embodiments, the bottom end of the deep trench isolation structure 301 is lower than the doped buried layer 103 to ensure the isolation effect.

[0093] In a possible implementation, the shallow trench isolation structure 104 is formed in the epitaxial layer 102, and the deep trench 106 extends into the substrate layer 101 through at least one of the interconnection layers 20, the shallow trench isolation structure 104, and the epitaxial layer 102 in sequence. Specifically, the deep trench 106 is located at the shallow trench isolation structure 104, preferably, referring to Figure 5 , the width of the shallow trench isolation structure 104 is greater than that of the deep trench 106, and the deep trench 106 extends into the substrate layer 101 through at least one of the interconnection layers 20, the shallow trench isolation structure 104, and the epitaxial layer 102 in sequence, thereby achieving the cooperative isolation of the device layer and the current interconnection layer 20 and avoiding device crosstalk. In this way, the conventional isolation is performed in combination with the shallow trench isolation structure 104 in the standard device, and the deep trench isolation structure 301 is further integrated at the position requiring high-voltage resistance or high electrical isolation, which is conducive to the positioning of the deep trench and significantly improves the device performance.

[0094] In a possible implementation, referring to Figure 9 and Figure 16 , the part of the filling material layer 30 filling the deep trench 106 forms the deep trench isolation structure 301, and the deep trench isolation structure 301 has a closed air gap 301b, which is located at least in the substrate 10. Preferably, the air gap 301b longitudinally spans the interconnection layer 20 and the substrate 10.

[0095] Specifically, the air gap 301b is enclosed in the filling isolation material, forming a closed cavity 501 in the deep trench 106, specifically, a gas gap structure. Alternatively, the air gap 301b can be a vacuum gap structure, an air gap structure, or other gas gap structure filled with low-dielectric gas, which can be formed by adjusting the deposition process parameters. The formation of the air gap 301b in the deep trench isolation structure 301 can improve the isolation performance, and at the same time, the air gap 301b forms an elastic buffer to improve the heat resistance and mechanical properties such as shock resistance of the device based on advanced process, thereby reducing the risk of thermal expansion and mechanical damage of the device.

[0096] In a possible implementation, referring to Figure 6 and Figure 10 , the filling material layer 30 includes at least a dielectric filling layer 302 covering the sidewall of the deep trench 106 and stacked on at least one of the interconnection layers 20, and the area of the dielectric filling layer 302 stacked on at least one of the interconnection layers 20 is reused as the dielectric layer 203 of the next interconnection layer 20.

[0097] In particular, the material of the dielectric fill layer 302 is consistent with the material of the dielectric layer 203 in the interconnection layer 20, and is formed by depositing a dielectric material. The fill material layer 30 can at least include the dielectric fill layer 302, so as to achieve electrical isolation of the deep trench isolation structure 301 from functional devices in the substrate 10, and avoid diffusion of the material of the deep trench isolation structure 301, form the dielectric fill layer 302 which can be reused as the dielectric layer 203, highly integrate the DTI structure preparation process, reduce the introduced preparation steps, and use the original deposition material, equipment and process of the machine, further reduce the integration complexity of the DTI structure.

[0098] In a possible implementation, the fill material layer 30 is deposited by a high-density plasma deposition process (HDP CVD), so as to form the deep trench isolation structure 301 with a high aspect ratio.

[0099] In some embodiments, referring to Figures 7-9 , the dielectric fill layer 302 fills the region of the deep trench 106 to form the deep trench isolation structure 301, and the deep trench isolation structure 301 has an air gap 301b enclosed by the dielectric fill layer 302, and the dielectric fill layer 302 is formed based on a high-density plasma deposition process.

[0100] In particular, the filling of the deep trench 106 is achieved by depositing a dielectric material, and the dielectric fill layer 302 covers the trench wall of the deep trench 106, i.e., covers the side wall and the bottom wall. Accordingly, the deep trench isolation structure 301 includes the region of the dielectric fill layer 302 in the deep trench 106 and the air gap 301b enclosed in the dielectric fill layer 302, and the region of the dielectric fill layer 302 stacked on the interconnection layer 20 serves as the dielectric layer 203 of the next interconnection layer 20, and the metal interconnection structure 202 and the metal layer 201 (see Figure 9 ) of the next interconnection layer 20 are arranged in the region. In this way, the deposition process of the back-end process not only achieves integration of the DTI structure, but also forms the air gap 301b at a proper position to improve the performance of the DTI structure.

[0101] In some embodiments, the position of the air gap 301b in the deep trench isolation structure 301 in the deep trench 106 is determined based on the sputtering rate and the deposition rate of the high-density plasma deposition process, and the position of the air gap 301b is adjusted by adjusting the deposition process parameters. In one embodiment, the bottom end of the air gap 301b can be lower than each functional element in the substrate 10, or lower than the epitaxial layer 102. The top end of the air gap 301b can be located in the substrate 10, or in the interconnection layer 20.

[0102] Accordingly, in some embodiments, referring to Figures 6-7S13: filling the isolation material into the deep trench 106 to form a filling material layer 30 filling the deep trench 106 and stacked on the at least one interconnection layer 20, comprising S131-S132:

[0103] S131: depositing a medium material to form an initial medium filling layer 50 filling the deep trench 106 and stacked on the at least one interconnection layer 20;

[0104] S132: performing a surface polishing process on the initial medium filling layer 50 to form a medium filling layer 302 as the filling material layer 30.

[0105] Specifically, after removing the first shielding layer 108, the medium material is deposited to fill the deep trench 106 and form the initial medium filling layer 50 covering the current exposed interconnection layer 20, and the area of the initial medium filling layer 50 filling the deep trench 106 forms the deep trench isolation structure 301 with a closed air gap 301b. Then, based on a planarization process such as chemical mechanical polishing, a surface polishing process is performed to planarize the surface to obtain the medium filling layer 302, which is directly used as the filling material layer 30 to realize the reuse of the medium layer 203 of the next interconnection layer 20. In the case of the first protective layer 40, the filling material layer 30 is stacked on the first protective layer 40. The two layers of materials can be consistent or different, and the deposition process can be consistent or different. In the case of the same material of the first protective layer 40 and the medium filling layer 302, there is no need to additionally introduce other material deposition processes and redundant cleaning processes, which significantly simplifies the process complexity.

[0106] In some embodiments, referring to Figures 8-9 After S13: performing a surface polishing process on the initial medium filling layer 50 to form a medium filling layer 302 as the filling material layer 30, the method further comprises S14-S15:

[0107] S14: performing a patterned etching on the medium filling layer 302 to form an interconnection via hole 305 corresponding to the metal interconnection structure 202 and an opening 304 corresponding to the metal layer 201;

[0108] S15: filling the interconnection via hole 305 and the opening 304 based on a metal deposition process to form the metal interconnection structure 202 and the metal layer 201 of the next interconnection layer 20.

[0109] Specifically, after the formation of the dielectric fill layer 302, the metal interconnect structure 202 and the metal layer 201 of the next interconnect layer 20 are prepared, the dielectric fill layer 302 is first masked, the masking layer is patterned and exposed to expose the dielectric fill layer region corresponding to the metal layer 201, and then the exposed region is etched to form an opening 304 for filling the metal wiring structure of the metal layer 201. Next, the dielectric fill layer region corresponding to the interconnect via 305 is patterned and exposed, and the exposed region is etched to form an interconnect via 305 through the dielectric fill layer 302. In one embodiment, the metal interconnect structure 202 and the metal layer 201 are Cu structures, which can be prepared based on a copper electrochemical plating (Cu ECP, Electrochemical Plating) process.

[0110] Specifically, after the removal of the masking layer on the dielectric fill layer 302, the metal material of the advanced process is deposited to fill the interconnect via 305, to obtain the metal interconnect structure 202 of the next interconnect layer 20, and the metal fill layer 303 is formed by depositing the metal material and stacking on the dielectric fill layer 302, and the metal fill layer 303 is subjected to chemical mechanical polishing treatment with the dielectric fill layer 302 as a stop layer, to obtain the metal layer 201 of the next interconnect layer 20. In some embodiments, before depositing the metal material, an isolation material is also deposited on the sidewall of the interconnect via and the inner wall of the opening to form a barrier layer, which can include but is not limited to silicon nitride, silicon oxynitride, etc., to protect the dielectric layer 203 and the metal structure, and avoid material diffusion and other problems. It can be understood that the materials of the metal interconnect structure 202 and the metal layer 201 can be the same or different.

[0111] In this embodiment, the deep trench 106 is filled with dielectric material and covers the interconnect layer 20, the deep trench isolation structure 301 formed by the dielectric material and the dielectric layer 203 of the next interconnect layer 20 are formed in the same deposition process, the DTI preparation is integrated into the dielectric layer 203 preparation process of the next interconnect layer 20, and the process is simplified.

[0112] In other embodiments, referring to Figure 13, the medium filling layer 302 is located in the region of the deep trench 106 and only covers the sidewall of the deep trench 106, and the filling material layer 30 further comprises a metal filling layer 303, part of the metal filling layer 303 is a metal plug structure 301a filling the deep trench 106, and part of the metal filling layer 303 is located in the region where the medium filling layer 302 is stacked on at least one interconnection layer 20, to reuse the metal layer 201 and the metal interconnection structure 202 of the next interconnection layer 20. In this way, the medium layer 203, the metal layer 201 and the metal interconnection structure 202 of the next interconnection layer 20 are formed by the cooperation of the medium material filling and the metal material filling of the DTI, so that the preparation of the next interconnection layer 20 is completed when the DTI is prepared, and the high integration of the DTI integration process and the interconnection layer preparation process is realized.

[0113] Specifically, the metal plug structure 301a is electrically connected with the substrate layer 101 of the substrate 10, and can serve as a ground electrode, thereby improving the isolation effect of the deep trench isolation structure 301.

[0114] Correspondingly, in some embodiments, with reference to Figures 10-14 S13: filling the deep trench 106 with isolation material to form a filling material layer 30 filling the deep trench 106 and stacked on at least one interconnection layer 20, comprising S133-S134:

[0115] S133: depositing a medium material to form a medium filling layer 302 covering the sidewall of the deep trench 106 and stacked on at least one interconnection layer 20;

[0116] S134: depositing a metal material to fill the deep trench 106, the interconnection via hole 305 corresponding to the metal interconnection structure 202 of the next interconnection layer 20, and the opening 304 corresponding to the metal layer 201 of the next interconnection layer 20, to obtain a metal filling layer 303.

[0117] Specifically, the medium filling layer 302 exposes the bottom of the deep trench 106, and has the interconnection via hole 305 corresponding to the metal interconnection structure 202 of the next interconnection layer 20 and the opening 304 corresponding to the metal layer 201 of the next interconnection layer 20. By forming the medium filling layer 302 with the interconnection via hole 305 and the opening 304 of the next interconnection layer 20, the process integration of DTI preparation and interconnection layer preparation is realized, and the process is simplified.

[0118] Specifically, the region of the dielectric filling layer 302 covering the sidewall of the deep trench 106 and the metal plug structure 301a of the metal filling layer 303 filling the deep trench 106 form a deep trench isolation structure 301, the region of the dielectric filling layer 302 laminated on at least one interconnection layer 20 is reused as a dielectric layer 203 of the next interconnection layer 20, the region of the metal filling layer 303 filling the interconnection via 305 is a metal interconnection structure 202 of the next interconnection layer 20, and the region of the metal filling layer 303 filling the opening 304 is a metal layer 201 of the next interconnection layer 20. Specifically, the metal plug structure 301a, the metal interconnection structure 202 and the metal layer 201 of the next interconnection layer 20 are formed based on the same metal material deposition process, further simplifying the process.

[0119] Specifically, the dielectric filling layer 302 isolates the metal plug structure 301a and the functional elements in the substrate 10, and isolates the metal plug structure 301a and the metal layer 201, achieving isolation and high pressure resistance effects.

[0120] In some embodiments, S133: depositing a dielectric material to form a dielectric filling layer 302 covering the sidewall of the deep trench 106 and laminated on at least one interconnection layer 20 includes S1331-S1333:

[0121] S1331: depositing an initial dielectric filling layer 50;

[0122] S1332: patterning and etching the initial dielectric filling layer 50 to form an opening 304 corresponding to the metal layer 201 of the next interconnection layer 20;

[0123] S1333: forming an interconnection via 305 corresponding to the metal interconnection structure 202 of the next interconnection layer 20 and exposing the bottom of the deep trench 106 based on the patterning and etching, to obtain the dielectric filling layer 302.

[0124] Specifically, the initial dielectric filling layer 50 covers the sidewall of the deep trench 106 and is laminated on at least one interconnection layer 20, and has a cavity 501 in the deep trench 106, which is enclosed by the initial dielectric filling layer 50. Referring to Figure 10 , the initial dielectric filling layer 50 covers the sidewall, bottom and the interconnection layer 20 currently located at the top layer of the deep trench 106, and preferably, the top end of the cavity 501 is higher than the interconnection layer 20 currently located at the top layer, so as to facilitate the electrical connection between the metal plug structure 301a and the metal layer 201.

[0125] In some embodiments, the initial dielectric fill layer 50 can be formed based on at least one of HDP, SACVD, HARP (High Aspect Ratio Process) or other CVD processes. In one example, the interconnect layer is formed based on Cu advanced process, the initial dielectric fill layer 50 and the dielectric fill layer 30 can include NDC (Nitride Doped Silicon Carbide) layer, low k BD (Low-k Bonding Dielectric) layer and PETEOS (Plasma-Enhanced Tetraethyl Orthosilicate) layer, or can include NDC layer, low k BD layer and HDP layer.

[0126] Specifically, the cavity 501 in the dielectric fill layer 302 for forming the metal plug structure 301a in the deep trench 106 is formed by adjusting the process parameters of the dielectric material deposition process.

[0127] It can be understood that before the initial dielectric fill layer 50 is patterned and etched, a surface polishing process is further included to achieve surface planarization. The thickness of the dielectric material of the initial dielectric fill layer 50 at the top of the cavity is greater than or equal to the thickness of the metal layer 201 of the next interconnect layer 20, and is preferably greater than the thickness of the metal layer 201 of the first interconnect layer 20, so as to facilitate the preparation of the opening 304.

[0128] Specifically, a second masking layer 109 is formed on the initial dielectric fill layer 50, and then the area corresponding to the metal layer 201 of the next interconnect layer 20 of the second masking layer 109 is exposed, so as to etch the initial dielectric fill layer 50 to form the opening 304 (see Figure 11 ).

[0129] In some embodiments, the opening 304 corresponding to the metal layer 201 of the next interconnect layer 20 includes a first opening 304a and a second opening 304b, the first opening 304a is located above the deep trench 106, and the second opening 304b is the opening 304 required to be formed in the original device structure for the next interconnect layer 20, for forming a metal wiring structure electrically connected to the interconnect layer 20 currently located at the top layer.

[0130] In one embodiment, the first opening 304a is located at the initial dielectric filling layer region at the top end of the cavity 501, so as to facilitate the direct electrical connection between the metal plug structure 301a and the metal layer 201, without the need to form an interconnection via hole 305 at this location, thereby reducing the process difficulty and the contact resistance between the metal plug structure 301a and the metal layer 201. In some cases, the opening 304 is formed to expose the top end of the cavity 501 (not shown). In other cases, referring to Figure 11 , after the opening 304 is formed, the thickness of the initial dielectric filling layer region at the top end of the cavity 501 matches the thickness of the initial dielectric filling layer region at the bottom of the deep trench 106, such as the thickness is consistent or the thickness is similar, so as to protect the dielectric material at the sidewall of the deep trench 106 during the subsequent dielectric etching back process.

[0131] Specifically, after the opening 304 is etched, the surface of the initial dielectric filling layer 203 and the opening 304 are shielded by the third shielding layer 110, then the region corresponding to the interconnection via hole 305 in the third shielding layer 110 is exposed, and the region at the top end of the cavity 501 is exposed, referring to Figure 12 , the exposed initial dielectric filling layer 50 region is etched, thereby forming the interconnection via hole 305, and in this process, the initial dielectric filling layer regions at the top end of the cavity 501 and the bottom of the deep trench 106 are etched back to expose the cavity 501 and the bottom of the deep trench 106, so as to realize the communication between the cavity 501 and the first opening 304a, and obtain the dielectric filling layer 302 (refer to Figure 12 ). In this way, it is beneficial to directly form the electrically connected metal layer 201 and the metal plug structure 301a by metal deposition, and to connect the metal plug structure 301a with the substrate 10.

[0132] In some embodiments, before S134: depositing a metal material to fill the deep trench 106, the interconnection via hole 305 corresponding to the metal interconnection structure 202 of the next interconnection layer 20, and the opening 304 corresponding to the metal layer 201 of the next interconnection layer 20, to obtain the metal filling layer 303, the method further comprises: performing ion implantation on the bottom of the deep trench 106 to form a doped structure 306 located at the bottom of the deep trench 106, and the metal plug structure 301a is connected with the doped structure 306. In this way, through the doped ion implantation process at the bottom of the trench, the substrate structure at the sidewall of the deep trench 106 can be effectively protected, and it is beneficial to the subsequent filling of the metal material and the full contact with the doped structure 306.

[0133] In some embodiments, referring to Figures 14-15The metal filling layer 303 also includes a region stacked on the dielectric filling layer 302. After S134, a metal material is deposited to fill the deep trench 106, the via hole 305 corresponding to the metal interconnection structure 202 of the next interconnection layer 20, and the opening 304 corresponding to the metal layer 201 of the next interconnection layer 20, thereby obtaining the metal filling layer 303. The method further includes S135, polishing the metal filling layer 303 with the dielectric filling layer 302 as a stop layer, to remove the region of the metal filling layer 303 stacked on the dielectric filling layer 302, thereby forming the metal layer 201 of the next interconnection layer 20.

[0134] Specifically, the metal filling layer 303 can be polished by a chemical mechanical polishing process. It can be understood that the polishing process of the metal filling layer is a self-process of the interconnection layer preparation, without the need of additional redundant process steps.

[0135] In some embodiments, referring to Figure 16 The metal plug structure 301a has an air gap 301b formed therein. Specifically, the air gap 301b can be formed by adjusting the process parameters of the metal deposition process. It can be understood that the metal material and the substrate 10 material have a large difference in thermal expansion coefficient, and the air gap 301b can play a role of elastic buffer in the heating process, thereby avoiding the problem of cracking of the substrate 10 material caused by the difference in thermal expansion coefficient.

[0136] In this embodiment, the deep trench isolation structure 301 with the dielectric filling layer 302 and the metal plug structure 301a is integrated in the device. During the preparation of the structure, the dielectric layer 203, the metal interconnection structure 202, and the metal layer 201 of the next interconnection layer 20 are formed simultaneously, thereby realizing the high integration of the DTI integration process.

[0137] Specifically, the next interconnection layer 20 can be the last interconnection layer 20 in the metal interconnection layer, and correspondingly, the metal layer 201 of the next interconnection layer 20 is a top metal layer, or it can also be an intermediate interconnection layer, and the metal layer 201 therein is also a corresponding intermediate metal layer.

[0138] In summary, the technical solution above etches the deep trench 106 after the preparation process of the first interconnection layer or the intermediate interconnection layer of the back end of line (BEOL), specifically, etches the trench after the CMP process of the metal layer 201 of the interconnection layer 20, so as to cooperatively prepare the dielectric layer 203 of the next interconnection layer 20 or the whole next interconnection layer 20 in the DTI preparation process, realize high integration of the process, and reduce the heat demand of the DTI process, thereby reducing the risk of device damage caused by DTI integration. Moreover, the integration of the DTI does not need to introduce additional dielectric layer 203 deposition or metal deposition processes, thereby avoiding thickening of the dielectric layer 203 or the metal layer 201 of the interconnection layer 20, and thus avoiding increasing the device resistance, which is beneficial to device size miniaturization.

[0139] The embodiments of the present application also provide a device based on an advanced process, which is prepared based on the preparation method described above. Referring to Figure 9 、 Figure 15 and Figure 16 The device based on the advanced process includes a substrate 10, at least one interconnection layer 20 located on the substrate 10, a deep trench 106, and a filling material layer 30; the substrate 10 is formed with functional elements of a semiconductor device; the interconnection layer 20 is prepared based on the advanced process, is located between a top metal layer and the substrate 10, and includes a metal layer 201, a metal interconnection structure 202, and a dielectric layer 203; the metal interconnection structure 202 longitudinally penetrates the dielectric layer 203 and is electrically connected with the metal layer 201; the deep trench 106 penetrates at least one interconnection layer 20 and then extends into the substrate 10; and the filling material layer 30 fills the deep trench 106 and is stacked on at least one interconnection layer 20, and a material region of the filling material layer 30 stacked on at least one interconnection layer 20 is reused by a next interconnection layer 20 adjacent to at least one interconnection layer 20.

[0140] In a possible implementation, a top interconnection layer 20 of the at least one interconnection layer 20 exposes a surface of the metal layer 201, and the device further includes a first protective layer 40 covering the metal layer 201 of the top interconnection layer 20 of the at least one interconnection layer 20, and the deep trench 106 penetrates the first protective layer 40 and the at least one interconnection layer 20 and then extends into the substrate 10.

[0141] In a possible implementation, the substrate 10 includes a substrate layer 101, an epitaxial layer 102, and a doped buried layer 103 longitudinally across the substrate layer 101 and the epitaxial layer 102, and the deep trench 106 penetrates the at least one interconnection layer 20 and the epitaxial layer 102 and then extends into the substrate layer 101; the deep trench 106 is connected with the doped buried layer 103, so as to isolate adjacent device modules.

[0142] In a possible implementation, the shallow trench isolation structure 104 is formed in the epitaxial layer 102, and the deep trench 106 extends through at least one interconnection layer 20, the shallow trench isolation structure 104, and the epitaxial layer 102 in sequence and extends into the substrate layer 101.

[0143] In a possible implementation, the part of the filling material layer 30 filling the deep trench 106 forms a deep trench isolation structure 301, and the deep trench isolation structure 301 has an enclosed air gap 301b.

[0144] In a possible implementation, the filling material layer 30 includes a dielectric filling layer 302 covering at least a sidewall of the deep trench 106 and stacked on at least one interconnection layer 20, and a region of the dielectric filling layer 302 stacked on at least one interconnection layer 20 is reused as a dielectric layer 203 of a next interconnection layer 20.

[0145] In some embodiments, the dielectric filling layer 302 fills a region of the deep trench 106 to form a deep trench isolation structure 301, and the deep trench isolation structure 301 has an air gap 301b enclosed by the dielectric filling layer 302.

[0146] In another embodiment, the filling material layer 30 further includes a metal filling layer 303, and part of the metal filling layer 303 is a metal plug structure 301a filling the deep trench 106, and part of the metal filling layer 303 is located in a region of the dielectric filling layer 302 stacked on at least one interconnection layer 20, to be reused as a metal layer 201 and a metal interconnection structure 202 of a next interconnection layer 20.

[0147] In a possible implementation, the device further includes a doped structure 306 at a bottom of the deep trench 106, and the metal plug structure 301a is connected to the doped structure 306.

[0148] In a possible implementation, the metal plug structure 301a has an air gap 301b.

[0149] It should be noted that the device embodiment based on the advanced process in the present application is implemented based on the device preparation method embodiment based on the advanced process, and both are based on the same inventive concept.

[0150] The device embodiment based on the advanced process in the present application also provides an electronic device including the device based on the advanced process. Specifically, the electronic device includes the device based on the advanced process and an electronic component connected to the device based on the advanced process.

[0151] The electronic device of the embodiments of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a pad, a notebook computer, a game machine, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PlayStation Portable (PSP), and the like, and can also be any intermediate product of an electronic device including the above-mentioned device manufactured based on an advanced process.

[0152] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The above-mentioned embodiments of the present application are described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from the order in the embodiments and still achieve the desired result. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In some embodiments, multi-task processing and parallel processing are possible or advantageous.

[0153] Each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0154] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by a program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0155] The above-mentioned is only the preferred embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A device fabrication method based on advanced process technology, characterized in that, include: An initial device structure is provided, the initial device structure including a substrate and at least one interconnect layer located on the substrate, wherein functional elements of a semiconductor device are formed in the substrate, including a substrate layer, an epitaxial layer, and a doped buried layer spanning the substrate layer and the epitaxial layer, a shallow trench isolation structure is formed in the epitaxial layer, the at least one interconnect layer is located between a top metal layer and the substrate, the interconnect layer is fabricated based on an advanced process and includes a metal layer, a metal interconnect structure and a dielectric layer, the metal interconnect structure extending longitudinally through the dielectric layer and electrically connected to the metal layer; A deep trench is formed in the initial device structure. The deep trench passes through the at least one interconnect layer, the shallow trench isolation structure and the epitaxial layer in sequence and then extends into the substrate layer. The deep trench is connected to the doped buried layer to isolate adjacent device modules. The deep trench is filled with an isolation material to form a filling material layer that fills the deep trench and is stacked on the at least one interconnect layer. The next interconnect layer adjacent to the at least one interconnect layer reuses the area of ​​the filling material layer stacked on the at least one interconnect layer.

2. The preparation method according to claim 1, characterized in that, The method further includes, prior to forming a deep trench in the initial device structure, the top interconnect layer of the at least one interconnect layer exposing the surface of the metal layer: A first protective layer is formed, which covers the metal layer of the top interconnect layer in the at least one interconnect layer, and the deep trench penetrates the first protective layer and the at least one interconnect layer and extends into the substrate.

3. The preparation method according to claim 1, characterized in that, The portion of the filling material layer that fills the deep trench forms a deep trench isolation structure, the deep trench isolation structure having a closed air gap, the air gap being at least located in the substrate.

4. The preparation method according to claim 1, characterized in that, The filling material layer includes at least a dielectric filling layer covering the sidewalls of the deep trench and stacked on the at least one interconnect layer; The region in the dielectric filling layer that is stacked on the at least one interconnect layer is reused as the dielectric layer of the next interconnect layer.

5. The preparation method according to claim 4, characterized in that, The dielectric filling layer fills the region of the deep trench to form a deep trench isolation structure, the deep trench isolation structure having an air gap sealed by the dielectric filling layer, the dielectric filling layer being formed based on a high-density plasma deposition process.

6. The preparation method according to claim 4, characterized in that, The filling material layer further includes a metal filling layer, part of which is a metal plug structure filling the deep trench, and part of which is located in the region where the dielectric filling layer is stacked on the at least one interconnect layer, so as to be reused as the metal layer and metal interconnect structure of the next interconnect layer.

7. The preparation method according to any one of claims 1-5, characterized in that, The step of filling the deep trench with an isolation material to form a filling material layer that fills the deep trench and is stacked on the at least one interconnect layer includes: A dielectric material is deposited to form an initial dielectric filling layer that fills the deep trench and is stacked on the at least one interconnect layer, wherein the region of the initial dielectric filling layer that fills the deep trench forms a deep trench isolation structure and has a closed air gap; The initial dielectric filling layer is surface polished to form a dielectric filling layer, which serves as the filling material layer.

8. The preparation method according to claim 7, characterized in that, After the initial dielectric filling layer is surface polished to form a dielectric filling layer as the filling material layer, the method further includes: The dielectric filling layer is patterned and etched to form interconnect vias corresponding to the metal interconnect structure and openings corresponding to the metal layer. The interconnect vias and openings are filled using a metal deposition process to form the metal interconnect structure and metal layer of the next interconnect layer.

9. The preparation method according to any one of claims 1-4 and 6, characterized in that, The step of filling the deep trench with an isolation material to form a filling material layer that fills the deep trench and is stacked on the at least one interconnect layer includes: A dielectric material is deposited to form a dielectric filling layer covering the sidewalls of the deep trench and stacked on the at least one interconnect layer, the dielectric filling layer exposing the bottom of the deep trench and having interconnect vias corresponding to the metal interconnect structure of the next interconnect layer and openings corresponding to the metal layer of the next interconnect layer; A metal material is deposited to fill the deep trench, the interconnect vias corresponding to the metal interconnect structure of the next interconnect layer, and the openings corresponding to the metal layer of the next interconnect layer, to obtain a metal filling layer. The area of ​​the dielectric filling layer covering the sidewall of the deep trench and the metal plug structure of the metal filling layer filling the deep trench form a deep trench isolation structure. The area of ​​the dielectric filling layer stacked on the at least one interconnect layer is reused as the dielectric layer of the next interconnect layer. The area of ​​the metal filling layer filling the interconnect vias is the metal interconnect structure of the next interconnect layer. The area of ​​the metal filling layer filling the openings is the metal layer of the next interconnect layer.

10. The preparation method according to claim 9, characterized in that, Before depositing the metal material to fill the deep trench, the interconnect vias corresponding to the metal interconnect structure of the next interconnect layer, and the openings corresponding to the metal layer of the next interconnect layer, to obtain the metal filling layer, the method further includes: Ion implantation is performed on the bottom of the deep trench to form a doped structure located at the bottom of the deep trench, and the metal plug structure is connected to the doped structure.

11. The preparation method according to claim 9, characterized in that, The deposition of dielectric material to form a dielectric filling layer covering the sidewalls of the deep trench and stacked on the at least one interconnect layer includes: An initial dielectric filling layer is deposited, the initial dielectric filling layer covering the trench walls and stacked on the at least one interconnect layer, and having a cavity located in the deep trench, the cavity being closed by the initial dielectric filling layer; The initial dielectric filling layer is patterned and etched to form an opening corresponding to the metal layer of the next interconnect layer. The opening corresponding to the metal layer of the next interconnect layer includes a first opening and a second opening. The first opening is located above the deep trench. Based on patterned etching, interconnect vias corresponding to the metal interconnect structure of the next interconnect layer are formed and the bottom of the deep trench is exposed to obtain the dielectric filling layer, and the cavity is connected to the first opening.

12. The preparation method according to claim 9, characterized in that, The metal filler layer further includes a region stacked on the dielectric filler layer. After depositing metal material to fill the deep trench, the interconnect vias corresponding to the metal interconnect structure of the next interconnect layer, and the openings corresponding to the metal layer of the next interconnect layer to obtain the metal filler layer, the method further includes: Using the dielectric filling layer as a stop layer, the metal filling layer is polished to remove the area where the metal filling layer overlaps the dielectric filling layer.

13. The preparation method according to claim 9, characterized in that, An air gap is formed in the metal plug structure.

14. The preparation method according to any one of claims 1-6, characterized in that, The advanced process is the Damascus process.

15. A device based on an advanced process technology, characterized in that, include: A substrate on which functional elements of a semiconductor device are formed, including a substrate layer, an epitaxial layer, and a doped buried layer spanning the substrate layer and the epitaxial layer, wherein a shallow trench isolation structure is formed in the epitaxial layer; At least one interconnect layer is located on the substrate, fabricated using advanced process technology, and situated between the top metal layer and the substrate. The interconnect layer includes a metal layer, a metal interconnect structure, and a dielectric layer. The metal interconnect structure extends longitudinally through the dielectric layer and is electrically connected to the metal layer. A deep trench extends sequentially through the at least one interconnect layer, the shallow trench isolation structure, and the epitaxial layer into the substrate layer. The deep trench is connected to the doped buried layer to isolate adjacent device modules. A filler material layer fills the deep trench and is stacked on the at least one interconnect layer, and the next interconnect layer adjacent to the at least one interconnect layer reuses the material region in the filler material layer that is stacked on the at least one interconnect layer.

16. The device according to claim 15, characterized in that, The advanced process is the Damascus process.

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