Package structure including inactive device, assembly structure and manufacturing method thereof

Abstract

The invention provides a packaging structure, an assembly structure and a preparation method thereof. The packaging structure comprises at least one semiconductor element, at least one inactive element and a packaging colloid. At least one inactive device is disposed around the at least one semiconductor device and includes a main portion and at least one via extending through the main portion. The encapsulant encapsulates the at least one semiconductor element and the at least one inactive element. A first surface of the encapsulant is substantially coplanar with a first surface of the at least one inactive element and a first surface of the at least one semiconductor element. A second surface of the encapsulant is substantially coplanar with a second surface of the at least one inactive device and a second surface of the at least one semiconductor device.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202410588612.0, entitled “Packaging structure, assembly structure and manufacturing method thereof including non-active elements”, filed on May 13, 2024. Application No. 202410588612.0 claims priority and benefits of U.S. formal application No. 18 / 600,997, filed on March 11, 2024. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a packaging structure, an assembly structure, and a method for manufacturing the same, and more particularly to a packaging structure including at least one non-active component, an assembly structure including the packaging structure, and a method for manufacturing the same. Background Art

[0003] Semiconductor electronic components are widely used in various electronic applications, and their size is constantly decreasing to meet the needs of current applications. However, reducing the size of semiconductor electronic components brings some challenges that affect their final electronic characteristics, quality, cost and yield. As semiconductor electronic components become smaller and smaller, they require multifunctionality and large-capacity data processing capabilities. Therefore, there is an increasing need to improve the integration of semiconductor elements used in these electronic components. However, due to the limitations of semiconductor integration technology, it is challenging to use only a single semiconductor chip to meet all the required functions. To solve this problem, semiconductor packages have been developed, which involve including multiple semiconductor chips.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the Invention

[0005] One embodiment of the present disclosure provides a packaging structure comprising a first molded structure, a first redistribution structure, and a second molded structure. The first molded structure has a first surface and a second surface opposite to the first surface, and comprises at least one semiconductor element, at least one non-active element, and a packaging colloid. The at least one non-active element is disposed around the at least one semiconductor element and comprises a main portion and at least one through hole passing through the main portion. The packaging colloid encapsulates the at least one semiconductor element and the at least one non-active element. The first redistribution structure is disposed on the first surface of the first molded structure. The second redistribution structure is disposed on the second surface of the first molded structure and is electrically connected to the first redistribution structure through the at least one through hole of the at least one non-active element.

[0006] Another embodiment of the present disclosure provides an assembly structure comprising a substrate, a first molded structure, a second molded structure, and an upper electronic component. The first molded structure is disposed above the substrate. The first molded structure includes at least one semiconductor component, at least one non-active component, and a packaging colloid that encapsulates the at least one semiconductor component and the at least one non-active component. The second molded structure is disposed between the first molded structure and the substrate. The second molded structure includes at least one semiconductor component, at least one non-active component, and a packaging colloid that encapsulates the at least one semiconductor component and the at least one non-active component. The upper electronic component is disposed above the first molded structure. The at least one non-active component of the first molded structure and the at least one non-active component of the second molded structure are configured to provide a vertical conductive path between the upper electronic component and the substrate.

[0007] Another embodiment of the present disclosure provides a manufacturing method. The manufacturing method includes forming a first molding structure on a first carrier; disposing an upper electronic component on the first molding structure; removing the first carrier; forming a second molding structure on a second carrier; attaching the upper electronic component and the first molding structure to the second molding structure; and removing the second carrier.

[0008] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0010] Figure 1 is a cross-sectional schematic diagram illustrating the assembly structure of some embodiments of the present disclosure.

[0011] Figure 2 This is a partial schematic diagram, illustrating Figure 1 The upper part of the assembly structure.

[0012] Figure 3 This is an enlarged schematic diagram, illustrating Figure 2 area "A".

[0013] Figure 4This is a partial schematic diagram, illustrating Figure 1 The lower part of the assembly structure.

[0014] Figure 5 This is an enlarged schematic diagram, illustrating Figure 4 area "B".

[0015] Figure 6 It is a top view schematic diagram, illustrating Figure 1 The first molded structure of the assembled structure.

[0016] Figure 7 It is a top view schematic diagram, illustrating Figure 1 The second molded structure of the assembled structure.

[0017] Figure 8 is a top view schematically illustrating a first molding structure according to some embodiments of the present disclosure.

[0018] Figure 9 is a top view schematically illustrating a second molding structure according to some embodiments of the present disclosure.

[0019] Figure 10 is a top view schematically illustrating a first molding structure according to some embodiments of the present disclosure.

[0020] Figure 11 is a top view schematically illustrating a second molding structure according to some embodiments of the present disclosure.

[0021] Figure 12 is a cross-sectional schematic diagram illustrating the assembly structure of some embodiments of the present disclosure.

[0022] Figure 13 is a cross-sectional schematic diagram illustrating the assembly structure of some embodiments of the present disclosure.

[0023] Figures 14 to 25 Schematic cross-sectional views illustrating various stages of a method of manufacturing an assembly structure according to some embodiments of the present disclosure.

[0024] Figure 26 Schematic diagram of a process illustrating a method for preparing an assembly structure according to some embodiments of the present disclosure.

[0025] Description of reference numerals:

[0026] 1: Assemble the structure

[0027] 1a: Assembling the structure

[0028] 1b: Assembling the structure

[0029] 2: Second molding structure

[0030] 2a: Second molding structure

[0031] 2b: Second molding structure

[0032] 3: Non-active components

[0033] 4: The third distribution structure

[0034] 5: First molding structure

[0035] 5a: First Molding Structure

[0036] 5b: First molded structure

[0037] 6: Non-active components

[0038] 7: First distribution structure

[0039] 8: Second distribution structure

[0040] 10: Package structure

[0041] 10b: Package structure

[0042] 12: Base

[0043] 14: Bump

[0044] 16: External connector

[0045] 18: Install electronic components

[0046] 19: Welding materials

[0047] 20: Semiconductor components

[0048] 21: First surface

[0049] 22: Second Surface

[0050] 23: Side surface

[0051] 25: First semiconductor element

[0052] 26: Second semiconductor element

[0053] 27: Encapsulation colloid

[0054] 31: First non-active element

[0055] 32: Second non-active element

[0056] 32b: Second non-active element

[0057] 33: The third non-active element

[0058] 33b: Third non-active element

[0059] 34: Fourth non-active element

[0060] 34b: Fourth non-active element

[0061] 41: First surface

[0062] 42: Second surface

[0063] 43: Side surface

[0064] 44: Dielectric layer

[0065] 45: Circuit layer

[0066] 46: Internal through hole

[0067] 47: Solder pad

[0068] 50: Semiconductor components

[0069] 51: First surface

[0070] 52: Second surface

[0071] 53: Side surface

[0072] 55: First semiconductor element

[0073] 56: Second semiconductor element

[0074] 57: Encapsulation colloid

[0075] 61: First non-active element

[0076] 62: Second non-active element

[0077] 62b: Second non-active element

[0078] 63: The third non-active element

[0079] 63b: Third non-active element

[0080] 64: Fourth non-active element

[0081] 64b: Fourth non-active element

[0082] 71: First surface

[0083] 72: Second surface

[0084] 73: Side surface

[0085] 74: Dielectric layer

[0086] 75: Circuit layer

[0087] 76: Internal through hole

[0088] 77: Solder pad

[0089] 81: First surface

[0090] 82: Second Surface

[0091] 83: Side surface

[0092] 84: Dielectric layer

[0093] 85: Circuit layer

[0094] 86: Internal through hole

[0095] 87: Solder pad

[0096] 90: First carrier

[0097] 91: Release layer

[0098] 92: Second carrier

[0099] 93: Release layer

[0100] 121: First surface

[0101] 122: Second surface

[0102] 123: Side surface

[0103] 141: First bump

[0104] 142: Second bump

[0105] 180: Main part

[0106] 181: First surface

[0107] 182: Second surface

[0108] 183: Side surface

[0109] 184: Active circuit structure

[0110] 185: Solder pad

[0111] 191: Welding materials

[0112] 250: Main part

[0113] 251: First surface

[0114] 252: Second surface

[0115] 253: Side surface

[0116] 254: Active circuit structure

[0117] 255: Solder pad

[0118] 271: First Surface

[0119] 272: Second surface

[0120] 273: Side surface

[0121] 281: Space

[0122] 282: Space

[0123] 283: Space

[0124] 310: Main part

[0125] 311: First surface

[0126] 312: Second surface

[0127] 313: Side surface

[0128] 314: Side surface

[0129] 315: Through hole

[0130] 441: Top dielectric layer

[0131] 442: Bottom dielectric layer

[0132] 550: Main part

[0133] 551: First surface

[0134] 552: Second surface

[0135] 553: Side surface

[0136] 554: Active circuit structure

[0137] 555: Solder pad

[0138] 571: First surface

[0139] 572: Second surface

[0140] 573: Side surface

[0141] 581: Space

[0142] 582: Space

[0143] 583: Space

[0144] 610: Main part

[0145] 611: First surface

[0146] 612: Second surface

[0147] 613: Side surface

[0148] 614: Side surface

[0149] 615: Through hole

[0150] 741: Top dielectric layer

[0151] 742: Bottom dielectric layer

[0152] 841: Bottom dielectric layer

[0153] 842: Top dielectric layer

[0154] 900: Preparation method

[0155] 1801: Lower surface

[0156] 2501: Upper surface

[0157] 3151: First surface

[0158] 3152: Second surface

[0159] 3153: Central axis

[0160] 5501: Top surface

[0161] 6151: First surface

[0162] 6152: Second surface

[0163] 6153: Central axis

[0164] g1: gap

[0165] g2: gap

[0166] g3: first gap

[0167] g4: Second gap

[0168] L1: length

[0169] L2: length

[0170] L3: Length

[0171] L4: Length

[0172] S901: Steps

[0173] S902: Step

[0174] S903: Step

[0175] S904: Steps

[0176] S905: Steps

[0177] S906: Steps

[0178] T1: thickness

[0179] T2: Thickness

[0180] T3: Thickness

[0181] T4: Thickness

[0182] W1: width

[0183] W2: width

[0184] W3: Width

[0185] W4: Width

[0186] W5: width

[0187] W6: Width DETAILED DESCRIPTION

[0188] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0189] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0190] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0191] Figure 12 is a cross-sectional schematic diagram illustrating an assembly structure 1 according to some embodiments of the present disclosure. Figure 2 This is a partial schematic diagram, illustrating Figure 1 The upper part of the assembly structure 1. Figure 3 This is an enlarged schematic diagram, illustrating Figure 2 area "A". Figure 4 This is a partial schematic diagram, illustrating Figure 1 The lower part of the assembly structure 1. Figure 5 This is an enlarged schematic diagram, illustrating Figure 4 In some embodiments, the assembly structure 1 may be a semiconductor electronic component, a semiconductor electronic structure, or a package structure. In some embodiments, the assembly structure 1 may include a package structure 10, a substrate 12, a plurality of bumps 14, and a plurality of external connectors 16.

[0192] Substrate 12 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials. In some embodiments, substrate 12 may include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, substrate 12 may include an organic material, glass, a ceramic material, or the like. For example, substrate 12 may include a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. For example, substrate 12 may include a homogeneous material. For example, the material of the substrate 12 may include epoxy FR5, FR4, bismaleimide triazine (BT), printed circuit board (PCB) material, prepreg (PP), Ajinomoto build film (ABF), or other suitable materials.

[0193] The substrate 12 may have a first surface 121 (e.g., an upper surface), a second surface 122 (e.g., a lower surface), and a side surface 123. The second surface 122 (e.g., a lower surface) may be opposite to the first surface 121 (e.g., an upper surface). The side surface 123 may extend between the first surface 121 (e.g., an upper surface) and the second surface 122 (e.g., a lower surface).

[0194] Package structure 10 may be disposed over first surface 121 of substrate 12 and may be attached to first surface 121 of substrate 12 via bumps 14. External connectors 16 may be disposed on second surface 122 of substrate 12 to provide electrical connections, such as I / O connections, to substrate 12. Each external connector 16 may include a reflowable material, such as a solder ball.

[0195] The package structure 10 may include a first molding structure 5 , a first redistribution structure 7 , a second redistribution structure 8 , a second molding structure 2 , a third redistribution structure 4 and an upper electronic component 18 .

[0196] The first molding structure 5 may be disposed above the substrate 12 and electrically connected to the substrate 12. The first molding structure 5 may have a first surface 51 (e.g., an upper surface), a second surface 52 (e.g., a lower surface), and a side surface 53. The second surface 52 (e.g., a lower surface) may be opposite to the first surface 51 (e.g., an upper surface). The side surface 53 may extend between the first surface 51 (e.g., an upper surface) and the second surface 52 (e.g., a lower surface).

[0197] Please refer to Figures 1 to 3 The first molded structure 5 may include at least one semiconductor element 50, at least one inactive element 6, and an encapsulant 57. The semiconductor element 50 may include a semiconductor die or a chip, such as a memory chip (e.g., a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.). The semiconductor element 50 may include a first semiconductor element 55 and a second semiconductor element 56 arranged side by side. In some embodiments, the size and function of the first semiconductor element 55 may be the same as the size and function of the second semiconductor element 56. The structure of the first semiconductor element 55 may be the same as the structure of the second semiconductor element 56. Both the first semiconductor element 55 and the second semiconductor element 56 may be memory dies.

[0198] The first semiconductor element 55 may have a first surface 551 (e.g., an upper surface or active surface), a second surface 552 (e.g., a lower surface or backside surface), and a side surface 553. The second surface 552 (e.g., the lower surface) may be opposite to the first surface 551 (e.g., the upper surface). The side surface 553 may extend between the first surface 551 (e.g., the upper surface) and the second surface 552 (e.g., the lower surface).

[0199] The first semiconductor element 55 may include a main portion 550 and an active circuit structure 554 disposed on an upper surface 5501 of the main portion 550. For example, a material of the main portion 550 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0200] The active circuit structure 554 may include multiple dielectric layers, multiple circuit layers, and multiple bonding pads 555. The dielectric layers may cover the circuit layers. The bonding pads 555 may be electrically connected to the circuit layers and embedded in the dielectric layers. The bonding pads 555 may be exposed from the first surface 551 of the first semiconductor element 55.

[0201] The non-active element 6 can be disposed around the semiconductor element 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56). The non-active element 6 can also be referred to as a "dummy die." The non-active element 6 can include a first non-active element 61 and a second non-active element 62 disposed around the first semiconductor element 55 and the second semiconductor element 56. The structure of the first non-active element 61 can be the same as or similar to that of the second non-active element 62.

[0202] The first passive element 61 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613 and 614. The second surface 612 (e.g., a lower surface) may be opposite to the first surface 611 (e.g., an upper surface). The side surfaces 613 and 614 may extend between the first surface 611 (e.g., an upper surface) and the second surface 612 (e.g., a lower surface).

[0203] The first non-active element 61 may include a main portion 610 and at least one through-hole 615 (or through-silicon via (TSV)) extending through the main portion 610. The main portion 610 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613 and 614. The second surface 612 (e.g., a lower surface) may be opposite to the first surface 611 (e.g., an upper surface). The side surfaces 613 and 614 may extend between the first surface 611 (e.g., an upper surface) and the second surface 612 (e.g., a lower surface). Therefore, the first surface 611, the second surface 612, and the side surfaces 613 and 614 of the first non-active element 61 may be the first surface 611, the second surface 612, and the side surfaces 613 and 614 of the main portion 610, respectively.

[0204] For example, the material of the main portion 610 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials. In some embodiments, the material of the main portion 550 of the first semiconductor element 55 may be the same as the material of the main portion 610 of the first inactive element 61.

[0205] A width W1 of the first semiconductor element 55 (or main portion 550 ) may be greater than a width W2 of the first passive element 61 (or main portion 610 ). A thickness T1 of the main portion 550 of the first semiconductor element 55 may be less than a thickness T2 of the main portion 610 of the first passive element 61 .

[0206] The semiconductor element 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56) does not include a vertical conductive path in its main portion. That is, the semiconductor element 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56) may not have a vertical conductive path to the substrate 12. For example, the first semiconductor element 55 does not include a vertical conductive path in its main portion 550.

[0207] The first passive element 61 may include a plurality of through holes 615. A gap g1 may be formed between two adjacent through holes 615. Each through hole 615 may have a central axis 6153.

[0208] The through hole 615 of the first non-active element 61 can have a first surface 6151 (e.g., an upper surface) and a second surface 6152 (e.g., a lower surface) opposite the first surface 6151 (e.g., an upper surface). The first surface 6151 of the first through hole 615 of the first non-active element 61 can be substantially coplanar with the first surface 611 of the first non-active element 61 and exposed from the first surface 611. The second surface 6152 of the through hole 615 of the first non-active element 61 can be substantially coplanar with the second surface 612 of the first non-active element 61 and exposed from the second surface 612 of the first non-active element 61. In other words, the through hole 615 of the first non-active element 61 can extend from the first surface 611 of the main portion 610 to the second surface 612 of the main portion 610.

[0209] Thus, the through-hole 615 of the first inactive component 61 can provide a vertical conductive path that extends to the main portion 610 of the first inactive component 61 and can be configured to transmit signals or power. Therefore, the first redistribution structure 7 and the upper electronic component 18 can be electrically connected to the second redistribution structure 8 and the substrate 12 through the through-hole 615 of the first inactive component 61, rather than through the semiconductor component 50 (including, for example, the first semiconductor component 55 and the second semiconductor component 56). There is no need to form a through-hole in the main portion (e.g., the main portion 550) of the semiconductor component 50 (e.g., the first semiconductor component 55 and the second semiconductor component 56).

[0210] In some embodiments, the non-active element 6 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active element 61 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 610. No horizontal conductive paths exist on the first surface 611 or the second surface 612 of the main portion 610. The non-active element 6 includes only vertical conductive paths.

[0211] The encapsulant 57 can seal the semiconductor element 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56) and the non-active element 6 (including, for example, the first non-active element 61 and the second non-active element 62). For example, the encapsulant 57 can be disposed in a space 581 between the first semiconductor element 55 and the first non-active element 61, in a space 582 between the first semiconductor element 55 and the second semiconductor element 56, and in a space 583 between the second semiconductor element 56 and the second non-active element 62. A material of the encapsulant 57 can include a molding compound with or without fillers.

[0212] The encapsulant 57 may have a first surface 571 (e.g., an upper surface), a second surface 572 (e.g., a lower surface), and a side surface 573. The second surface 572 (e.g., a lower surface) may be opposite to the first surface 571 (e.g., an upper surface). The side surface 573 may extend between the first surface 571 (e.g., an upper surface) and the second surface 572 (e.g., a lower surface).

[0213] The first surface 571 of the encapsulant 57 can be substantially coplanar or aligned with the first surface 611 of the first non-active component 61 and the first surface 551 of the first semiconductor component 55. Therefore, the first surface 51 of the first molded structure 5 can include the first surface 571 of the encapsulant 57, the first surface 611 of the first non-active component 61, and the first surface 551 of the first semiconductor component 55. Furthermore, the second surface 572 of the encapsulant 57 can be substantially coplanar or aligned with the second surface 612 of the first non-active component 61 and the second surface 552 of the first semiconductor component 55. Therefore, the second surface 52 of the first molded structure 5 can include the second surface 572 of the encapsulant 57, the second surface 612 of the first non-active component 61, and the second surface 552 of the first semiconductor component 55.

[0214] The first redistribution structure 7 can be disposed on the first surface 51 of the first molding structure 5 and electrically connected to the first surface 51. For example, the first redistribution structure 7 can be disposed on the first surface 571 of the encapsulant 57, the first surface 611 of the first inactive device 61, and the first surface 551 of the first semiconductor device 55, and electrically connected to the through-holes 615 of the first semiconductor device 55 and the first inactive device 61.

[0215] The first redistribution structure 7 may be a fan-out structure. The first redistribution structure 7 may have a first surface 71 (e.g., an upper surface), a second surface 72 (e.g., a lower surface), and a side surface 73. The second surface 72 (e.g., a lower surface) may be opposite to the first surface 71 (e.g., an upper surface). The side surface 73 may extend between the first surface 71 (e.g., an upper surface) and the second surface 72 (e.g., a lower surface). The second surface 72 of the first redistribution structure 7 may directly contact the first surface 51 of the first molding structure 5.

[0216] The first redistribution structure 7 may include a plurality of dielectric layers 74, a plurality of circuit layers 75, a plurality of inner through-holes 76, and a plurality of pads 77. The dielectric layer 74 may include a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The materials of the dielectric layers 74 may be the same as each other. In some embodiments, the material of the topmost dielectric layer 741 may be different from the materials of the other dielectric layers 74. The topmost dielectric layer 741 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. In some embodiments, the bottommost dielectric layer 742 may be omitted. The circuit layer 75 may be directly disposed on the first surface 51 of the first molded structure 5.

[0217] The circuit layer 75 may be covered by or embedded in the dielectric layer 74. The circuit layer 75 may be a fan-out circuit layer. The inner vias 76 may be embedded in the dielectric layer 74 and may connect two adjacent circuit layers 75. The inner vias 76 may gradually taper toward the first molded structure 5. The solder pads 77 may be electrically connected to the circuit layer 75 and embedded in the dielectric layer 74 (e.g., the topmost dielectric layer 741). The solder pads 77 may be exposed from the first surface 71 of the first redistribution structure 7. Each solder pad 77 may be a hybrid bonding (HB) solder pad and may include Cu or Al.

[0218] The second redistribution structure 8 can be disposed on the second surface 52 of the first molded structure 5 and electrically connected to the second surface 52 of the first molded structure 5. For example, the second redistribution structure 8 can be disposed on the second surface 572 of the encapsulant 57, the second surface 612 of the first inactive device 61, and the second surface 552 of the first semiconductor device 55, and electrically connected to the through-hole 615 of the first inactive device 61.

[0219] The second redistribution structure 8 may be a fan-out structure. The second redistribution structure 8 may have a first surface 81 (e.g., an upper surface), a second surface 82 (e.g., a lower surface), and a side surface 83. The second surface 82 (e.g., a lower surface) may be opposite to the first surface 81 (e.g., an upper surface). The side surface 83 may extend between the first surface 81 (e.g., an upper surface) and the second surface 82 (e.g., a lower surface). The first surface 81 of the second redistribution structure 8 may directly contact the second surface 52 of the first molding structure 5.

[0220] The second redistribution structure 8 may include a plurality of dielectric layers 84, a plurality of circuit layers 85, a plurality of inner through-holes 86, and a plurality of pads 87. The dielectric layer 84 may include a cured photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The materials of the dielectric layers 84 may be the same as each other. In some embodiments, the material of the bottommost dielectric layer 841 may be different from the materials of the other dielectric layers 84. The bottommost dielectric layer 841 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. In some embodiments, the topmost dielectric layer 842 may be omitted. The circuit layer 85 may be directly disposed on the second surface 52 of the first molded structure 5.

[0221] The circuit layer 85 may be covered by the dielectric layer 84 or embedded in the dielectric layer 84. The circuit layer 85 may be a fan-out circuit layer. The inner through-hole 86 may be embedded in the dielectric layer 84 and may connect two adjacent circuit layers 85. The inner through-hole 86 may gradually taper toward the first molded structure 5. The solder pad 77 may be electrically connected to the circuit layer 75 and embedded in the dielectric layer 84 (e.g., the bottommost dielectric layer 841). The solder pad 87 may be exposed from the second surface 82 of the second redistribution structure 8. Each solder pad 87 may be a hybrid bonding (HB) solder pad and may include Cu or Al.

[0222] The upper electronic component 18 can be disposed above the first surface 71 of the first redistribution structure 7 and electrically connected to the first surface 71 of the first redistribution structure 7. The upper electronic component 18 can also be disposed on the first surface 51 of the first molding structure 5 (including, for example, the first surface 571 of the encapsulant 57, the first surface 611 of the first inactive component 61, and the first surface 551 of the first semiconductor component 55).

[0223] The upper electronic component 18 may include a semiconductor die or a chip, such as a signal processing die (e.g., a digital signal processing (DSP) die), a logic die (e.g., an application processor (AP), a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a front-end chip (e.g., an analog front-end (AFE) die), or other active components.

[0224] The upper electronic component 18 may have a first surface 181 (e.g., an upper surface or a backside surface), a second surface 182 (e.g., a lower surface or an active surface), and a side surface 183. The second surface 182 (e.g., the lower surface) may be opposite to the first surface 181 (e.g., the upper surface). The side surface 183 may extend between the first surface 181 (e.g., the upper surface) and the second surface 182 (e.g., the lower surface).

[0225] The upper electronic component 18 may include a main portion 180 and an active circuit structure 184 disposed on a lower surface 1801 of the main portion 180. For example, a material of the main portion 180 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0226] The active circuit structure 184 may include a plurality of dielectric layers, a plurality of circuit layers, and a plurality of bonding pads 185. The dielectric layer may cover the circuit layer. The bonding pads 185 may be electrically connected to the circuit layer and embedded in the dielectric layer. The bonding pads 185 may be exposed from the second surface 182 of the upper electronic component 18. The active circuit structure 184 may include a bottommost dielectric layer surrounding the bonding pads 185. The bottommost dielectric layer may be a hybrid bond (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. Each bonding pad 185 may be a hybrid bond (HB) pad and may include Cu or Al.

[0227] The upper electronic component 18 can be attached to and electrically connected to the first surface 71 of the first redistribution structure 7 via hybrid bonding. That is, the second surface 182 of the upper electronic component 18 can directly contact the first surface 71 of the first redistribution structure 7. Therefore, the active circuit structure 184 of the upper electronic component 18 can be directly attached to, connected to, and in contact with the topmost dielectric layer 741 of the first redistribution structure 7. The pads 185 of the upper electronic component 18 can be directly attached to, connected to, and in contact with the pads 77 of the first redistribution structure 7.

[0228] The size and function of the upper electronic component 18 may be different from the size and function of the semiconductor element 50 (e.g., including the first semiconductor element 55 and the second semiconductor element 56) of the first mold structure 5 and the size and function of the semiconductor element 20 (e.g., including the first semiconductor element 25 and the second semiconductor element 26) of the second mold structure 2.

[0229] A width W3 of the upper electronic component 18 can be substantially equal to a width W4 of the first molding structure 5 (or a width W4 of the encapsulant 57) and a width W4 of the second molding structure 2 (or a width W4 of the encapsulant 27). A side surface 183 of the upper electronic component 18 can be substantially aligned with a side surface 53 of the first molding structure 5 (or a side surface 573 of the encapsulant 57) and a side surface 23 of the second molding structure 2 (or a side surface 273 of the encapsulant 27). The upper electronic component 18 can vertically overlap the non-active components 6 (including, for example, the first non-active component 61 and the second non-active component 62).

[0230] Please refer to Figure 1 、 Figure 4 and Figure 5The second molded structure 2 may be disposed above the substrate 12 and electrically connected to the substrate 12. The second molded structure 2 may be disposed below the first molded structure 5. The second molded structure 2 may have a first surface 21 (e.g., an upper surface), a second surface 22 (e.g., a lower surface), and a side surface 23. The second surface 22 (e.g., a lower surface) may be opposite to the first surface 21 (e.g., an upper surface). The side surface 23 may extend between the first surface 21 (e.g., an upper surface) and the second surface 22 (e.g., a lower surface).

[0231] The second molding structure 2 may include at least one semiconductor element 20, at least one passive element 3, and an encapsulant 27. The semiconductor element 20 may include a semiconductor die or a chip, such as a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.). The semiconductor element 20 may include a first semiconductor element 25 and a second semiconductor element 26 arranged side by side. In some embodiments, the size and function of the first semiconductor element 25 may be the same as those of the second semiconductor element 26. Both the first semiconductor element 25 and the second semiconductor element 26 may be memory dies.

[0232] The first semiconductor element 25 may have a first surface 251 (e.g., an upper surface or active surface), a second surface 252 (e.g., a lower surface or backside surface), and a side surface 253. The second surface 252 (e.g., the lower surface) may be opposite to the first surface 251 (e.g., the upper surface). The side surface 253 may extend between the first surface 251 (e.g., the upper surface) and the second surface 252 (e.g., the lower surface).

[0233] The first semiconductor element 25 may include a main portion 250 and an active circuit structure 254 disposed on an upper surface 2501 of the main portion 250. For example, a material of the main portion 250 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0234] The active circuit structure 254 may include multiple dielectric layers, multiple circuit layers, and multiple bonding pads 255. The dielectric layers may cover the circuit layers. The bonding pads 255 may be electrically connected to the circuit layers and embedded in the dielectric layers. The bonding pads 255 may be exposed from the first surface 251 of the first semiconductor element 25.

[0235] The non-active element 3 can be disposed around the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26). The non-active element 3 can also be referred to as a "dummy die." The non-active element 3 can include a first non-active element 31 and a second non-active element 32 disposed around the first semiconductor element 25 and the second semiconductor element 26. The structure of the first non-active element 31 can be the same as or similar to the structure of the second non-active element 32.

[0236] The first passive element 31 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a lower surface) may be opposite to the first surface 311 (e.g., an upper surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., an upper surface) and the second surface 312 (e.g., a lower surface).

[0237] The first non-active element 31 may include a main portion 310 and at least one through-hole 315 (or through-silicon via (TSV)) extending through the main portion 310. The main portion 310 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a lower surface) may be opposite to the first surface 311 (e.g., an upper surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., an upper surface) and the second surface 312 (e.g., a lower surface). Therefore, the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the first non-active element 31 may be the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the main portion 310, respectively.

[0238] For example, a material of the main portion 310 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials. In some embodiments, the material of the main portion 250 of the first semiconductor element 25 may be the same as the material of the main portion 310 of the first inactive element 31.

[0239] A width W5 of the first semiconductor element 25 (or main portion 250) can be greater than a width W6 of the first non-active element 31 (or main portion 310). The width W6 of the first non-active element 31 (or main portion 310) of the second molded structure 2 can be equal to or different from the width W2 of the first non-active element 61 (or main portion 610) of the first molded structure 5. A thickness T3 of the main portion 250 of the first semiconductor element 25 can be less than a thickness T4 of the main portion 310 of the first non-active element 31. The thickness T4 of the main portion 310 of the first non-active element 31 of the second molded structure 2 can be equal to or different from the thickness T2 of the main portion 610 of the first non-active element 61 of the first molded structure 5.

[0240] The semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) does not include a vertical conductive path in its main portion. That is, the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) may not have a vertical conductive path to the substrate 12. For example, the first semiconductor element 25 does not include a vertical conductive path in its main portion 250.

[0241] The first passive element 31 may include a plurality of through-holes 315. A gap g2 may be formed between two adjacent through-holes 315. Each through-hole 315 may have a central axis 3153. In some embodiments, the gap g1 between two adjacent through-holes 615 of the first molded structure 5 may be different from or smaller than the gap g2 between two adjacent through-holes 315 of the second molded structure 2. In some embodiments, the central axis 6153 of a through-hole 615 of the first molded structure 5 may be substantially aligned with the central axis 3153 of a through-hole 315 of the second molded structure 2. In some embodiments, the central axes 6153 of all through-holes 615 of the first molded structure 5 may be aligned or misaligned with the central axes 3153 of all through-holes 315 of the second molded structure 2.

[0242] The through hole 315 of the first non-active element 31 can have a first surface 3151 (e.g., an upper surface) and a second surface 3152 (e.g., a lower surface) opposite the first surface 3151 (e.g., an upper surface). The first surface 3151 of the first through hole 315 of the first non-active element 31 can be substantially coplanar with the first surface 311 of the first non-active element 31 and exposed from the first surface 311. The second surface 3152 of the through hole 315 of the first non-active element 31 can be substantially coplanar with the second surface 312 of the first non-active element 31 and exposed from the second surface 312 of the first non-active element 31. In other words, the through hole 315 of the first non-active element 31 can extend from the first surface 311 of the main portion 310 to the second surface 312 of the main portion 310.

[0243] Thus, the through-hole 315 of the first inactive device 31 can provide a vertical conductive path extending through the main portion 310 of the first inactive device 31 and can be configured to transmit signals or power. Therefore, the third redistribution structure 4 can be electrically connected to the substrate 12 through the through-hole 315 of the first inactive device 31, rather than through the semiconductor device 20 (including, for example, the first semiconductor device 25 and the second semiconductor device 26).

[0244] In some embodiments, the non-active component 3 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active component 31 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 310. No horizontal conductive paths exist on the first surface 311 or the second surface 312 of the main portion 310. The non-active component 3 includes only vertical conductive paths.

[0245] The encapsulant 27 can seal the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) and the non-active element 3 (including, for example, the first non-active element 31 and the second non-active element 32). For example, the encapsulant 27 can be disposed in a space 281 between the first semiconductor element 25 and the first non-active element 31, in a space 282 between the first semiconductor element 25 and the second semiconductor element 26, and in a space 283 between the second semiconductor element 26 and the second non-active element 32. The material of the encapsulant 27 can include a molding compound with or without fillers. A material of the encapsulant 27 can include a molding compound with or without fillers.

[0246] The encapsulant 27 may have a first surface 271 (e.g., an upper surface), a second surface 272 (e.g., a lower surface), and a side surface 273. The second surface 272 (e.g., a lower surface) may be opposite to the first surface 271 (e.g., an upper surface). The side surface 273 may extend between the first surface 271 (e.g., an upper surface) and the second surface 272 (e.g., a lower surface).

[0247] The first surface 271 of the encapsulant 27 can be substantially coplanar or aligned with the first surface 311 of the first non-active component 31 and the first surface 251 of the first semiconductor element 25. Therefore, the first surface 21 of the second molded structure 2 can include the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active component 31, and the first surface 251 of the first semiconductor element 25. Furthermore, the second surface 272 of the encapsulant 27 can be substantially coplanar or aligned with the second surface 312 of the first non-active component 31 and the second surface 252 of the first semiconductor element 25. Therefore, the second surface 22 of the second molded structure 2 can include the second surface 272 of the encapsulant 27, the second surface 312 of the first non-active component 31, and the second surface 252 of the first semiconductor element 25.

[0248] The third redistribution structure 4 can be disposed on the first surface 21 of the second molded structure 2 and electrically connected to the first surface 21 of the second molded structure 2. For example, the third redistribution structure 4 can be disposed on the first surface 271 of the encapsulant 27, the first surface 311 of the first inactive device 31, and the first surface 251 of the first semiconductor device 25, and electrically connected to the through-holes 315 of the first semiconductor device 25 and the first inactive device 31.

[0249] The third redistribution structure 4 may be a fan-out structure. The third redistribution structure 4 may have a first surface 41 (e.g., an upper surface), a second surface 42 (e.g., a lower surface), and a side surface 43. The second surface 42 (e.g., a lower surface) may be opposite to the first surface 41 (e.g., an upper surface). The side surface 43 may extend between the first surface 41 (e.g., an upper surface) and the second surface 42 (e.g., a lower surface). The second surface 42 of the third redistribution structure 4 may directly contact the first surface 21 of the second molding structure 2.

[0250] The third redistribution structure 4 may include a plurality of dielectric layers 44, a plurality of circuit layers 45, a plurality of inner through-holes 46, and a plurality of pads 47. The dielectric layer 44 may include a cured photoimageable dielectric (PID) material, an epoxy resin or a polyimide (PI) including a photoinitiator. The materials of the dielectric layers 44 may be the same as each other. In some embodiments, the material of the topmost dielectric layer 441 may be different from the materials of the other dielectric layers 44. The topmost dielectric layer 441 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. In some embodiments, the bottommost dielectric layer 442 may be omitted. The circuit layer 45 may be directly disposed on the first surface 21 of the second molded structure 2.

[0251] The circuit layer 45 may be covered by the dielectric layer 44 or embedded in the dielectric layer 44. The circuit layer 45 may be a fan-out circuit layer. The inner via 46 may be embedded in the dielectric layer 44 and may connect two adjacent circuit layers 45. The inner via 46 may gradually taper toward the second molded structure 2. The solder pad 47 may be electrically connected to the circuit layer 45 and embedded in the dielectric layer 44 (e.g., the topmost dielectric layer 441). The solder pad 47 may be exposed from the first surface 41 of the third redistribution structure 4. Each solder pad 47 may be a hybrid bonding (HB) solder pad and may include Cu or Al.

[0252] The second redistribution structure 8 may be disposed above the first surface 41 of the third redistribution structure 4 and electrically connected to the first surface 41 of the third redistribution structure 4. Thus, the first redistribution structure 7 may be disposed between the first molding structure 5 and the upper electronic component 18. The second redistribution structure 8 may be disposed below the first molding structure 5. The third redistribution structure 4 may be disposed between the second redistribution structure 8 and the second molding structure 2.

[0253] The second redistribution structure 8 can be attached to and electrically connected to the first surface 41 of the third redistribution structure 4 via hybrid bonding. That is, the second surface 82 of the second redistribution structure 8 can directly contact the first surface 41 of the third redistribution structure 4. Therefore, the bottommost dielectric layer 841 of the second redistribution structure 8 can be directly attached to, connected to, and in contact with the topmost dielectric layer 441 of the third redistribution structure 4. The pads 87 of the second redistribution structure 8 can be directly attached to, connected to, and in direct contact with the pads 47 of the third redistribution structure 4. Therefore, the first molding structure 5 can be electrically connected to the second molding structure 2 via hybrid bonding.

[0254] The bumps 14 may be disposed on the second surface 22 of the second molded structure 2. For example, the bumps 14 may include a plurality of first bumps 141 and a plurality of second bumps 142. The first bumps 141 may be disposed on the second surface 3152 (e.g., the lower surface) of the through-hole 315. Thus, the first bumps 141 may physically and electrically connect the through-hole 315 to the first surface 121 of the substrate 12. The second bumps 142 may be disposed on the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25). Thus, the second bumps 142 may connect the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25) to the first surface 121 of the substrate 12. The second bumps 142 may not have any electronic function and may be dummy pads.

[0255] In some embodiments, the first bumps 141 and the second bumps 142 can be formed simultaneously during the manufacturing process. In some embodiments, the first bumps 141 and / or the second bumps 142 can include a reflowable material configured to control a gap between the second molded structure 2 and the substrate 12 to prevent the second molded structure 2 from tilting relative to the substrate 12. Furthermore, a first gap g3 between two adjacent first bumps 141 can be smaller than a second gap g4 between two adjacent second bumps 142.

[0256] Figure 6 It is a top view schematic diagram, illustrating Figure 1 The first molded structure 5 of the assembly structure 1 is shown. The first non-active element 61 may include multiple rows of through-holes 615, for example, three rows of through-holes 615. The pads 555 of the first semiconductor element 55 may be arranged in an array. The size and structure of the second semiconductor element 56 may be the same as the size and structure of the first semiconductor element 55. The size and structure of the second non-active element 62 may be the same as the size and structure of the first non-active element 61. The second non-active element 62 and the first non-active element 61 may be disposed on opposite sides of the second semiconductor element 56 and the first semiconductor element 55.

[0257] Figure 7 It is a top view schematic diagram, illustrating Figure 1 The second molded structure 2 of the assembly structure 1 is formed. The first non-active element 31 may include multiple rows of through-holes 315, for example, two rows of through-holes 315. The pads 255 of the first semiconductor element 25 may be arranged in an array. The size and structure of the second semiconductor element 26 may be the same as the size and structure of the first semiconductor element 25. The size and structure of the second non-active element 32 may be the same as the size and structure of the first non-active element 31. The second non-active element 32 and the first non-active element 31 may be disposed on opposite sides of the second semiconductor element 26 and the first semiconductor element 25.

[0258] exist Figures 1 to 7 In the illustrated embodiment, the non-active elements 6 of the first molded structure 5 (including, for example, the first non-active element 61 and the second non-active element 62) are configured to provide a vertical conductive path between the upper electronic component 18 (or the first redistribution structure 7) and the second redistribution structure 8. The non-active elements 3 of the second molded structure 2 (including, for example, the first non-active element 31 and the second non-active element 32) are configured to provide a vertical conductive path between the third redistribution structure 4 and the substrate 12. Therefore, the non-active elements 6 of the first molded structure 5 (including, for example, the first non-active element 61 and the second non-active element 62) and the non-active elements 3 of the second molded structure 2 (including, for example, the first non-active element 31 and the second non-active element 32) are configured to provide a vertical conductive path between the upper electronic component 18 and the substrate 12.

[0259] The upper electronic component 18 is not electrically connected to the substrate 12 through the semiconductor element 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56) and the semiconductor element 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26). It is not necessary to form a through hole in the main portion (e.g., the main portion 550) of the semiconductor element 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56). It is not necessary to form a through hole in the main portion (e.g., the main portion 250) of the semiconductor element 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26). Vertical conductive paths can be provided outside the semiconductor element 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26) and the semiconductor element 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56). Therefore, design flexibility is increased and manufacturing costs are reduced.

[0260] Furthermore, the active surface of the semiconductor element 50 (e.g., the first surface 551 (or active surface) of the first semiconductor element 55) faces the active surface of the upper electronic element 18 (e.g., the first surface 181 of the upper electronic element 18). Therefore, the upper electronic element 18 can quickly read from and / or write to the semiconductor element 50 (e.g., the first semiconductor element 55). Consequently, the performance of the package structure 10 can be improved.

[0261] Figure 8 : is a top view schematically illustrating a first molded structure 5a of some embodiments of the present disclosure. The first molded structure 5a may be similar to Figure 6 The first molded structure 5a is similar to the first molded structure 5, and the differences are described below. The first molded structure 5a may further include a third non-active element 63 and a fourth non-active element 64. The third non-active element 63 and the fourth non-active element 64 may be disposed on opposite sides of the second semiconductor element 56 and the first semiconductor element 55. The size and structure of the third non-active element 63 and the fourth non-active element 64 may be the same or similar to the size and structure of the first non-active element 61 and the second non-active element 62. The first non-active element 61, the second non-active element 62, the third non-active element 63, and the fourth non-active element 64 may surround the second semiconductor element 56 and the first semiconductor element 55.

[0262] Figure 9 2 is a top view schematically illustrating a second molded structure 2a of some embodiments of the present disclosure. The second molded structure 2a may be similar to Figure 7The second molded structure 2a is a molded structure 2a, and the differences are described as follows. The first non-active element 31 and the second non-active element 32 may include three rows of through holes 315. The second molded structure 2a may also include a third non-active element 33 and a fourth non-active element 34. The third non-active element 33 and the fourth non-active element 34 may be arranged on opposite sides of the second semiconductor element 26 and the first semiconductor element 25. The size and structure of the third non-active element 33 and the fourth non-active element 34 may be the same or similar to the size and structure of the first non-active element 31 and the second non-active element 32. The first non-active element 31, the second non-active element 32, the third non-active element 33 and the fourth non-active element 34 may surround the second semiconductor element 26 and the first semiconductor element 25.

[0263] Figure 10 1 is a top view schematically illustrating a first molded structure 5b of some embodiments of the present disclosure. The first molded structure 5b may be similar to Figure 8 The first molded structure 5a is different from the first non-active element 61 in a top view. The dimensions of the first non-active element 61 can differ from those of the second non-active element 62b. For example, a length L1 of the first non-active element 61 can be greater than a length L2 of the second non-active element 62b. Furthermore, each of the third non-active element 63b and the fourth non-active element 64b can be L-shaped and can be positioned adjacent to or around a corner of the second semiconductor element 56.

[0264] Figure 11 2 is a top view schematically illustrating the second molded structure 2b of some embodiments of the present disclosure. The second molded structure 2b may be similar to Figure 9 The second molded structure 2a is described below. From a top view, the dimensions of the first non-active element 31 can differ from those of the second non-active element 32b. For example, a length L3 of the first non-active element 31 can be greater than a length L4 of the second non-active element 32b. Furthermore, each of the third non-active element 33b and the fourth non-active element 34b can be L-shaped and can be positioned adjacent to or around a corner of the second semiconductor element 26.

[0265] Figure 12 The sectional view is a schematic diagram illustrating the assembly structure 1a of some embodiments of the present disclosure. In addition to the structure and size of the non-active element 3 (including, for example, the first non-active element 31 and the second non-active element 32) of the second molded structure 2, the assembly structure 1a can be Figure 1The second molded structure 2 is similar to the assembled structure 1. For example, the width W6 of the first non-active element 31 (or main portion 310) of the second molded structure 2 can be smaller than the width W2 of the first non-active element 31 (or main portion 310) of the first molded structure 5. All central axes 3153 of all through-holes 315 of the second molded structure 2 can be aligned with the central axes 6153 of the corresponding through-holes 615 of the first molded structure 5.

[0266] Figure 13 1 is a cross-sectional view illustrating an assembly structure 1b of some embodiments of the present disclosure. In addition to the structure of the package structure 10b, the assembly structure 1b may be similar to Figure 1 assembly structure 1. In the package structure 10b, the second surface 182 of the upper electronic component 18 does not contact the first surface 71 of the first redistribution structure 7. The second surface 182 of the upper electronic component 18 is separated from the first surface 71 of the first redistribution structure 7. The solder pads 185 of the upper electronic component 18 can be electrically connected to the solder pads 77 of the first redistribution structure 7 through a plurality of soldering materials 191. The soldering material 191 may include a reflowable material such as AgSn. Therefore, the electrical connection between the upper electronic component 18 and the first redistribution structure 7 is not achieved by hybrid bonding, but by solder bonding. The solder pads 185 of the upper electronic component 18 and the solder pads 77 of the first redistribution structure 7 may be solder bonding pads.

[0267] In addition, the second surface 82 of the second redistribution structure 8 does not contact the first surface 41 of the third redistribution structure 4. The second surface 82 of the second redistribution structure 8 is separated from the first surface 41 of the third redistribution structure 4. The pads 87 of the second redistribution structure 8 can be electrically connected to the pads 47 of the third redistribution structure 4 through a plurality of soldering materials 19. The soldering material 19 may include a reflowable material such as AgSn. Therefore, the electrical connection between the second redistribution structure 8 and the third redistribution structure 4 is not achieved by hybrid bonding, but by solder bonding. The pads 87 of the second redistribution structure 8 and the pads 47 of the third redistribution structure 4 can be solder bonding pads. Therefore, the first molded structure 5 can be electrically connected to the second molded structure 2 through the soldering material 19.

[0268] Figures 14 to 25 1 is a schematic cross-sectional view illustrating various stages of a method for manufacturing an assembly structure 1 according to some embodiments of the present disclosure.

[0269] Please refer to Figure 14 and Figure 15 , a first molding structure 5 can be formed on a first carrier 90. Please refer to Figure 14, at least one semiconductor element 50 and at least one non-active element 6 can be disposed side by side on a first carrier 90. In some embodiments, the first carrier 90 may include a release layer 91 on one surface thereof. The semiconductor element 50 and the non-active element 6 can be disposed on the release layer 91. In some embodiments, the singulated semiconductor elements 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56) and the singulated non-active elements 6 (e.g., the first non-active element 61 and the second non-active element 62) can be reconstructed or reconfigured on the release layer 91 of the first carrier 90. In some embodiments, only known good dies are used, such as known good semiconductor elements 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56) and known good non-active elements 6 (e.g., the first non-active element 61 and the second non-active element 62).

[0270] In some embodiments, the size and function of the first semiconductor element 55 may be the same as the size and function of the second semiconductor element 56. Both the first semiconductor element 55 and the second semiconductor element 56 may be memory dies.

[0271] The first semiconductor element 55 may have a first surface 551 (e.g., an upper surface or active surface), a second surface 552 (e.g., a lower surface or backside surface), and a side surface 553. The second surface 552 (e.g., the lower surface) may be opposite to the first surface 551 (e.g., the upper surface). The side surface 553 may extend between the first surface 551 (e.g., the upper surface) and the second surface 552 (e.g., the lower surface).

[0272] The first semiconductor element 55 may include a main portion 550 and an active circuit structure 554 disposed on an upper surface 5501 of the main portion 550. The active circuit structure 554 may include multiple dielectric layers, multiple circuit layers, and multiple bonding pads 555. The dielectric layers may cover the circuit layers. The bonding pads 555 may be electrically connected to the circuit layers and embedded in the dielectric layers. The bonding pads 555 may be exposed from the first surface 551 of the first semiconductor element 55. The active circuit structure 554 and the bonding pads 555 may face upward. The second surface 552 (e.g., the lower surface) of the first semiconductor element 55 may contact the release layer 91 of the first carrier 90.

[0273] The passive element 6 may include a first passive element 61 and a second passive element 62 disposed around the first semiconductor element 55 and the second semiconductor element 56. The structure of the first passive element 61 may be the same as or similar to that of the second passive element 62.

[0274] The first passive element 61 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613 and 614. The second surface 612 (e.g., a lower surface) may be opposite to the first surface 611 (e.g., an upper surface). The side surfaces 613 and 614 may extend between the first surface 611 (e.g., an upper surface) and the second surface 612 (e.g., a lower surface).

[0275] A space 581 may be formed between the first semiconductor element 55 and the first inactive element 61. A space 582 may be formed between the first semiconductor element 55 and the second semiconductor element 56. A space 583 may be formed between the second semiconductor element 56 and the second inactive element 62.

[0276] The first non-active element 61 may include a main portion 610 and at least one through-hole 615 (or through-silicon via (TSV)) extending through the main portion 610. The main portion 610 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613 and 614. The second surface 612 (e.g., a lower surface) may be opposite to the first surface 611 (e.g., an upper surface). The side surfaces 613 and 614 may extend between the first surface 611 (e.g., an upper surface) and the second surface 612 (e.g., a lower surface). Therefore, the first surface 611, the second surface 612, and the side surfaces 613 and 614 of the first non-active element 61 may be the first surface 611, the second surface 612, and the side surfaces 613 and 614 of the main portion 610, respectively.

[0277] The semiconductor element 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56) does not include a vertical conductive path in its main portion. For example, the first semiconductor element 55 does not include a vertical conductive path in its main portion 550.

[0278] The through-hole 615 of the first non-active element 61 may have a first surface 6151 (e.g., an upper surface) and a second surface 6152 (e.g., a lower surface) opposite the first surface 6151 (e.g., an upper surface). The first surface 6151 of the first through-hole 615 of the first non-active element 61 may be substantially coplanar with the first surface 611 of the first non-active element 61 and exposed from the first surface 611. The second surface 6152 of the through-hole 615 of the first non-active element 61 may be substantially coplanar with the second surface 612 of the first non-active element 61 and exposed from the second surface 612 of the first non-active element 61.

[0279] In some embodiments, the non-active component 6 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active component 61 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 610. No horizontal conductive paths exist on either the first surface 611 or the second surface 612 of the main portion 610. The non-active component 6 includes only vertical conductive paths. The second surface 612 of the non-active component 6 can contact the release layer 91 of the first carrier 90.

[0280] Please refer to Figure 15 A packaging compound 57 may be formed on the release layer 91 of the first carrier 90 to seal the semiconductor elements 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56) and the inactive elements 6 (for example, the first inactive element 61 and the second inactive element 62). The packaging compound 57 may be disposed in the spaces 581, 582, and 583.

[0281] Then, a grinding process may be performed to form a first molding structure 5 on the first carrier 90. The first molding structure 5 may include a semiconductor device 50, a non-active device 6, and an encapsulant 57. The first molding structure 5 may have a first surface 51 (e.g., an upper surface) and a second surface 52 (e.g., a lower surface) opposite to the first surface 51 (e.g., an upper surface).

[0282] The encapsulant 57 may have a first surface 571 (e.g., an upper surface) and a second surface 572 (e.g., a lower surface) opposite the first surface 571 (e.g., an upper surface). The first surface 571 of the encapsulant 57 may be substantially coplanar with, or aligned with, the first surface 611 of the first non-active component 61 and the first surface 551 of the first semiconductor component 55. Thus, the first surface 51 of the first molded structure 5 may include the first surface 571 of the encapsulant 57, the first surface 611 of the first non-active component 61, and the first surface 551 of the first semiconductor component 55. Furthermore, the second surface 572 of the encapsulant 57 may be substantially coplanar with, or aligned with, the second surface 612 of the first non-active component 61 and the second surface 552 of the first semiconductor component 55. Thus, the second surface 52 of the first molded structure 5 may include the second surface 572 of the encapsulant 57, the second surface 612 of the first non-active component 61, and the second surface 552 of the first semiconductor component 55.

[0283] Please refer to Figure 16The first redistribution structure 7 can be formed or disposed on the first surface 51 of the first molding structure 5. For example, the first redistribution structure 7 can be formed or disposed on the first surface 571 of the encapsulant 57, the first surface 611 of the first inactive device 61, and the first surface 551 of the first semiconductor device 55. The first redistribution structure 7 can be electrically connected to the semiconductor device 50 (e.g., the first semiconductor device 55 and the second semiconductor device 56) and the through-hole 615 of the inactive device 6 (e.g., the first inactive device 61 and the second inactive device 62).

[0284] The first redistribution structure 7 may be a fan-out structure. The first redistribution structure 7 may have a first surface 71 (e.g., an upper surface) and a second surface 72 (e.g., a lower surface) opposite the first surface 71 (e.g., an upper surface). The second surface 72 of the first redistribution structure 7 may directly contact the first surface 51 of the first molding structure 5.

[0285] The first redistribution structure 7 may include a plurality of dielectric layers 74, a plurality of circuit layers 75, a plurality of inner vias 76, and a plurality of pads 77. The dielectric layers 74 may be made of the same material. In some embodiments, the material of the topmost dielectric layer 741 may be different from the materials of the other dielectric layers 74. The topmost dielectric layer 741 may be a hybrid bond (HB) dielectric layer. In some embodiments, the bottommost dielectric layer 742 may be omitted. The circuit layer 75 may be disposed directly on the first surface 51 of the first molding structure 5.

[0286] The circuit layer 75 may be covered by or embedded in the dielectric layer 74. The circuit layer 75 may be a fan-out circuit layer. The inner vias 76 may be embedded in the dielectric layer 74 and may connect two adjacent circuit layers 75. The inner vias 76 may gradually taper toward the first molded structure 5. The solder pads 77 may be electrically connected to the circuit layer 75 and embedded in the dielectric layer 74 (e.g., the topmost dielectric layer 741). The solder pads 77 may be exposed from the first surface 71 of the first redistribution structure 7. Each solder pad 77 may be a hybrid bonding (HB) solder pad.

[0287] Please refer to Figure 17 The upper electronic component 18 can be disposed on the first surface 71 of the first redistribution structure 7 and electrically connected to the first surface 71. The upper electronic component 18 can be a wafer-type, panel-type, or chip-type. The upper electronic component 18 can have a first surface 181 (e.g., an upper surface or backside surface) and a second surface 182 (e.g., a lower surface or active surface) opposite the first surface 181 (e.g., an upper surface).

[0288] The upper electronic component 18 may include a main portion 180 and an active circuit structure 184 disposed on a lower surface 1801 of the main portion 180. The active circuit structure 184 may include multiple dielectric layers, multiple circuit layers, and multiple bonding pads 185. The dielectric layers may cover the circuit layers. The bonding pads 185 may be electrically connected to the circuit layers and embedded in the dielectric layers. The bonding pads 185 may be exposed from the second surface 182 of the upper electronic component 18. The active circuit structure 184 may include a bottommost dielectric layer surrounding the bonding pads 185. The bottommost dielectric layer may be a hybrid bond (HB) dielectric layer. Each bonding pad 185 may be a hybrid bond (HB) bonding pad.

[0289] The upper electronic component 18 can be attached to and electrically connected to the first surface 71 of the first redistribution structure 7 by hybrid bonding. That is, the second surface 182 of the upper electronic component 18 can directly contact the first surface 71 of the first redistribution structure 7. Therefore, the active circuit structure 184 of the upper electronic component 18 can be directly attached to, connected to, and contact the topmost dielectric layer 741 of the first redistribution structure 7. The bonding pads 185 of the upper electronic component 18 can be directly attached to, connected to, and contact the bonding pads 77 of the first redistribution structure 7.

[0290] Please refer to Figure 18 , the release layer 91 and the first carrier 90 may be removed from the first molding structure 5. Then, a grinding process may be performed on the second surface 52 of the first molding structure 5.

[0291] Please refer to Figure 19 The second redistribution structure 8 can be formed or disposed on the second surface 52 of the first molding structure 5. For example, the second redistribution structure 8 can be formed or disposed on the second surface 572 of the encapsulant 57, the second surface 612 of the first inactive device 61, and the second surface 552 of the first semiconductor device 55. The second redistribution structure 8 can be electrically connected to the through-holes 615 of the inactive devices 6 (e.g., the first inactive device 61 and the second inactive device 62).

[0292] The second redistribution structure 8 can be a fan-out structure. The second redistribution structure 8 can have a first surface 81 (e.g., an upper surface) and a second surface 82 (e.g., a lower surface) opposite the first surface 81 (e.g., an upper surface). The second surface 82 of the second redistribution structure 8 can directly contact the second surface 52 of the first molding structure 5.

[0293] The second redistribution structure 8 may include a plurality of dielectric layers 84, a plurality of circuit layers 85, a plurality of inner vias 86, and a plurality of pads 87. The dielectric layers 84 may be made of the same material. In some embodiments, the material of the bottommost dielectric layer 841 may be different from the materials of the other dielectric layers 84. The bottommost dielectric layer 841 may be a hybrid bond (HB) dielectric layer. In some embodiments, the topmost dielectric layer 842 may be omitted. The circuit layer 85 may be directly disposed on the second surface 52 of the first molding structure 5.

[0294] The circuit layer 85 may be covered by a dielectric layer 84 or embedded in the dielectric layer 84. The circuit layer 85 may be a fan-out circuit layer. The inner via 86 may be embedded in the dielectric layer 84 and may connect two adjacent circuit layers 85. The inner via 86 may gradually taper toward the first molded structure 5. The solder pad 87 may be electrically connected to the circuit layer 85 and embedded in the dielectric layer 84 (e.g., the bottommost dielectric layer 841). The solder pad 87 may be exposed from the second surface 82 of the second redistribution structure 8. Each solder pad 87 may be a hybrid bonding (HB) solder pad.

[0295] Please refer to Figure 20 and Figure 21 , the second molding structure 2 can be formed on a second carrier 92. Please refer to Figure 20 , at least one semiconductor element 20 and at least one non-active element 3 can be disposed side by side on a second carrier 92. In some embodiments, the second carrier 92 may include a release layer 93 on a surface thereof. The semiconductor element 20 and the non-active element 3 can be disposed on the release layer 93. In some embodiments, the singulated semiconductor elements 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26) and the singulated non-active elements 3 (e.g., the first non-active element 31 and the second non-active element 32) can be reconstructed or reconfigured on the release layer 93 of the second carrier 92. In some embodiments, only known good dies are used, such as known good semiconductor elements 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26) and known good non-active elements 3 (e.g., the first non-active element 31 and the second non-active element 32).

[0296] The first semiconductor element 25 may have a first surface 251 (e.g., an upper surface or active surface), a second surface 252 (e.g., a lower surface or backside surface), and a side surface 253. The second surface 252 (e.g., the lower surface) may be opposite to the first surface 251 (e.g., the upper surface). The side surface 253 may extend between the first surface 251 (e.g., the upper surface) and the second surface 252 (e.g., the lower surface).

[0297] The first semiconductor element 25 may include a main portion 250 and an active circuit structure 254 disposed on an upper surface 2501 of the main portion 250. The active circuit structure 254 may include multiple dielectric layers, multiple circuit layers, and multiple bonding pads 255. The dielectric layers may cover the circuit layers. The bonding pads 255 may be electrically connected to the circuit layers and embedded in the dielectric layers. The bonding pads 255 may be exposed from the first surface 251 of the first semiconductor element 25. The active circuit structure 254 and the bonding pads 255 may face upward. The second surface 252 (e.g., the lower surface) of the first semiconductor element 25 may contact the release layer 93 of the second carrier 92.

[0298] The passive element 3 may include a first passive element 31 and a second passive element 32 disposed around the first semiconductor element 25 and the second semiconductor element 26. The structure of the first passive element 31 may be the same as or similar to that of the second passive element 32.

[0299] The first passive element 31 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a lower surface) may be opposite to the first surface 311 (e.g., an upper surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., an upper surface) and the second surface 312 (e.g., a lower surface).

[0300] A space 281 may be formed between the first semiconductor element 25 and the first inactive element 31. A space 282 may be formed between the first semiconductor element 25 and the second semiconductor element 26. A space 283 may be formed between the second semiconductor element 26 and the second inactive element 32.

[0301] The first non-active element 31 may include a main portion 310 and at least one through-hole 315 (or through-silicon via (TSV)) extending through the main portion 310. The main portion 310 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a lower surface) may be opposite to the first surface 311 (e.g., an upper surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., an upper surface) and the second surface 312 (e.g., a lower surface). Therefore, the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the first non-active element 31 may be the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the main portion 310, respectively.

[0302] The through hole 315 of the first non-active element 31 may have a first surface 3151 (e.g., an upper surface) and a second surface 3152 (e.g., a lower surface) opposite the first surface 3151 (e.g., an upper surface). The first surface 3151 of the first through hole 315 of the first non-active element 31 may be substantially coplanar with the first surface 311 of the first non-active element 31 and exposed from the first surface 311. The second surface 3152 of the through hole 315 of the first non-active element 31 may be substantially coplanar with the second surface 312 of the first non-active element 31 and exposed from the second surface 312 of the first non-active element 31.

[0303] In some embodiments, the non-active component 3 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active component 31 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 310. No horizontal conductive paths exist on either the first surface 311 or the second surface 312 of the main portion 310. The non-active component 3 includes only vertical conductive paths. The second surface 312 of the non-active component 3 can contact the release layer 93 of the second carrier 92.

[0304] Please refer to Figure 21 Next, an encapsulant 27 can be formed on the release layer 93 of the second carrier 92 to encapsulate the semiconductor elements 20 (e.g., including the first semiconductor element 25 and the second semiconductor element 26) and the inactive elements 3 (e.g., the first inactive element 31 and the second inactive element 32). The encapsulant 27 can be disposed in the spaces 281, 282, and 283.

[0305] Then, a grinding process may be performed to form a second molded structure 2 on the second carrier 92. The second molded structure 2 may include the semiconductor device 20, the inactive device 3, and the encapsulant 27. The second molded structure 2 may have a first surface 21 (e.g., an upper surface) and a second surface 22 (e.g., a lower surface) opposite to the first surface 21 (e.g., an upper surface).

[0306] The encapsulant 27 may have a first surface 271 (e.g., an upper surface) and a second surface 272 (e.g., a lower surface) opposite the first surface 271 (e.g., an upper surface). The first surface 271 of the encapsulant 27 may be substantially coplanar with, or aligned with, the first surface 311 of the first non-active component 31 and the first surface 251 of the first semiconductor component 25. Therefore, the first surface 21 of the second molded structure 2 may include the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active component 31, and the first surface 251 of the first semiconductor component 25. Furthermore, the second surface 272 of the encapsulant 27 may be substantially coplanar with, or aligned with, the second surface 312 of the first non-active component 31 and the second surface 252 of the first semiconductor component 25. Therefore, the second surface 22 of the second molded structure 2 may include the second surface 272 of the encapsulant 27, the second surface 312 of the first non-active component 31, and the second surface 252 of the first semiconductor component 25.

[0307] Please refer to Figure 22 A third redistribution structure 4 can be formed or disposed on the first surface 21 of the second molding structure 2. For example, the third redistribution structure 4 can be formed or disposed on the first surface 271 of the encapsulant 27, the first surface 311 of the first inactive device 31, and the first surface 251 of the first semiconductor device 25. The third redistribution structure 4 can be electrically connected to the semiconductor device 20 (e.g., the first semiconductor device 25 and the second semiconductor device 26) through the through-holes 315 of the inactive device 3 (e.g., the first inactive device 31 and the second inactive device 32).

[0308] The third redistribution structure 4 may be a fan-out structure. The third redistribution structure 4 may have a first surface 41 (e.g., an upper surface) and a second surface 42 (e.g., a lower surface) opposite the first surface 41 (e.g., an upper surface). The second surface 42 of the third redistribution structure 4 may directly contact the first surface 21 of the second molding structure 2.

[0309] The third redistribution structure 4 may include a plurality of dielectric layers 44, a plurality of circuit layers 45, a plurality of inner vias 46, and a plurality of pads 47. The dielectric layers 44 may be made of the same material. In some embodiments, the material of the topmost dielectric layer 441 may be different from the materials of the other dielectric layers 44. The topmost dielectric layer 441 may be a hybrid bond (HB) dielectric layer. In some embodiments, the bottommost dielectric layer 442 may be omitted. The circuit layer 45 may be directly disposed on the first surface 21 of the second mold structure 2.

[0310] The circuit layer 45 may be covered by the dielectric layer 44 or embedded in the dielectric layer 44. The circuit layer 45 may be a fan-out circuit layer. The inner through-hole 46 may be embedded in the dielectric layer 44 and may connect two adjacent circuit layers 45. The inner through-hole 46 may gradually taper toward the second molded structure 2. The solder pad 47 may be electrically connected to the circuit layer 45 and embedded in the dielectric layer 44 (e.g., the topmost dielectric layer 441). The solder pad 47 may be exposed from the first surface 41 of the third redistribution structure 4. Each solder pad 47 may be a hybrid bonding (HB) solder pad.

[0311] Please refer to Figure 23 , the upper electronic component 18 and the first mold structure 5 can be attached to the second mold structure 2 and electrically connected to the second mold structure 2 through hybrid bonding. That is, the second surface 82 of the second redistribution structure 8 can directly contact the first surface 41 of the third redistribution structure 4. Therefore, the pads 87 of the second redistribution structure 8 can be directly attached to, connected to, and can directly contact the pads 47 of the third redistribution structure 4.

[0312] Please refer to Figure 24 , the release layer 93 and the second carrier 92 can be removed from the second molded structure 2. Then, a grinding process can be performed on the second surface 22 of the second molded structure 2. Then, a plurality of bumps 14 can be formed or disposed on the second surface 22 of the second molded structure 2. For example, the bumps 14 can include a plurality of first bumps 141 and a plurality of second bumps 142. The first bumps 141 can be formed or disposed on the second surface 3152 (e.g., the lower surface) of the through-hole 315. The second bumps 142 can be formed or disposed on the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25). In some embodiments, the first bumps 141 and the second bumps 142 can be formed simultaneously at the same stage.

[0313] Please refer to Figure 25 , the second molding structure 2, the third redistribution structure 4, the second redistribution structure 8, the first molding structure 5, the first redistribution structure 7, and the upper electronic component 18 can be cut to form the package structure 10. Then, the bumps 14 (e.g., the first bumps 141 and the second bumps) can be attached to the substrate 12. Therefore, the package structure 10 can be attached to the substrate 12 through the bumps 14 (e.g., the first bumps 141 and the second bumps).

[0314] Then, a plurality of external connectors 16 may be formed or disposed on the second surface 122 of the substrate 12 to provide electrical connections, such as I / O connections, to the substrate 12. Figure 1 Assembly structure 1.

[0315] Figure 261 is a flow chart illustrating a method 900 for preparing an assembly structure 1 according to some embodiments of the present disclosure.

[0316] In some embodiments, the manufacturing method 900 may include step S901, forming a first molding structure on a first carrier. Figure 15 As shown, a first molding structure 5 may be formed on the first carrier 90 .

[0317] In some embodiments, the manufacturing method 900 may include step S902, disposing an electronic component on the first molding structure. Figure 17 As shown, an upper electronic component 18 may be disposed on the first mold structure 5 .

[0318] In some embodiments, the preparation method 900 may include step S903, removing the first carrier. Figure 18 As shown, the first carrier 90 may be removed.

[0319] In some embodiments, the preparation method 900 may include step S904, forming a second molding structure on a second carrier. Figure 21 As shown, a second molding structure 2 may be formed on a second carrier 92 .

[0320] In some embodiments, the manufacturing method 900 may include step S905 of attaching the upper electronic component and the first molding structure to the second molding structure. Figure 23 As shown, the upper electronic component 18 and the first mold structure 5 may be attached to the second mold structure 2 .

[0321] In some embodiments, the preparation method 900 may include step S906, removing the second carrier. Figure 24 As shown, the second carrier 92 may be removed.

[0322] One embodiment of the present disclosure provides a packaging structure comprising a first molded structure, a first redistribution structure, and a second molded structure. The first molded structure has a first surface and a second surface opposite to the first surface, and comprises at least one semiconductor element, at least one non-active element, and a packaging colloid. The at least one non-active element is disposed around the at least one semiconductor element and comprises a main portion and at least one through hole passing through the main portion. The packaging colloid encapsulates the at least one semiconductor element and the at least one non-active element. The first redistribution structure is disposed on the first surface of the first molded structure. The second redistribution structure is disposed on the second surface of the first molded structure and is electrically connected to the first redistribution structure through the at least one through hole of the at least one non-active element.

[0323] Another embodiment of the present disclosure provides an assembly structure comprising a substrate, a first molded structure, a second molded structure, and an upper electronic component. The first molded structure is disposed above the substrate. The first molded structure includes at least one semiconductor component, at least one non-active component, and a packaging colloid that encapsulates the at least one semiconductor component and the at least one non-active component. The second molded structure is disposed between the first molded structure and the substrate. The second molded structure includes at least one semiconductor component, at least one non-active component, and a packaging colloid that encapsulates the at least one semiconductor component and the at least one non-active component. The upper electronic component is disposed above the first molded structure. The at least one non-active component of the first molded structure and the at least one non-active component of the second molded structure are configured to provide a vertical conductive path between the upper electronic component and the substrate.

[0324] Another embodiment of the present disclosure provides a manufacturing method. The manufacturing method includes forming a first molding structure on a first carrier; disposing an upper electronic component on the first molding structure; removing the first carrier; forming a second molding structure on a second carrier; attaching the upper electronic component and the first molding structure to the second molding structure; and removing the second carrier.

[0325] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0326] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. An assembly structure comprising: a base; a first molding structure disposed above the substrate, wherein the first molding structure includes at least one semiconductor element, at least one passive element, and an encapsulation compound encapsulating the at least one semiconductor element and the at least one passive element; a second molding structure disposed between the first molding structure and the substrate, wherein the second molding structure includes at least one semiconductor element, at least one passive element, and an encapsulation compound encapsulating the at least one semiconductor element and the at least one passive element; as well as An upper electronic component is disposed above the first mold structure, wherein the at least one inactive component of the first mold structure and the at least one inactive component of the second mold structure are configured to provide a vertical conductive path between the upper electronic component and the substrate. 2 . The assembly structure of claim 1 , wherein the upper electronic component is electrically connected to the first molding structure by hybrid bonding, and the first molding structure is electrically connected to the second molding structure by hybrid bonding. 3 . The assembly structure as claimed in claim 1 , wherein the upper electronic component is electrically connected to the first molding structure through a plurality of soldering materials, and the first molding structure is electrically connected to the second molding structure through the soldering materials. 4 . The assembly structure as claimed in claim 1 , wherein the upper electronic component vertically overlaps the at least one passive component of the first molding structure and the at least one passive component of the second molding structure. 5 . The assembly structure as claimed in claim 1 , wherein a width of the upper electronic component is substantially equal to a width of the first molding structure, and the width of the upper electronic component is substantially equal to a width of the second molding structure. 6 . The assembly structure as claimed in claim 1 , wherein a side surface of the upper electronic component is substantially aligned with a side surface of the first molding structure and a side surface of the second molding structure. 7 . The assembly structure as claimed in claim 1 , wherein a function of the upper electronic component is different from a function of the at least one semiconductor component of the first molding structure, and the function of the upper electronic component is different from a function of the at least one semiconductor component of the second molding structure.

8. The assembly structure of claim 1 , wherein the at least one non-active component of the first molding structure comprises a main portion and at least one through-hole extending through the main portion, and a second surface of the encapsulant of the first molding structure is substantially coplanar with a second surface of the at least one non-active component of the first molding structure and a second surface of the at least one semiconductor component of the first molding structure.

9. The assembly structure of claim 1 , wherein the at least one inactive component of the second molding structure comprises a main portion and at least one through-hole extending through the main portion, and a second surface of the encapsulant of the second molding structure is substantially coplanar with a second surface of the at least one inactive component of the second molding structure and a second surface of the at least one semiconductor component of the second molding structure.

10. The assembly structure according to claim 9, further comprising: at least one first bump connecting the at least one through hole of the second molding structure and the substrate; as well as At least one second bump connects the at least one semiconductor element of the second molding structure and the substrate. The assembly structure according to claim 10 , wherein the at least one first bump and the at least one second bump are formed simultaneously. 12 . The assembly structure as claimed in claim 10 , wherein the at least one second bump comprises a reflowable material for controlling a gap between the second molding structure and the substrate.

13. The assembly structure as claimed in claim 10, wherein the at least one first bump comprises a plurality of first bumps, the at least one second bump comprises a plurality of second bumps, and a first gap between two adjacent first bumps among the first bumps is smaller than a second gap between two adjacent second bumps among the second bumps.

14. The assembly structure according to claim 1, further comprising: a first redistribution structure disposed between the first molding structure and the upper electronic component; a second redistribution structure disposed below the first molding structure; as well as A third redistribution structure is disposed between the second redistribution structure and the second molding structure.

15. The assembly structure according to claim 14, wherein the first redistribution structure comprises: multiple dielectric layers; a plurality of circuit layers covered by the dielectric layers; as well as A plurality of inner through holes connecting two adjacent ones of the circuit layers, The inner through holes are gradually tapered toward the first molding structure. 16 . The assembly structure of claim 14 , wherein the upper electronic component is attached to the first redistribution structure by hybrid bonding, and the second redistribution structure is attached to the third redistribution structure by hybrid bonding.

17. The assembly structure as described in claim 1, wherein the at least one non-active component of the first molded structure includes a plurality of through holes, and the at least one non-active component of the second molded structure includes a plurality of through holes, wherein a gap between two adjacent through holes of the first molded structure is different from a gap between two adjacent through holes of the second molded structure. 18 . The assembly structure of claim 17 , wherein a central axis of one of the through holes of the first molding structure is substantially aligned with a central axis of one of the through holes of the second molding structure.

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