Package substrate structure based on polycrystalline silicon and manufacturing method thereof

Abstract

The invention provides a polycrystalline silicon-based packaging substrate structure and a manufacturing method thereof, the polycrystalline silicon-based packaging substrate structure comprises a core plate, insulating layers and metal wiring layers, the core plate is polycrystalline silicon, interconnecting through holes are formed in the core plate, filling metal is arranged in the interconnecting through holes, the insulating layers are arranged on the surfaces of the metal wiring layers, and at least two metal wiring layers are respectively arranged on the upper surface and the lower surface of the core plate. A connecting hole is arranged between two adjacent metal wiring layers, and filling metal is arranged in the connecting hole. The polycrystalline silicon material is adopted as the core plate of the packaging substrate, the heat conductivity is high, the substrate can be prevented from losing efficacy due to overheating, the mechanical strength and the structural stability are high, and the micro through holes are easy to machine.

Description

Technical Field

[0001] The present invention belongs to the technical field of wafer-level packaging, and particularly relates to a packaging substrate structure based on polysilicon and a manufacturing method thereof. Background Art

[0002] Current challenges facing packaging substrates include thermal management, signal integrity, electrical isolation, material cost, and reliability. As the power density of electronic devices increases, the thermal resistance and heat dissipation capacity of substrates are insufficient, leading to heat accumulation and device failure. Unstable electrical performance can cause signal interference and short circuits. Furthermore, balancing material selection and cost is a challenge, especially in high-performance packaging, where the reliability and dimensional stability of substrate materials are increasingly demanding.

[0003] Polycrystalline silicon substrates, due to their excellent thermal conductivity and mechanical strength, are widely used in solar cells, LED packaging, and MEMS applications. They not only effectively improve thermal management capabilities and extend device life, but are also used as composite substrate materials in high-power, high-frequency packaging to address efficient heat dissipation and electrical isolation, promising significant future applications in electronic packaging technology. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present application provides a polysilicon-based packaging substrate structure and a manufacturing method thereof to solve the above technical defects.

[0005] According to a first aspect of the present invention, a packaging substrate structure based on polysilicon is proposed, including a core board, an ABF insulation layer, and a metal wiring layer. The core board is polysilicon, and interconnection through-holes are provided in the core board, and filling metal is provided in the interconnection through-holes. The ABF insulation layer is provided on the surface of the metal wiring layer, and at least two layers of metal wiring layers are respectively provided on the upper and lower surfaces of the core board, and a connection hole is provided between two adjacent metal wiring layers, and filling metal is provided in the connection hole.

[0006] In this structural setup, polysilicon is used as the core of the package substrate. Its high thermal conductivity allows for rapid heat transfer to the heat dissipation channels, preventing substrate failure due to overheating. It also offers high mechanical strength and structural stability, maintaining structural stability in harsh environments such as external impact and thermal cycling, and resisting cracking or deformation. Furthermore, filling metal is placed in the connection holes between adjacent metal wiring layers, enabling interconnection between multiple layers of circuitry within the polysilicon substrate.

[0007] In a specific embodiment, the thermal expansion coefficient of polysilicon is 2.6 ppm / °C. The thermal expansion coefficient of silicon chips is approximately 2.6 to 3.0 ppm / °C. This highly matched thermal expansion coefficient of polysilicon and silicon chips effectively prevents material expansion or contraction caused by temperature changes during the packaging process.

[0008] In a specific embodiment, the polysilicon-based package substrate structure further includes a Ti / Cu seed layer disposed below the metal wiring layer. This structure, in which the Ti / Cu seed layer is disposed, can enhance the bonding strength between the metal wiring layer and the substrate while providing good electrical conductivity.

[0009] According to a second aspect of the present invention, a method for manufacturing a polysilicon-based packaging substrate structure is provided, comprising the following steps:

[0010] S1: preparing interconnection through-holes penetrating the polysilicon core board;

[0011] S2: Filling copper in the interconnected through-holes and forming high-precision circuit patterns on the upper and lower surfaces;

[0012] S3: ABF film is laminated onto the high-precision circuit pattern and pre-cured to form connection holes;

[0013] S4: depositing a seed layer on the upper and lower surfaces of the core plate by surface sputtering;

[0014] S5: The photoresist dry film is laminated to the upper and lower surfaces of the core board and patterned;

[0015] S6: Metal filling is performed in the area not protected by the photoresist dry film layer by double-sided electroplating;

[0016] S7: removing the photoresist dry film, removing the seed layer, and completely curing the ABF film layer;

[0017] S8: Steps S3 to S7 are repeated to form multiple layers of conductive circuits on the upper and lower sides of the polysilicon core board, and finally a finished product is formed.

[0018] In this process design, polysilicon is used as the core board of the packaging substrate, and combined with advanced packaging processes such as ABF thin film and laser opening, which solves the problems of poor thermal conductivity of organic material substrates in existing packaging substrates and high brittleness and easy cracking of ceramic substrates.

[0019] In a specific embodiment, in step S1, interconnect vias are formed on a polysilicon core board using deep silicon etching, laser etching, or reactive ion etching. Deep silicon etching or laser etching can form interconnect vias with a depth-to-width ratio greater than 5:1, making them suitable for 3D packaging and high-density interconnects, and enabling the production of high-density RDL wiring. Reactive ion etching is suitable for shallow, high-precision structures, typically with a depth-to-width ratio of 3:1 to 5:1, and is widely used for etching dielectric and metal layers in integrated circuits, as well as for micron-scale patterning.

[0020] In a specific embodiment, in step S1, a layer of insulating material is deposited on the walls of the interconnection vias. The insulating material is silicon dioxide or silicon nitride. In this process design, depositing a layer of insulating material on the walls of the interconnection vias provides electrical isolation, preventing direct contact between the conductive metal in the interconnection vias and the surrounding polysilicon core board, thereby preventing short circuits.

[0021] In a specific embodiment, in step S2, copper or other conductive material is filled into the interconnect vias by sputtering, electroplating, or chemical mechanical polishing. In this process design, sputtering is used to form a seed layer inside the interconnect vias so that the subsequent electroplating process can evenly deposit the filler material; electroplating is the main step in filling the interconnect vias, ensuring that the filler material completely fills the interconnect vias; and chemical mechanical polishing is used to remove excess filler material and flatten the surface for subsequent process steps.

[0022] In a specific embodiment, in step S3, the ABF film is laminated onto the circuit pattern on the polysilicon surface using vacuum lamination or roller lamination. Laser drilling is used to form connection holes in the film. In this process design, vacuum lamination is suitable for applications requiring high precision and low bubble reduction, while roller lamination is suitable for large-scale production with high production speeds. Laser drilling is used to form connection holes in the film to maintain electrical connection with the substrate for subsequent processes.

[0023] In a specific embodiment, in steps S4 and S7, the seed layer includes a Ti seed layer and a Cu seed layer. The Ti seed layer serves as an adhesion layer, and the Cu seed layer serves as a conductive layer. In this process design, the Ti seed layer primarily serves to enhance the bonding between the subsequent metal wiring layer and the substrate, while the Cu seed layer provides the conductive path required for electroplating. The sputtered Ti / Cu double-layer structure ensures adhesion while providing good conductivity.

[0024] In a specific embodiment, in step S8, after the multi-layer circuit process is completed on both the upper and lower surfaces of the polysilicon core substrate, a full curing process is performed. The full curing temperature is 150-200°C and the curing time is 30-60 minutes. Through this process design, the multi-layer circuit package substrate is completely cured and leveled, effectively reducing warping of the package structure. Furthermore, the manufacturing process of the package substrate is simplified, improving processing efficiency.

[0025] Compared with the prior art, the present invention has the following advantages:

[0026] First, polycrystalline silicon is used as the core substrate, which has high thermal conductivity. The thermal conductivity of polycrystalline silicon is approximately 130-150 W / m·K, which is much higher than that of common organic substrate materials and some ceramic substrates. In high-power semiconductor devices, LED packages, and power modules, polycrystalline silicon can effectively and quickly conduct heat to the heat dissipation channel, preventing device failure due to overheating.

[0027] Second, polycrystalline silicon substrates have high hardness and strength, can maintain good structural stability in harsh environments such as external force impact and thermal cycling, and are not prone to cracking or deformation.

[0028] 3. Polycrystalline silicon substrates can form high aspect ratio through-holes through deep silicon etching or laser etching technology, which is suitable for 3D packaging and high-density interconnection, and can also prepare high-density RDL wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and, together with the description, serve to explain the principles of the present invention. Other embodiments and many of the expected advantages of the embodiments will be readily apparent as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals designate corresponding similar parts.

[0030] Figure 1 is a process flow chart of a method for manufacturing a polysilicon-based packaging substrate structure according to the present invention;

[0031] Figure 2 is a schematic diagram of the structure after executing step S1 according to an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of the structure after executing step S2 according to an embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of the structure after executing step S3 according to an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of the structure after executing step S4 according to an embodiment of the present invention;

[0035] Figure 6 is a schematic diagram of the structure after executing step S5 according to an embodiment of the present invention;

[0036] Figure 7 is a schematic diagram of the structure after executing step S6 according to an embodiment of the present invention;

[0037] Figure 8 is a schematic structural diagram after executing step S7 according to an embodiment of the present invention;

[0038] Figure 9 is a schematic structural diagram of a finished multi-layer polysilicon substrate according to an embodiment of the present invention;

[0039] Figure 10aThis is the S23 stress cloud diagram of the HBM corner solder when glass is used as the substrate;

[0040] Figure 10b This is the S23 stress cloud diagram of the ASIC corner solder when glass is used as the substrate;

[0041] Figure 11 This is the warpage cloud image of the substrate module when glass is used as the substrate.

[0042] The meaning of the numbers in the figure: 01-core board, 02-ABF insulation layer, 03-core board metal layer, 04-interconnection through hole, 05-connection hole, 06-Ti / Cu seed layer, 07-photoresist dry film layer, 08-electroplated metal layer. DETAILED DESCRIPTION

[0043] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and are illustrated by illustrative specific embodiments in which the present invention may be practiced. To this end, directional terms, such as "top," "bottom," "left," "right," "up," "down," etc., are used with reference to the orientation of the figures being described. Because the components of the embodiments may be positioned in several different orientations, directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be adopted in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0044] Figure 1 FIG. 1 is a process flow chart of a method for manufacturing a polysilicon-based packaging substrate structure according to the present invention. Figure 1 As shown, a method for manufacturing a polysilicon-based packaging substrate structure includes the following steps:

[0045] S1: preparing interconnection through-holes penetrating the polysilicon core board;

[0046] S2: Filling copper in the interconnected through-holes and forming high-precision circuit patterns on the upper and lower surfaces;

[0047] S3: ABF film is laminated onto the high-precision circuit pattern and pre-cured to form connection holes;

[0048] S4: depositing a seed layer on the upper and lower surfaces of the core plate by surface sputtering;

[0049] S5: The photoresist dry film is laminated to the upper and lower surfaces of the core board and patterned;

[0050] S6: Metal filling is performed in the area not protected by the photoresist dry film layer by double-sided electroplating;

[0051] S7: removing the photoresist dry film, removing the seed layer, and completely curing the ABF film layer;

[0052] S8: Steps S3 to S7 are repeated to form multiple layers of conductive circuits on the upper and lower sides of the polysilicon core board, and finally a finished product is formed.

[0053] In this process design, polysilicon is used as the core board of the packaging substrate, and combined with advanced packaging processes such as ABF thin film and laser opening, which solves the problems of poor thermal conductivity of organic material substrates in existing packaging substrates and high brittleness and easy cracking of ceramic substrates.

[0054] In a specific implementation, when executing step S1, a polysilicon core board is selected, photoresist is coated on the surface of the polysilicon core board, and then the pattern of the through hole is transferred to the photoresist through a photolithography process; reactive ion etching is used to form interconnected through holes on the polysilicon layer; a layer of insulating material, such as silicon dioxide or silicon nitride, is deposited on the wall of the through hole to provide electrical isolation to prevent the conductive metal in the interconnected through hole from directly contacting the surrounding polysilicon core board to avoid short circuit.

[0055] In a specific embodiment, when executing step S1, the core substrate surface needs to be cleaned to remove particles and contaminants to ensure the quality of subsequent processes. Etching residues need to be removed after reactive ion etching, usually using a stripper or plasma oxidation to clean the photoresist and contaminants.

[0056] In specific embodiments, reactive ion etching (RIE) technology is suitable for shallow, high-precision structures with aspect ratios typically ranging from 3:1 to 5:1. It is widely used in etching dielectric and metal layers in integrated circuits, as well as for micron-scale patterning. In addition to RIE, deep silicon etching and laser etching can also be used on polysilicon substrates to form interconnect vias with aspect ratios greater than 5:1, making them suitable for 3D packaging and high-density interconnects, while also enabling the production of high-density RDL wiring.

[0057] In a specific embodiment, during step S2, the vias are filled with copper or other conductive materials through sputtering, electroplating, chemical mechanical polishing, or other methods, and high-precision circuit patterns are formed on the upper and lower surfaces. In this example, sputtering is used to form a seed layer within the interconnect vias, allowing for uniform deposition of the filler material during the subsequent electroplating process. Electroplating is the primary step in filling the interconnect vias, ensuring that the filler material completely fills the interconnect vias. Chemical mechanical polishing is used to remove excess filler material and flatten the surface for subsequent process steps.

[0058] In a specific embodiment, during step S3, the ABF film material is laminated onto the polysilicon surface circuit pattern using vacuum lamination or roller lamination. After pre-curing, connection holes are formed in the film using laser drilling. In this process design, vacuum lamination is suitable for applications requiring high precision and low bubbles, while roller lamination is suitable for scenarios requiring large-scale production and faster production speeds. Laser drilling is used to form connection holes in the film to maintain electrical connection with the substrate for subsequent processes.

[0059] In a specific embodiment, when step S4 is performed, a seed layer is deposited on the upper and lower surfaces of the core substrate by surface sputtering. The seed layer includes a Ti seed layer and a Cu seed layer, the Ti seed layer is an adhesion layer, and the Cu seed layer is a conductive layer. In this process design, the main function of the Ti seed layer is to enhance the bonding strength between the subsequent metal layer and the substrate, while the Cu seed layer is used to provide a conductive path required for electroplating. The role of the sputtered Ti / Cu double-layer structure is to provide good conductivity while ensuring adhesion.

[0060] In a specific embodiment, during step S5, a photoresist dry film is laminated on the upper and lower surfaces of the core substrate, and windows are opened in specific areas to create surface patterning. In this example, the photoresist dry film forms a precise circuit pattern on the substrate through exposure and development. This process design allows for defined areas for subsequent electroplating or other metal processing steps, ensuring that metal is deposited only where needed.

[0061] In a specific embodiment, step S6 is performed using a step-by-step etching process (e.g., using H2O2 / H2SO4 to etch the Cu seed layer; using HF / HNO3 to etch the Ti seed layer), and the ABF is fully cured at a temperature of 180°C for 40 minutes. In this process design, the photoresist dry film is removed to expose the Ti / Cu seed layer area not covered by the electroplated metal, providing a precise target area for subsequent wet etching; the Ti / Cu seed layer is removed to remove redundant Ti / Cu seed layers and retain the target circuit pattern; and the ABF is fully cured to enhance the mechanical and electrical properties of the substrate, eliminate stress within the substrate, reduce warping, and improve insulation performance.

[0062] In a specific embodiment, after the multi-layer circuit process is completed on both the upper and lower surfaces of the polysilicon core substrate, a full curing process is performed. The full curing temperature is 150-200°C and the curing time is 30-60 minutes. Through this process design, the multi-layer circuit package substrate is completely cured and leveled, effectively reducing warping of the package structure. This also simplifies the manufacturing process of the package substrate, improving processing efficiency.

[0063] Figure 2 1 is a schematic diagram of the structure after executing step S1 according to an embodiment of the present invention. Figure 2As shown, after executing step S1, interconnection through-holes 04 are provided in the polysilicon core board 01, and multiple interconnection through-holes 04 are arranged at intervals, penetrating the core board 01. This structural arrangement creates conditions for achieving vertical electrical conduction between the upper and lower surfaces of the substrate and the internal structure, and the multiple interconnection through-holes 04 arranged at intervals can avoid signal path intersection, support multi-channel parallel transmission, and improve integration density.

[0064] Figure 3 1 is a schematic diagram of the structure after executing step S2 according to an embodiment of the present invention. Figure 2 and Figure 3 As shown, after executing step S2, the interconnection through-holes 04 of the polysilicon core board 01 and the upper and lower surfaces of the polysilicon core board 01 are filled with metal, and the upper and lower surfaces form the core board metal layer 03. Through this structural setting, high-density circuit patterns are formed on the upper and lower surfaces of the core board 01, and by filling the interconnection through-holes 04 with metal, vertical interconnection of the circuits on the upper and lower surfaces of the core board 01 can be achieved.

[0065] Figure 4 1 is a schematic diagram of the structure after the upper and lower surfaces of the core board are laminated with windows and pre-cured according to an embodiment of the present invention. Figure 4 As shown, the ABF insulation layer 02 is tightly attached to the core metal layer 03, and multiple connection holes 05 are formed on the ABF insulation layer 02 by laser drilling. In this example, the ABF insulation layer 02 is an ABF thin film material, and the thickness of the film material can be 10um to 100um. In this structural setting, the ABF insulation layer 02 plays an insulating and protective role in the circuit, and the provision of connection holes 05 is equivalent to creating a channel on the ABF insulation layer 02, so that circuits on different layers can be electrically connected through these connection holes 05, which is conducive to achieving vertical interconnection between multi-layer circuits and increasing wiring flexibility and density. In addition, when the ABF film material is thinner, it can reduce the distance between layers, increase signal transmission speed, and is suitable for high-density wiring; when the ABF film material is thicker, it can provide better mechanical support and thermal management, but the wiring density is lower.

[0066] Figure 5 This is a schematic diagram of the structure after the Ti / Cu seed layer 06 is sputtered on the upper and lower surfaces of the core plate according to an embodiment of the present invention. Figure 5 As shown, Ti / Cu seed layers 06 are deposited on the upper and lower surfaces of the polysilicon core 01. The Ti / Cu seed layers 06 are specifically distributed on the surfaces of the formed core metal layer 03 and the ABF insulation layer 02. This structural arrangement ensures good adhesion to the substrate surface while providing good conductivity.

[0067] Figure 6 Schematic diagram of the structure after the photoresist dry film is laminated and patterned on the upper and lower surfaces of the core board according to an embodiment of the present invention. Figure 6As shown, a photoresist dry film layer 07 is applied to the upper and lower surfaces of the polysilicon core substrate 01. Areas of the photoresist dry film layer 07 that will subsequently be metal-filled are exposed, that is, the photoresist dry film layer 07 is removed from these areas. This structural arrangement protects the surface of the core substrate 01, preventing accidental etching or contamination in these areas during subsequent processing. Exposing specific areas allows precise circuit connections to be formed where conduction is required, while maintaining insulation where it is not.

[0068] Figure 7 Schematic diagram of the structure of metal filling in the area not protected by the photoresist dry film layer according to an embodiment of the present invention. Figure 7 As shown, an electroplated metal layer 08 is provided in the area where the photoresist dry film layer 07 is not provided. Through this structural arrangement, a conductive path can be formed in the area of ​​the electroplated metal layer 08.

[0069] Figure 8 Schematic diagram of the structure after the dry film is removed, the Ti / Cu seed layer is etched, and the ABF layer is completely cured according to an embodiment of the present invention. Figure 8 As shown, Figure 7 Compared with the conventional method, the photoresist dry film layer 07 and the Ti / Cu seed layer 06 covered by the photoresist dry film layer 07 are reduced. Through this structural setting, the redundant Ti / Cu seed layer 06 is removed and the target circuit pattern is retained.

[0070] Figure 9 Schematic diagram of the finished product structure of the multi-layer polysilicon substrate according to the embodiment of the present invention. Steps S3 to S7 are repeated several times to form multi-layer conductive circuits on the upper and lower polysilicon core boards, and finally form a finished product such as Figure 9 A polysilicon-based package substrate structure includes a core substrate 01, an ABF insulation layer 02, and a metal wiring layer. The core substrate 01 is polysilicon, with interconnection vias 04 provided within the core substrate 01. The interconnection vias 04 are filled with metal. The ABF insulation layer 02 is provided on the surface of the metal wiring layer. The metal wiring layer includes a core metal layer 03 and multiple electroplated metal layers 08. A Ti / Cu seed layer 06 is provided below the electroplated metal layer 08. At least two metal wiring layers are provided on the upper and lower surfaces of the core substrate 01.

[0071] In this structural setup, the Ti / Cu seed layer 06 strengthens the bonding between the metal wiring layer and the substrate while providing good electrical conductivity. The polysilicon core of the package substrate boasts high thermal conductivity, effectively transferring heat to the heat dissipation channels and preventing substrate failure due to overheating. It also offers high mechanical strength and structural stability, maintaining structural stability in harsh environments such as external impact and thermal cycling, preventing cracking or deformation.

[0072] In a specific embodiment, a connection hole 05 is provided between two adjacent metal wiring layers, and a filling metal is provided in the connection hole 05. This structural arrangement enables interconnection between multiple layers of circuits in a polysilicon substrate.

[0073] In a specific embodiment, the thermal expansion coefficient of polysilicon is 2.6 ppm / °C. The thermal expansion coefficient of silicon chips is approximately 2.6 to 3.0 ppm / °C. This highly matched thermal expansion coefficient of polysilicon and silicon chips effectively prevents material expansion or contraction caused by temperature changes during the packaging process.

[0074] Figure 10a and Figure 10b The S23 stress cloud diagrams of HBM and ASIC corner solder when glass is used as substrate are shown respectively. Figure 10a and Figure 10b The S23 stress data of HBM and ASIC corner solder can be obtained when glass is used as the substrate. By integrating multiple sets of stress data with the stress data of polysilicon as the substrate, Table 1 is obtained, as shown below:

[0075]

[0076] Table 1

[0077] Table 1 shows the S23 stress statistics for HBM and ASIC corner solder joints using polysilicon and glass as substrates. As shown in Table 1, compared to polysilicon substrates, when glass is used as the substrate, the S23 stress at the corner solder joints of both HBM and ASIC increases by 13% and 41%, respectively (based on a glass CTE of 7.2 ppm / k). These stresses increase linearly with increasing CTE. For glass CTEs ranging from 5 ppm / k to 10 ppm / k, the stress at the corner solder joints of HBM and ASIC increases by 4% and 17%, respectively.

[0078] Figure 11 This is the warpage cloud diagram of the substrate module at 260°C when glass is used as the substrate. Figure 11 The warpage data of the substrate module with glass as the substrate can be obtained. The warpage data of the substrate module with glass as the substrate is integrated with the warpage data of the substrate module with polysilicon as the substrate to obtain Table 2, as shown in the following table:

[0079]

[0080] Table 2

[0081] Table 2 shows the warpage statistics for substrate modules using polysilicon and glass as substrates. As shown in Table 2, compared to polysilicon substrates, the warpage of the substrate module during assembly increases significantly when glass is used as the substrate, exceeding 127% (based on a glass CTE of 7.2 ppm / k). The warpage increases linearly with the glass CTE, with a 110% increase in warpage from 5 ppm / k to 10 ppm / k.

[0082] The CTE of polysilicon increases nonlinearly with increasing temperature. At low temperatures (<0°C), the growth rate is slow (CTE is 1.5-2.0 ppm / °C), at medium temperatures (20-500°C), the growth rate is nearly linear (CTE is 2.6-3.5 ppm / °C), and at high temperatures (>500°C), the growth rate accelerates (CTE>4.0 ppm / °C). Since polysilicon, as a packaging substrate, operates at medium temperatures over a long period of time, a polysilicon with a room-temperature CTE of 2.6 ppm / °C is used as a reference in Tables 1 and 2.

[0083] Combining Tables 1 and 2, we can conclude that the mechanical strength of polysilicon as a substrate is superior to that of glass. Using polysilicon as a substrate overcomes the brittleness of glass substrates, which can easily break or crack under intense thermal cycling and shock. Furthermore, the thermal conductivity of polysilicon at room temperature is 150 W / m·K, far higher than that of organic materials (such as FR4 and BT resin). Using polysilicon as a substrate overcomes the poor thermal conductivity of organic materials, which can easily lead to heat accumulation and affect device reliability and performance.

[0084] Obviously, those skilled in the art can make various modifications and changes to the embodiments of the present invention without departing from the spirit and scope of the present invention. In this way, if these modifications and changes are within the scope of the claims of the present invention and their equivalents, the present invention is also intended to cover these modifications and changes. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be considered as limiting the scope.

Claims

1. A polysilicon-based packaging substrate structure, characterized in that: It includes a core board, an ABF insulation layer, and a metal wiring layer. The core board is polysilicon, and interconnection through holes are provided in the core board. Filling metal is provided in the interconnection through holes. The ABF insulation layer is provided on the surface of the metal wiring layer. At least two layers of the metal wiring layers are respectively provided on the upper and lower surfaces of the core board, and a connecting hole is provided between two adjacent layers of the metal wiring layers. The filling metal is provided in the connecting hole.

2. The polysilicon-based packaging substrate structure according to claim 1, characterized in that: The thermal expansion coefficient of the polysilicon is 2.6 ppm / °C.

3. The polysilicon-based packaging substrate structure according to claim 1, characterized in that: The system further includes a Ti / Cu seed layer, which is disposed below the metal wiring layer.

4. A method for manufacturing a polysilicon-based packaging substrate structure according to any one of claims 1 to 3, characterized in that: The following steps are involved: S1: preparing interconnection through holes penetrating the polysilicon core board on the core board; S2: Filling the interconnection through-holes with copper and forming high-precision circuit patterns on the upper and lower surfaces; S3: laminating the ABF film onto the high-precision circuit pattern and pre-curing the film to form connection holes; S4: depositing a seed layer on the upper and lower surfaces of the core plate by surface sputtering; S5: laminating a photoresist dry film onto the upper and lower surfaces of the core board and patterning the same; S6: performing metal filling in the area not protected by the photoresist dry film layer by a double-sided electroplating method; S7: removing the photoresist dry film, removing the seed layer, and completely curing the ABF thin film layer; S8: looping steps S3 to S7 to form multiple layers of conductive circuits on the upper and lower sides of the polysilicon core board, and finally forming a finished product.

5. The method for manufacturing a polysilicon-based packaging substrate structure according to claim 4, wherein: In step S1, the interconnection through-holes are formed on the polysilicon core board by using deep silicon etching technology, laser etching technology or reactive ion etching technology.

6. The method for manufacturing a polysilicon-based packaging substrate structure according to claim 5, wherein: In step S1, a layer of insulating material is deposited on the wall surface of the interconnection through hole, and the insulating material is silicon dioxide or silicon nitride.

7. The method for manufacturing a polysilicon-based packaging substrate structure according to claim 4, wherein: In step S2, the interconnection through-holes are filled with metal copper or other conductive materials by sputtering, electroplating or chemical mechanical polishing.

8. The method for manufacturing a polysilicon-based packaging substrate structure according to claim 4, wherein: In step S3, the ABF film is laminated onto the circuit pattern on the polysilicon surface by vacuum lamination or roller lamination; and connection holes are formed on the ABF film by laser drilling.

9. The method for manufacturing a polysilicon-based packaging substrate structure according to claim 4, wherein: In step S4 and step S7, the seed layer includes a Ti seed layer and a Cu seed layer, the Ti seed layer is an adhesion layer, and the Cu seed layer is a conductive layer.

10. The method for manufacturing a polysilicon-based packaging substrate structure according to claim 4, wherein: In step S8, after the multi-layer circuit process is completed on the upper and lower surfaces of the polysilicon core board, a full curing treatment is performed, and the full curing temperature is 150-200° C. and the time is 30-60 minutes.

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