Semiconductor structure, preparation method thereof and packaging structure

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a packaging structure, and relates to the technical field of semiconductors. The semiconductor structure comprises a semiconductor substrate, a metal bonding pad, a first protection layer, a second protection layer and a bump structure, the first protection layer is provided with a first opening and a second opening along the thickness direction of the semiconductor substrate, the first opening extends to the metal bonding pad and at least partially exposes the metal bonding pad, and the caliber of the first opening is smaller than that of the second opening; the second protection layer is provided with a third opening, the third opening and the second opening are correspondingly arranged, the caliber of the third opening is increased in the direction away from the semiconductor substrate, and the caliber of the third opening is larger than that of the second opening; the bump structure is connected with the metal pad, and the diameter of the bump structure is smaller than the caliber of the second opening. According to the invention, the influence of incident light on the photoresist in the non-exposure area in the photoetching process is reduced, and the residual of the photoresist in the bump hole in the second protection layer after development is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and a packaging structure. Background Art

[0002] Flip chip packaging technology is an interconnection method based on small chip size, high input / I / O density, and excellent electrical and thermal performance. Solder balls or bumps are prepared on the chip pads and then mounted on the circuit board.

[0003] In related technologies, a passivation layer is usually formed on the chip. When the passivation layer is exposed to form a large-sized opening, the inner wall of the passivation layer at the opening is tilted, reflecting the incident light, causing the bottom of the photoresist under the photomask that does not need to be exposed to be exposed. After the photoresist is cross-linked and developed, residual glue is generated at the bottom of the large-sized opening, reducing the conductivity and adhesion of the bump, and affecting the reliability of the package.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a preparation method and a packaging structure thereof, which at least to a certain extent overcome the problem that the semiconductor structure provided in the related art is prone to produce residual glue, reduce the conductivity and adhesion of the bumps, and affect the reliability of the packaging.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate; a metal pad disposed on the semiconductor substrate; a first protective layer disposed on the semiconductor substrate, the first protective layer being provided with a first opening and a second opening along a thickness direction of the semiconductor substrate, the first opening extending to the metal pad and at least partially exposing the metal pad, the caliber of the first opening being smaller than the caliber of the second opening; a second protective layer disposed on a side of the first protective layer away from the semiconductor substrate, the second protective layer being provided with a third opening, the third opening being arranged corresponding to the second opening, the caliber of the third opening increasing in a direction away from the semiconductor substrate, the caliber of the third opening being larger than the caliber of the second opening; and a bump structure connected to the metal pad, the diameter of the bump structure being smaller than the caliber of the second opening.

[0008] In one embodiment of the present disclosure, the first protective layer includes a first sub-protective layer and a second sub-protective layer, the first sub-protective layer is arranged on the semiconductor substrate, and the first sub-protective layer is provided with the first opening; the second sub-protective layer is arranged on the first sub-protective layer, and the second sub-protective layer is provided with the second opening.

[0009] In one embodiment of the present disclosure, the first sub-protection layer includes two film layers, wherein the second sub-protection layer and the film layer of the first sub-protection layer close to the semiconductor substrate are made of the same material.

[0010] In one embodiment of the present disclosure, the dielectric constant of the second sub-protection layer is smaller than the dielectric constant of the film layer in the first sub-protection layer away from the semiconductor substrate.

[0011] In one embodiment of the present disclosure, the absorption rate of the material of the first protective layer for ultraviolet light used in the photolithography process is greater than the absorption rate of the material of the second protective layer for ultraviolet light used in the photolithography process, or the reflectivity of the material of the first protective layer for ultraviolet light used in the photolithography process is less than the reflectivity of the material of the second protective layer for ultraviolet light used in the photolithography process.

[0012] In one embodiment of the present disclosure, a stepped hole is formed on the inner wall of the second opening, and the aperture of the second opening increases in the direction away from the semiconductor substrate. The minimum diameter of the second opening is larger than the diameter of the first opening, the maximum diameter of the second opening is smaller than the diameter of the third opening, and the diameter of the bump structure is smaller than the minimum diameter of the second opening.

[0013] In one embodiment of the present disclosure, the semiconductor structure further includes: a metal layer, at least a portion of the metal layer is sandwiched between the metal pad and the bump structure.

[0014] In one embodiment of the present disclosure, the bump structure includes: a bump, arranged on the metal pad; a first solder layer, arranged on a side of the bump away from the metal pad; a metal barrier layer, arranged on a side of the first solder layer away from the bump; and a second solder layer, arranged on a side of the metal barrier layer away from the first solder layer.

[0015] According to another aspect of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a semiconductor substrate, on which a metal pad is formed; forming a first protective layer on the semiconductor substrate, wherein the first protective layer is provided with a first opening and a second opening along a thickness direction of the semiconductor substrate, the first opening extending to the metal pad and at least partially exposing the metal pad, and the diameter of the first opening is smaller than the diameter of the second opening; forming a second protective layer on a side of the first protective layer away from the semiconductor substrate, wherein the second protective layer is provided with a third opening, the third opening being arranged corresponding to the second opening, the diameter of the third opening increasing in a direction away from the semiconductor substrate, and the diameter of the third opening is larger than the diameter of the second opening; and forming a bump structure, the bump structure connecting the metal pad, the diameter of the bump structure being smaller than the diameter of the second opening.

[0016] In one embodiment of the present disclosure, the forming of the first protective layer on the semiconductor substrate includes: forming a first material layer on the semiconductor substrate; forming a first mask layer on the first material, wherein a first hole is formed at a position of the first mask layer corresponding to the first opening; etching the first material layer to form the first opening of a first sub-protective layer, and removing the first mask layer; forming a second material layer on a side of the first sub-protective layer away from the semiconductor substrate; forming a second mask layer on the second material layer, wherein a second hole is formed at a position of the second mask layer corresponding to the second opening; etching the second material layer to form the second opening of the second sub-protective layer, and removing the second mask layer to obtain the first protective layer.

[0017] In one embodiment of the present disclosure, the first sub-protection layer includes two film layers, wherein the second sub-protection layer and the film layer of the first sub-protection layer close to the semiconductor substrate are made of the same material.

[0018] In one embodiment of the present disclosure, the dielectric constant of the second sub-protection layer is smaller than the dielectric constant of the film layer in the first sub-protection layer away from the semiconductor substrate.

[0019] In one embodiment of the present disclosure, the absorption rate of the material of the first protective layer for ultraviolet light used in the photolithography process is greater than the absorption rate of the material of the second protective layer for ultraviolet light used in the photolithography process, or the reflectivity of the material of the first protective layer for ultraviolet light used in the photolithography process is less than the reflectivity of the material of the second protective layer for ultraviolet light used in the photolithography process.

[0020] In one embodiment of the present disclosure, the forming of the first protective layer on the semiconductor substrate includes: forming a third material layer on the semiconductor substrate; forming a third mask layer on the third material layer; patterning the third mask layer to form a third hole at a position corresponding to the second opening; patterning the third mask layer to form a fourth hole at a position corresponding to the first opening; etching the third material layer to form the second opening and the first opening to obtain the first protective layer.

[0021] In one embodiment of the present disclosure, the bump structure is formed on the metal pad, including: after forming the second protective layer, forming a metal layer on the metal pad, the first protective layer and the second protective layer, forming a fourth mask layer on the metal layer, and forming a bump hole at a position of the fourth mask layer corresponding to the bump structure; forming the bump structure in the bump hole, removing the fourth mask layer; and removing the metal layer outside the bump structure.

[0022] In one embodiment of the present disclosure, the bump structure is formed on the metal pad, including: forming a fifth mask layer on the metal pad, the first protective layer and the second protective layer, and a bump hole is formed at a position of the fifth mask layer corresponding to the bump structure; forming a metal layer and the bump structure on the upper surface of the first protective layer and the metal pad in the bump hole, and removing the fifth mask layer.

[0023] According to another aspect of the present disclosure, a packaging structure is also provided, including a packaging substrate and the above-mentioned semiconductor structure, wherein the semiconductor structure is flip-chip mounted on the packaging substrate, the bump structure is adhered to the packaging substrate, the periphery of the semiconductor structure is formed in a plastic encapsulation layer, and the plastic encapsulation layer wraps the bump structure.

[0024] In an embodiment of the present disclosure, a semiconductor structure includes a semiconductor substrate, a metal pad, a first protective layer, a second protective layer, and a bump structure. The first protective layer is provided with a first opening and a second opening along the thickness direction of the semiconductor substrate. The first opening extends to the metal pad and at least partially exposes the metal pad. The diameter of the first opening is smaller than the diameter of the second opening. The second protective layer is provided with a third opening. The third opening is provided corresponding to the second opening. The diameter of the third opening increases in a direction away from the semiconductor substrate. The diameter of the third opening is larger than the diameter of the second opening. The bump structure is connected to the metal pad. The diameter of the bump structure is smaller than the diameter of the second opening. By providing the second opening, the diameter of the second opening is between the diameter of the bump structure and the diameter of the third opening, thereby reducing the impact of incident light on the photoresist in the non-exposed area during the photolithography process. This effectively improves the residual adhesive residue after the photoresist is developed during the formation of the bump hole in the large opening structure of the second protective layer, thereby improving the packaging performance.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0027] Figure 1 FIG. 1 is a schematic structural diagram showing exposure of a fourth mask layer when forming a bump hole in a semiconductor structure according to an exemplary embodiment.

[0028] Figure 2 FIG. 1 is a schematic structural diagram of a semiconductor structure after forming a bump hole according to an exemplary embodiment.

[0029] Figure 3 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.

[0030] Figure 4 is a schematic structural diagram of a semiconductor structure according to another exemplary embodiment.

[0031] Figure 5 is a schematic structural diagram of a semiconductor structure according to yet another exemplary embodiment.

[0032] Figure 6 is a flow chart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0033] Figure 7 1 is a schematic structural diagram of a method for preparing a semiconductor structure after forming a first mask layer according to an exemplary embodiment.

[0034] Figure 8 It is a structural schematic diagram of a method for preparing a semiconductor structure after removing a first mask layer according to an exemplary embodiment.

[0035] Figure 9 FIG. 1 is a schematic structural diagram of a method for preparing a semiconductor structure after forming a second mask layer according to an exemplary embodiment.

[0036] Figure 10 It is a structural schematic diagram of a method for preparing a semiconductor structure after removing the second mask layer according to an exemplary embodiment.

[0037] Figure 11 FIG. 1 is a schematic structural diagram of a method for preparing a semiconductor structure after forming a second protective layer according to an exemplary embodiment.

[0038] Figure 12 FIG. 1 is a schematic structural diagram of a method for preparing a semiconductor structure after forming a metal layer according to an exemplary embodiment.

[0039] Figure 13 The figure is a structural schematic diagram of an exposure process after forming a third mask layer in a method for preparing a semiconductor structure according to an exemplary embodiment.

[0040] Figure 14 FIG. 1 is a schematic structural diagram of a method for preparing a semiconductor structure after forming a third hole according to an exemplary embodiment.

[0041] Figure 15 FIG. 1 is a schematic structural diagram of a method for preparing a semiconductor structure after forming a bump structure according to an exemplary embodiment.

[0042] Figure 16 It is a structural schematic diagram of a method for preparing a semiconductor structure after removing the third mask layer according to an exemplary embodiment.

[0043] Figure 17 It is a schematic structural diagram of a method for preparing a semiconductor structure according to an exemplary embodiment after removing the metal layer outside the bump structure.

[0044] Figure 18 1 is a schematic structural diagram of a semiconductor structure manufacturing method after reflow soldering of a bump structure according to an exemplary embodiment.

[0045] Figure 19 A schematic structural diagram of a packaging structure provided by an embodiment of the present disclosure is shown.

[0046] The description of the accompanying drawings is as follows:

[0047] 110. Semiconductor substrate; 210. Metal pad; 310. First protective layer; 3101. First sub-protective layer; 3102. Second sub-protective layer; 311. First opening; 312. Second opening; 410. Second protective layer; 411. Third opening; 510. Bump structure; 511. Bump; 512. First solder layer; 513. Metal barrier layer; 514. Second solder layer; 610. Metal layer; 710. First mask layer; 711. First hole; 720. Second mask layer; 721. Second hole; 730. Fourth mask layer; 731. Bump hole; 810. Package substrate; 910. Plastic layer. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the specified features. Throughout the description of this application, "plurality" means two or more, unless otherwise specified.

[0050] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0051] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, these are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0052] It should be pointed out that, in the absence of conflict, the embodiments of the present invention and the technical features therein may be combined with each other.

[0053] This exemplary implementation is described in detail below with reference to the accompanying drawings and examples.

[0054] like Figure 1 and Figure 2As shown, a semiconductor structure includes a semiconductor substrate 110, a metal pad 210 disposed on the semiconductor substrate 110, a first protective layer disposed on the semiconductor substrate 110, a first opening 311 disposed in the first protective layer 310, and a second protective layer 410 disposed on a side of the first protective layer 310 away from the semiconductor substrate 110. The second protective layer 410 has a third opening 411. When a bump hole 731 is formed in a fourth mask layer 730 using a photolithography process, the second protective layer 410 reflects incident light at the inclined inner sidewall formed by the third opening 411 or at the metal layer 610. The reflected light exposes the fourth mask layer 730 (e.g., photoresist) at the bottom of the non-exposed area below the mask plate. The photoresist is cross-linked after exposure, and residual adhesive is generated at the bottom edge of the bump hole 731 after development. As a result, during the flip-chip packaging process, the adhesion of the bump structure 510 is deteriorated, and the electrical connectivity between the bump structure 510 and the packaging substrate 810 is deteriorated.

[0055] In order to at least partially solve the above technical problems, the present disclosure provides a semiconductor structure, wherein a first opening 311 and a second opening 312 are provided in a first protective layer 310, and a third opening 411 is provided in a second protective layer 410, and the diameter of the first opening 311 is smaller than the diameter of the second opening 312, and the diameter of the second opening 312 is between the diameter of the bump structure 510 and the diameter of the third opening 411, that is, the diameter of the second opening 312 is between the diameter of the bump hole 731 and the diameter of the third opening 411, so that the inclined inner side wall formed by the third opening 411 or the inclined inner wall of the metal layer 610 reflects the incident light, and after reflection The light is irradiated on the upper surface of the flat first protective layer 310 or the upper surface of the flat metal layer 610. The secondary reflection or scattering by the upper surface of the first protective layer 310 or the upper surface of the flat metal layer 610 of the platform can greatly weaken the intensity of the incident light, thereby reducing the impact of the incident light on the photoresist at the bottom of the non-exposure area, avoiding the problem of residual glue after exposure and development of the photoresist at the bottom of the non-exposure area by reflected light, effectively improving the situation of residual photoresist after development in the process of forming the bump hole 731 of the large opening structure of the third opening 411, and improving the adhesion of the bump structure 510 and the electrical connectivity between the bump structure 510 and the packaging substrate 810.

[0056] like Figure 3As shown, in one embodiment, the present disclosure provides a semiconductor structure, which includes a semiconductor substrate 110; a metal pad 210, which is disposed on the semiconductor substrate 110; a first protective layer 310, which is disposed on the semiconductor substrate 110, and the first protective layer 310 is provided with a first opening 311 and a second opening 312 along the thickness direction of the semiconductor substrate 110, the first opening 311 extends to the metal pad 210 and at least partially exposes the metal pad 210, and the diameter of the first opening 311 is smaller than the diameter of the second opening 312; a second protective layer 410, which is disposed on a side of the first protective layer 310 away from the semiconductor substrate 110, and the second protective layer 410 is provided with a third opening 411, the third opening 411 is disposed corresponding to the second opening 312, the diameter of the third opening 411 increases in a direction away from the semiconductor substrate 110, and the diameter of the third opening 411 is larger than the diameter of the second opening 312; and a bump structure 510, which is connected to the metal pad 210, and the diameter of the bump structure 510 is smaller than the diameter of the second opening 312.

[0057] In an embodiment of the present disclosure, the semiconductor structure includes a semiconductor substrate 110, a metal pad 210, a first protective layer 310, a second protective layer 410 and a bump structure 510. The first protective layer 310 is provided with a first opening 311 and a second opening 312 along the thickness direction of the semiconductor substrate 110. The first opening 311 extends to the metal pad 210 and at least partially exposes the metal pad 210. The diameter of the first opening 311 is smaller than the diameter of the second opening 312; the second protective layer 410 is provided with a third opening 411, and the third opening 411 is arranged corresponding to the second opening 312. The diameter of the third opening 411 increases in the direction away from the semiconductor substrate 110, and the diameter of the third opening 411 is larger than the diameter of the second opening 312; the bump structure 510 is connected to the metal pad 210, and the diameter of the bump structure 510 is smaller than the diameter of the second opening 312. The present disclosure sets a second opening 312, the diameter of which is between the diameter of the bump structure 510 and the diameter of the third opening 411, thereby reducing the impact of incident light on the photoresist in the non-exposed area during the photolithography process, effectively improving the large opening structure of the second protective layer 410 and preventing residual glue from appearing after the photoresist is developed during the formation of the bump hole 731, thereby improving the stability of the bump structure.

[0058] In one embodiment, the semiconductor base 110 may include a semiconductor substrate, a number of IC circuits and an insulating layer; the material of the metal pad 210 may be aluminum or copper, the metal pad 210 may be placed inside the semiconductor base 110 and the metal pad 210 may be exposed, or the metal pad 210 may be set on the upper surface of the semiconductor base 110. This disclosure does not make any specific restrictions on this.

[0059] In one embodiment, the semiconductor structure includes a first protective layer 310 disposed on a semiconductor substrate 110. The first protective layer 310 has a first opening 311 and a second opening 312 along the thickness of the semiconductor substrate 110. The first opening 311 is disposed proximate to the semiconductor substrate 110, extending to the metal pad 210 and at least partially exposing the metal pad 210. In other words, the first protective layer 310 covers the axial outer edge of the metal pad 210. The second opening 312 is disposed distally from the semiconductor substrate 110. In other words, the first opening 311 is disposed between the second opening 312 and the semiconductor substrate 110. The first opening 311 and the second opening 312 are coaxially disposed with the metal pad 210, forming a stepped opening to expose the metal pad 210. The material of the first protective layer 310 may be silicon dioxide, silicon nitride, silicon carbonitride, or a combination thereof.

[0060] In one embodiment, the semiconductor structure includes a second protective layer 410, which is arranged on the upper surface of the first protective layer 310. The second protective layer 410 has a third opening 411 arranged corresponding to the second opening 312. The diameter of the third opening 411 is larger than the diameter of the second opening 312. The material of the second protective layer 410 can be polyimide.

[0061] In one embodiment, the semiconductor structure includes a bump structure 510, which is arranged in a stepped hole formed by the third opening 411, the second opening 312 and the first opening 311. The bump structure 510 is connected to the metal pad 210. The bump structure 510 protrudes from the third opening 411 in a direction away from the semiconductor base 110. The bump structure 510 realizes electrical and mechanical connection between the semiconductor structure and the packaging substrate 810. The electrical signal can be transmitted from the semiconductor structure to the packaging substrate 810, thereby completing the communication between the semiconductor structure and the external system.

[0062] In one embodiment, the bump structure 510 can at least cover the bottom surface and side wall surface of the first opening 311, and at least a portion of the bump structure 510 is disposed in the first opening 311, that is, the longitudinal section of the bump structure 510 is an inverted convex shape; or, a portion of the bump structure 510 is disposed in the first opening 311, and the bump structure 510 covers the bottom surface of the first opening 311, that is, the cross-section of the bump structure 510 is a rectangle, and the present disclosure does not make any specific limitations on this.

[0063] In one embodiment, the semiconductor structure further includes a metal layer 610, at least a portion of which is sandwiched between the metal pad 210 and the bump structure 510. The metal layer 610 is also called an under-bump metallization (UBM) layer. The material of the metal layer 610 may include one or a combination of titanium, copper, nickel, etc. The metal layer 610 may be prepared using physical vapor deposition technology, electroplating technology, etc. The metal layer 610 is electrically connected to the metal pad 210 so that the bump 511 does not directly contact the metal pad 210, thereby enhancing the adhesion between the bump 511 and the metal pad 210 and preventing metal diffusion of the bump 511.

[0064] In one embodiment, the second protective layer 410 is usually thicker. When the second protective layer 410 is etched using a photolithography process to form a third opening 411 to accommodate the bump structure 510, the diameter of the third opening 411 is relatively large, causing the diameter of the third opening 411 to gradually increase in a direction away from the semiconductor substrate 110, so that the third opening 411 forms an inclined inner sidewall.

[0065] It should be noted that the values ​​of parameters such as the thickness of the first protective layer 310, the thickness of the first sub-protective layer 311, the thickness of the second sub-protective layer 312, the aperture size of the second opening 312, the aperture size of the third opening 312, and the diameter of the bump hole 731 can be determined according to actual needs, and this disclosure does not make specific restrictions on this.

[0066] In one embodiment, the material of the first protective layer 310 has a higher absorptivity for ultraviolet light used in the photolithography process than the material of the second protective layer 410, or the material of the first protective layer 310 has a lower reflectivity for ultraviolet light used in the photolithography process than the material of the second protective layer 410. The material of the first protective layer 310 has a high absorptivity for ultraviolet light used in the photolithography process, for example, an absorptivity greater than 80%, or the material of the first protective layer 310 has a low reflectivity for ultraviolet light used in the photolithography process, for example, an absorptivity less than 3%. For example, the material of the first protective layer 310 can be silicon dioxide. When light reflected by the second protective layer 410 strikes the first protective layer 310, the first protective layer 310 absorbs the reflected ultraviolet light or minimizes the reflected ultraviolet light, further improving the adhesive residue at the bottom of the bump hole 731, effectively enhancing the electrical performance and adhesion of the semiconductor structure, and ensuring the packaging performance of the semiconductor structure.

[0067] It should be noted that the values ​​of the above-mentioned absorptivity and reflectivity can be determined according to actual needs and are not specifically limited in this disclosure.

[0068] like Figure 4 As shown, in one embodiment, the first protective layer 310 includes a first sub-protective layer 3101 and a second sub-protective layer 3102. The first sub-protective layer 3101 is arranged on the semiconductor substrate 110, and the first sub-protective layer 3101 is provided with a first opening 311; the second sub-protective layer 3102 is arranged on the first sub-protective layer 3101, and the second sub-protective layer 3102 is provided with a second opening 312.

[0069] In one embodiment, the first sub-protective layer 3101 and the second sub-protective layer 3102 may include any one of silicon dioxide, silicon nitride, and silicon carbonitride, or a combination thereof. For example, the first sub-protective layer 3101 and the second sub-protective layer 3102 may both be silicon dioxide. The semiconductor substrate 110 having the first sub-protective layer 3101 formed thereon may be used as the initial structure, and the second sub-protective layer 3102 may be formed on the basis of the first sub-protective layer 3101, thereby improving the flexibility of the semiconductor structure fabrication process.

[0070] In one embodiment, the first sub-protection layer 3101 includes two film layers, wherein the second sub-protection layer 3102 and the film layer of the first sub-protection layer 3101 close to the semiconductor substrate 110 are made of the same material.

[0071] For example, the film layer close to the semiconductor substrate 110 in the second sub-protective layer 3102 and the first sub-protective layer 3101 (called the lower film layer) are both formed of silicon dioxide, and the film layer away from the semiconductor substrate 110 in the first sub-protective layer 3101 (called the upper film layer) is formed of silicon nitride, that is, the first sub-protective layer 3101 and the second sub-protective layer 3102 form a sandwich structure of silicon dioxide-silicon nitride-silicon dioxide. Through the sandwich structure, the silicon dioxide film forming temperature in the first sub-protective layer 3101 close to the semiconductor substrate 110 is low, which can avoid the alloying temperature limitation of the metal pad 210, and the silicon dioxide has lower film stress, which can avoid wafer warping or film peeling caused by stress; the silicon nitride of the first sub-protective layer 3101 enables the adhesion between the lower film layer and the second sub-protective layer 3102; the silicon dioxide of the second sub-protective layer 3102 effectively avoids the film stress generated by the second protective layer 410 in the high-temperature process, thereby improving the film forming rate of the second protective layer 410.

[0072] In one embodiment, the dielectric constant of the second sub-protective layer 3102 is smaller than the dielectric constant of the film layer in the first sub-protective layer 3101 away from the semiconductor substrate 110. For example, the material of the second sub-protective layer 3102 may be silicon dioxide, and the material of the first sub-protective layer 3101 may be silicon nitride, thereby utilizing the low dielectric constant k value of silicon dioxide to reduce parasitic capacitance and significantly alleviate signal delay.

[0073] like Figure 5As shown, in one embodiment, a stepped hole is formed on the inner wall of the second opening 312, and the aperture of the second opening 312 increases in the direction away from the semiconductor substrate 110, the minimum diameter of the second opening 312 is larger than the diameter of the first opening 311, the maximum diameter of the second opening 312 is smaller than the diameter of the third opening 411, and the diameter of the bump structure 510 is smaller than the minimum diameter of the second opening 312.

[0074] It should be noted that the number of steps of the stepped hole formed on the inner wall of the second opening 312 can be determined according to actual needs, and this disclosure does not make any specific limitation on this.

[0075] In the embodiment of the present disclosure, a stepped hole is provided so that the reflected ultraviolet light can be irradiated on a certain step of the stepped hole. When the irradiated step is close to the bump structure 510, the path of the ultraviolet light to the non-exposed area can be extended, which can reduce the energy of the ultraviolet light. After the first protective layer 310 absorbs the ultraviolet light, the reflected energy of the ultraviolet light is further reduced, effectively reducing the residual glue generated by the exposure of the photoresist in the non-exposed area by the reflected ultraviolet light, thereby improving the conductivity and adhesion of the bump structure 510.

[0076] Continue to refer Figure 3-Figure 5 In one embodiment, the semiconductor structure includes a bump structure 510, and the bump structure 510 includes: a bump 511, which is arranged on the metal pad 210; a first solder layer 512, which is arranged on the side of the bump 511 away from the metal pad 210; a metal barrier layer 513, which is arranged on the side of the first solder layer 512 away from the bump 511; and a second solder layer 514, which is arranged on the side of the metal barrier layer 513 away from the first solder layer 512.

[0077] Within the bump hole 731, a bump 511, a first solder layer 512, a metal barrier layer 513, and a second solder layer 514 can be sequentially formed on the upper surface of the metal layer 610. The first solder layer 512 and the second solder layer 514 can be one of lead, tin, and silver, or an alloy containing any of the above solder metals. For example, the first solder layer 512 and / or the second solder layer 514 can be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. The metal barrier layer 513 can be made of nickel. The metal barrier layer 513, the first solder layer 512, and the second solder layer 514 can be columnar in shape. The bump 511 can be formed of copper, and the longitudinal cross-section of the bump 511 can be in the shape of an inverted convex.

[0078] The metal layer 610 is formed by physical vapor deposition or electroplating of a metal material layer such as titanium, titanium tungsten, or copper on the metal pad 210. The metal material such as titanium, titanium tungsten, or copper can be used to adhere to and block metal copper from entering the semiconductor substrate 110, and the copper layer is used to form an electroplated electrode.

[0079] like Figure 6 As shown, an embodiment of the present disclosure further provides a method for preparing a semiconductor structure, comprising:

[0080] S602, providing a semiconductor substrate 110, on which a metal pad 210 is formed;

[0081] S604, forming a first protection layer 310 on the semiconductor substrate 110, wherein the first protection layer 310 has a first opening 311 and a second opening 312 along the thickness direction of the semiconductor substrate 110, the first opening 311 extending to the metal pad 210 and at least partially exposing the metal pad 210, and the diameter of the first opening 311 is smaller than the diameter of the second opening 312;

[0082] S606: Form a second protective layer 410 on a side of the first protective layer 310 away from the semiconductor substrate 110, wherein the second protective layer 410 is provided with a third opening 411, the third opening 411 being arranged corresponding to the second opening 312, and the diameter of the third opening 411 increasing in a direction away from the semiconductor substrate 110, and the diameter of the third opening 411 is larger than the diameter of the second opening 312;

[0083] S608 , forming a bump structure 510 , wherein the bump structure 510 is connected to the metal pad 210 , and the diameter of the bump structure 510 is smaller than the diameter of the second opening 312 .

[0084] In one embodiment, S604 forms a first protective layer 310 on the semiconductor substrate 110, including: forming a first material layer on the semiconductor substrate 110; forming a first mask layer 710 on the first material, wherein a first hole 711 is formed at a position of the first mask layer 710 corresponding to the first opening 311; etching the first material layer to form the first opening 311 of the first sub-protective layer 3101, and removing the first mask layer 710; forming a second material layer on a side of the first sub-protective layer 3101 away from the semiconductor substrate 110; forming a second mask layer 720 on the second material layer, wherein a second hole 721 is formed at a position of the second mask layer 720 corresponding to the second opening 312; etching the second material layer to form the second opening 312 of the second sub-protective layer 3102, and removing the second mask layer 720 to obtain the first protective layer 310. The materials of the first material layer and the second material layer may include one of silicon dioxide, silicon nitride, and silicon carbonitride, or a combination thereof. The first mask layer 710 and the second mask layer 720 may be photoresists.

[0085] In one embodiment, the first sub-protection layer 3101 includes two film layers, wherein the second sub-protection layer 3102 and the film layer of the first sub-protection layer 3101 close to the semiconductor substrate 110 are made of the same material.

[0086] In one embodiment, the dielectric constant of the second sub-protecting layer 3102 is smaller than the dielectric constant of the film layer in the first sub-protecting layer 3101 away from the semiconductor substrate 110 .

[0087] In one embodiment, the absorption rate of the material of the first protective layer 310 for ultraviolet light used in the photolithography process is greater than the absorption rate of the material of the second protective layer 410 for ultraviolet light used in the photolithography process, or the reflectivity of the material of the first protective layer 310 for ultraviolet light used in the photolithography process is less than the reflectivity of the material of the second protective layer 410 for ultraviolet light used in the photolithography process.

[0088] In one embodiment, S604 forms a first protective layer 310 on the semiconductor substrate 110, including: forming a third material layer on the semiconductor substrate 110; forming a third mask layer on the third material layer; patterning the third mask layer to form a third hole at a position corresponding to the second opening 312; patterning the third mask layer to form a fourth hole at a position corresponding to the first opening 311; and etching the third material layer to form the second opening 312 and the first opening 311, thereby obtaining the first protective layer 310. The material of the third material layer may include one of silicon dioxide, silicon nitride, and silicon carbonitride, or a combination thereof. The third mask layer may be a photoresist.

[0089] In one embodiment, S608 forms a conductive structure of a bump 511 on the metal pad 210, including: after forming the second protective layer 410, forming a metal layer 610 on the metal pad 210, the first protective layer 310 and the second protective layer 410, forming a fourth mask layer 730 on the metal layer 610, and forming a bump hole 731 at a position of the fourth mask layer 730 corresponding to the bump structure 510; forming a bump structure 510 in the bump hole 731, removing the fourth mask layer 730; and removing the metal layer 610 outside the bump structure 510.

[0090] In one embodiment, S608 forms a bump structure 510 on the metal pad 210, including: forming a fifth mask layer on the metal pad 210, the first protective layer 310 and the second protective layer 410, and forming a bump hole 731 at a position of the fifth mask layer corresponding to the bump structure 510; forming a metal layer 610 and a bump structure 510 on the upper surface of the first protective layer 310 and the metal pad 210 in the bump hole 731, and removing the fifth mask layer.

[0091] In one embodiment, a method for preparing a semiconductor structure includes the following steps:

[0092] like Figure 7As shown, a semiconductor substrate 110 is provided, on which a metal pad 210 is formed. A first material layer is formed on the semiconductor substrate 110 and the metal pad 210, and a first mask layer 710 is formed on the first material layer. A first hole 711 is formed in the first mask layer 710 at a location where the first opening 311 was pre-formed using a photolithography process. The first material layer is etched to form the first opening 311 of the first sub-protective layer 3101. The material of the first sub-protective layer 3101 can be one of silicon dioxide, silicon nitride, and silicon carbonitride, or a combination thereof, and the first mask layer 710 can be photoresist. The material of the metal pad 210 can be aluminum or copper.

[0093] like Figure 8 As shown, the first mask layer 710 is removed.

[0094] like Figure 9 As shown, a second material layer is formed on the upper surface of the first sub-protective layer 3101 and the metal pad 210 using a deposition process, a second mask layer 720 is formed on the second material layer, a second hole 721 is formed in the second mask layer 720 at the position where the second opening 312 is pre-prepared using a photolithography process, and the second material layer is etched to form a second opening 312 in the second sub-protective layer 3102, wherein the diameter of the second opening 312 is larger than the diameter of the first opening 311. The material of the second sub-protective layer 3102 can be one of silicon dioxide, silicon nitride, silicon carbonitride, or a combination thereof, and the second mask layer 720 can be a photoresist. For example, the thickness of the formed second sub-protective layer 3102 can be 2μm, and the diameter of the second opening 312 can be 30μm.

[0095] like Figure 10 As shown, the second mask layer 720 is removed.

[0096] like Figure 11 As shown, a second protective layer 410 is formed on the upper surfaces of the second sub-protective layer 3102, the first sub-protective layer 3101, and the metal pad 210 using a deposition process. A third opening 411 is formed in the second protective layer 410 using a photolithography process. The third opening 411 is arranged corresponding to the second opening 312, and the diameter of the third opening 411 increases as it moves away from the semiconductor substrate 110. The diameter of the third opening 411 is larger than the diameter of the second opening 312. The diameter of the third opening 411 increases as it moves away from the semiconductor substrate 110, so that the inner sidewall of the third opening 411 forms an outwardly inclined surface. During the subsequent photolithography process, the inner sidewall of the third opening 411 reflects incident light, and the reflected light affects the photoresist in the non-exposed area, which can easily cause residual photoresist after development. The material of the second protective layer 410 can be polyimide.

[0097] like Figure 12As shown, a metal layer 610 is formed on the upper surface of the second protective layer 410, the second sub-protective layer 3102, the first sub-protective layer 3101, and the metal pad 210 using a deposition process. The metal layer 610 can be prepared by physical vapor deposition. The material of the metal layer 610 may include titanium, titanium tungsten, copper, etc.

[0098] like Figure 13 As shown, a fourth mask layer 730 is formed on the upper surface of the metal layer 610. The non-exposure area is shielded by the mask plate Mask, and the fourth mask layer 730 in the exposure area Exp is exposed. Incident light passes through the fourth mask layer 730 and irradiates the surface of the metal layer 610. The metal layer 610 reflects the incident light at the inclined inner sidewall of the third opening 411 in the second protective layer 410. The light reflected by the inclined inner wall is incident on the flat metal layer 610 above the second sub-protective layer 3102, thereby avoiding affecting the fourth mask layer 730 in the non-exposure area. The fourth mask layer 730 can be a photoresist.

[0099] like Figure 14 As shown, the fourth mask layer 730 in the non-exposed area is developed to form a third hole in the fourth mask layer 730 .

[0100] like Figure 15 As shown, a bump 511, a first solder layer 512, a metal barrier layer 513, and a second solder layer 514 are sequentially formed on the upper surface of the metal layer 610 within the third hole. The first solder layer 512 and the second solder layer 514 can be made of one of lead, tin, and silver, or an alloy containing any of the above solder metals. The material of the metal barrier layer 513 can include nickel. The bump 511 can be formed of copper.

[0101] like Figure 16 As shown, the fourth mask layer 730 is removed.

[0102] like Figure 17 As shown, the metal layer 610 outside the bump structure 510 is removed.

[0103] like Figure 18 As shown, a high temperature reflow process is used to form solder bumps on the surface of the second solder layer 514, and the solder bumps are obtained as shown in FIG. Figure 2 The semiconductor structure shown.

[0104] In another embodiment, a method for preparing a semiconductor structure specifically includes the following steps:

[0105] forming a third material layer on the semiconductor substrate 110 , wherein the material of the third material layer may include one of silicon dioxide, silicon nitride, and silicon carbonitride, or a combination thereof;

[0106] forming a third mask layer on the third material layer, wherein the third mask layer may include photoresist;

[0107] Performing a patterning process on the third mask layer to form a third hole at a position corresponding to the second opening 312 , wherein the patterning process may include an exposure process and a development process;

[0108] Performing patterning on the third mask layer to form a fourth hole at a position corresponding to the first opening 311;

[0109] The third material layer is etched to form a second opening 312 and a first opening 311 , thereby obtaining a first protective layer 310 .

[0110] After forming the first protective layer 310, Figures 11-18 The processing method is to obtain Figure 1 The semiconductor structure shown.

[0111] It should be noted that the above-mentioned method for preparing the semiconductor structure is Figure 1 and Figure 2 The semiconductor structure is illustrated as an example. Figure 3 The semiconductor structure shown can be obtained by performing multiple photolithography processes on the first protection layer 310 , which will not be described in detail here.

[0112] In one embodiment, the metal layer 610 can be formed before the bump hole 731 is formed, and a portion of the metal layer 610 can be removed after the bump structure 510 is formed. Alternatively, after the bump hole 731 is formed, the metal layer 610 can be first formed within the bump hole 731, and then the bump structure 510 can be formed on the upper surface of the metal layer 610. The present disclosure does not specifically limit the formation method of the metal layer 610. The above embodiment is described by taking the example of forming the metal layer 610 before forming the bump hole 731 and removing a portion of the metal layer 610 after forming the bump structure 510.

[0113] For a semiconductor structure in which the metal layer 610 is formed after the bump hole 731 is formed, Figure 11 After the structure, execute Figure 13 and Figure 14 The corresponding steps form the bump hole 731 , and the metal layer 610 and the bump structure 510 are formed on the upper surface of the first sub-protection layer 3101 and the metal pad 210 in the bump hole 731 . Similarities are not repeated here.

[0114] like Figure 19As shown, in an optional embodiment, the present disclosure further provides a packaging structure, which includes a packaging substrate 810 and the above-mentioned semiconductor structure, the semiconductor structure is flip-chip mounted on the packaging substrate 810, the bump structure 510 is attached to the packaging substrate 810, and a plastic layer 910 is formed on the periphery of the semiconductor structure, and the plastic layer 910 wraps the bump structure 510. The semiconductor structure is bonded to the packaging substrate 810, and the plastic layer 910 formed on the periphery of the semiconductor structure can be made of epoxy resin. The plastic layer 910 wraps the bump structure 510, and the first solder layer 512 and the second solder layer 514 pass through the plastic layer 910 and are bonded to the packaging substrate 810. The plastic layer 910 can protect the bump structure 510 and at the same time make it difficult for the semiconductor structure to fall off from the packaging substrate 810.

[0115] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0116] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0117] The above is a detailed introduction to a semiconductor structure provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

[0118] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: semiconductor substrates; A metal pad is provided on the semiconductor substrate; a first protective layer disposed on the semiconductor substrate, the first protective layer having a first opening and a second opening along a thickness direction of the semiconductor substrate, the first opening extending to the metal pad and at least partially exposing the metal pad, the first opening having a smaller diameter than the second opening; a second protective layer disposed on a side of the first protective layer away from the semiconductor substrate, the second protective layer being provided with a third opening, the third opening being disposed corresponding to the second opening, the diameter of the third opening increasing in a direction away from the semiconductor substrate, and the diameter of the third opening being larger than the diameter of the second opening; A bump structure is connected to the metal pad, and a diameter of the bump structure is smaller than a diameter of the second opening.

2. The semiconductor structure according to claim 1, wherein: The first protective layer includes a first sub-protective layer and a second sub-protective layer, the first sub-protective layer is disposed on the semiconductor substrate, and the first sub-protective layer is provided with the first opening; The second sub-protective layer is disposed on the first sub-protective layer, and the second sub-protective layer is provided with the second opening.

3. The semiconductor structure according to claim 2, wherein: The first sub-protection layer includes two film layers, wherein the second sub-protection layer and the film layer of the first sub-protection layer close to the semiconductor substrate are made of the same material.

4. The semiconductor structure according to claim 2, wherein: The dielectric constant of the second sub-protection layer is smaller than the dielectric constant of the film layer in the first sub-protection layer far away from the semiconductor substrate.

5. The semiconductor structure according to claim 1, wherein: The absorption rate of the material of the first protective layer for ultraviolet light used in the photolithography process is greater than the absorption rate of the material of the second protective layer for ultraviolet light used in the photolithography process, or The reflectivity of the material of the first protective layer with respect to ultraviolet light used in the photolithography process is lower than the reflectivity of the material of the second protective layer with respect to ultraviolet light used in the photolithography process. The semiconductor structure according to claim 1 , wherein: A stepped hole is formed on the inner wall of the second opening. The aperture of the second opening increases in the direction away from the semiconductor substrate. The minimum aperture of the second opening is larger than the aperture of the first opening. The maximum aperture of the second opening is smaller than the aperture of the third opening. The diameter of the bump structure is smaller than the minimum aperture of the second opening.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: A metal layer, at least a portion of which is sandwiched between the metal pad and the bump structure.

8. The semiconductor structure according to any one of claims 1 to 7, wherein: The bump structure includes: a bump, disposed on the metal pad; a first solder layer, disposed on a side of the bump away from the metal pad; a metal barrier layer, disposed on a side of the first solder layer away from the bump; The second solder layer is arranged on a side of the metal barrier layer away from the first solder layer.

9. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein a metal pad is formed on the semiconductor substrate; forming a first protective layer on the semiconductor substrate, wherein the first protective layer is provided with a first opening and a second opening along a thickness direction of the semiconductor substrate, the first opening extending to the metal pad and at least partially exposing the metal pad, and the diameter of the first opening is smaller than the diameter of the second opening; forming a second protective layer on a side of the first protective layer away from the semiconductor substrate, wherein the second protective layer is provided with a third opening, the third opening being arranged corresponding to the second opening, and the diameter of the third opening increasing in a direction away from the semiconductor substrate, and the diameter of the third opening is larger than the diameter of the second opening; A bump structure is formed, wherein the bump structure is connected to the metal pad, and a diameter of the bump structure is smaller than a diameter of the second opening.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The step of forming a first protective layer on the semiconductor substrate comprises: forming a first material layer on the semiconductor substrate; forming a first mask layer on the first material, wherein a first hole is formed at a position of the first mask layer corresponding to the first opening; Etching the first material layer to form the first opening of the first sub-protection layer, and removing the first mask layer; forming a second material layer on a side of the first sub-protection layer away from the semiconductor substrate; forming a second mask layer on the second material layer, wherein a second hole is formed at a position of the second mask layer corresponding to the second opening; The second material layer is etched to form the second opening of the second sub-protective layer, and the second mask layer is removed to obtain the first protective layer.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The first sub-protection layer includes two film layers, wherein the second sub-protection layer and the film layer of the first sub-protection layer close to the semiconductor substrate are made of the same material.

12. The semiconductor structure according to claim 11, wherein: The dielectric constant of the second sub-protection layer is smaller than the dielectric constant of the film layer in the first sub-protection layer far away from the semiconductor substrate.

13. The method for preparing a semiconductor structure according to claim 9, wherein: The absorption rate of the material of the first protective layer for ultraviolet light used in the photolithography process is less than 100% and greater than 80%, or The reflectivity of the material of the first protective layer to ultraviolet light used in the photolithography process is less than 3%.

14. The method for preparing a semiconductor structure according to claim 9, wherein: The step of forming a first protective layer on the semiconductor substrate comprises: forming a third material layer on the semiconductor substrate; a third mask layer on the third material layer; performing patterning on the third mask layer to form a third hole at a position corresponding to the second opening; performing patterning on the third mask layer to form a fourth hole at a position corresponding to the first opening; The third material layer is etched to form the second opening and the first opening, thereby obtaining the first protective layer.

15. The method for preparing a semiconductor structure according to any one of claims 9 to 14, characterized in that: The step of forming a bump structure on the metal pad includes: After forming the second protection layer, forming a metal layer on the metal pad, the first protection layer and the second protection layer; forming a fourth mask layer on the metal layer, wherein a bump hole is formed at a position of the fourth mask layer corresponding to the bump structure; forming the bump structure in the bump hole, and removing the fourth mask layer; The metal layer outside the bump structure is removed.

16. The method for preparing a semiconductor structure according to any one of claims 9 to 14, characterized in that: The step of forming a bump structure on the metal pad includes: forming a fifth mask layer on the metal pad, the first protective layer and the second protective layer, wherein a bump hole is formed at a position of the fifth mask layer corresponding to the bump structure; The metal layer and the bump structure are formed on the upper surfaces of the first protection layer and the metal pad in the bump hole, and the fifth mask layer is removed.

17. A packaging structure, characterized in that: It comprises a packaging substrate and a semiconductor structure according to any one of claims 1 to 8, wherein the semiconductor structure is flip-chip mounted on the packaging substrate, the bump structure is attached to the packaging substrate, and a plastic encapsulation layer is formed around the semiconductor structure, and the plastic encapsulation layer wraps the bump structure.

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