Package structure

Abstract

The invention provides a packaging structure. The packaging structure comprises at least one semiconductor element, at least one inactive element and packaging glue. The at least one inactive device is disposed around the at least one semiconductor device and includes a main portion and at least one via extending through the main portion. The encapsulant encapsulates the at least one semiconductor element and the at least one inactive element. A first surface of the encapsulant is substantially coplanar with a first surface of the at least one inactive device and a first surface of the at least one semiconductor device. A second surface of the encapsulant is substantially coplanar with a second surface of the at least one inactive device and a second surface of the at least one semiconductor device.

Description

Technical Field

[0001] The present invention claims priority to U.S. patent application Ser. No. 18 / 600,988 (i.e., priority date is “March 11, 2024”), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a packaging structure, an assembly structure, and a method for manufacturing the same, and more particularly to a packaging structure including at least one non-active component, an assembly structure including the packaging structure, and a method for manufacturing the same. Background Art

[0003] Semiconductor electronic components are widely used in various electronic applications, and their size continues to shrink to meet the needs of current applications. However, shrinking the size of semiconductor electronic components brings some challenges that affect their ultimate electrical characteristics, quality, cost and yield. As semiconductor electronic components become smaller and smaller, they require multifunctionality and large-capacity data processing capabilities. Therefore, there is an increasing need to improve the integration level of semiconductor elements used in these electronic components. However, due to the limitations of semiconductor integration technology, it is challenging to use only a single semiconductor chip to meet all the required functions. To solve this problem, semiconductor packages have been developed, which involve including multiple semiconductor chips.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not form the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present invention. Summary of the Invention

[0005] The present disclosure aims to provide a packaging structure to solve at least one of the above problems.

[0006] One aspect of the present disclosure provides a packaging structure comprising at least one semiconductor component, at least one non-active component, and an encapsulant. The at least one non-active component is disposed around the at least one semiconductor component and includes a main portion and at least one through-hole extending through the main portion. The encapsulant encapsulates the at least one semiconductor component and the at least one non-active component. A first surface of the encapsulant is substantially coplanar with a first surface of the at least one non-active component and a first surface of the at least one semiconductor component. A second surface of the encapsulant is substantially coplanar with a second surface of the at least one non-active component and a second surface of the at least one semiconductor component.

[0007] Another aspect of the present disclosure provides an assembly structure comprising a substrate, a molded structure, a redistribution structure, and a higher electronic component. The molded structure is disposed on the substrate and electrically connected thereto. The molded structure comprises at least one semiconductor component, at least one non-active component, and a packaging adhesive that encapsulates the at least one semiconductor component and the at least one non-active component. The redistribution structure is disposed on the molded structure and electrically connected thereto. The higher electronic component is disposed on the redistribution structure and electrically connected thereto. The at least one non-active component is configured to provide a vertical conductive path between the higher electronic component and the substrate. The higher electronic component is not electrically connected to the substrate through the at least one semiconductor component.

[0008] Another aspect of the present disclosure provides a manufacturing method. The manufacturing method includes: disposing at least one semiconductor element and at least one non-active element on a carrier, wherein the at least one non-active element includes an active portion and at least one through-hole extending through the active portion; forming a packaging adhesive on the carrier to encapsulate the at least one semiconductor element and the at least one non-active element; forming a redistribution structure on a first surface of the packaging adhesive, a first surface of the at least one non-active element, and a first surface of the at least one semiconductor element, wherein the redistribution structure is electrically connected to the at least one semiconductor element and the at least one through-hole of the at least one non-active element; disposing a higher electronic component on the redistribution structure; and removing the carrier.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purposes as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims when considered in conjunction with the accompanying drawings, in which like reference characters represent like elements throughout the drawings, and:

[0011] Figure 1 A cross-sectional schematic diagram of an assembly structure is shown according to some embodiments of the present disclosure.

[0012] Figure 2 yes Figure 1 Magnified view of area "A".

[0013] Figure 3 yes Figure 1A top view of the molded structure of the assembled structure.

[0014] Figure 4 According to some embodiments of the present disclosure, a top view of a molded structure is shown.

[0015] Figure 5 According to some embodiments of the present disclosure, a top view of a molded structure is shown.

[0016] Figure 6 A cross-sectional schematic diagram of an assembly structure is shown according to some embodiments of the present disclosure.

[0017] Figures 7 to 13 According to some embodiments of the present disclosure, various stages of a method for preparing an assembly structure are shown.

[0018] Figure 14 A flow chart showing a method for preparing an assembly structure according to some embodiments of the present disclosure is provided.

[0019] The reference numerals are as follows:

[0020] 1: Assemble the structure

[0021] 1a: Assembling the structure

[0022] 2: Molded structure

[0023] 2a: Molded structure

[0024] 2b: Molded structure

[0025] 3: Non-active components

[0026] 4: Redistribution structure

[0027] 10: Packaging structure

[0028] 10a: Packaging structure

[0029] 12:Substrate

[0030] 14: Bump

[0031] 16: External connector

[0032] 18: Higher electronic components

[0033] 19:Solder material

[0034] 20: Semiconductor components

[0035] 21: First surface

[0036] 22: Second surface

[0037] 23: Side surface

[0038] 25: First semiconductor element

[0039] 26: Second semiconductor element

[0040] 27: Packaging glue

[0041] 31: First non-active element

[0042] 32: Second non-active element

[0043] 32b: Second non-active element

[0044] 33: The third non-active element

[0045] 33b: Third non-active element

[0046] 34: Fourth non-active element

[0047] 34b: Fourth non-active element

[0048] 41: first surface

[0049] 42: Second surface

[0050] 43: Side surface

[0051] 44: dielectric layer

[0052] 45: Circuit layer

[0053] 46:Inner perforation

[0054] 47: Padding

[0055] 80:Carrier

[0056] 82: Release layer

[0057] 121: first surface

[0058] 122: Second surface

[0059] 123: side surface

[0060] 141: first bump

[0061] 142: Second bump

[0062] 180: Main part

[0063] 181: first surface

[0064] 182: Second surface

[0065] 183: Side surface

[0066] 184: Active circuit structure

[0067] 185:Padding

[0068] 250: Main part

[0069] 251: first surface

[0070] 252: Second surface

[0071] 253: side surface

[0072] 254: Active circuit structure

[0073] 255:Padding

[0074] 271: first surface

[0075] 272: Second surface

[0076] 273: side surface

[0077] 281: Space

[0078] 282: Space

[0079] 283: Space

[0080] 310: Main part

[0081] 311: first surface

[0082] 312: Second surface

[0083] 313: side surface

[0084] 314: side surface

[0085] 315:Piercing

[0086] 441: top dielectric layer

[0087] 442: bottom dielectric layer

[0088] 900:Method

[0089] 1801: bottom surface

[0090] 2501: Top surface

[0091] 3151:First surface

[0092] 3152: Second surface

[0093] A: Area

[0094] g1: gap

[0095] g2: gap

[0096] L1: Length

[0097] L2: Length

[0098] S901: Step

[0099] S902: Step

[0100] S903: Step

[0101] S904: Step

[0102] S905: Step

[0103] T1:Thickness

[0104] T2: Thickness

[0105] W1: width

[0106] W2: width

[0107] W3: Width

[0108] W4: Width DETAILED DESCRIPTION

[0109] Specific language will be used below to describe the embodiments or examples of the present disclosure shown in the accompanying drawings. It should be understood that no limitation of the scope of the present disclosure is intended hereby. Any changes or modifications to the described embodiments, and any further application of the principles described herein, will be considered normal occurrences for those skilled in the art to which the present disclosure relates. Reference symbols may be reused throughout the embodiments, but this does not necessarily mean that components of one embodiment are applicable to another embodiment, even if they use the same reference symbols.

[0110] It should be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited to these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0111] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the concepts of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" also include the plural forms. It should be understood that the terms "comprises" and "comprising" when used in this specification indicate the presence of the described parts, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more parts, integers, steps, operations, elements, components, or combinations thereof.

[0112] Figure 1 A cross-sectional schematic diagram of an assembly structure 1 is shown according to some embodiments of the present disclosure. Figure 2 yes Figure 1 FIG. 1 is an enlarged view of region “A” of FIG. 1 . In some embodiments, assembly structure 1 may be a semiconductor electronic component, a semiconductor electronic structure, or a package structure. In some embodiments, assembly structure 1 may include package structure 10, substrate 12, a plurality of bumps 14, and a plurality of external connectors 16.

[0113] Substrate 12 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials. In some embodiments, substrate 12 may include a semiconductor-on-insulator (SOS) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (SGOI) substrate. In some embodiments, substrate 12 may include an organic material, glass, a ceramic material, or the like. For example, substrate 12 may include a curable photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) containing a photoinitiator. For example, the substrate 12 may include a homogeneous material, such as epoxy FR5, FR4, bismaleimide triazine (BT), printed circuit board (PCB) material, prepreg (PP), Ajinomoto build-up film (ABF), or other suitable materials.

[0114] The substrate 12 may have a first surface 121 (e.g., a top surface), a second surface 122 (e.g., a bottom surface), and a side surface 123. The second surface 122 (e.g., a bottom surface) may be opposite to the first surface 121 (e.g., a top surface). The side surface 123 may extend between the first surface 121 (e.g., a top surface) and the second surface 122 (e.g., a bottom surface).

[0115] Package structure 10 may be disposed on first surface 121 of substrate 12 and may be attached to first surface 121 of substrate 12 via bumps 14. External connectors 16 may be disposed on second surface 122 of substrate 12 to provide electrical connections, such as I / O connections, to substrate 12. Each external connector 16 may include a reflowable material, such as a solder ball.

[0116] The package structure 10 may include a mold structure 2, a redistribution structure 4, and a higher electronic component 18. The mold structure 2 may be disposed on and electrically connected to the substrate 12. The mold structure 2 may have a first surface 21 (e.g., a top surface), a second surface 22 (e.g., a bottom surface), and side surfaces 23.

[0117] The second surface 22 (eg, bottom surface) may be opposite to the first surface 21 (eg, top surface). The side surface 23 may extend between the first surface 21 (eg, top surface) and the second surface 22 (eg, bottom surface).

[0118] The molded structure 2 may include at least one semiconductor element 20, at least one passive element 3, and an encapsulant 27. The semiconductor element 20 may include a semiconductor die or chip, such as a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.). The semiconductor element 20 may include a first semiconductor element 25 and a second semiconductor element 26 arranged side by side. In some embodiments, the size and function of the first semiconductor element 25 may be the same as the size and function of the second semiconductor element 26. The structure of the first semiconductor element 25 may be the same as the structure of the second semiconductor element 26. Both the first semiconductor element 25 and the second semiconductor element 26 may be memory dies.

[0119] The first semiconductor element 25 may have a first surface 251 (e.g., a top surface or active surface), a second surface 252 (e.g., a bottom surface or backside surface), and a side surface 253. The second surface 252 (e.g., a bottom surface) may be opposite the first surface 251 (e.g., a top surface). The side surface 253 may extend between the first surface 251 (e.g., a top surface) and the second surface 252 (e.g., a bottom surface).

[0120] The first semiconductor element 25 may include a main portion 250 and an active circuit structure 254 disposed on a top surface 2501 of the main portion 250. The material of the main portion 250 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0121] The active circuit structure 254 may include multiple dielectric layers, multiple circuit layers, and multiple pads 255. The dielectric layers may cover the circuit layers. The pads 255 may be electrically connected to the circuit layers and embedded in the dielectric layers. The pads 255 may be exposed from the first surface 251 of the first semiconductor element 25.

[0122] Inactive elements 3 may be disposed around semiconductor element 20 (including, for example, first semiconductor element 25 and second semiconductor element 26). Inactive elements 3 may also be referred to as "dummy dies." Inactive elements 3 may include first and second inactive elements 31 and 32 disposed around first and second semiconductor elements 25 and 26. The structure of first inactive element 31 may be the same as or similar to that of second inactive element 32.

[0123] The first passive element 31 may have a first surface 311 (e.g., a top surface), a second surface 312 (e.g., a bottom surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a bottom surface) may be opposite the first surface 311 (e.g., a top surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., a top surface) and the second surface 312 (e.g., a bottom surface).

[0124] The first non-active element 31 may include a main portion 310 and at least one through-hole 315 (or through silicon via (TSV)) extending through the main portion 310. The main portion 310 may have a first surface 311 (e.g., a top surface), a second surface 312 (e.g., a bottom surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a bottom surface) may be opposite to the first surface 311 (e.g., a top surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., a top surface) and the second surface 312 (e.g., a bottom surface). Therefore, the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the first non-active element 31 may be the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the main portion 310, respectively.

[0125] The material of the main portion 310 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials. In some embodiments, the material of the main portion 250 of the first semiconductor element 25 may be the same as the material of the main portion 310 of the first inactive element 31.

[0126] The width W1 of the first semiconductor element 25 (or main portion 250 ) may be greater than the width W2 of the first passive element 31 (or main portion 310 ). The thickness T1 of the main portion 250 of the first semiconductor element 25 may be less than the thickness T2 of the main portion 310 of the first passive element 31 .

[0127] The semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) does not include a vertical conductive path in its main portion. That is, the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) may not have a vertical conductive path to the substrate 12. For example, the first semiconductor element 25 does not include a vertical conductive path in its main portion 250.

[0128] The through-hole 315 of the first non-active element 31 may have a first surface 3151 (e.g., a top surface) and a second surface 3152 (e.g., a bottom surface) opposite the first surface 3151 (e.g., the top surface). The first surface 3151 of the through-hole 315 of the first non-active element 31 may be substantially coplanar with the first surface 311 of the first non-active element 31 and exposed from the first surface 311 of the first non-active element 31. The second surface 3152 of the through-hole 315 of the first non-active element 31 may be substantially coplanar with the second surface 312 of the first non-active element 31 and exposed from the second surface 312 of the first non-active element 31. In other words, the through-hole 315 of the first non-active element 31 may extend from the first surface 311 of the main portion 310 to the second surface 312 of the main portion 310.

[0129] Thus, the through-holes 315 of the first non-active component 31 can provide a vertical conductive path extending through the main portion 310 of the first non-active component 31 and can be configured to transmit signals or power. Therefore, the redistribution structure 4 and the higher electronic components 18 can be electrically connected to the substrate 12 through the through-holes 315 of the first non-active component 31, rather than through the semiconductor components 20 (including, for example, the first semiconductor component 25 and the second semiconductor component 26). It is not necessary to form through-holes in the main portion (e.g., the main portion 250) of the semiconductor components 20 (e.g., the first semiconductor component 25 and the second semiconductor component 26).

[0130] In some embodiments, the non-active component 3 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active component 31 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 310. There are no horizontal conductive paths on either the first surface 311 or the second surface 312 of the main portion 310. The non-active component 3 includes only vertical conductive paths.

[0131] The encapsulant 27 can encapsulate the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) and the non-active element 3 (including, for example, the first non-active element 31 and the second non-active element 32). For example, the encapsulant 27 can be disposed in the space 281 between the first semiconductor element 25 and the first non-active element 31, the space 282 between the first semiconductor element 25 and the second semiconductor element 26, and the space 283 between the second semiconductor element 26 and the second non-active element 32. The material of the encapsulant 27 can include a molding compound with or without a filler.

[0132] The encapsulant 27 may have a first surface 271 (e.g., a top surface), a second surface 272 (e.g., a bottom surface), and a side surface 273. The second surface 272 (e.g., a bottom surface) may be opposite to the first surface 271 (e.g., a top surface). The side surface 273 may extend between the first surface 271 (e.g., a top surface) and the second surface 272 (e.g., a bottom surface).

[0133] The first surface 271 of the encapsulant 27 can be substantially coplanar or aligned with the first surface 311 of the first non-active component 31 and the first surface 251 of the first semiconductor component 25. Therefore, the first surface 21 of the molded structure 2 can include the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active component 31, and the first surface 251 of the first semiconductor component 25. Furthermore, the second surface 272 of the encapsulant 27 can be substantially coplanar or aligned with the second surface 312 of the first non-active component 31 and the second surface 252 of the first semiconductor component 25. Therefore, the second surface 22 of the molded structure 2 can include the second surface 272 of the encapsulant 27, the second surface 312 of the first non-active component 31, and the second surface 252 of the first semiconductor device 25.

[0134] The redistribution structure 4 can be disposed on the first surface 21 of the molded structure 2 and electrically connected thereto. For example, the redistribution structure 4 can be disposed on the first surface 271 of the encapsulant 27, the first surface 311 of the first inactive device 31, and the first surface 251 of the first semiconductor device 25, and electrically connected to the through-holes 315 of the first semiconductor device 25 and the first inactive device 31.

[0135] The redistribution structure 4 may be a fan-out structure. The redistribution structure 4 may have a first surface 41 (e.g., top surface), a second surface 42 (e.g., bottom surface), and side surfaces 43. The second surface 42 (e.g., bottom surface) may be opposite to the first surface 41 (e.g., top surface). The side surfaces 43 may extend between the first surface 41 (e.g., top surface) and the second surface 42 (e.g., bottom surface). The second surface 42 of the redistribution structure 4 may directly contact the first surface 21 of the molding structure 2.

[0136] The redistribution structure 4 may include a plurality of dielectric layers 44, a plurality of circuit layers 45, a plurality of inner through-holes 46, and a plurality of pads 47. The dielectric layer 44 may include a curable photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The materials of the dielectric layers 44 may be the same as each other. In some embodiments, the material of the topmost dielectric layer 441 may be different from the materials of the other dielectric layers 44. The topmost dielectric layer 441 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN and / or SiON. In some embodiments, the bottommost dielectric layer 442 may be omitted. The circuit layer 45 may be directly disposed on the first surface 21 of the mold structure 2.

[0137] The circuit layer 45 may be covered by the dielectric layer 44 or embedded in the dielectric layer 44. The circuit layer 45 may be a fan-out circuit layer. The inner through-hole 46 may be embedded in the dielectric layer 44 and may connect two adjacent circuit layers 45. The inner through-hole 46 may gradually taper toward the molded structure 2. The pad 47 may be electrically connected to the circuit layer 45 and embedded in the dielectric layer 44 (e.g., the topmost dielectric layer 441). The pad 47 may expose the first surface 41 of the self-weight distribution structure 4. Each pad 47 may be a hybrid bond (HB) pad and may include Cu or Al.

[0138] The higher electronic component 18 can be disposed on and electrically connected to the first surface 41 of the redistribution structure 4. The higher electronic component 18 can also be disposed on and electrically connected to the first surface 21 of the molding structure 2 (including, for example, the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active component 31, and the first surface 251 of the first semiconductor component 25).

[0139] The higher electronic components 18 may include semiconductor dies or chips, such as signal processing dies (e.g., digital signal processing (DSP) dies), logic dies (e.g., application processors (AP), system-on-a-chip (SoC), central processing units (CPU), graphics processing units (GPU), microcontrollers, etc.), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, front-end dies (e.g., analog front-end (AFE) dies), or other active components.

[0140] The upper electronic component 18 may have a first surface 181 (e.g., a top surface or backside surface), a second surface 182 (e.g., a bottom surface or active surface), and a side surface 183. The second surface 182 (e.g., the bottom surface) may be opposite the first surface 181 (e.g., the top surface). The side surface 183 may extend between the first surface 181 (e.g., the top surface) and the second surface 182 (e.g., the bottom surface).

[0141] The upper electronic component 18 may include a main portion 180 and an active circuit structure 184 disposed on a bottom surface 1801 of the main portion 180. The material of the main portion 180 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, Group III-V, or Group II-VI semiconductor materials.

[0142] Active circuit structure 184 may include multiple dielectric layers, multiple circuit layers, and multiple pads 185. The dielectric layers may cover the circuit layers. Pads 185 may be electrically connected to the circuit layers and embedded in the dielectric layers. Pads 185 may be exposed from second surface 182 of upper electronic component 18. Active circuit structure 184 may include a bottommost dielectric layer surrounding pads 185. The bottommost dielectric layer may include SiO2, SiCN, and / or SiON. Each pad 185 may be a hybrid bond (HB) pad and may include Cu or Al.

[0143] The upper electronic component 18 can be attached and electrically connected to the first surface 41 of the redistribution structure 4 by hybrid bonding. That is, the second surface 182 of the upper electronic component 18 can directly contact the first surface 41 of the redistribution structure 4. Therefore, the active circuit structure 184 of the upper electronic component 18 can be attached to, connected to, and can directly contact the topmost dielectric layer 441 of the redistribution structure 4. The pad 185 of the upper electronic component 18 can be attached to, connected to, and can directly contact the pad 47 of the redistribution structure 4.

[0144] The size and function of the taller electronic component 18 can differ from the size and function of the semiconductor components 20 (including, for example, the first semiconductor component 25 and the second semiconductor component 26). The width W3 of the taller electronic component 18 can be substantially equal to the width W4 of the mold structure 2 or the width W4 of the encapsulant 27. The side surface 183 of the taller electronic component 18 can be substantially aligned with the side surface 23 of the mold structure 2 or the side surface 273 of the encapsulant 27. The taller electronic component 18 can vertically overlap the inactive components 3 (including, for example, the first inactive component 31 and the second inactive component 32).

[0145] The bumps 14 may be disposed on the second surface 22 of the molded structure 2. For example, the bumps 14 may include a plurality of first bumps 141 and a plurality of second bumps 142. The first bumps 141 may be disposed on the second surface 3152 (e.g., the bottom surface) of the through-hole 315. Thus, the first bumps 141 may physically and electrically connect the through-hole 315 and the first surface 121 of the substrate 12. The second bumps 142 may be disposed on the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25). Thus, the second bumps 142 may connect the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25) and the first surface 121 of the substrate 12. The second bumps 142 may not have an electrical function and may be dummy pads.

[0146] In some embodiments, the first bumps 141 and the second bumps 142 can be formed simultaneously during the manufacturing process. In some embodiments, the first bumps 141 and / or the second bumps 142 can include a reflowable material configured to control the gap between the mold structure 2 and the substrate 12 to prevent the mold structure 2 from tilting relative to the substrate 12. Furthermore, the first gap g1 between two adjacent first bumps 141 can be smaller than the second gap g2 between two adjacent second bumps 142.

[0147] Figure 3 yes Figure 1 FIG2 is a top view of the molded structure 2 of the assembled structure 1. The first non-active element 31 may include multiple rows of through-holes 315, for example, two rows of through-holes 315. The pads 255 of the first semiconductor element 25 may be arranged in an array. The size and structure of the second semiconductor element 26 may be the same as the size and structure of the first semiconductor element 25. The size and structure of the second non-active element 32 may be the same as the size and structure of the first non-active element 31. The second non-active element 32 and the first non-active element 31 may be disposed on opposite sides of the second semiconductor element 26 and the first semiconductor element 25.

[0148] exist Figures 1 to 3In the illustrated embodiment, the passive components 3 (including, for example, the first passive component 31 and the second passive component 32) are configured to provide a vertical conductive path between the upper electronic component 18 and the substrate 12. The upper electronic component 18 is not electrically connected to the substrate 12 through the semiconductor components 20 (e.g., the first semiconductor component 25 and the second semiconductor component 26). There is no need to form a through-hole in the main portion (e.g., the main portion 250) of the semiconductor components 20 (e.g., the first semiconductor component 25 and the second semiconductor component 26). The vertical conductive path can be provided outside the semiconductor components 20 (e.g., the first semiconductor component 25 and the second semiconductor component 26). Therefore, design flexibility is increased and manufacturing costs are reduced.

[0149] Furthermore, the active surface of the semiconductor element 20 (e.g., the first surface 251 (or active surface) of the first semiconductor element 25) faces the active surface of the upper electronic element 18 (e.g., the first surface 181 of the upper electronic element 18). Therefore, the upper electronic element 18 can quickly read and / or write from the semiconductor element 20 (e.g., the first semiconductor element 25). Consequently, the performance of the package structure 10 can be improved.

[0150] Figure 4 According to some embodiments of the present disclosure, a top view of a molded structure 2a is shown. The molded structure 2a may be similar to Figure 3 The molded structure 2a has the following differences. The first non-active element 31 and the second non-active element 32 may include three rows of through-holes 315. The molded structure 2a may also include a third non-active element 33 and a fourth non-active element 34. The third non-active element 33 and the fourth non-active element 34 may be disposed on opposite sides of the second semiconductor element 26 and the first semiconductor element 25. The size and structure of the third non-active element 33 and the fourth non-active element 34 may be the same as or similar to the size and structure of the first non-active element 31 and the second non-active element 32. The first non-active element 31, the second non-active element 32, the third non-active element 33, and the fourth non-active element 34 may surround the second semiconductor element 26 and the first semiconductor element 25.

[0151] Figure 5 According to some embodiments of the present disclosure, a top view of a molded structure 2b is shown. The molded structure 2b may be similar to Figure 4The molded structure 2a is different from the molded structure 2a, as described below. From a top view, the dimensions of the first non-active element 31 can differ from the dimensions of the second non-active element 32b. For example, the length L1 of the first non-active element 31 can be greater than the length L2 of the second non-active element 32b. Furthermore, each of the third non-active element 33b and the fourth non-active element 34b can be L-shaped and can be positioned adjacent to the second semiconductor element 26 or around a corner of the second semiconductor element 26.

[0152] Figure 6 According to some embodiments of the present disclosure, a cross-sectional schematic diagram of an assembly structure 1a is shown. In addition to the structure of the package structure 10a, the assembly structure 1a may be similar to Figure 1 Assembly structure 1. In the package structure 10a, the second surface 182 of the higher electronic component 18 does not contact the first surface 41 of the redistribution structure 4. The second surface 182 of the higher electronic component 18 is spaced apart from the first surface 41 of the redistribution structure 4. The pad 185 of the higher electronic component 18 can be electrically connected to the pad 47 of the redistribution structure 4 through a plurality of solder materials 19. The solder material 19 can include a reflowable material such as AgSn. Therefore, the higher electronic component 18 is electrically connected to the redistribution structure 4 by solder bonding rather than hybrid bonding. The pad 185 of the higher electronic component 18 and the pad 47 of the redistribution structure 4 can be solder pads.

[0153] Figures 7 to 13 Various stages of a method for preparing an assembly structure 1 are shown according to some embodiments of the present disclosure.

[0154] Reference Figure 7 , at least one semiconductor element 20 and at least one non-active element 3 can be disposed side by side on a carrier 80. In some embodiments, the carrier 80 may include a release layer 82 on a surface thereof. The semiconductor element 20 and the non-active element 3 can be disposed on the release layer 82. In some embodiments, the singulated semiconductor elements 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26) and the singulated non-active elements 3 (e.g., the first non-active element 31 and the second non-active element 32) can be reconstructed or reconfigured on the release layer 82 of the carrier 80. In some embodiments, only known good dies, e.g., known good semiconductor elements 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26) and known good non-active elements 3 (e.g., the first non-active element 31 and the second non-active element 32) are used.

[0155] In some embodiments, the size and function of the first semiconductor element 25 may be the same as the size and function of the second semiconductor element 26. Both the first semiconductor element 25 and the second semiconductor element 26 may be memory dies.

[0156] The first semiconductor element 25 may have a first surface 251 (e.g., a top surface or active surface), a second surface 252 (e.g., a bottom surface or backside surface), and a side surface 253. The second surface 252 (e.g., a bottom surface) may be opposite the first surface 251 (e.g., a top surface). The side surface 253 may extend between the first surface 251 (e.g., a top surface) and the second surface 252 (e.g., a bottom surface).

[0157] The first semiconductor element 25 may include a main portion 250 and an active circuit structure 254 disposed on a top surface 2501 of the main portion 250. The active circuit structure 254 may include a plurality of dielectric layers, a plurality of circuit layers, and a plurality of pads 255. The dielectric layers may cover the circuit layers. The pads 255 may be electrically connected to the circuit layers and embedded in the dielectric layers. The pads 255 may be exposed from the first surface 251 of the first semiconductor element 25. The active circuit structure 254 and the pads 255 may face upward. The second surface 252 (e.g., bottom surface) of the first semiconductor element 25 may contact the release layer 82 of the carrier 80.

[0158] The passive element 3 may include a first passive element 31 and a second passive element 32 disposed around the first semiconductor element 25 and the second semiconductor element 26. The structure of the first passive element 31 may be the same as or similar to that of the second passive element 32.

[0159] The first passive element 31 may have a first surface 311 (e.g., a top surface), a second surface 312 (e.g., a bottom surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a bottom surface) may be opposite the first surface 311 (e.g., a top surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., a top surface) and the second surface 312 (e.g., a bottom surface).

[0160] A space 281 may be formed between the first semiconductor element 25 and the first inactive element 31 . A space 282 may be formed between the first semiconductor element 25 and the second semiconductor element 26 . A space 283 may be formed between the second semiconductor element 26 and the second inactive element 32 .

[0161] The first non-active element 31 may include a main portion 310 and at least one through-hole 315 (or through-silicon via (TSV)) extending through the main portion 310. The main portion 310 may have a first surface 311 (e.g., a top surface), a second surface 312 (e.g., a bottom surface), and two side surfaces 313 and 314. The second surface 312 (e.g., a bottom surface) may be opposite to the first surface 311 (e.g., a top surface). The side surfaces 313 and 314 may extend between the first surface 311 (e.g., a top surface) and the second surface 312 (e.g., a bottom surface). Therefore, the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the first non-active element 31 may be the first surface 311, the second surface 312, and the side surfaces 313 and 314 of the main portion 310, respectively.

[0162] In some embodiments, the material of the main portion 250 of the first semiconductor element 25 may be the same as the material of the main portion 310 of the first inactive element 31 .

[0163] The width W1 of the first semiconductor element 25 (or main portion 250 ) may be greater than the width W2 of the first passive element 31 (or main portion 310 ). The thickness T1 of the main portion 250 of the first semiconductor element 25 may be less than the thickness T2 of the main portion 310 of the first passive element 31 .

[0164] The semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) does not include a vertical conductive path in its main portion. For example, the first semiconductor element 25 does not include a vertical conductive path in its main portion 250.

[0165] The through-hole 315 of the first non-active element 31 may have a first surface 3151 (e.g., a top surface) and a second surface 3152 (e.g., a bottom surface) opposite the first surface 3151 (e.g., the top surface). The first surface 3151 of the through-hole 315 of the first non-active element 31 may be substantially coplanar with the first surface 311 of the first non-active element 31 and exposed from the first surface 311 of the first non-active element 31. The second surface 3152 of the through-hole 315 of the first non-active element 31 may be substantially coplanar with the second surface 312 of the first non-active element 31 and exposed from the second surface 312 of the first non-active element 31. In other words, the through-hole 315 of the first non-active element 31 may extend from the first surface 311 of the main portion 310 to the second surface 312 of the main portion 310.

[0166] In some embodiments, the non-active component 3 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active component 31 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 310. Neither the first surface 311 nor the second surface 312 of the main portion 310 have horizontal conductive paths. The non-active component 3 includes only vertical conductive paths. The second surface 312 of the non-active component 3 can contact the release layer 82 of the carrier 80.

[0167] Reference Figure 8 A packaging adhesive 27 may be formed on the release layer 82 of the carrier 80 to encapsulate the semiconductor elements 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26) and the inactive elements 3 (for example, the first inactive element 31 and the second inactive element 32). The packaging adhesive 27 may be disposed in the spaces 281, 282, and 283.

[0168] Then, a grinding process may be performed to form a molded structure 2 on the carrier 80. The molded structure 2 may include a semiconductor device 20, a non-active device 3, and a packaging compound 27. The molded structure 2 may have a first surface 21 (e.g., a top surface) and a second surface 22 (e.g., a bottom surface) opposite to the first surface 21 (e.g., the top surface).

[0169] The encapsulant 27 may have a first surface 271 (e.g., a top surface) and a second surface 272 (e.g., a bottom surface) opposite the first surface 271 (e.g., the top surface). The first surface 271 of the encapsulant 27 may be substantially coplanar with, or aligned with, the first surface 311 of the first non-active component 31 and the first surface 251 of the first semiconductor component 25. Thus, the first surface 21 of the molded structure 2 may include the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active component 31, and the first surface 251 of the first semiconductor component 25. Furthermore, the second surface 272 of the encapsulant 27 may be substantially coplanar with, or aligned with, the second surface 312 of the first non-active component 31 and the second surface 252 of the first semiconductor component 25. Thus, the second surface 22 of the molded structure 2 may include the second surface 272 of the encapsulant 27, the second surface 312 of the first non-active component 31, and the second surface 252 of the first semiconductor device 25.

[0170] Reference Figure 9A redistribution structure 4 may be formed or disposed on the first surface 21 of the molded structure 2. For example, the redistribution structure 4 may be formed or disposed on the first surface 271 of the encapsulant 27, the first surface 311 of the first inactive device 31, and the first surface 251 of the first semiconductor device 25. The redistribution structure 4 may be electrically connected to the through-holes 315 of the semiconductor devices 20 (e.g., the first and second semiconductor devices 25, 26) and the first inactive devices 31 (e.g., the first and second inactive devices 31, 32).

[0171] The redistribution structure 4 may be a fan-out structure. The redistribution structure 4 may have a first surface 41 (e.g., a top surface) and a second surface 42 (e.g., a bottom surface) opposite the first surface 41 (e.g., the top surface). The second surface 42 of the redistribution structure 4 may directly contact the first surface 21 of the molding structure 2.

[0172] The redistribution structure 4 may include a plurality of dielectric layers 44, a plurality of circuit layers 45, a plurality of inner through-vias 46, and a plurality of pads 47. The dielectric layers 44 may be made of the same material. In some embodiments, the material of the topmost dielectric layer 441 may be different from the materials of the other dielectric layers 44. The topmost dielectric layer 441 may be a hybrid bond (HB) dielectric layer. In some embodiments, the bottommost dielectric layer 442 may be omitted. The circuit layer 45 may be directly disposed on the first surface 21 of the mold structure 2.

[0173] The circuit layer 45 may be covered by the dielectric layer 44 or embedded in the dielectric layer 44. The circuit layer 45 may be a fan-out circuit layer. The inner through-hole 46 may be embedded in the dielectric layer 44 and may connect two adjacent circuit layers 45. The inner through-hole 46 may gradually taper toward the molded structure 2. The pad 47 may be electrically connected to the circuit layer 45 and embedded in the dielectric layer 44 (e.g., the topmost dielectric layer 441). The pad 47 may expose the first surface 41 of the self-weight distribution structure 4. Each pad 47 may be a hybrid bond (HB) pad.

[0174] Reference Figure 10 The upper electronic component 18 can be disposed on the first surface 41 of the redistribution structure 4 and electrically connected thereto. The upper electronic component 18 can be a wafer type, a panel type, or a chip type. The upper electronic component 18 can have a first surface 181 (e.g., a top surface or backside surface) and a second surface 182 (e.g., a bottom surface or active surface) opposite the first surface 181 (e.g., the top surface).

[0175] The upper electronic component 18 may include a main portion 180 and an active circuit structure 184 disposed on a bottom surface 1801 of the main portion 180. The active circuit structure 184 may include multiple dielectric layers, multiple circuit layers, and multiple pads 185. The dielectric layers may cover the circuit layers. The pads 185 may be electrically connected to the circuit layers and embedded in the dielectric layers. The pads 185 may be exposed from the second surface 182 of the upper electronic component 18. The active circuit structure 184 may include a bottommost dielectric layer surrounding the pads 185. The bottommost dielectric layer may be a hybrid bond (HB) dielectric layer. Each pad 185 may be a hybrid bond (HB) pad.

[0176] The upper electronic component 18 can be attached and electrically connected to the first surface 41 of the redistribution structure 4 by hybrid bonding. That is, the second surface 182 of the upper electronic component 18 can directly contact the first surface 41 of the redistribution structure 4. Therefore, the active circuit structure 184 of the upper electronic component 18 can be attached to, connected to, and can directly contact the topmost dielectric layer 441 of the redistribution structure 4. The pad 185 of the upper electronic component 18 can be attached to, connected to, and can directly contact the pad 47 of the redistribution structure 4.

[0177] Reference Figure 11 , the release layer 82 and the carrier 80 can be removed from the mold structure 2 .

[0178] Reference Figure 12 A plurality of bumps 14 may be formed or disposed on the second surface 22 of the mold structure 2. For example, the bumps 14 may include a plurality of first bumps 141 and a plurality of second bumps 142. The first bumps 141 may be disposed on the second surface 3152 (e.g., the bottom surface) of the through-hole 315. The second bumps 142 may be disposed on the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25).

[0179] In some embodiments, the first bumps 141 and the second bumps 142 can be formed simultaneously in the same stage. In some embodiments, the first bumps 141 and / or the second bumps 142 can include a reflowable material. Furthermore, the first gap g1 between two adjacent first bumps 141 can be smaller than the second gap g2 between two adjacent second bumps 142. Alternatively, the first gap g1 can be equal to the second gap g2.

[0180] Reference Figure 13The encapsulant 27, the redistribution structure 4, and the taller electronic component 18 can be cut to form the package structure 10. Therefore, the side surface 183 of the taller electronic component 18 can be substantially aligned with the side surface 23 of the molding structure 2 (or the side surface 273 of the encapsulant 27) and the side surface 43 of the redistribution structure 4. The width W3 of the taller electronic component 18 can be substantially equal to the width W4 of the molding structure 2 or the width W4 of the encapsulant 27.

[0181] Then, the bumps 14 (eg, first and second bumps 141 and 142) may be attached to the substrate 12. Thus, the package structure 10 may be attached to the substrate 12 via the bumps 14 (eg, first and second bumps 141 and 142).

[0182] Then, a plurality of external connectors 16 may be formed or disposed on the second surface 122 of the substrate 12 to provide electrical connections, such as I / O connections, to the substrate 12. Figure 1 Assembly structure 1.

[0183] Figure 14 A flow chart showing a method 900 for preparing an assembly structure 1 according to some embodiments of the present disclosure is shown.

[0184] In some embodiments, the method 900 may include step S901 of disposing at least one semiconductor element and at least one passive element on a carrier, wherein the at least one passive element includes a main portion and at least one through-hole extending through the main portion. Figure 7 As shown, at least one semiconductor element 20 (e.g., a first semiconductor element 25 and a second semiconductor element 26) and at least one passive element 3 (e.g., a first passive element 31 and a second passive element 32) may be disposed on a carrier 80. The first passive element 31 may include a main portion 310 and at least one through-hole 315 extending through the main portion 310.

[0185] In some embodiments, the method 900 may include step S902 of forming an encapsulant on a carrier to encapsulate at least one semiconductor device and at least one inactive device. Figure 8 As shown, a packaging glue 27 may be formed on the carrier 80 to encapsulate at least one semiconductor element 20 (eg, the first semiconductor element 25 and the second semiconductor element 26 ) and at least one passive element 3 (eg, the first passive element 31 and the second passive element 32 ).

[0186] In some embodiments, the method 900 may include step S903 of forming a redistribution structure on the first surface of the encapsulant, the first surface of the at least one inactive component, and the first surface of the at least one semiconductor component, wherein the redistribution structure is electrically connected to at least one through-hole of the at least one semiconductor component and the at least one inactive component. Figure 9 As shown, a redistribution structure 4 can be formed on the first surface 271 of the encapsulant 27, the first surface 311 of the at least one first inactive device 31, and the first surface 251 of the at least one semiconductor device 25. The redistribution structure 4 can be electrically connected to the at least one first semiconductor device 25 and the at least one through-hole 315 of the at least one first inactive device 31.

[0187] In some embodiments, the method 900 may include step S904, disposing a higher electronic component on the redistribution structure. Figure 10 As shown, a taller electronic component 18 may be disposed on the redistribution structure 4 .

[0188] In some embodiments, the method 900 may include step S905, removing the carrier. Figure 11 As shown, the carrier 80 may be removed.

[0189] One aspect of the present disclosure provides an electronic component comprising a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip and electrically connected to the first semiconductor chip via hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip and electrically connected to the second semiconductor chip via a plurality of bumps.

[0190] Another aspect of the present disclosure provides an electronic component comprising a first component and a second component. The first component comprises a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip via hybrid bonding. The second component comprises a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip via hybrid bonding. The second component is electrically connected to the first component via a plurality of bumps.

[0191] Yet another aspect of the present disclosure provides a manufacturing method. The manufacturing method includes providing a first component comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip via hybrid bonding; providing a second component comprising a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip via hybrid bonding; and electrically connecting the second component to the first component via a plurality of bumps.

[0192] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other process combinations.

[0193] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will appreciate from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of the present invention.

Claims

1. A packaging structure, comprising: at least one semiconductor element; at least one inactive element disposed around the at least one semiconductor element and comprising a main portion and at least one through-hole extending through the main portion; and A packaging adhesive encapsulates the at least one semiconductor component and the at least one non-active component, wherein a first surface of the packaging adhesive is substantially coplanar with a first surface of the at least one non-active component and a first surface of the at least one semiconductor component, and a second surface of the packaging adhesive is substantially coplanar with a second surface of the at least one non-active component and a second surface of the at least one semiconductor component. 2 . The package structure as claimed in claim 1 , wherein a width of the at least one semiconductor device is greater than a width of the at least one inactive device.

3. The package structure as claimed in claim 1 , wherein the at least one semiconductor element comprises a main portion and an active circuit structure disposed on the main portion, wherein a thickness of the main portion of the at least one semiconductor element is smaller than a thickness of the main portion of the at least one inactive element. 4 . The package structure as claimed in claim 3 , wherein a material of the main portion of the at least one semiconductor device is the same as a material of the main portion of the at least one inactive device. 5 . The package structure as claimed in claim 3 , wherein the active circuit structure comprises at least one pad exposed from the first surface of the at least one semiconductor device. 6 . The package structure of claim 3 , wherein the at least one semiconductor element does not include a vertical conductive path in the main portion of the at least one semiconductor element. 7 . The package structure of claim 1 , wherein the at least one passive component does not include a horizontal conductive path on the main portion of the at least one passive component.

8. The package structure as claimed in claim 1, wherein a first surface of the at least one through-hole of the at least one non-active component is exposed from the first surface of the at least one non-active component, and a second surface of the at least one through-hole of the at least one non-active component is exposed from the second surface of the at least one non-active component. 9 . The package structure as claimed in claim 1 , wherein the at least one semiconductor element comprises a first semiconductor element and a second semiconductor element disposed side by side.

10. The package structure as claimed in claim 9, wherein the packaging glue is disposed in a space between the first semiconductor element and a first non-active element among the at least one non-active element, a space between the first semiconductor element and the second semiconductor element, and a space between the second semiconductor element and a second non-active element among the at least one non-active element.

11. The package structure according to claim 1 , further comprising: A redistribution structure is disposed on the first surface of the packaging adhesive, the first surface of the at least one inactive component, and the first surface of the at least one semiconductor component, and is electrically connected to the at least one semiconductor component and the at least one through-hole of the at least one inactive component.

12. The package structure according to claim 1, further comprising: A higher electronic component is disposed on the first surface of the packaging glue, the first surface of the at least one inactive component, and the first surface of the at least one semiconductor component, and is electrically connected to the at least one semiconductor component and the at least one through-hole of the at least one inactive component. 13 . The package structure as claimed in claim 12 , wherein a side surface of the taller electronic component is substantially aligned with a side surface of the packaging adhesive.

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