Delay compensation segmented driving system of GaN sealing module

Abstract

The invention discloses a delay compensation segmented driving system of a GaN sealing module, which comprises a segmented driving controller, and the segmented driving controller is connected with a dV / dt detection unit, a high-speed driving module and a protection logic unit. The dV / dt detection unit is connected with a phase detection unit, the phase detection unit is connected with a voltage / current / temperature detection module and a delay compensation controller, efficient and accurate control over the GaN power device is achieved, and the GaN power device can be effectively and accurately controlled by monitoring the switching state in real time, dynamically adjusting the driving current and integrating multiple protection mechanisms. The problems that in a traditional driving circuit, time delay is too long (larger than 50 ns), reverse recovery loss is large (Qrr is larger than 100 nC), and switching waveform distortion exists are solved. According to the system, a sectional driving strategy is adopted, optimization is carried out in the turn-on stage and the turn-off stage respectively, meanwhile, a dynamic feedback delay compensation mechanism is introduced, and the performance of a GaN power device in the high-frequency hard switch topology is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of GaN sealing technology, and in particular to a delay compensation segmented driving system for a GaN sealing module. Background Art

[0002] With the development of third-generation semiconductor devices, gallium nitride (GaN) power devices, due to their advantages such as high breakdown voltage, high electron mobility, and low gate charge, are widely used in high-frequency, high-efficiency power electronics systems such as fast-charging power supplies, server power supplies, and automotive electric drives. Especially in applications requiring high voltage, high frequency, and high efficiency, GaN devices are gradually replacing traditional silicon-based MOSFETs and becoming the mainstream choice.

[0003] However, the high-speed characteristics of GaN devices, while bringing performance improvements, also bring new technical challenges, including:

[0004] High drive timing requirements: The turn-on and turn-off time of GaN devices are extremely short, and the dV / dt and di / dt during the switching process are very high, which places extremely high requirements on the timing accuracy of the drive circuit. Any delay may cause waveform distortion or misconduction.

[0005] Serious reverse recovery problem: Traditional MOSFETs have the problem of body diode reverse recovery loss. Although GaN HEMT is a "no reverse recovery" device, the actual driving process is still affected by switching noise and parasitic parameters.

[0006] The problem of mis-turn-on is prominent: GaN devices are prone to mis-turn-on under high dV / dt due to their small gate capacitance and narrow gate drive voltage range. This must be suppressed by negative voltage shutdown, RC absorption, and other methods.

[0007] Insufficient feedback and protection mechanisms: Existing drive circuits usually only have simple overcurrent or overtemperature protection, lack precise switch state detection and dynamic feedback control, and are unable to meet the dynamic performance and reliability requirements of high-speed hard-switching topologies.

[0008] Imperfect segmented drive strategy: Most traditional drive methods use fixed drive strength, which makes it difficult to optimize and adjust the start-up and shutdown stages separately, making it impossible to achieve a good balance between efficiency and reliability.

[0009] Therefore, there is an urgent need for a high-performance, highly integrated drive system that combines a segmented drive strategy, a real-time feedback delay compensation mechanism, and comprehensive protection features to achieve precise control of GaN devices under different operating conditions. This is particularly true in high-frequency hard-switching applications such as LLC, PFC, and full-bridge topologies, where high dV / dt control capability, fast response, and low latency are essential to ensure system stability and safety.

[0010] Therefore, a delay compensation segmented driving system for GaN packaged modules is proposed. Summary of the Invention

[0011] The object of the present invention is to provide a delay compensation segmented driving system for a GaN packaged module to solve the problems raised in the above background technology.

[0012] To achieve the above objectives, the present invention provides the following technical solutions: a delay compensation segmented drive system for a GaN packaged module, comprising a segmented drive controller, to which a dV / dt detection unit, a high-speed drive module, and a protection logic unit are connected;

[0013] The dV / dt detection unit is connected to a phase detection unit, the phase detection unit is connected to a voltage / current / temperature detection module and a delay compensation controller, the delay compensation controller is connected to a high-speed drive module, and the voltage / current / temperature detection module is connected to a protection logic unit;

[0014] The high-speed driving module is connected to a GaN HEMT module, a negative voltage generating unit and a power management unit, and the GaN HEMT module is connected to a gate absorption network unit.

[0015] Preferably: the segmented drive controller includes a PWM_IN pin, a dV / dt_FB pin, a FAULT pin, a DRIVE_H pin, a DRIVE_L pin and an EN pin;

[0016] The PWM_IN pin is connected to a PWM_IN unit, the dV / dt_FB pin is connected to a dV / dt detection unit, the FAULT pin is connected to a protection logic unit, and the DRIVE_H pin and the DRIVE_L pin are connected to a high-speed drive module.

[0017] Preferably: the high-speed drive module includes a high-side drive unit and a low-side drive unit; the high-side drive unit and the low-side drive unit both include an IN pin, a COMP pin, an OUT+ pin and an OUT- pin; the IN pins of the high-side drive unit and the low-side drive unit are respectively connected to the DRIVE_H pin and the DRIVE_L pin of the segmented drive controller, and the OUT- pin is respectively connected to the negative pressure generation unit and the power management unit.

[0018] Preferably, the GaN HEMT module includes a GaN HEMT high-side unit and a GaN HEMT low-side unit; the GaN HEMT high-side unit and the GaN HEMT low-side unit both include a G+ pin and a G- pin, and the G+ pin and G- pin of the GaN HEMT high-side unit and the GaN HEMT low-side unit are respectively connected to the OUT+ pin and OUT- pin of the high-side drive unit and the low-side drive unit.

[0019] Preferably, the gate absorption network unit includes an RC absorption high side, an RC absorption low side and two embedded magnetic beads FB; the two embedded magnetic beads FB are respectively connected to the G-pins of the GaN HEMT high side unit and the GaN HEMT low side unit.

[0020] Preferably, the delay compensation controller includes a dV / dt pin, an I_FB pin, a COMP_H pin and a COMP_L pin; the COMP_H pin and the COMP_L pin are connected to the COMP pins of the high-side drive unit and the low-side drive unit respectively.

[0021] Preferably, the phase detection unit includes a dV / dt pin, a COMP pin and an I_FB pin; the COMP pin is connected to the dV / dt pin of the delay compensation controller, and the dV / dt pin is connected to the dV / dt detection unit.

[0022] Preferably, the protection logic unit includes an I_FB pin, a TEMP pin and a FAULT pin; the FAULT pin is connected to the FAULT pin of the segmented drive controller.

[0023] Preferably: the voltage / current / temperature detection module includes a voltage / current detection unit and a temperature detection unit; the temperature detection unit and the voltage / current detection unit are connected to the protection logic unit, and the voltage / current detection unit is also connected to the I_FB pin of the phase detection unit.

[0024] Compared with existing technologies, this invention achieves efficient and precise control of GaN power devices. By real-time monitoring of switching states, dynamic adjustment of drive current, and integrated multiple protection mechanisms, it addresses issues such as long delay (>50ns), large reverse recovery loss (Qrr>100nC), and switching waveform distortion found in traditional drive circuits. The system employs a segmented drive strategy, optimizing both the turn-on and turn-off phases separately, while also incorporating a dynamic feedback delay compensation mechanism. This significantly improves the performance of GaN power devices in high-frequency hard-switching topologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a system block diagram of the present invention. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] See also Figure 1 The present invention provides a technical solution: a delay compensation segmented drive system for a GaN packaged module, comprising a segmented drive controller, the segmented drive controller being connected to a dV / dt detection unit, a high-speed drive module, and a protection logic unit;

[0028] The dV / dt detection unit is connected to the phase detection unit, the phase detection unit is connected to the voltage / current / temperature detection module and the delay compensation controller, the delay compensation controller is connected to the high-speed drive module, and the voltage / current / temperature detection module is connected to the protection logic unit;

[0029] The high-speed driving module is connected to a GaN HEMT module, a negative voltage generating unit and a power management unit, and the GaN HEMT module is connected to a gate absorption network unit.

[0030] Key parameters: Turn-on phase: >2A, 30-100V / ns; Turn-off phase: -3V to -5V negative voltage; Overcurrent protection: >40A, shutdown within 60ns; Temperature protection: disabled at >150°C; Dynamic response time: <100ns, real-time monitoring of dV / dt; Parasitic inductance: <0.1nH; Gate absorption: R=10Ω, C=100pF.

[0031] Logical description of core functional modules:

[0032] 1. Segmented drive controller: The segmented drive controller includes the PWM_IN pin, dV / dt_FB pin, FAULT pin, DRIVE_H pin, DRIVE_L pin, and EN pin. The PWM_IN pin is connected to the PWM_IN unit, the dV / dt_FB pin is connected to the dV / dt detection unit, the FAULT pin is connected to the protection logic unit, and the DRIVE_H pin and DRIVE_L pin are connected to the high-speed drive module.

[0033] Functional logic: Receives the input signal of the PWM_IN unit and generates drive signals optimized for the turn-on and turn-off phases based on the dV / dt feedback and current feedback information.

[0034] Implement a segmented control strategy: provide high current drive in the start-up phase, introduce negative voltage suppression in the shutdown phase, respond to FAULT signals, quickly shut down the drive in abnormal conditions to protect GaN devices, and output DRIVE_H and DRIVE_L signals to control the high-side and low-side drive units respectively.

[0035] Working Principle: The controller integrates internal timing control logic. The rising edge of the PWM input triggers the turn-on phase, providing a high-current drive signal greater than 2A. The falling edge triggers the turn-off phase, activating the negative voltage drive path. Simultaneously, the controller continuously monitors the dV / dt feedback signal and dynamically adjusts the drive strength when it detects a change in the switch state, achieving precise on-off timing control.

[0036] 2. dV / dt detection unit: Functional logic: Real-time monitoring of the voltage change rate (dV / dt) of the GaN switch node, converting the voltage change into a quantifiable current signal through an RC differential circuit, and outputting the dV / dt information to the segmented drive controller and phase detection unit.

[0037] Working Principle: The dV / dt detection unit uses a high-speed RC differential circuit to differentiate the switch node voltage via a capacitor, and a resistor to convert the differential current into a voltage signal. When the switch node voltage changes rapidly (e.g., 30-100V / ns), an output signal proportional to the rate of change is generated. This signal is fed into the controller for real-time adjustment of drive strength and timing.

[0038] 3. High-speed drive module: The high-speed drive module includes a high-side drive unit and a low-side drive unit; both the high-side drive unit and the low-side drive unit include an IN pin, a COMP pin, an OUT+ pin, and an OUT- pin; the IN pins of the high-side drive unit and the low-side drive unit are respectively connected to the DRIVE_H pin and the DRIVE_L pin of the segmented drive controller, and the OUT- pin is respectively connected to the negative voltage generation unit and the power management unit.

[0039] Functional logic: Receives the drive signal from the segmented drive controller and the compensation signal from the delay compensation controller, provides a high current drive capability of >2A, and achieves a gate charging rate of 30-100V / ns.

[0040] Working Principle: The high-speed driver module utilizes a push-pull output stage, capable of delivering drive currents exceeding 2A, enabling rapid charging and discharging of the GaN device gate. During the turn-on phase, the driver module provides high-current forward drive, achieving a slew rate of 30-100V / ns. During the turn-off phase, the driver module collaborates with the negative voltage generation unit to provide a negative voltage drive of -3V to -5V, effectively preventing false turn-on.

[0041] 4. GaN HEMT module: The GaN HEMT module consists of a GaN HEMT high-side unit and a GaN HEMT low-side unit. Both the GaN HEMT high-side unit and the GaN HEMT low-side unit include G+ and G- pins, which are connected to the OUT+ and OUT- pins of the high-side driver unit and the low-side driver unit, respectively. The GaN HEMT high-side unit and the GaN HEMT low-side unit use vertical CNT interconnects, with a parasitic inductance of less than 0.1nH.

[0042] 5. Gate Snubber Network: The gate snubber network consists of a high-side RC snubber, a low-side RC snubber, and two embedded ferrite beads (FB). The two embedded ferrite beads (FB) are connected to the G- pins of the GaN HEMT high-side and low-side cells, respectively. The embedded ferrite beads (FB) and the high-side and low-side RC snubbers suppress ringing.

[0043] 6. Delay compensation controller: The delay compensation controller includes a dV / dt pin, an I_FB pin, a COMP_H pin, and a COMP_L pin; the COMP_H pin and the COMP_L pin are connected to the COMP pins of the high-side drive unit and the low-side drive unit, respectively.

[0044] Functional logic: Receives the compensation signal from the phase detection unit and generates compensation control signals for high-side and low-side drive, achieving a dynamic response time of <100ns.

[0045] Working Principle: The delay compensation controller dynamically calculates the required compensation based on the delay information provided by the phase detection unit and generates COMP_H and COMP_L signals to control the drive strength of the high-side and low-side driver units, respectively. When the controller detects an increase in switching delay, it increases the drive strength; when it detects a decrease in delay, it reduces the drive strength, thus achieving closed-loop control and maintaining optimal switching performance.

[0046] 7. Phase detection unit: The phase detection unit includes a dV / dt pin, a COMP pin, and an I_FB pin; the COMP pin is connected to the dV / dt pin of the delay compensation controller, and the dV / dt pin is connected to the dV / dt detection unit.

[0047] Functional logic: Analyzes the phase relationship between the dV / dt signal and the current feedback signal, calculates the actual switching delay, generates a compensation control signal, and outputs the phase information to the delay compensation controller.

[0048] Working Principle: The phase detection unit receives the dV / dt signal and the current feedback signal. Using a high-speed comparator and phase detector, it analyzes the time difference between the two signals to calculate the actual switching delay. If the delay deviates from the ideal value, a corresponding compensation signal is generated. The delay compensation controller dynamically adjusts the drive strength to keep the delay within 100ns.

[0049] 8. Protection logic unit: The protection logic unit includes the I_FB pin, TEMP pin and FAULT pin; the FAULT pin is connected to the FAULT pin of the segmented drive controller.

[0050] Functional logic: Integrates overcurrent protection and overtemperature protection functions, receives current feedback and temperature feedback signals, and generates FAULT signals in abnormal states.

[0051] Working Principle: The protection logic unit continuously monitors current and temperature feedback signals. When it detects a current exceeding 40A or a junction temperature exceeding 150°C, it immediately generates a FAULT signal, triggering the protection mechanism of the segmented drive controller. The overcurrent protection response time is less than 60ns, ensuring rapid shutdown of the GaN device in the event of a short circuit or overload, preventing damage.

[0052] 9. Voltage / current / temperature detection module: The voltage / current / temperature detection module includes a voltage / current detection unit and a temperature detection unit; the temperature detection unit and the voltage / current detection unit are connected to the protection logic unit, and the voltage / current detection unit is also connected to the I_FB pin of the phase detection unit.

[0053] Temperature detection unit functional logic: monitors the junction temperature of the GaN device, converts the temperature information into a voltage signal through an NTC thermistor, and outputs a temperature feedback signal to the protection logic unit.

[0054] Working Principle: The temperature detection unit uses an NTC thermistor, whose resistance decreases as temperature increases. By measuring the voltage drop across the NTC resistor, the junction temperature of the GaN device can be calculated. When the junction temperature exceeds 150°C, the temperature detection unit outputs a high-level signal, triggering the overtemperature protection mechanism of the protection logic unit, disabling the driver to prevent device overheating and damage.

[0055] Current detection unit functional logic: monitors the current state of the GaN device, provides overcurrent protection, converts current information into a voltage signal through the shunt resistor RSENSE, and outputs a current feedback signal to the segmented drive controller and protection logic unit.

[0056] Working Principle: The current sensing unit uses a high-precision shunt resistor, RSENSE. When current flows through the shunt resistor, a voltage drop proportional to the current is generated. This voltage signal is amplified and compared before being output to the controller. If the detected current exceeds 40A, the overcurrent protection mechanism is triggered within 60ns, rapidly shutting down the driver to protect the GaN device.

[0057] 10. Negative voltage generation unit: Functional logic: Generates -3V to -5V negative voltage power supply, provides negative voltage shutdown capability for high-speed drive modules, and suppresses the mis-conduction phenomenon of GaN devices.

[0058] Working Principle: The negative voltage generation unit uses a charge pump structure to convert the positive power supply VCC into a negative voltage of -3V to -5V. During the GaN device's turn-off phase, a negative voltage is applied to the gate, reducing the gate-source voltage to a negative value. This effectively increases noise margin and prevents false turn-on under high dV / dt conditions.

[0059] Turn-on phase control logic: The rising edge of the PWM input signal triggers the turn-on phase control. The segmented drive controller generates a high-current drive signal. The high-speed drive module provides a drive current greater than 2A. The dV / dt detection unit monitors the switch node voltage change. The phase detection unit analyzes the actual switching delay. The delay compensation controller dynamically adjusts the drive strength. The GaN device is quickly turned on to achieve a slew rate of 30-100V / ns.

[0060] Turn-off stage control logic: The falling edge of the PWM input signal triggers the turn-off stage control. The segmented drive controller activates the negative voltage drive path. The negative voltage generation unit provides a negative voltage of -3V to -5V. The high-speed drive module applies the negative voltage to the gate of the GaN device. The dV / dt detection unit monitors the voltage change of the switch node. The phase detection unit analyzes the actual turn-off delay. The delay compensation controller dynamically adjusts the turn-off strength. The GaN device is quickly turned off, effectively suppressing the mis-turn-on phenomenon.

[0061] Protection mechanism control logic: The voltage / current detection unit and temperature detection unit continuously monitor the status of the GaN device. When the current is detected to be greater than 40A or the junction temperature is greater than 150°C, the protection logic unit generates a FAULT signal. The segmented drive controller receives the FAULT signal and immediately shuts down the drive. The high-speed drive module applies negative voltage to the gate of the GaN device to ensure rapid shutdown. The protection mechanism response time is <60ns, effectively preventing device damage.

[0062] Performance advantages and technical features

[0063] High-speed switching performance: Achieve slew rates of 30-100V / ns, significantly reducing switching losses.

[0064] Precise delay control: Dynamic feedback compensation mechanism controls the delay within 100ns.

[0065] Effectively suppress mis-turn-on: Negative voltage shutdown technology effectively prevents mis-turn-on under high dV / dt conditions.

[0066] Fast protection response: Overcurrent protection response time is <60ns, ensuring device safety.

[0067] Perfect temperature management: automatically disable the driver when the junction temperature is greater than 150℃ to prevent overheating damage.

[0068] Highly integrated design: Integrates drive, detection, protection and compensation functions to simplify system design.

[0069] Through the collaborative work of the above functional modules, the segmented drive circuit detection and control system achieves efficient and precise control of GaN power devices, significantly improving the performance and reliability of high-frequency hard-switching topologies.

[0070] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A delay compensation segmented drive system for a GaN packaged module, including a segmented drive controller, is characterized by: The segmented drive controller is connected to a dV / dt detection unit, a high-speed drive module and a protection logic unit; The dV / dt detection unit is connected to a phase detection unit, the phase detection unit is connected to a voltage / current / temperature detection module and a delay compensation controller, the delay compensation controller is connected to a high-speed drive module, and the voltage / current / temperature detection module is connected to a protection logic unit; The high-speed driving module is connected to a GaN HEMT module, a negative voltage generating unit and a power management unit, and the GaN HEMT module is connected to a gate absorption network unit.

2. The delay compensation segmented driving system for the GaN packaged module according to claim 1, characterized in that: The segmented drive controller includes a PWM_IN pin, a dV / dt_FB pin, a FAULT pin, a DRIVE_H pin, a DRIVE_L pin and an EN pin; The PWM_IN pin is connected to a PWM_IN unit, the dV / dt_FB pin is connected to a dV / dt detection unit, the FAULT pin is connected to a protection logic unit, and the DRIVE_H pin and the DRIVE_L pin are connected to a high-speed drive module.

3. The delay compensation segmented driving system for the GaN packaged module according to claim 2, characterized in that: The high-speed driving module includes a high-side driving unit and a low-side driving unit; The high-side drive unit and the low-side drive unit each include an IN pin, a COMP pin, an OUT+ pin, and an OUT- pin; The IN pins of the high-side drive unit and the low-side drive unit are respectively connected to the DRIVE_H pin and the DRIVE_L pin of the segmented drive controller, and the OUT- pins are respectively connected to the negative pressure generating unit and the power management unit.

4. The delay compensation segmented driving system for the GaN packaged module according to claim 3 is characterized in that: The GaN HEMT module includes a GaN HEMT high-side unit and a GaN HEMT low-side unit; The GaN HEMT high-side unit and the GaN HEMT low-side unit each include a G+ pin and a G- pin, and the G+ pin and G- pin of the GaN HEMT high-side unit and the GaN HEMT low-side unit are respectively connected to the OUT+ pin and OUT- pin of the high-side drive unit and the low-side drive unit.

5. The delay compensation segmented driving system for the GaN packaged module according to claim 4, characterized in that: The gate absorption network unit includes an RC absorption high side, an RC absorption low side and two embedded magnetic beads FB; The two embedded magnetic beads FB are respectively connected to the G-pins of the GaN HEMT high-side unit and the GaN HEMT low-side unit.

6. The delay compensation segmented driving system for the GaN packaged module according to claim 3, characterized in that: The delay compensation controller includes a dV / dt pin, an I_FB pin, a COMP_H pin and a COMP_L pin; The COMP_H pin and the COMP_L pin are connected to the COMP pins of the high-side driving unit and the low-side driving unit respectively.

7. The delay compensation segmented driving system for the GaN packaged module according to claim 6, characterized in that: The phase detection unit includes a dV / dt pin, a COMP pin and an I_FB pin; The COMP pin is connected to the dV / dt pin of the delay compensation controller, and the dV / dt pin is connected to the dV / dt detection unit.

8. The delay compensation segmented driving system for the GaN packaged module according to claim 7, characterized in that: The protection logic unit includes an I_FB pin, a TEMP pin and a FAULT pin; The FAULT pin is connected to the FAULT pin of the segmented drive controller.

9. The delay compensation segmented driving system for the GaN packaged module according to claim 8, characterized in that: The voltage / current / temperature detection module includes a voltage / current detection unit and a temperature detection unit; The temperature detection unit and the voltage / current detection unit are connected to the protection logic unit, and the voltage / current detection unit is also connected to the I_FB pin of the phase detection unit.

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