Power supply chip and electronic equipment

Abstract

The invention discloses a power supply chip and electronic equipment, and belongs to the technical field of electronic equipment. The power supply chip comprises an integrated circuit unit, the integrated circuit unit comprises a plurality of pins, the integrated circuit unit further comprises a power circuit, the power circuit comprises a plurality of switch tubes, each switch tube comprises a first main terminal, a second main terminal and a control terminal, and the first main terminal and the second main terminal of each switch tube are electrically connected with one pin respectively; the input end of the switching circuit is used for receiving a control signal, the output end of the switching circuit is electrically connected with the control terminal of each switching tube, the switching circuit has a plurality of switching states, and the switching circuit is used for switching the switching states so as to switch the chip function of the power supply chip.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and specifically relates to a power chip and electronic equipment. Background Art

[0002] In the related art, the three-level architecture is used as a charging integrated circuit (IC) to improve charging efficiency, so it is widely used. The three-level architecture includes 4 power tubes. Since the power tube area inside the chip usually accounts for more than 60%, in order to make full use of the power tube function, the three-level BUCK (step-down) circuit can be used as a boost architecture to achieve reverse charging according to the control logic involved in the two-level boost circuit when working in reverse. However, the impedance value of the power tube in the reverse power path is higher than when used as a three-level, resulting in low power supply and charging efficiency of the power chip. Summary of the Invention

[0003] The present application aims to provide a power chip and an electronic device that can solve the problem of low power supply or charging efficiency of power chips in related technologies.

[0004] In a first aspect, an embodiment of the present application provides a power chip, the power chip comprising:

[0005] The integrated circuit unit includes a plurality of pins and further includes:

[0006] A power circuit includes a plurality of switching tubes, each of which includes a first main terminal, a second main terminal, and a control terminal. The first main terminal and the second main terminal of each switching tube are electrically connected to a pin respectively;

[0007] The switching circuit has an input end for receiving a control signal, and an output end for electrically connecting to a control terminal of each switching tube. The switching circuit has multiple switching states, and the switching circuit is used to switch the switching state to switch the chip function of the power chip.

[0008] In a second aspect, an embodiment of the present application proposes an electronic device, comprising the power chip proposed in the first aspect.

[0009] This application adds a switching circuit inside the integrated circuit unit, that is, inside the Die, and switches the control signals of the control ends of each switching tube in the power circuit through the switching circuit, so that the charging chip can be packaged into power chips compatible with multiple architectures in one tape-out to realize different chip functions. There is no need to modify the three-level BUCK circuit according to the control logic involved in the two-level boost circuit, so it will not increase the impedance value of the power tube, and improve the power supply or charging efficiency of the power chip.

[0010] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0012] Figure 1 A circuit diagram of a neutral point clamped three-level buck circuit chip according to some embodiments of the present application is shown;

[0013] Figure 2 A schematic diagram showing the packaging structure of a neutral point clamped three-level buck circuit chip according to some embodiments of the present application is shown;

[0014] Figure 3 A schematic diagram showing the structure of a controller for generating a control signal for a power chip according to some embodiments of the present application is shown;

[0015] Figure 4 A circuit diagram showing a reverse boost circuit chip according to some embodiments of the present application is shown;

[0016] Figure 5 A circuit diagram of a step-down circuit chip according to some embodiments of the present application is shown;

[0017] Figure 6 A schematic diagram showing the packaging structure of a voltage regulating circuit chip according to some embodiments of the present application is shown;

[0018] Figure 7 A circuit diagram of a 1:2 voltage multiplication charge pump circuit chip according to some embodiments of the present application is shown;

[0019] Figure 8 A circuit diagram of a 2:1 voltage divider charge pump circuit chip according to some embodiments of the present application is shown.

[0020] Reference numerals:

[0021] 10 power chip, 12 integrated circuit unit, 121 pin, 122 power circuit, 1222 switch tube, 123 switch circuit, 14 substrate;

[0022] a first main terminal, b second main terminal, c control terminal;

[0023] P1 first pin, P2 second pin, P3 third pin, P4 fourth pin, P5 fifth pin, P6 sixth pin, SW switch node pin, GND ground pin;

[0024] Q1 is the first switch tube, Q2 is the second switch tube, Q3 is the third switch tube, and Q4 is the fourth switch tube;

[0025] S1 is the first switch element, S2 is the second switch element, S3 is the third switch element, S4 is the fourth switch element, S5 is the fifth switch element, S6 is the sixth switch element, S7 is the seventh switch element, and S8 is the eighth switch element;

[0026] Vin input terminal, Vout output terminal, C1 first capacitor, C2 second capacitor, C3 third capacitor, C4 fourth capacitor, C5 fifth capacitor, L1 first inductor, L2 second inductor. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly refer to one or more of the features. Throughout the description of this application, unless otherwise specified, "plurality" means two or more. Furthermore, "and / or" in the specification and claims refers to at least one of the connected entities, and the character " / " generally indicates an "or" relationship between the connected entities.

[0029] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0031] The following combination Figures 1 to 8 A power chip and an electronic device according to embodiments of the present application are described.

[0032] In some embodiments of the present application, a power chip is provided. Figure 1 FIG1 shows a circuit diagram of a neutral point clamped three-level buck circuit chip according to some embodiments of the present application. Figure 2 FIG. 1 shows a schematic diagram of the packaging structure of a neutral point clamped three-level buck circuit chip according to some embodiments of the present application, as shown in FIG. Figure 1 and Figure 2 As shown, the power chip 10 includes:

[0033] The integrated circuit unit 12 includes a plurality of pins 121 and further includes:

[0034] The power circuit 122 includes a plurality of switch tubes 1222 . The switch tubes 1222 include a first main terminal a, a second main terminal b, and a control terminal c. The first main terminal a and the second main terminal b of each switch tube 1222 are electrically connected to one pin 121 , respectively.

[0035] The switch circuit 123 has an input end for receiving a control signal, and an output end of the switch circuit 123 is electrically connected to a control terminal c of each switch tube 1222. The switch circuit 123 has multiple switch states, and the switch circuit 123 is used to switch the switch state to switch the chip function of the power chip 10.

[0036] In the embodiment of the present application, the power chip 10 can be a charging chip or a power supply chip. For example, the power chip 10 is a power supply chip within an electronic device, capable of providing power to power devices within the electronic device. For example, the power chip 10 is a charging chip, which is provided in an electronic device or a charging device and can charge an independent battery or a battery within the electronic device.

[0037] The power chip 10 includes an integrated circuit unit 12, which is also known as the chip die. Integrated circuit unit 12 includes a power circuit 122, which includes multiple switching transistors 1222. Exemplarily, switching transistors 1222 are metal-oxide-semiconductor field-effect transistors (MOSFETs). Switching transistors 1222 include a first main terminal a, a second main terminal b, and a control terminal c. Control terminal c is the gate of the MOSFET, while the first main terminal a and the second main terminal b are the drain and source of the MOSFET, respectively. Exemplarily, for an NPN-type MOSFET, the first main terminal a is the drain, and the second main terminal b is the source. Exemplarily, for a PNP-type MOSFET, the first main terminal a is the source, and the second main terminal b is the drain. During operation, different switching transistors 1222 are combined and turned on at different phases, which can reduce output voltage ripple and narrow the voltage fluctuation range, thereby improving power supply efficiency.

[0038] The integrated circuit unit 12 is provided with multiple pins 121, each of which is electrically connected to the first main terminal a or the second main terminal b of a switch tube 1222, that is, electrically connected to the drain or source of the MOFSET. The first main terminal a of each switch tube 1222 is electrically connected to a pin 121, and the second main terminal b of each switch tube 1222 is also electrically connected to a pin 121, and each pin 121 is only connected to one main terminal. By reserving pins 121 electrically connected to the main terminals of each switch tube 1222, during packaging, only the connection method of the substrate 14 needs to be changed, and multiple versions of the chip can be packaged in a single wafer, realizing different chip functions, such as a forward three-level buck circuit, a reverse boost circuit, a normal buck circuit, a voltage doubler charge pump circuit, or a voltage divider charge pump circuit.

[0039] The present application adds a switching circuit 123 inside the integrated circuit unit 12, that is, inside the Die, and switches the control signal of the control end of each switch tube 1222 in the power circuit 122 through the switching circuit 123, so that the charging chip can be packaged into a power chip 10 compatible with multiple architectures in one tape-out, realizing different chip functions. There is no need to modify the three-level BUCK circuit according to the control logic involved in the two-level boost circuit, so the impedance value of the power tube will not be increased, thereby improving the power supply or charging efficiency of the power chip 10.

[0040] In some embodiments of the present application, the switch circuit 123 is further used to switch the switch state to switch the correspondence between the control terminals c of the multiple switch tubes 1222 and the control signal to switch the chip function of the power chip.

[0041] In an embodiment of the present application, a switch circuit 123 is added to the integrated circuit unit 12, i.e., the Die. The switch circuit 123 includes a plurality of switch elements. The switch circuit 123 has a plurality of different switch states. In different switch states, the switch elements switch between a closed state or an open state in different combinations, thereby switching the correspondence between the control terminals of the plurality of switch tubes 1222 and the control signals. In this way, it is possible to switch the plurality of switch tubes 1222 to independently receive control signals, or to switch at least two switch tubes 1222 to be connected in parallel, thereby adapting to different power supply circuits, such as a forward three-level BUCK circuit, a reverse Boost circuit, a normal BUCK circuit, a voltage doubling charge pump circuit, or a voltage dividing charge pump circuit.

[0042] In some embodiments of the present application, the power chip 10 is a neutral point clamped three-level buck circuit chip or a charge pump circuit chip; the multiple switch tubes 1222 include a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4; the input end of the switch circuit 123 is used to receive the control signal of the first switch tube Q1, the control signal of the second switch tube Q2, the control signal of the third switch tube Q3 and the control signal of the fourth switch tube Q4, so as to control the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 to be turned on or off respectively.

[0043] In the embodiment of the present application, the power chip 10 functions as a neutral point clamped three-level buck circuit chip or a charge pump circuit chip. When the power chip 10 is a neutral point clamped three-level buck circuit chip or a charge pump circuit chip, the multiple switching transistors in the power chip 10, including the first switching transistor Q1, the second switching transistor Q2, the third switching transistor Q3, and the fourth switching transistor Q4, are independently controlled.

[0044] Exemplarily, the input end of the switching circuit 123 receives the control signal of the first switching tube Q1, the control signal of the second switching tube Q2, the control signal of the third switching tube Q3 and the control signal of the fourth switching tube Q4, respectively, and by adjusting the switching state, these control signals are separately transmitted to the first switching tube Q1, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4, thereby controlling the four switching tubes 1222 to be turned on in four phase combinations, thereby improving power supply efficiency.

[0045] In some embodiments of the present application, the power chip 10 is a voltage regulating circuit chip; the multiple switch tubes 1222 include a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4, the first switch tube Q1 and the second switch tube Q2 are connected in parallel, and the third switch tube Q3 and the fourth switch tube Q4 are connected in parallel; the input end of the switch circuit 123 is used to receive control signals of the first switch tube Q1 and the second switch tube Q2, as well as control signals of the third switch tube Q3 and the fourth switch tube Q4, so as to control the first switch tube Q1 and the second switch tube Q2 to be synchronously turned on or off, and to control the third switch tube Q3 and the fourth switch tube Q4 to be synchronously turned on or off.

[0046] In the embodiment of the present application, the chip function of the power chip 10 includes a voltage regulating circuit chip. The voltage regulating circuit chip can be a boost circuit chip, such as a reverse boost circuit chip, or a buck circuit chip, such as a buck circuit chip. The first switch tube Q1 and the second switch tube Q2 are connected in parallel and are controlled to be turned on or off together by a control signal. The third switch tube Q3 and the fourth switch tube Q4 are connected in parallel and are controlled to be turned on or off together by another control signal. By connecting the switch tubes synchronously in parallel, the on-resistance of the power tube can be reduced, thereby improving the power supply efficiency.

[0047] In some embodiments of the present application, the multiple pins 121 include a first pin P1, a second pin P2, a third pin P3, a fourth pin P4, a fifth pin P5, a sixth pin P6, a switch node pin SW and a ground pin GND; the multiple switch tubes 1222 include a first switch tube Q1, a second switch tube Q2, a third switch tube Q3 and a fourth switch tube Q4.

[0048] Among them, the first pin P1 is electrically connected to the second main terminal b of the first switch transistor Q1, the second pin P2 is electrically connected to the first main terminal a of the second switch transistor Q2, the third pin P3 is electrically connected to the second main terminal b of the third switch transistor Q3, the fourth pin P4 is electrically connected to the first main terminal a of the fourth switch transistor Q4, the fifth pin P5 is electrically connected to the second main terminal b of the second switch transistor Q2, the sixth pin P6 is electrically connected to the first main terminal a of the first switch transistor Q1, the switch node pin SW is electrically connected to the first main terminal a of the third switch transistor Q3, and the ground pin GND is electrically connected to the second main terminal b of the fourth switch transistor Q4.

[0049] In the embodiment of the present application, the integrated circuit unit 12 includes a first pin P1, a second pin P2, a third pin P3, a fourth pin P4, a fifth pin P5, a sixth pin P6, a switch node pin SW and a ground pin GND. Figure 1 and Figure 2As shown, the sixth pin P6 can be used as a signal input or output terminal, and the ground pin GND is used for grounding. The switch node pin SW can provide a charging and discharging path for the bootstrap capacitor, thereby ensuring a stable driving voltage of the gate of the high-side MOSFET.

[0050] The first pin P1, the second pin P2, the third pin P3, the fourth pin P4, and the fifth pin P5 are respectively electrically connected to the main terminals of the four switching transistors 1222. By adjusting the connection relationship between different pins 121 and the substrate 14, or adjusting the connection relationship between different pins 121, and adjusting the connection relationship between different pins 121 and external devices, the integrated circuit unit 12, or die, can be used for power chips 10 with different functions. This allows power chips 10 compatible with different architectures to be packaged through a single tape-out, thereby improving efficiency.

[0051] In some embodiments of the present application, Figure 1 As shown, the switch circuit 123 includes: a first switch element S1, a first end of the first switch element S1 is electrically connected to the control terminal c of the first switch tube Q1, and a second end of the first switch element S1 is electrically connected to the input end of the switch circuit 123; a second switch element S2, a first end of the second switch element S2 is electrically connected to the first end of the first switch element S1; a third switch element S3, a first end of the third switch element S3 is electrically connected to the second end of the second switch element S2, and a second end of the third switch element S3 is electrically connected to the control terminal c of the second switch tube Q2; a fourth switch element S4, a first end of the fourth switch element S4 is electrically connected to the second end of the third switch element S3, and a second end of the fourth switch element S4 is electrically connected to the input end of the switch circuit 123. The first end of the fifth switch element S5 is electrically connected to the control terminal c of the third switch tube Q3, and the second end of the fifth switch element S5 is electrically connected to the input end of the switch circuit 123; the sixth switch element S6, the first end of the sixth switch element S6 is electrically connected to the first end of the fifth switch element S5; the seventh switch element S7, the first end of the seventh switch element S7 is electrically connected to the second end of the sixth switch element S6, and the second end of the seventh switch element S7 is electrically connected to the control terminal c of the fourth switch tube Q4; the eighth switch element S8, the first end of the eighth switch element S8 is electrically connected to the second end of the seventh switch element S7, and the second end of the eighth switch element S8 is electrically connected to the input end of the switch circuit 123.

[0052] In the embodiment of the present application, the switch circuit 123 includes eight different switch elements, namely, a first switch element S1, a second switch element S2, a third switch element S3, a fourth switch element S4, a fifth switch element S5, a sixth switch element S6, a seventh switch element S7, and an eighth switch element S8. The first switch element S1, the fourth switch element S4, the fifth switch element S5, and the eighth switch element S8 are electrically connected to the control terminals of the first switch transistor Q1, the second switch transistor Q2, the third switch transistor Q3, and the fourth switch transistor Q4, respectively. The ends of the first switch element S1, the fourth switch element S4, the fifth switch element S5, and the eighth switch element S8 that are not connected to the control terminal of the switch transistor 1222 each serve as a receiving end for a control signal.

[0053] The common end of the second switching element S2 and the third switching element S3 forms a control signal receiving end, and the common end of the sixth switching element S6 and the seventh switching element S7 forms a control signal receiving end.

[0054] In different switching states, the above-mentioned 8 switching elements can form different connection states of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 by switching the closed or open state, and can independently control the correspondence between the control end of each switch tube 1222 and different control signals, so that the integrated circuit unit 12, that is, Die, can adapt to power chips 10 with different architectures.

[0055] Exemplarily, the on / off switching of the eight switching elements can be achieved through software configuration. Exemplarily, the on / off switching of the eight switching elements can be achieved by reducing the number of fuses during the production of the power chip 10. Exemplarily, the on / off switching of the eight switching elements can be achieved by writing content to a one-time programmable memory (OTP) or other storage device to achieve software-configured switch combinations.

[0056] In some embodiments of the present application, the power chip 10 is a neutral point clamped three-level buck circuit chip, the first pin P1 is short-circuited with the second pin P2, the third pin P3 and the fourth pin P4 are short-circuited, and the fifth pin P5 and the switch node pin SW are short-circuited. The switching state of the circuit is: the first switch element S1, the fourth switch element S4, the fifth switch element S5 and the eighth switch element S8 are closed, and the second switch element S2, the third switch element S3, the sixth switch element S6 and the seventh switch element S7 are disconnected.

[0057] In the embodiment of the present application, the power chip 10 is specifically a neutral point clamped three-level buck circuit chip, that is, a forward three-level BUCK circuit chip. Figure 1As shown, when packaging the neutral point clamped three-level buck circuit chip, the first pin P1 and the second pin P2 are short-circuited, the third pin P3 and the fourth pin P4 are short-circuited, and the fifth pin P5 and the switch node pin SW are short-circuited or set to one pin 121. At this time, the second main terminal b of the second switch tube Q2 is electrically connected to the first main terminal a of the third switch tube Q3.

[0058] At the same time, the switching state of the switch circuit 123 is set to: the first switch element S1, the fourth switch element S4, the fifth switch element S5 and the eighth switch element S8 are closed, and the second switch element S2, the third switch element S3, the sixth switch element S6 and the seventh switch element S7 are opened.

[0059] In this case, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are each controlled to turn on or off by an independent control signal. By controlling the four switches 1222 to conduct in four phase combinations, the fluctuation range of the voltage standing wave ratio (VSWR) can be limited to 1 / 2 of the input voltage. This also reduces the fluctuation range of the inductor current and output voltage ripple of the neutral-point-clamped three-level buck circuit by half, thereby improving power supply efficiency.

[0060] In some embodiments of the present application, Figure 1 As shown, the power chip 10 also includes: an input terminal Vin and an output terminal Vout, the input terminal Vin is electrically connected to the sixth pin P6; a first capacitor C1, a first end of the first capacitor C1 is electrically connected to the second pin P2, and a second end of the first capacitor C1 is electrically connected to the third pin P3; a first inductor L1, a first end of the first inductor L1 is electrically connected to the switch node pin SW, and a second end of the first inductor L1 is electrically connected to the output terminal Vout; a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the second end of the first inductor L1, and a second end of the second capacitor C2 is grounded.

[0061] In the embodiment of the present application, the power chip 10 further includes a substrate 14, which is connected to the integrated circuit unit 12. The substrate 14 includes an input terminal Vin and an output terminal Vout. The substrate 14 is provided with a first capacitor C1, a first inductor L1, and a second capacitor C2. Figure 1 and Figure 2As shown, the first capacitor C1 and the first inductor L1 form a charge-discharge circuit, and the second capacitor C2 serves as an output capacitor. For example, the first pin P1 and the second pin P2 on the integrated circuit unit 12 are connected together on the substrate 14, and are connected to the top plate of the first capacitor C1 via a contact A1 located further from the substrate 14. Similarly, the third pin P3 and the fourth pin P4 are connected together on the substrate 14, and are directly connected to the bottom plate of the first capacitor C1 via a contact B1 located further from the substrate 14.

[0062] When packaging different power chips 10, the same integrated circuit unit 12, that is, the same bare die, can be used for different applications and connections. By simply changing the connection method of the substrate 14, multiple versions of the power chip 10 can be packaged in one go. Compared with the method of routing on a printed circuit board (PCB), the connection distance between the integrated circuit unit 12 and the substrate 14 in the embodiment of the present application is shorter, the impedance is lower, and the interference is smaller, thereby improving power efficiency.

[0063] In some embodiments of the present application, the input end of the switching circuit 123 is used to receive a first control signal, a second control signal, a third control signal, and a fourth control signal, the second end of the first switch element S1 is used to receive the first control signal, the second end of the fourth switch element S4 is used to receive the second control signal, the second end of the fifth switch element S5 is used to receive the third control signal, and the second end of the eighth switch element S8 is used to receive the fourth control signal.

[0064] The neutral point clamped three-level buck circuit chip has a first phase, a second phase, a third phase, and a fourth phase. When the signal duty cycle of the neutral point clamped three-level buck circuit chip is less than a duty cycle threshold, in the first phase, the first switch tube Q1 and the third switch tube Q3 are turned on, and the second switch tube Q2 and the fourth switch tube Q4 are turned off. In the second phase, the third switch tube Q3 and the fourth switch tube Q4 are turned on, and the first switch tube Q1 and the second switch tube Q2 are turned off. In the third phase, the second switch tube Q2 and the fourth switch tube Q4 are turned on, and the first switch tube Q1 and the third switch tube Q3 are turned off. In the fourth phase, the third switch tube Q3 and the fourth switch tube Q4 are turned on, and the first switch tube Q1 and the second switch tube Q2 are turned off.

[0065] When the signal duty cycle of the neutral point clamped three-level buck circuit chip is greater than or equal to the duty cycle threshold, in the first phase, the first switch tube Q1 and the second switch tube Q2 are turned on, and the third switch tube Q3 and the fourth switch tube Q4 are turned off; in the second phase, the first switch tube Q1 and the third switch tube Q3 are turned on, and the second switch tube Q2 and the fourth switch tube Q4 are turned off; in the third phase, the first switch tube Q1 and the second switch tube Q2 are turned on, and the third switch tube Q3 and the fourth switch tube Q4 are turned off; in the fourth phase, the second switch tube Q2 and the fourth switch tube Q4 are turned on, and the first switch tube Q1 and the third switch tube Q3 are turned off.

[0066] In the embodiment of the present application, the control terminals of the four switch tubes 1222 receive four control signals, namely the first control signals PWM_up1, PWM_up2, PWM_down1 and PWM_down2. Figure 3 FIG. 1 shows a schematic diagram of a controller for generating a control signal for a power chip 10 in some embodiments of the present application. Figure 3 As shown in the figure, four control signals are generated via a reference voltage, op amp, comparator, sawtooth waveform generator, and phase-shift controller. Duty cycle determination is also implemented in the phase-shift controller. The comparator output signals generate two duty cycles, D and Ds, in the phase-shift controller. D and Ds are 180° out of phase with each other and have their own complementary signals.

[0067] During the operation of the power chip 10, there are a total of four phases, namely the first phase phase 1, the second phase phase 2, the third phase phase 3 and the fourth phase phase 4. The operating logic is as follows:

[0068] If the duty cycle is less than the duty cycle threshold, for example, less than 50%, then in the first phase, phase 1, the first and third switches Q1 and Q3 are turned on, while the second and fourth switches Q2 and Q4 are turned off. At this time, the first capacitor C1 is charged and the first inductor L1 is discharged. In the second phase, phase 2, the third and fourth switches Q3 and Q4 are turned on, while the first and second switches Q1 and Q2 are turned off. At this time, the first capacitor C1 remains charged, while the first inductor L1 is discharged. In the third phase, phase 3, the second and fourth switches Q2 and Q4 are turned on, while the first and third switches Q1 and Q3 are turned off. At this time, the first capacitor C1 is discharged, while the first inductor L1 is charged. In the fourth phase, phase 4, the third and fourth switches Q3 and Q4 are turned on, while the first and second switches Q1 and Q2 are turned off. At this time, the first capacitor C1 remains charged, while the first inductor L1 is discharged.

[0069] If the duty cycle is greater than or equal to the duty cycle threshold, for example, if the duty cycle is ≥50%, then in the first phase, phase 1, the first and second switches Q1 and Q2 are turned on, while the third and fourth switches Q3 and Q4 are turned off. At this time, the first capacitor C1 is kept charged, while the first inductor L1 is charged. In the second phase, phase 2, the first and third switches Q1 and Q3 are turned on, while the second and fourth switches Q2 and Q4 are turned off. At this time, the first capacitor C1 is charged, while the first inductor L1 is discharged. In the third phase, phase 3, the first and second switches Q1 and Q2 are turned on, while the third and fourth switches Q3 and Q4 are turned off. At this time, the first capacitor C1 is kept charged, while the first inductor L1 is charged. In the fourth phase, phase 4, the second and fourth switches Q2 and Q4 are turned on, while the first and third switches Q1 and Q3 are turned off. At this time, the first capacitor C1 is discharged, while the first inductor L1 is discharged.

[0070] In some embodiments of the present application, the power chip 10 is a voltage regulating circuit chip, the first pin P1, the fourth pin P4 and the switch node pin SW are electrically connected, the fifth pin P5 and the switch node pin SW are short-circuited, the third pin and the ground pin GND are electrically connected, the second pin P2 and the sixth pin P6 are electrically connected, and the switching state is: the first switch element S1, the fourth switch element S4, the fifth switch element S5 and the eighth switch element S8 are disconnected, and the second switch element S2, the third switch element S3, the sixth switch element S6 and the seventh switch element S7 are closed.

[0071] In the embodiment of the present application, the power chip 10 is a voltage regulating circuit chip. Exemplarily, the voltage regulating circuit chip can be a reverse boost circuit (reverse Boost circuit) chip or a buck circuit (BUCK circuit) chip. Figure 4 A circuit diagram of a reverse boost circuit chip according to some embodiments of the present application is shown. Figure 5 Schematic diagrams of the step-down circuit chips of some embodiments of the present application are shown. Figure 4 and Figure 5 As shown, when packaging the voltage regulating circuit chip, the first pin P1, the fourth pin P4, the fifth pin P5 and the switch node pin SW are electrically connected together, and the third pin P3 is short-circuited with the ground pin GND, and the second pin P2 is short-circuited with the sixth pin P6.

[0072] At the same time, the switching state of the switch circuit 123 is set so that the first switch element S1, the fourth switch element S4, the fifth switch element S5 and the eighth switch element S8 are opened, and the second switch element S2, the third switch element S3, the sixth switch element S6 and the seventh switch element S7 are closed.

[0073] In this case, the first switch Q1 and the second switch Q2 are connected in parallel and are controlled to be turned on or off by one control signal. The third switch Q3 and the fourth switch Q4 are connected in parallel and are controlled to be turned on or off by another control signal.

[0074] The second and third switches S2 and S3 prevent gate signal asynchrony between the first and second switches Q1 and Q2. The second and third switches S2 and S3 require matching during circuit and layout design. By programming fuses or using software, the first and fourth switches S1 and S4 are controlled to disconnect, while the second and third switches S2 and S3 are controlled to close. Similarly, the sixth and seventh switches S6 and S7 prevent gate signal asynchrony between the third and fourth switches Q3 and Q4. By programming fuses or using software, the fifth and eighth switches S5 and S8 are controlled to disconnect, while the sixth and seventh switches S6 and S7 are controlled to close, ensuring that the PWM_up signal is transmitted synchronously to the control terminals of the first and second switches Q1 and Q2, and that the PWM_down signal is transmitted synchronously to the control terminals of the third and fourth switches Q3 and Q4.

[0075] In this way, a reverse Boost circuit or a Buck circuit can be realized. The parallel switch tube 1222 can halve the on-resistance of the power tube, thereby improving the power supply efficiency.

[0076] In some embodiments of the present application, Figure 6 Schematic diagram of the packaging structure of the voltage regulating circuit chip of some embodiments of the present application is shown. Figure 4 and Figure 6 As shown, the power chip 10 also includes: an input terminal Vin and an output terminal Vout, the output terminal Vout is electrically connected to the sixth pin P6; a second inductor L2, a first end of the second inductor L2 is electrically connected to the switch node pin SW, and a second end of the second inductor L2 is electrically connected to the input terminal Vin; a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the input terminal Vin, and a second end of the third capacitor C3 is grounded.

[0077] In the embodiment of the present application, the voltage regulating circuit chip is a reverse boost circuit chip. The power supply chip 10 further includes a substrate 14, which is connected to the integrated circuit unit 12. The substrate 14 includes an input terminal Vin and an output terminal Vout. A second inductor L2 and a third capacitor C3 are provided on the substrate 14. Figure 4 and Figure 6As shown, the switch node pin SW and the fifth pin P5 on the integrated circuit unit 12 are configured as a single pin 121. The switch node pin SW, the first pin P1, and the fourth pin P4 are connected together on the substrate 14 and directly connected to an external power inductor, namely the second inductor L2, through a contact SW2 located behind the substrate 14. Similarly, the third pin P3 and the ground pin GND are connected together on the substrate 14, and the ground pin of the substrate 14 serves as the ground pin of the power chip 10. The second pin P2 and the sixth pin P6 are connected together, serving as the output pin of the power chip 10. The common end of the second inductor L2 and the third capacitor C3 is connected to the input terminal Vin of the power chip 10.

[0078] In some embodiments of the present application, Figure 5 and Figure 6 As shown, the power chip 10 also includes: an input terminal Vin and an output terminal Vout, the input terminal Vin is electrically connected to the sixth pin P6; a second inductor L2, a first end of the second inductor L2 is electrically connected to the switch node pin SW, and a second end of the second inductor L2 is electrically connected to the output terminal Vout; a third capacitor C3, a first end of the third capacitor C3 is electrically connected to the output terminal Vout, and a second end of the third capacitor C3 is grounded.

[0079] In the embodiment of the present application, by swapping the input terminal Vin and the output terminal Vout, a conventional BUCK architecture can be realized through the same distance to obtain a step-down circuit chip. Figure 5 Compared with a conventional BUCK circuit having only two switches 1222 , the buck circuit chip of the present application can reduce switch impedance and improve heavy-load efficiency by connecting the switches 1222 in parallel.

[0080] In some embodiments of the present application, the power supply chip 10 is a charge pump circuit chip, the first pin P1 is short-circuited with the switch node pin SW, the second pin P2 is short-circuited with the sixth pin P6, the fifth pin P5 is short-circuited with the fourth pin P4, and the third pin P3 is electrically connected to the ground pin GND. The switching state of the switching circuit 123 is: the first switch element S1, the fourth switch element S4, the fifth switch element S5 and the eighth switch element S8 are closed, and the second switch element S2, the third switch element S3, the sixth switch element S6 and the seventh switch element S7 are disconnected.

[0081] In the embodiment of the present application, the power chip 10 is a charge pump circuit chip, and the charge pump circuit chip can be a voltage-doubling charge pump circuit chip or a voltage-dividing charge pump circuit chip. Figure 7 A circuit diagram of a 1:2 voltage multiplication charge pump circuit chip according to some embodiments of the present application is shown. Figure 8 FIG. 1 shows a circuit diagram of a 2:1 voltage divider charge pump circuit chip according to some embodiments of the present application. Figure 7 and Figure 8 As shown, when packaging the charge pump circuit chip, the first pin P1 is short-circuited with the switch node pin SW, the second pin P2 is short-circuited with the sixth pin P6, and the fifth pin P5 is short-circuited with the fourth pin P4.

[0082] At the same time, the switching state of the switch circuit 123 is set so that the first switch element S1, the fourth switch element S4, the fifth switch element S5 and the eighth switch element S8 are closed, and the second switch element S2, the third switch element S3, the sixth switch element S6 and the seventh switch element S7 are open.

[0083] When used as a charge pump circuit chip, a charge pump controller can be provided inside the power chip 10. Since the charge pump controller has a small area, it has little impact on the overall area of ​​the power chip 10.

[0084] In some embodiments of the present application, the power chip 10 further includes: an input terminal Vin and an output terminal Vout, the input terminal Vin is electrically connected to the sixth pin P6; a fourth capacitor C4, a first end of the fourth capacitor C4 is electrically connected to the first pin P1, and a second end of the fourth capacitor C4 is electrically connected to the fifth pin P5; a fifth capacitor C5, a first end of the fifth capacitor C5 is electrically connected to the output terminal Vout, and a second end of the fifth capacitor C5 is grounded.

[0085] In the embodiments of this application, Figure 7 As shown, the charge pump circuit chip is specifically a 1:2 voltage multiplication charge pump circuit chip. A fourth capacitor C4 and a fifth capacitor C5 are provided on substrate 14. A 1:2 voltage multiplication charge pump is implemented on substrate 14 by short-circuiting the second pin P2 with the input terminal Vin, short-circuiting the fifth pin P5 with the fourth pin P4, and connecting the first pin P1 and the fifth pin P5 via a flying capacitor.

[0086] In some embodiments of the present application, the input end of the switching circuit 123 is used to receive a fifth control signal, a sixth control signal, a seventh control signal, and an eighth control signal, the second end of the first switch element S1 is used to receive the fifth control signal, the second end of the fourth switch element S4 is used to receive the sixth control signal, the second end of the fifth switch element S5 is used to receive the seventh control signal, and the second end of the eighth switch element S8 is used to receive the eighth control signal; wherein, the charge pump circuit chip has a first phase and a second phase; in the first phase, the first switch tube Q1 and the fourth switch tube Q4 are turned on, and the second switch tube Q2 and the third switch tube Q3 are turned off; in the second phase, the second switch tube Q2 and the third switch tube Q3 are turned on, and the first switch tube Q1 and the fourth switch tube Q4 are turned off.

[0087] In this technical solution, the four switching transistors 1222 are controlled on and off by four control signals: a fifth control signal PWM1, a sixth control signal PMW2, a seventh control signal PMW3, and an eighth control signal PMW4. These fifth, sixth, seventh, and eighth control signals PWM1, PMW2, PMW3, and PMW4 are generated by a charge pump controller and can control the switching between two phases: the first and second phases, achieving a double voltage boost.

[0088] The control logic is as follows:

[0089] In the first phase, the first switch tube Q1 and the fourth switch tube Q4 are controlled to be turned on, and the second switch tube Q2 and the third switch tube Q3 are controlled to be turned off. At this time, the upper plate of the third capacitor C3 is charged, and the voltage difference across the third capacitor C3 is equal to the input voltage.

[0090] In the second phase, the second switch tube Q2 and the third switch tube Q3 are controlled to be turned on, and the first switch tube Q1 and the fourth switch tube Q4 are controlled to be turned off. The potential of the lower plate of the third capacitor C3 is raised to the input voltage. Since the voltage difference across it does not change suddenly, the voltage output by the output terminal Vout at this time is equal to twice the input voltage.

[0091] The present application can realize a 1:2 voltage doubling charge pump through a single tape-out, so that the four switching tubes 1222 in the integrated circuit unit 12 can be fully utilized.

[0092] In some embodiments of the present application, the power chip 10 further includes: an input terminal Vin and an output terminal Vout, the output terminal Vout being electrically connected to the sixth pin P6; a fourth capacitor C4, the first end of the fourth capacitor C4 being electrically connected to the switch node pin SW, and the second end of the fourth capacitor C4 being electrically connected to the input terminal Vin; and a fifth capacitor C5, the first end of the fifth capacitor C5 being electrically connected to the input terminal Vin, and the second end of the fifth capacitor C5 being grounded.

[0093] In the embodiment of the present application, as shown in FIG8 , the charge pump circuit chip is specifically a 2:1 voltage divider charge pump circuit chip. A fourth capacitor C4 and a fifth capacitor C5 are provided on substrate 14. Compared to a 2:1 voltage multiplication charge pump circuit chip, a 2:1 voltage divider charge pump can be achieved by swapping the input terminal Vin and the output terminal Vout.

[0094] In some embodiments of the present application, the input end of the switching circuit 123 is used to receive a fifth control signal, a sixth control signal, a seventh control signal, and an eighth control signal, the second end of the first switch element S1 is used to receive the fifth control signal, the second end of the fourth switch element S4 is used to receive the sixth control signal, the second end of the fifth switch element S5 is used to receive the seventh control signal, and the second end of the eighth switch element S8 is used to receive the eighth control signal; wherein, the charge pump circuit chip has a first phase and a second phase; in the first phase, the second switch tube Q2 and the third switch tube Q3 are turned on, and the first switch tube Q1 and the fourth switch tube Q4 are turned off; in the second phase, the first switch tube Q1 and the fourth switch tube Q4 are turned on, and the second switch tube Q2 and the third switch tube Q3 are turned off.

[0095] In this technical solution, the four switching transistors 1222 are controlled on and off by four control signals: a fifth control signal PWM1, a sixth control signal PMW2, a seventh control signal PMW3, and an eighth control signal PMW4. These fifth, sixth, seventh, and eighth control signals PWM1, PMW2, PMW3, and PMW4 are generated by a charge pump controller and can control the switching between two phases, namely the first and second phases, to achieve a 1 / 2 voltage division.

[0096] The control logic is as follows:

[0097] In the first phase, the second switch tube Q2 and the third switch tube Q3 are controlled to be turned on, the first switch tube Q1 and the fourth switch tube Q4 are controlled to be turned off, the third capacitor C3 is charged, and the voltage difference between the upper and lower plates of the third capacitor C3 is equal to the difference between the input voltage and the output voltage.

[0098] In the second phase, the first switch tube Q1 and the fourth switch tube Q4 are controlled to be turned on, and the second switch tube Q2 and the third switch tube Q3 are controlled to be turned off. The voltage difference between the upper and lower plates of the third capacitor C3 is equal to the output voltage. Since the capacitor voltage does not change suddenly, the input voltage minus the output voltage equals the output voltage, that is, the output voltage is equal to half of the input voltage.

[0099] The present application can realize a 2:1 voltage-dividing charge pump through a single tape-out, so that the four switching tubes 1222 in the integrated circuit unit 12 can be fully utilized.

[0100] The present application provides an electronic device, including a power chip 10 as in any of the above embodiments, and thus can also achieve the same technical effects. To avoid repetition, it will not be described here.

[0101] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0102] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A power chip, characterized in that: The power chip includes: An integrated circuit unit, the integrated circuit unit comprising a plurality of pins, the integrated circuit unit further comprising: A power circuit, the power circuit comprising a plurality of switching tubes, the switching tubes comprising a first main terminal, a second main terminal and a control terminal, the first main terminal and the second main terminal of each switching tube being electrically connected to one of the pins respectively; A switching circuit, wherein the input end of the switching circuit is used to receive a control signal, the output end of the switching circuit is electrically connected to the control terminal of each of the switching tubes respectively, the switching circuit has multiple switching states, and the switching circuit is used to switch the switching states to switch the chip function of the power chip.

2. The power chip according to claim 1, characterized in that: The switch circuit is further configured to switch the switch state to switch the corresponding relationship between the control terminals of the plurality of switch tubes and the control signals to switch the chip function of the power chip.

3. The power chip according to claim 2, characterized in that: The power supply chip is a neutral point clamped three-level buck circuit chip or a charge pump circuit chip; The plurality of switch tubes include a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; The input end of the switching circuit is used to receive the control signal of the first switching tube, the control signal of the second switching tube, the control signal of the third switching tube and the control signal of the fourth switching tube, so as to control the first switching tube, the second switching tube, the third switching tube and the fourth switching tube to be turned on or off respectively.

4. The power chip according to claim 2, characterized in that: The power supply chip is a voltage regulating circuit chip; The plurality of switch tubes include a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, the first switch tube and the second switch tube are connected in parallel, and the third switch tube and the fourth switch tube are connected in parallel; The input end of the switching circuit is used to receive control signals of the first switching tube and the second switching tube, as well as control signals of the third switching tube and the fourth switching tube, so as to control the first switching tube and the second switching tube to be synchronously turned on or off, and to control the third switching tube and the fourth switching tube to be synchronously turned on or off.

5. The power chip according to claim 2, characterized in that: The plurality of pins include a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a switch node pin and a ground pin; The plurality of switch tubes include a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; Among them, the first pin is electrically connected to the second main terminal of the first switch tube, the second pin is electrically connected to the first main terminal of the second switch tube, the third pin is electrically connected to the second main terminal of the third switch tube, the fourth pin is electrically connected to the first main terminal of the fourth switch tube, the fifth pin is electrically connected to the second main terminal of the second switch tube, the sixth pin is electrically connected to the first main terminal of the first switch tube, the switch node pin is electrically connected to the first main terminal of the third switch tube, and the ground pin is electrically connected to the second main terminal of the fourth switch tube.

6. The power chip according to claim 5, characterized in that: The switching circuit comprises: a first switch element, wherein a first end of the first switch element is electrically connected to the control terminal of the first switch tube, and a second end of the first switch element is electrically connected to the input end of the switch circuit; a second switch element, wherein a first end of the second switch element is electrically connected to the first end of the first switch element; a third switch element, wherein a first end of the third switch element is electrically connected to the second end of the second switch element, and a second end of the third switch element is electrically connected to the control terminal of the second switch tube; a fourth switch element, wherein a first end of the fourth switch element is electrically connected to the second end of the third switch element, and a second end of the fourth switch element is electrically connected to the input end of the switch circuit; a fifth switch element, wherein a first end of the fifth switch element is electrically connected to the control terminal of the third switch tube, and a second end of the fifth switch element is electrically connected to the input end of the switch circuit; a sixth switch element, wherein a first end of the sixth switch element is electrically connected to the first end of the fifth switch element; a seventh switch element, wherein a first end of the seventh switch element is electrically connected to the second end of the sixth switch element, and a second end of the seventh switch element is electrically connected to the control terminal of the fourth switch tube; An eighth switch element, wherein a first end of the eighth switch element is electrically connected to the second end of the seventh switch element, and a second end of the eighth switch element is electrically connected to the input end of the switch circuit.

7. The power chip according to claim 6, characterized in that: The power supply chip is a neutral point clamped three-level buck circuit chip, the first pin and the second pin are short-circuited, the third pin and the fourth pin are short-circuited, and the fifth pin and the switch node pin are short-circuited. The switching state is: the first switch element, the fourth switch element, the fifth switch element, and the eighth switch element are closed, and the second switch element, the third switch element, the sixth switch element, and the seventh switch element are open.

8. The power chip according to claim 7, characterized in that: The power chip further includes: an input terminal and an output terminal, wherein the input terminal is electrically connected to the sixth pin; a first capacitor, wherein a first end of the first capacitor is electrically connected to the second pin, and a second end of the first capacitor is electrically connected to the third pin; a first inductor, wherein a first end of the first inductor is electrically connected to the switch node pin, and a second end of the first inductor is electrically connected to the output terminal; A second capacitor, wherein a first end of the second capacitor is electrically connected to the second end of the first inductor, and a second end of the second capacitor is grounded.

9. The power chip according to claim 7 or 8, characterized in that: The input end of the switching circuit is used to receive a first control signal, a second control signal, a third control signal, and a fourth control signal; the second end of the first switching element is used to receive the first control signal; the second end of the fourth switching element is used to receive the second control signal; the second end of the fifth switching element is used to receive the third control signal; and the second end of the eighth switching element is used to receive the fourth control signal; The neutral point clamped three-level buck circuit chip has a first phase, a second phase, a third phase, and a fourth phase. When the signal duty cycle of the neutral point clamped three-level buck circuit chip is less than a duty cycle threshold, in the first phase, the first switch tube and the third switch tube are turned on, and the second switch tube and the fourth switch tube are turned off; in the second phase, the third switch tube and the fourth switch tube are turned on, and the first switch tube and the second switch tube are turned off; in the third phase, the second switch tube and the fourth switch tube are turned on, and the first switch tube and the third switch tube are turned off; in the fourth phase, the third switch tube and the fourth switch tube are turned on, and the first switch tube and the second switch tube are turned off; When the signal duty cycle of the neutral point clamped three-level buck circuit chip is greater than or equal to the duty cycle threshold, in the first phase, the first switch tube and the second switch tube are turned on, and the third switch tube and the fourth switch tube are turned off; in the second phase, the first switch tube and the third switch tube are turned on, and the second switch tube and the fourth switch tube are turned off; in the third phase, the first switch tube and the second switch tube are turned on, and the third switch tube and the fourth switch tube are turned off; in the fourth phase, the second switch tube and the fourth switch tube are turned on, and the first switch tube and the third switch tube are turned off.

10. The power chip according to claim 6, characterized in that: The power supply chip is a voltage regulating circuit chip, the first pin, the fourth pin, the fifth pin and the switch node pin are electrically connected, the third pin and the ground pin are electrically connected, and the second pin and the sixth pin are electrically connected. The switching state is: the first switch element, the fourth switch element, the fifth switch element and the eighth switch element are disconnected, and the second switch element, the third switch element, the sixth switch element and the seventh switch element are closed.

11. The power chip according to claim 10, characterized in that: The power chip further includes: an input terminal and an output terminal, wherein the output terminal is electrically connected to the sixth pin; a second inductor, wherein a first end of the second inductor is electrically connected to the switch node pin, and a second end of the second inductor is electrically connected to the input terminal; A third capacitor, wherein a first end of the third capacitor is electrically connected to the input terminal, and a second end of the third capacitor is grounded.

12. The power chip according to claim 10, characterized in that: The power chip further includes: an input terminal and an output terminal, wherein the input terminal is electrically connected to the sixth pin; a second inductor, wherein a first end of the second inductor is electrically connected to the switch node pin, and a second end of the second inductor is electrically connected to the output terminal; A third capacitor, wherein a first end of the third capacitor is electrically connected to the output terminal, and a second end of the third capacitor is grounded.

13. The power chip according to claim 6, characterized in that: The power supply chip is a charge pump circuit chip, the first pin is short-circuited with the switch node pin, the second pin is short-circuited with the sixth pin, the fifth pin is short-circuited with the fourth pin, and the third pin is electrically connected to the ground pin. The switching state of the switching circuit is: the first switch element, the fourth switch element, the fifth switch element and the eighth switch element are closed, and the second switch element, the third switch element, the sixth switch element and the seventh switch element are disconnected.

14. The power chip according to claim 13, characterized in that: The power chip further includes: an input terminal and an output terminal, wherein the input terminal is electrically connected to the sixth pin; a fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the first pin, and a second end of the fourth capacitor is electrically connected to the fifth pin; a fifth capacitor, wherein a first end of the fifth capacitor is electrically connected to the output terminal, and a second end of the fifth capacitor is grounded.

15. The power chip according to claim 14, characterized in that: The input end of the switching circuit is used to receive a fifth control signal, a sixth control signal, a seventh control signal, and an eighth control signal; the second end of the first switching element is used to receive the fifth control signal, the second end of the fourth switching element is used to receive the sixth control signal, the second end of the fifth switching element is used to receive the seventh control signal, and the second end of the eighth switching element is used to receive the eighth control signal; In which, the charge pump circuit chip has a first phase and a second phase; in the first phase, the first switch tube and the fourth switch tube are turned on, and the second switch tube and the third switch tube are turned off; in the second phase, the second switch tube and the third switch tube are turned on, and the first switch tube and the fourth switch tube are turned off.

16. The power chip according to claim 13, characterized in that: The power chip further includes: an input terminal and an output terminal, wherein the output terminal is electrically connected to the sixth pin; a fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the switch node pin, and a second end of the fourth capacitor is electrically connected to the input terminal; a fifth capacitor, wherein a first end of the fifth capacitor is electrically connected to the input terminal, and a second end of the fifth capacitor is grounded.

17. The power chip according to claim 16, characterized in that: The input end of the switching circuit is used to receive a fifth control signal, a sixth control signal, a seventh control signal, and an eighth control signal; the second end of the first switching element is used to receive the fifth control signal, the second end of the fourth switching element is used to receive the sixth control signal, the second end of the fifth switching element is used to receive the seventh control signal, and the second end of the eighth switching element is used to receive the eighth control signal; The charge pump circuit chip has a first phase and a second phase; in the first phase, the second switch tube and the third switch tube are turned on, and the first switch tube and the fourth switch tube are turned off; in the second phase, the first switch tube and the fourth switch tube are turned on, and the second switch tube and the third switch tube are turned off.

18. An electronic device, characterized in that: include: The power chip according to any one of claims 1 to 17.

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