A Low-Jitter Injection Locked Phase-Locked Loop Based on Multiphase Injection

Abstract

This invention relates to the field of radio frequency integrated circuit technology, specifically providing a low-jitter injection-locked phase-locked loop (PLL) based on multiphase injection, comprising an injection-locking path unit, a locking unit, and an injection-locked ring oscillator. The injection-locking path unit generates a multiphase injection signal and a complementary injection signal based on a received reference signal. The injection-locked ring oscillator receives the multiphase injection signal and the complementary injection signal and generates an oscillation signal. Then, the locking unit locks the injection-locked PLL based on the generated oscillation signal. This application generates multiphase injection signals and complementary injection signals through the injection-locking path unit, thereby performing multiphase direct injection and cross-coupled complementary injection on the injection-locked ring oscillator. Multiphase direct injection can reduce the jitter of the ring oscillator-based PLL, and cross-coupled complementary injection eliminates the phase shift caused by multiphase direct injection, further improving the injection strength and effectively expanding the noise suppression bandwidth.

Description

Technical Field

[0001] This application relates to the field of radio frequency integrated circuit technology, and in particular to a low-jitter injection-locked phase-locked loop based on multiphase injection. Background Technology

[0002] A phase-locked loop (PLL) is a precision electronic control system whose core function is to precisely and automatically track and lock the phase and frequency of an output signal to an input reference signal. It works by continuously comparing the phase difference between the input signal and the feedback output signal, converting this difference into an error voltage. This error voltage is then processed by a loop filter to control the output frequency of a voltage-controlled oscillator (VCO), thus forming a closed-loop feedback circuit. The ultimate goal is to reduce the phase error to near zero, achieving a high degree of synchronization between the output and input signals in both frequency and phase. Due to this characteristic, PLLs are widely used in frequency synthesis, clock recovery, modulation and demodulation, and various electronic systems requiring high-precision clock synchronization.

[0003] In system-on-chip (SoC) design, phase-locked loops (PLLs) implemented with ring oscillators are favored due to their significant advantages: compared to LC oscillator PLLs, they offer a wider frequency tuning range (accommodating multi-band requirements), an extremely compact circuit structure (saving area and reducing cost), and inherent multi-phase clock output capability (such as quadrature signals, crucial for high-speed serial interfaces and clock distribution networks). However, their inherently relatively poor phase noise and jitter performance constitute a key bottleneck. This high jitter significantly increases the timing uncertainty of the clock signal, making it difficult to meet the performance requirements of applications with extremely stringent timing accuracy and noise requirements (such as high-speed ADC / DAC sampling clocks and millimeter-wave communications). Therefore, despite their significant advantages in area and integration, phase noise / jitter remains a major constraint limiting the widespread application of ring oscillator PLLs in high-performance applications.

[0004] Therefore, effectively improving the phase noise suppression capability and jitter performance of ring oscillators-based phase-locked loops to overcome their inherent defects and fully unleash their application potential in wide tuning range, small area and multi-phase output is a key technical challenge that urgently needs to be solved by technicians in this field. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a low-jitter injection-locked loop (PLL) based on multiphase injection, which not only reduces the jitter of PLLs based on ring oscillators but also improves the phase noise suppression capability of PLLs based on ring oscillators.

[0006] To achieve the objectives of this application, the following technical solution is provided:

[0007] This application provides a low-jitter injection-locked phase-locked loop based on multiphase injection, comprising: an injection locking path unit and an injection-locked phase-locked loop;

[0008] The injection-locked phase-locked loop includes a locking unit and an injection-locked ring oscillator. The input terminal of the injection-locked ring oscillator is connected to the output terminal of the locking unit and the output terminal of the injection-locked path unit.

[0009] The input terminal of the locking unit is connected to the output terminal of the injection locking ring oscillator;

[0010] The injection locking path unit is used to receive a reference signal and generate an injection signal based on the reference signal. The injection signal includes a polyphase injection signal and a complementary injection signal.

[0011] The injection-locked ring oscillator is used to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is a control voltage signal output by the locking unit;

[0012] The locking unit is used to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal. The first signal is used for locking the injection-locked phase-locked loop.

[0013] Furthermore, the injection locking path unit includes a pulse generator, a phase shifter, and a complementary injection unit;

[0014] The input terminal of the pulse generator is connected to the reference signal, and the output terminal is connected to the input terminal of the phase shifter, the input terminal of the complementary injection unit, and the input terminal of the injection-locked ring oscillator.

[0015] The output of the phase shifter and the output of the complementary injection unit are both connected to the input of the injection-locked ring oscillator.

[0016] The multiphase injection signal includes a first phase shift injection signal, a second phase shift injection signal, and a third phase shift injection signal;

[0017] The pulse generator is used to receive a reference signal and generate a first phase-shift injection signal based on the reference signal;

[0018] The phase shifter is used to receive the first phase shift injection signal and generate the second phase shift injection signal and the third phase shift injection signal based on the first phase shift injection signal;

[0019] The complementary injection unit is used to receive the first phase-shift injection signal and generate the complementary injection signal based on the first phase-shift injection signal.

[0020] Furthermore, in the multiphase injection signals, the phase shifts of the first phase shift injection signal, the second phase shift injection signal, and the third phase shift injection signal are 60°, 120°, and 180°, respectively.

[0021] Furthermore, the pulse generator includes an AND gate, a first NOT gate, and a variable delay unit;

[0022] The input terminal of the variable delay unit and the first input terminal of the AND gate are both connected to the reference signal;

[0023] The input of the first NOT gate is connected to the output of the variable delay unit;

[0024] The second input terminal of the AND gate is connected to the output terminal of the first NOT gate;

[0025] The AND gate is used to receive the reference signal and the signal output by the first NOT gate, and to generate the first phase-shift injection signal based on the reference signal and the signal output by the first NOT gate.

[0026] Furthermore, the phase shifter includes a multiphase filter and a dual Gilbert unit;

[0027] The multiphase filter includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor;

[0028] One end of the first resistor is connected to the positive input terminal of the multiphase filter and one end of the first capacitor, and the other end is connected to one end of the second resistor, one end of the second capacitor and one end of the seventh capacitor.

[0029] The other end of the second resistor is connected to one end of the eighth capacitor and the first output terminal of the polyphase filter;

[0030] One end of the third resistor and one end of the third capacitor are both grounded, and the other end is connected to the other end of the first capacitor, one end of the fourth resistor and one end of the fourth capacitor.

[0031] The other end of the fourth resistor is connected to the other end of the second capacitor and the second output terminal of the polyphase filter;

[0032] One end of the fifth resistor and one end of the fifth capacitor are both grounded, and the other end is connected to the other end of the third capacitor, one end of the sixth resistor, and one end of the sixth capacitor.

[0033] The other end of the sixth resistor is connected together with the other end of the fourth capacitor and the third output terminal of the polyphase filter;

[0034] One end of the seventh resistor is connected to the other end of the seventh capacitor and the negative input terminal of the multiphase filter, and the other end is connected to the other end of the fifth capacitor, the other end of the eighth capacitor and one end of the eighth resistor.

[0035] The other end of the eighth resistor is connected together with the other end of the sixth capacitor and the fourth output terminal of the polyphase filter;

[0036] The first, second, third, and fourth output terminals of the polyphase filter are respectively connected to the first, second, third, and fourth input terminals of the dual Gilbert unit.

[0037] Furthermore, the dual Gilbert unit includes a ninth resistor, a tenth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

[0038] The first input terminal of the dual Gilbert unit is connected to the gates of the twelfth and thirteenth NMOS transistors, the second input terminal is connected to the gates of the eighteenth and fifteenth NMOS transistors, the third input terminal is connected to the gates of the eleventh and fourteenth NMOS transistors, the fourth input terminal is connected to the gates of the sixteenth and seventeenth NMOS transistors, the first output terminal is connected to the drains of the eleventh, thirteenth, fifteenth, and seventeenth NMOS transistors and one end of the ninth resistor, and the second output terminal is connected to the drains of the twelfth, fourteenth, sixteenth, and eighteenth NMOS transistors and one end of the tenth resistor.

[0039] The other end of the ninth resistor and the other end of the tenth resistor are both connected to a power source;

[0040] The gates of both the first NMOS transistor and the second NMOS transistor are connected to a fixed bias voltage;

[0041] The drain of the first NMOS transistor is connected to the source of the seventh and eighth NMOS transistors; the drain of the second NMOS transistor is connected to the source of the ninth and tenth NMOS transistors.

[0042] The drain of the seventh NMOS transistor is connected to the sources of the eleventh and twelfth NMOS transistors; the drain of the eighth NMOS transistor is connected to the sources of the thirteenth and fourteenth NMOS transistors; the drain of the ninth NMOS transistor is connected to the sources of the fifteenth and sixteenth NMOS transistors; and the drain of the tenth NMOS transistor is connected to the sources of the seventeenth and eighteenth NMOS transistors.

[0043] The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor, and its drain is connected to the gate of the seventh NMOS transistor and the source of the first PMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the second PMOS transistor, and its drain is connected to the gate of the eighth NMOS transistor and the source of the second PMOS transistor. The drains of the first PMOS transistor and the second PMOS transistor are connected.

[0044] The gate of the fifth NMOS transistor is connected to the gate of the third PMOS transistor, and its drain is connected to the gate of the ninth NMOS transistor and the source of the third PMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor, and its drain is connected to the gate of the tenth NMOS transistor and the source of the fourth PMOS transistor. The drains of the third PMOS transistor and the fourth PMOS transistor are connected.

[0045] The sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all grounded.

[0046] Furthermore, the complementary injection unit includes a second NOT gate and a transmission gate;

[0047] The input terminals of the second NOT gate and the transmission gate are both connected to the output terminal of the pulse generator;

[0048] The outputs of the second NOT gate and the transmission gate are respectively connected to the first output and the second output of the complementary injection unit;

[0049] The second NOT gate is used to receive the first phase shift injection signal and generate a first complementary injection signal based on the first phase shift injection signal;

[0050] The transmission gate is used to receive the first phase-shift injection signal and generate a second complementary injection signal based on the first phase-shift injection signal.

[0051] Furthermore, the injection-locked ring oscillator includes three injection transistors and three differential delay units, wherein the injection transistors are NMOS transistors;

[0052] The first input terminal and the second input terminal of the first differential delay unit are respectively connected to the first output terminal and the second output terminal of the third differential delay unit; the first input terminal and the second input terminal of the second differential delay unit are respectively connected to the first output terminal and the second output terminal of the first differential delay unit; the first input terminal and the second input terminal of the third differential delay unit are respectively connected to the first output terminal and the second output terminal of the second differential delay unit.

[0053] The gate of the first injection transistor is connected to the output terminal of the pulse generator, and its drain and source are respectively connected to the first output terminal and the second output terminal of the first differential delay unit; the gate of the second injection transistor is connected to the first output terminal of the dual Gilbert unit, and its drain and source are respectively connected to the first output terminal and the second output terminal of the second differential delay unit; the gate of the third injection transistor is connected to the second output terminal of the dual Gilbert unit, and its drain and source are respectively connected to the first output terminal and the second output terminal of the third differential delay unit.

[0054] The third and fourth input terminals of the second differential delay unit are respectively connected to the first and second output terminals of the complementary injection unit, and are used to receive the first complementary injection signal and the second complementary injection signal.

[0055] The first injection tube, the second injection tube, and the third injection tube are respectively used to receive the first phase shift injection signal, the second phase shift injection signal, and the third phase shift injection signal.

[0056] Furthermore, the second differential delay unit includes a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor;

[0057] The first input terminal of the second differential delay unit is connected to the gates of the 20th NMOS transistor and the 6th PMOS transistor, the second input terminal is connected to the gates of the 19th NMOS transistor and the 5th PMOS transistor, the first output terminal is connected to the drains of the 20th NMOS transistor, the 6th PMOS transistor, the second injection transistor, the 24th NMOS transistor, the 10th PMOS transistor, and the gates of the 22nd NMOS transistor and the 8th PMOS transistor, and the second output terminal is connected to the drains of the 19th NMOS transistor, the 5th PMOS transistor, the 22nd NMOS transistor, and the 8th PMOS transistor, the gates of the 24th NMOS transistor and the 10th PMOS transistor, and the source of the second injection transistor.

[0058] The gates of the seventh PMOS transistor and the ninth PMOS transistor are both connected to the third input terminal of the second differential delay unit, for receiving the first complementary injection signal.

[0059] The gates of the 21st NMOS transistor and the 23rd NMOS transistor are both connected to the fourth input terminal of the second differential delay unit to receive the second complementary injection signal;

[0060] The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the drain of the twenty-first NMOS transistor is connected to the source of the twenty-second NMOS transistor; and the drain of the twenty-third NMOS transistor is connected to the source of the twenty-fourth NMOS transistor.

[0061] The sources of the fifth, sixth, seventh, and ninth PMOS transistors are all connected to a power supply.

[0062] The sources of the nineteenth NMOS transistor, the twentieth NMOS transistor, the twentieth eleventh NMOS transistor, and the twenty-third NMOS transistor are all grounded.

[0063] Furthermore, the locking unit includes a subsampling loop unit, a frequency-locking loop unit, a loop filter, and a buffer;

[0064] The input terminal of the loop filter is connected to the output terminal of the subsampling loop unit and the output terminal of the frequency-locked loop unit, and the output terminal is connected to the input terminal of the injection-locked ring oscillator;

[0065] The loop filter is used to receive current signals and generate control voltage signals based on the current signals. The current signals include a first current signal and a second current signal, which are the current signals output by the subsampling loop unit and the frequency-locked loop unit, respectively. The control voltage signals include a first control voltage signal and a second control voltage signal, whereby the first control voltage signal is generated based on the first current signal and the second control voltage signal is generated based on the second current signal.

[0066] The input terminal of the buffer is connected to the output terminal of the injection-locked ring oscillator, and is used to receive the first oscillation signal and perform drive enhancement processing on the first oscillation signal to obtain the second oscillation signal;

[0067] The frequency-locked loop unit includes a frequency divider, a frequency-phase detector, and a charge pump; the input terminal of the frequency divider is connected to the output terminal of the buffer; the first input terminal of the frequency-phase detector is connected to the output terminal of the frequency divider, and the second input terminal is connected to the reference signal; the input terminal of the charge pump is connected to the output terminal of the frequency-phase detector, and the output terminal is connected to the input terminal of the loop filter; the frequency-locked loop is used to receive the reference signal and the second oscillation signal, and generate the first current signal based on the reference signal and the second oscillation signal;

[0068] The subsampling loop unit includes a subsampling phase detector and a transconductance module; the first input terminal of the subsampling phase detector is connected to a reference signal, and the second input terminal is connected to the output terminal of the buffer; the input terminal of the transconductance module is connected to the output terminal of the subsampling phase detector, and the output terminal is connected to the loop filter; the subsampling loop unit is used to receive the reference signal and the second oscillation signal, and generate the second current signal based on the reference signal and the second oscillation signal.

[0069] Beneficial effects:

[0070] This application generates multi-phase injection signals and complementary injection signals by injecting a locked path unit, thereby performing multi-phase direct injection and cross-coupled complementary injection on the injection-locked ring oscillator. Multi-phase direct injection can reduce the jitter of the ring oscillator-based phase-locked loop, and then multi-path injection is performed through cross-coupled complementary injection, thereby eliminating the phase offset caused by multi-phase direct injection, further improving the injection strength, and effectively expanding the noise suppression bandwidth of the ring oscillator-based phase-locked loop. Attached Figure Description

[0071] The accompanying drawings are provided to further understand this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof.

[0072] Figure 1 This application provides a schematic diagram of the composition structure of a low-jitter injection-locked phase-locked loop based on multiphase injection, as shown in the embodiments of this application.

[0073] Figure 2 A schematic diagram of the composition structure of a low-jitter injection-locked phase-locked loop based on multiphase injection provided in this application embodiment;

[0074] Figure 3 A circuit diagram of a pulse generator based on a low-jitter injection-locked phase-locked loop provided in this application embodiment;

[0075] Figure 4 A schematic diagram of signal injection for a phase shifter and an injection-locked ring oscillator based on a low-jitter injection-locked phase-locked loop using multiphase injection, provided for an embodiment of this application.

[0076] Figure 5 A circuit diagram of a low-jitter injection-locked phase-locked loop (PLL) based on multiphase injection is provided for an embodiment of this application.

[0077] Figure 6 A circuit diagram of a dual Gilbert cell based on a low-jitter injection-locked phase-locked loop provided in an embodiment of this application;

[0078] Figure 7 The circuit diagram shows the second differential delay unit of a ring oscillator based on a low-jitter injection-locked phase-locked loop with multiphase injection, as provided in an embodiment of this application. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0080] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this application, unless otherwise stated, "multiple" means two or more.

[0081] An embodiment of this application provides a low-jitter injection-locked phase-locked loop based on multiphase injection, comprising: an injection locking path unit and an injection-locked phase-locked loop;

[0082] The injection-locked phase-locked loop includes a locking unit and an injection-locked ring oscillator. The input terminal of the injection-locked ring oscillator is connected to the output terminal of the locking unit and the output terminal of the injection-locked path unit.

[0083] The input terminal of the locking unit is connected to the output terminal of the injection locking ring oscillator;

[0084] The injection locking path unit is used to receive a reference signal and generate an injection signal based on the reference signal. The injection signal includes a polyphase injection signal and a complementary injection signal.

[0085] The injection-locked ring oscillator is used to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is a control voltage signal output by the locking unit;

[0086] The locking unit is used to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal. The first signal is used for locking the injection-locked phase-locked loop.

[0087] The technical solution of the present invention is described below with reference to the embodiments shown in the accompanying drawings:

[0088] like Figure 1 As shown, a low-jitter injection-locked phase-locked loop based on multiphase injection includes an injection locking path unit 11 and an injection locking phase-locked loop 12;

[0089] The injection-locked phase-locked loop 12 includes a locking unit 121 and an injection-locked ring oscillator 122. The input terminal of the injection-locked ring oscillator 122 is connected to the output terminal of the locking unit 121 and the output terminal of the injection-locked path unit 11.

[0090] The input terminal of the locking unit 121 is connected to the output terminal of the injection locking ring oscillator 122;

[0091] The injection locking path unit 11 is used to receive a reference signal and generate an injection signal based on the reference signal. The injection signal includes a polyphase injection signal and a complementary injection signal.

[0092] The injection-locked ring oscillator 122 is used to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is the control voltage signal output by the locking unit 121;

[0093] The locking unit 121 is used to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal. The first signal is used for locking the injection-locked phase-locked loop 12.

[0094] It should be noted that phase noise and jitter are major limiting factors for the widespread application of ring oscillator phase-locked loops (PLLs) in high-performance applications. Therefore, both problems need to be addressed simultaneously to enable PLLs to be used in applications with wide tuning ranges, small area, and multi-phase output. Thus, the injection-locked-path unit of this invention improves the jitter performance of the PLL through multi-phase injection, and also utilizes both direct injection and cross-coupling complementary injection for multi-path injection. The phase shift from direct injection is eliminated through the injection of complementary signals, thereby further improving the injection strength and expanding the noise suppression bandwidth.

[0095] In the embodiments of this application, such as Figure 2 As shown, the injection locking path unit includes a pulse generator, a phase shifter, and a complementary injection unit;

[0096] The input terminal of the pulse generator is connected to the reference signal, and the output terminal is connected to the input terminal of the phase shifter, the input terminal of the complementary injection unit, and the input terminal of the injection-locked ring oscillator.

[0097] The output of the phase shifter and the output of the complementary injection unit are both connected to the input of the injection-locked ring oscillator.

[0098] The multiphase injection signal includes a first phase shift injection signal, a second phase shift injection signal, and a third phase shift injection signal;

[0099] The pulse generator is used to receive a reference signal and generate a first phase-shift injection signal based on the reference signal;

[0100] The phase shifter is used to receive the first phase shift injection signal and generate the second phase shift injection signal and the third phase shift injection signal based on the first phase shift injection signal;

[0101] The complementary injection unit is used to receive the first phase-shift injection signal and generate the complementary injection signal based on the first phase-shift injection signal.

[0102] Understandably, the pulse generator generates a first phase-shift injection signal based on a reference signal. This first phase-shift injection signal is then used as the initial signal, processed by a phase shifter to generate a second and third phase-shift injection signal. These three signals correspond to the three differential delay units of the injection-locked ring oscillator, respectively, thus enabling multi-phase direct injection into the injection-locked ring oscillator. The first phase-shift injection signal is then processed by a complementary injection unit to generate a complementary injection signal, which is used for subsequent cross-coupling complementary injection into the injection-locked ring oscillator.

[0103] In this embodiment, the phase shifts of the first phase shift injection signal, the second phase shift injection signal, and the third phase shift injection signal are 60°, 120°, and 180°, respectively.

[0104] It is understandable that, since this embodiment uses a three-stage ring oscillator, the output phase shift difference of each differential delay unit of the three-stage ring oscillator is 60° in order to meet the oscillation conditions. Therefore, the phase shift of the multiphase injection signal should correspond to the output phase shift of each differential delay unit of the three-stage ring oscillator to achieve a good injection effect.

[0105] In this embodiment, as Figure 3 As shown, the pulse generator includes an AND gate, a first NOT gate, and a variable delay unit;

[0106] The input terminal of the variable delay unit and the first input terminal of the AND gate are both connected to the reference signal;

[0107] The input of the first NOT gate is connected to the output of the variable delay unit;

[0108] The second input terminal of the AND gate is connected to the output terminal of the first NOT gate;

[0109] The AND gate is used to receive the reference signal and the signal output by the first NOT gate, and to generate the first phase-shift injection signal based on the reference signal and the signal output by the first NOT gate.

[0110] Understandably, the pulse generator employs an AND gate, a variable delay unit, and a first NOT gate to form a narrow pulse generation circuit. The reference signal is delayed by the variable delay unit, flipped by the NOT gate, and then input together with the original reference signal into the AND gate. This logical AND operation generates a Pul_60 narrow pulse, i.e., a 60° phase-shifted pulse. The variable delay unit uses a transistor-level delay unit design, enabling precise adjustable delay. If its delay is... Then the narrow pulse width of the AND gate output is also... This pulse signal serves as the initial injection signal, i.e., the first phase-shift injection signal.

[0111] In this embodiment, as Figure 4 As shown, the phase shifter includes a multiphase filter and a dual Gilbert unit;

[0112] like Figure 5 As shown, the multiphase filter includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8.

[0113] One end of the first resistor R1 is connected to the positive input terminal VIN+ of the multiphase filter and one end of the first capacitor C1, and the other end is connected to one end of the second resistor R2, one end of the second capacitor C2 and one end of the seventh capacitor C7.

[0114] The other end of the second resistor R2 is connected to one end of the eighth capacitor C8 and the first output terminal VI- of the polyphase filter;

[0115] One end of the third resistor R3 and one end of the third capacitor C3 are both grounded, and the other end is connected to the other end of the first capacitor C1, one end of the fourth resistor R4 and one end of the fourth capacitor C4.

[0116] The other end of the fourth resistor R4 is connected to the other end of the second capacitor C2 and the second output terminal VQ+ of the polyphase filter.

[0117] One end of the fifth resistor R5 and one end of the fifth capacitor C5 are both grounded, and the other end is connected to the other end of the third capacitor C3, one end of the sixth resistor R6 and one end of the sixth capacitor C6.

[0118] The other end of the sixth resistor R6 is connected to the other end of the fourth capacitor C4 and the third output terminal VI+ of the polyphase filter.

[0119] One end of the seventh resistor R7 is connected to the other end of the seventh capacitor C7 and the negative input terminal VIN- of the multiphase filter, and the other end is connected to the other end of the fifth capacitor C5, the other end of the eighth capacitor C8 and one end of the eighth resistor R8.

[0120] The other end of the eighth resistor R8 is connected to VQ- along with the other end of the sixth capacitor C6 and the fourth output terminal of the polyphase filter.

[0121] The first output terminal VI-, the second output terminal VQ+, the third output terminal VI+, and the fourth output terminal VQ- of the polyphase filter are respectively connected to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the dual Gilbert unit.

[0122] It is understandable that the input signals of the first input terminal VIN+ and the second input terminal VIN- of the polyphase filter are a pair of differential inverted signals, that is, the first input terminal VIN+ of the polyphase filter is connected to the Pul_60 signal, and the second input terminal is connected to the inverted signal of Pul_60.

[0123] like Figure 6 As shown, the dual Gilbert unit includes a ninth resistor R9, a tenth resistor R10, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4;

[0124] The first input terminal I- of the dual Gilbert unit is connected to the gates of the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13. The second input terminal Q+ is connected to the gates of the eighteenth NMOS transistor N18 and the fifteenth NMOS transistor N15. The third input terminal I+ is connected to the gates of the eleventh NMOS transistor N11 and the fourteenth NMOS transistor N14. The fourth input terminal Q- is connected to the gates of the sixteenth NMOS transistor N16 and the seventeenth NMOS transistor N17. The first output terminal... The second output terminal is connected together with the drains of the eleventh NMOS transistor N11, the thirteenth NMOS transistor N13, the fifteenth NMOS transistor N15, and the seventeenth NMOS transistor N17, as well as one end of the ninth resistor R9. It is connected together with the drains of the twelfth NMOS transistor N12, the fourteenth NMOS transistor N14, the sixteenth NMOS transistor N16 and the eighteenth NMOS transistor N18, as well as one end of the tenth resistor R10;

[0125] The other end of the ninth resistor R9 and the other end of the tenth resistor R10 are both connected to a power source.

[0126] The gates of both the first NMOS transistor N1 and the second NMOS transistor N2 are connected to a fixed bias voltage;

[0127] The drain of the first NMOS transistor N1 is connected to the source of the seventh NMOS transistor N7 and the eighth NMOS transistor N8; the drain of the second NMOS transistor N2 is connected to the source of the ninth NMOS transistor N9 and the tenth NMOS transistor N10.

[0128] The drain of the seventh NMOS transistor N7 is connected to the sources of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12; the drain of the eighth NMOS transistor N8 is connected to the sources of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14; the drain of the ninth NMOS transistor N9 is connected to the sources of the fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16; and the drain of the tenth NMOS transistor N10 is connected to the sources of the seventeenth NMOS transistor N17 and the eighteenth NMOS transistor N18.

[0129] The gate of the third NMOS transistor N3 is connected to the gate of the first PMOS transistor P1, and its drain is connected to the gate of the seventh NMOS transistor N7 and the source of the first PMOS transistor P1. The gate of the fourth NMOS transistor N4 is connected to the gate of the second PMOS transistor P2, and its drain is connected to the gate of the eighth NMOS transistor N8 and the source of the second PMOS transistor P2. The drains of the first PMOS transistor P1 and the second PMOS transistor P2 are connected.

[0130] The gate of the fifth NMOS transistor N5 is connected to the gate of the third PMOS transistor P3, and its drain is connected to the gate of the ninth NMOS transistor N9 and the source of the third PMOS transistor P3. The gate of the sixth NMOS transistor N6 is connected to the gate of the fourth PMOS transistor P4, and its drain is connected to the gate of the tenth NMOS transistor N10 and the source of the fourth PMOS transistor P4. The drains of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected.

[0131] The sources of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are all grounded.

[0132] Understandably, in combination Figure 5 and Figure 6As shown, the first output terminal VI-, the second output terminal VQ+, the third output terminal VI+, and the fourth output terminal VQ- of the multiphase filter are respectively connected to the first input terminal I-, the second input terminal Q+, the third input terminal I+, and the fourth input terminal Q- of the dual Gilbert unit. The phase shifter includes a multiphase filter and a current vector synthesizer. The multiphase filter uses four sets of RC networks, each generating a fixed delay to filter and phase-modulate Pul_60, generating multi-phase pulse signals. The current vector synthesizer is based on the dual Gilbert unit design, vector-adding the multi-phase pulse signals after RC filtering to finally generate Pul_120 (120° phase shift) and Pul_180 (180° phase shift) pulse signals, which, along with Pul_60, are used for subsequent multiphase direct injection. The dual Gilbert unit includes a first Gilbert unit and a second Gilbert unit. The output terminal VOUT+ of the first Gilbert unit outputs the Pul_120 signal, and the output terminal VOUT+ of the second Gilbert unit outputs the Pul_180 signal.

[0133] In this embodiment, as Figure 2 As shown, the complementary injection unit includes a second NOT gate and a transmission gate;

[0134] The input terminals of the second NOT gate and the transmission gate are both connected to the output terminal of the pulse generator;

[0135] The outputs of the second NOT gate and the transmission gate are respectively connected to the first output and the second output of the complementary injection unit;

[0136] The second NOT gate is used to receive the first phase shift injection signal and generate a first complementary injection signal based on the first phase shift injection signal;

[0137] The transmission gate is used to receive the first phase-shift injection signal and generate a second complementary injection signal based on the first phase-shift injection signal.

[0138] It is understood that after the transmission gate of the complementary injection unit receives the initial signal Pul_60, it outputs the first complementary injection signal INJ_P; after the second NOT gate of the complementary injection unit receives the initial signal Pul_60, it outputs the second complementary injection signal INJ_N; INJ_N and INJ_P are complementary injection signals, that is, a pair of inverted pulse signals. The signal after the Pul_60 signal is transmitted through the transmission gate is in phase with the Pul_60 signal, and the signal after the Pul_60 signal is output through the inverter is inverted with the Pul_60 signal. Therefore, they constitute a pair of complementary injection signals for subsequent cross-coupling complementary injection.

[0139] In this embodiment, the injection-locked ring oscillator includes three injection transistors and three differential delay units, wherein the injection transistors are NMOS transistors;

[0140] The first input terminal and the second input terminal of the first differential delay unit are respectively connected to the first output terminal and the second output terminal of the third differential delay unit; the first input terminal and the second input terminal of the second differential delay unit are respectively connected to the first output terminal and the second output terminal of the first differential delay unit; the first input terminal and the second input terminal of the third differential delay unit are respectively connected to the first output terminal and the second output terminal of the second differential delay unit.

[0141] The gate of the first injection transistor is connected to the output terminal of the pulse generator, and its drain and source are respectively connected to the first output terminal and the second output terminal of the first differential delay unit; the gate of the second injection transistor is connected to the first output terminal of the dual Gilbert unit, and its drain and source are respectively connected to the first output terminal and the second output terminal of the second differential delay unit; the gate of the third injection transistor is connected to the second output terminal of the dual Gilbert unit, and its drain and source are respectively connected to the first output terminal and the second output terminal of the third differential delay unit.

[0142] The third and fourth input terminals of the second differential delay unit are respectively connected to the first and second output terminals of the complementary injection unit, and are used to receive the first complementary injection signal and the second complementary injection signal.

[0143] The first injection tube, the second injection tube, and the third injection tube are respectively used to receive the first phase shift injection signal, the second phase shift injection signal, and the third phase shift injection signal.

[0144] It is understandable that, such as Figure 4 As shown, the injection-locked ring oscillator consists of three stages of differential delay units and three injection transistors. The CK0 and CK180 signals are the inputs to the first-stage delay unit, indicating that the phases of the signals entering the first-stage delay unit are 0° and 180°, respectively. The CK60 and CK240 signals are the inputs to the second-stage delay unit, indicating that the phases of the signals entering the second-stage delay unit are 60° and 240°, respectively. The CK120 and CK300 signals are the inputs to the third-stage delay unit, indicating that the phases of the signals entering the third-stage delay unit are 120° and 300°, respectively. The injection terminal of the injection transistor corresponding to the first-stage differential delay unit is INJ3, used to receive the Pul_180 signal; the injection terminal corresponding to the second-stage differential delay unit is INJ1, used to receive the Pul_60 signal; and the injection terminal corresponding to the third-stage differential delay unit is INJ2, used to receive the Pul_120 signal. The delay calculation formula for each stage of the delay unit is as follows:

[0145] ;

[0146] in, Delay for each delay unit, Let be the frequency of the oscillator. The clock period of the oscillator can be obtained from its frequency using the following formula:

[0147] ;

[0148] in, The frequency of the oscillator. Given the oscillator's period time, the total delay for the three stages can be obtained as follows: Furthermore, the phase shift of each differential delay unit is 60°, satisfying the oscillation conditions of a ring oscillator. An injection transistor is connected in parallel to the output of each differential delay unit. The gate of each injection transistor is controlled by a connected polyphase injection signal. For example, the polyphase injection signal connected to the gate of the injection transistor connected in parallel to the output of a first-stage differential delay unit is the first phase shift injection signal. The phase shift of each differential delay unit corresponds to the phase shift of the connected polyphase injection signal. When the injection transistor is turned on, it changes the current distribution of the differential pair, adjusting the phase of the oscillator to eliminate accumulated jitter. Because three injection points are used, the degradation of reference spurious signals caused by using large-size injection transistors is avoided.

[0149] In this embodiment, as Figure 7 As shown, the second differential delay unit includes the nineteenth NMOS transistor N19, the twentieth NMOS transistor N20, the twenty-first NMOS transistor N21, the twenty-second NMOS transistor N22, the twenty-third NMOS transistor N23, the twenty-fourth NMOS transistor N24, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the ninth PMOS transistor P9, and the tenth PMOS transistor P10;

[0150] The first input terminal of the second differential delay unit is connected to the gates of the twentieth NMOS transistor N20 and the sixth PMOS transistor P6. The second input terminal is connected to the gates of the nineteenth NMOS transistor N19 and the fifth PMOS transistor P5. The first output terminal is connected to the drains of the twentieth NMOS transistor N20, the sixth PMOS transistor P6, the second injection transistor, the twenty-fourth NMOS transistor N24, the tenth PMOS transistor P10, and the gates of the twelfth NMOS transistor N22 and the eighth PMOS transistor P8. The second output terminal is connected to the drains of the nineteenth NMOS transistor N19, the fifth PMOS transistor P5, the twenty-second NMOS transistor N22 and the eighth PMOS transistor P8, the gates of the twenty-fourth NMOS transistor N24 and the tenth PMOS transistor P10, and the source of the second injection transistor.

[0151] The gates of the seventh PMOS transistor P7 and the ninth PMOS transistor P9 are both connected to the third input terminal of the second differential delay unit, for receiving the first complementary injection signal.

[0152] The gates of the 21st NMOS transistor N21 and the 23rd NMOS transistor N23 are both connected to the fourth input terminal of the second differential delay unit to receive the second complementary injection signal;

[0153] The drain of the seventh PMOS transistor P7 is connected to the source of the eighth PMOS transistor P8; the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10; the drain of the twenty-first NMOS transistor N21 is connected to the source of the twenty-second NMOS transistor N22; and the drain of the twenty-third NMOS transistor N23 is connected to the source of the twenty-fourth NMOS transistor N24.

[0154] The sources of the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, and the ninth PMOS transistor P9 are all connected to a power supply.

[0155] The sources of the nineteenth NMOS transistor N19, the twentieth NMOS transistor N20, the eleventh NMOS transistor N21, and the thirteenth NMOS transistor N23 are all grounded.

[0156] It is understandable that, such as Figure 7 As shown, the injection terminal of the multiphase injection signal in each differential delay unit is the gate of the corresponding injection transistor. In the second differential delay unit, in addition to using the Pul_60 signal to inject the second differential delay unit's injection terminal INJ1, i.e., the gate of the first injection transistor N0, the second differential delay unit is also cross-coupled with INJ_N and INJ_P for complementary injection, thereby eliminating the phase shift caused by direct injection and multiphase injection, and extending the noise suppression bandwidth of the ring oscillator-based phase-locked loop.

[0157] Furthermore, it is understandable that, such as Figure 7As shown, after direct injection into Pul_60, if the current flows from the first output terminal to the second output terminal during the rising half of the Pul_60 pulse, the first injection transistor N0 provides an additional pull-down path, thereby accelerating the discharge process and causing the zero-crossing point of the oscillation signal to arrive earlier. Since this application uses complementary injection signals INJ_N and INJ_P for cross-coupling complementary injection, when the voltage at the second output terminal rises from GND (ground) to VDD / 2 (half the power supply voltage), the current flows from VDD to the first output terminal through inverter A, which consists of the 23rd NMOS transistor N23, the 24th NMOS transistor N24, the 9th PMOS transistor P9, and the 10th PMOS transistor P10. At the same time, the current flows from the second output terminal to ground through inverter B, which consists of the 21st NMOS transistor N21, the 22nd NMOS transistor N22, the 7th PMOS transistor P7, and the 8th PMOS transistor P8, thereby generating current negative feedback and slowing down the edge switching rate of the oscillation signal.

[0158] Similarly, if the voltage at the first output terminal is lower than the voltage at the second output terminal during the falling half of the Pul_60 pulse, the current of the N0 transistor reverses, slowing down the edge rise rate of the oscillation signal. Since this application uses complementary injection signals INJ_N and INJ_P for cross-coupling complementary injection, when the voltage at the second output terminal rises from the half-supply voltage VDD / 2 to the supply voltage VDD, current will flow from the first output terminal to ground through inverter A, and simultaneously, current will flow from VDD to the second output terminal through inverter B, thereby generating positive current feedback and accelerating the edge transition rate of the oscillation signal.

[0159] Since direct injection and complementary injection have opposite effects on the edge transition rate of the oscillation signal, complementary injection cancels out the phase shift of the oscillation signal caused by direct injection. At the same time, complementary injection increases the number of injection points, thereby increasing the injection intensity and thus improving the injection lock-in range, i.e., the noise suppression bandwidth.

[0160] In this embodiment, as Figure 2 As shown, the locking unit includes a subsampling loop unit, a frequency-locking loop unit, a loop filter, and a buffer;

[0161] The input terminal of the loop filter is connected to the output terminal of the subsampling loop unit and the output terminal of the frequency-locked loop unit, and the output terminal is connected to the input terminal of the injection-locked ring oscillator;

[0162] The loop filter is used to receive current signals and generate control voltage signals based on the current signals. The current signals include a first current signal and a second current signal, which are the current signals output by the subsampling loop unit and the frequency-locked loop unit, respectively. The control voltage signals include a first control voltage signal and a second control voltage signal, whereby the first control voltage signal is generated based on the first current signal and the second control voltage signal is generated based on the second current signal.

[0163] The input terminal of the buffer is connected to the output terminal of the injection-locked ring oscillator, and is used to receive the first oscillation signal and perform drive enhancement processing on the first oscillation signal to obtain the second oscillation signal;

[0164] The frequency-locked loop unit includes a frequency divider, a frequency-phase detector, and a charge pump; the input terminal of the frequency divider is connected to the output terminal of the buffer; the first input terminal of the frequency-phase detector is connected to the output terminal of the frequency divider, and the second input terminal is connected to the reference signal; the input terminal of the charge pump is connected to the output terminal of the frequency-phase detector, and the output terminal is connected to the input terminal of the loop filter; the frequency-locked loop is used to receive the reference signal and the second oscillation signal, and generate the first current signal based on the reference signal and the second oscillation signal;

[0165] The subsampling loop unit includes a subsampling phase detector and a transconductance module; the first input terminal of the subsampling phase detector is connected to a reference signal, and the second input terminal is connected to the output terminal of the buffer; the input terminal of the transconductance module is connected to the output terminal of the subsampling phase detector, and the output terminal is connected to the loop filter; the subsampling loop unit is used to receive the reference signal and the second oscillation signal, and generate the second current signal based on the reference signal and the second oscillation signal.

[0166] Understandably, the subsampling loop and the frequency-locked loop are used to lock the phase and frequency of the phase-locked loop, respectively. The frequency-locked loop works first to lock the frequency. After the frequency is locked, the frequency-locked loop stops working, and the subsampling loop starts phase tracking, which eventually locks the phase-locked loop based on the ring oscillator.

[0167] The frequency-locked loop uses a traditional tri-state phase detector (PFD) with dead time. The PFD detects the phase difference between the reference signal and the divider output signal. When the reference signal frequency... Oscillator frequency after division by N ,Right now At this time, the PFD outputs a "leading" pulse to control the charge pump's current injection. At this point, the PFD outputs a "hysteresis" pulse to control the charge pump's current extraction. The charge pump employs a current-driven design, outputting current... The control voltage is generated after integration by a third-order RC loop filter. , Adjust the oscillation frequency of the injection-locked ring oscillator until After frequency locking is completed, the loop bandwidth should be designed to be 1 / 10 to 1 / 20 of the reference frequency to balance locking time and stability. Once frequency locking is achieved, the subsampling loop begins operation. In this loop, the subsampling phase detector uses a low-frequency reference signal to subsample the high-frequency oscillator output signal, converting the phase error between the reference signal and the oscillator output into a voltage signal. Includes phase error information The signal is converted into a current signal by the transconductance module, and then a smooth control voltage signal is generated by a third-order loop filter. The phase of the oscillator output signal is precisely adjusted to ensure phase locking. This embodiment improves the injection strength and expands the noise suppression bandwidth through multi-phase injection and multi-path injection techniques, effectively suppressing jitter. At the same time, the subsampling phase-locked loop structure further reduces phase noise, providing a technical solution for the application of ring oscillators in millimeter-wave communication and high-speed data conversion systems with high clock accuracy and low jitter requirements.

[0168] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0169] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. This application is not limited to the exact structures described above and illustrated in the accompanying drawings, and it should not be considered that the specific implementation of this application is limited to these descriptions. For those skilled in the art, various changes and modifications made without departing from the concept of this application should be considered to fall within the protection scope of this application.

Claims

1. A low-jitter injection-locked phase-locked loop based on multiphase injection, characterized in that, Includes injection locking path unit and injection locking phase-locked loop; The injection-locked phase-locked loop includes a locking unit and an injection-locked ring oscillator. The input terminal of the injection-locked ring oscillator is connected to the output terminal of the locking unit and the output terminal of the injection-locked path unit. The input terminal of the locking unit is connected to the output terminal of the injection locking ring oscillator; The injection locking path unit is used to receive a reference signal and generate an injection signal based on the reference signal. The injection signal includes a polyphase injection signal and a complementary injection signal. The injection locking path unit includes a pulse generator, a phase shifter, and a complementary injection unit; The input terminal of the pulse generator is connected to the reference signal, and the output terminal is connected to the input terminal of the phase shifter, the input terminal of the complementary injection unit, and the input terminal of the injection-locked ring oscillator. The output of the phase shifter and the output of the complementary injection unit are both connected to the input of the injection-locked ring oscillator. The multiphase injection signal includes a first phase shift injection signal, a second phase shift injection signal, and a third phase shift injection signal; The pulse generator is used to receive a reference signal and generate a first phase-shift injection signal based on the reference signal; The phase shifter is used to receive the first phase shift injection signal and generate the second phase shift injection signal and the third phase shift injection signal based on the first phase shift injection signal; The complementary injection unit is used to receive the first phase-shift injection signal and generate the complementary injection signal based on the first phase-shift injection signal; The injection-locked ring oscillator is used to receive a first signal and the injection signal, and generate a first oscillation signal based on the first signal and the injection signal, wherein the first signal is a control voltage signal output by the locking unit; The locking unit is used to receive the reference signal and the first oscillation signal, and generate the first signal based on the reference signal and the first oscillation signal. The first signal is used for locking the injection-locked phase-locked loop.

2. The low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 1, characterized in that, In the multiphase injection signal, the phase shifts of the first phase shift injection signal, the second phase shift injection signal, and the third phase shift injection signal are 60°, 120°, and 180°, respectively.

3. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 2, characterized in that, The pulse generator includes an AND gate, a first NOT gate, and a variable delay unit; The input terminal of the variable delay unit and the first input terminal of the AND gate are both connected to the reference signal; The input of the first NOT gate is connected to the output of the variable delay unit; The second input terminal of the AND gate is connected to the output terminal of the first NOT gate; The AND gate is used to receive the reference signal and the signal output by the first NOT gate, and to generate the first phase-shift injection signal based on the reference signal and the signal output by the first NOT gate.

4. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 3, characterized in that, The phase shifter includes a multiphase filter and a dual Gilbert unit; The multiphase filter includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor; One end of the first resistor is connected to the positive input terminal of the multiphase filter and one end of the first capacitor, and the other end is connected to one end of the second resistor, one end of the second capacitor and one end of the seventh capacitor. The other end of the second resistor is connected to one end of the eighth capacitor and the first output terminal of the polyphase filter; One end of the third resistor and one end of the third capacitor are both grounded, and the other end is connected to the other end of the first capacitor, one end of the fourth resistor and one end of the fourth capacitor. The other end of the fourth resistor is connected to the other end of the second capacitor and the second output terminal of the polyphase filter; One end of the fifth resistor and one end of the fifth capacitor are both grounded, and the other end is connected to the other end of the third capacitor, one end of the sixth resistor, and one end of the sixth capacitor. The other end of the sixth resistor is connected together with the other end of the fourth capacitor and the third output terminal of the polyphase filter; One end of the seventh resistor is connected to the other end of the seventh capacitor and the negative input terminal of the multiphase filter, and the other end is connected to the other end of the fifth capacitor, the other end of the eighth capacitor and one end of the eighth resistor. The other end of the eighth resistor is connected together with the other end of the sixth capacitor and the fourth output terminal of the polyphase filter; The first, second, third, and fourth output terminals of the polyphase filter are respectively connected to the first, second, third, and fourth input terminals of the dual Gilbert unit.

5. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 4, characterized in that, The dual Gilbert unit includes a ninth resistor, a tenth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; The first input terminal of the dual Gilbert unit is connected to the gates of the twelfth and thirteenth NMOS transistors, the second input terminal is connected to the gates of the eighteenth and fifteenth NMOS transistors, the third input terminal is connected to the gates of the eleventh and fourteenth NMOS transistors, the fourth input terminal is connected to the gates of the sixteenth and seventeenth NMOS transistors, the first output terminal is connected to the drains of the eleventh, thirteenth, fifteenth, and seventeenth NMOS transistors and one end of the ninth resistor, and the second output terminal is connected to the drains of the twelfth, fourteenth, sixteenth, and eighteenth NMOS transistors and one end of the tenth resistor. The other end of the ninth resistor and the other end of the tenth resistor are both connected to a power source; The gates of both the first NMOS transistor and the second NMOS transistor are connected to a fixed bias voltage; The drain of the first NMOS transistor is connected to the source of the seventh and eighth NMOS transistors; the drain of the second NMOS transistor is connected to the source of the ninth and tenth NMOS transistors. The drain of the seventh NMOS transistor is connected to the sources of the eleventh and twelfth NMOS transistors; the drain of the eighth NMOS transistor is connected to the sources of the thirteenth and fourteenth NMOS transistors; the drain of the ninth NMOS transistor is connected to the sources of the fifteenth and sixteenth NMOS transistors; and the drain of the tenth NMOS transistor is connected to the sources of the seventeenth and eighteenth NMOS transistors. The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor, and its drain is connected to the gate of the seventh NMOS transistor and the source of the first PMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the second PMOS transistor, and its drain is connected to the gate of the eighth NMOS transistor and the source of the second PMOS transistor. The drains of the first PMOS transistor and the second PMOS transistor are connected. The gate of the fifth NMOS transistor is connected to the gate of the third PMOS transistor, and its drain is connected to the gate of the ninth NMOS transistor and the source of the third PMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor, and its drain is connected to the gate of the tenth NMOS transistor and the source of the fourth PMOS transistor. The drains of the third PMOS transistor and the fourth PMOS transistor are connected. The sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all grounded.

6. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 5, characterized in that, The complementary injection unit includes a second NOT gate and a transmission gate; The input terminals of the second NOT gate and the transmission gate are both connected to the output terminal of the pulse generator; The outputs of the second NOT gate and the transmission gate are respectively connected to the first output and the second output of the complementary injection unit; The second NOT gate is used to receive the first phase shift injection signal and generate a first complementary injection signal based on the first phase shift injection signal; The transmission gate is used to receive the first phase-shift injection signal and generate a second complementary injection signal based on the first phase-shift injection signal.

7. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 6, characterized in that, The injection-locked ring oscillator includes three injection transistors and three differential delay units, wherein the injection transistors are NMOS transistors; The first input terminal and the second input terminal of the first differential delay unit are respectively connected to the first output terminal and the second output terminal of the third differential delay unit; the first input terminal and the second input terminal of the second differential delay unit are respectively connected to the first output terminal and the second output terminal of the first differential delay unit. The first input terminal and the second input terminal of the third differential delay unit are respectively connected to the first output terminal and the second output terminal of the second differential delay unit; The gate of the first injection transistor is connected to the output terminal of the pulse generator, and its drain and source are respectively connected to the first output terminal and the second output terminal of the first differential delay unit; the gate of the second injection transistor is connected to the first output terminal of the dual Gilbert unit, and its drain and source are respectively connected to the first output terminal and the second output terminal of the second differential delay unit; the gate of the third injection transistor is connected to the second output terminal of the dual Gilbert unit, and its drain and source are respectively connected to the first output terminal and the second output terminal of the third differential delay unit. The third and fourth input terminals of the second differential delay unit are respectively connected to the first and second output terminals of the complementary injection unit, and are used to receive the first complementary injection signal and the second complementary injection signal. The first injection tube, the second injection tube, and the third injection tube are respectively used to receive the first phase shift injection signal, the second phase shift injection signal, and the third phase shift injection signal.

8. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 7, characterized in that, The second differential delay unit includes the nineteenth NMOS transistor, the twentieth NMOS transistor, the twenty-first NMOS transistor, the twenty-second NMOS transistor, the twenty-third NMOS transistor, the twenty-fourth NMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor; The first input terminal of the second differential delay unit is connected to the gates of the 20th NMOS transistor and the 6th PMOS transistor, the second input terminal is connected to the gates of the 19th NMOS transistor and the 5th PMOS transistor, the first output terminal is connected to the drains of the 20th NMOS transistor, the 6th PMOS transistor, the second injection transistor, the 24th NMOS transistor, the 10th PMOS transistor, and the gates of the 22nd NMOS transistor and the 8th PMOS transistor, and the second output terminal is connected to the drains of the 19th NMOS transistor, the 5th PMOS transistor, the 22nd NMOS transistor, and the 8th PMOS transistor, the gates of the 24th NMOS transistor and the 10th PMOS transistor, and the source of the second injection transistor. The gates of the seventh PMOS transistor and the ninth PMOS transistor are both connected to the third input terminal of the second differential delay unit, for receiving the first complementary injection signal. The gates of the 21st NMOS transistor and the 23rd NMOS transistor are both connected to the fourth input terminal of the second differential delay unit to receive the second complementary injection signal; The drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor; the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor; the drain of the twenty-first NMOS transistor is connected to the source of the twenty-second NMOS transistor; and the drain of the twenty-third NMOS transistor is connected to the source of the twenty-fourth NMOS transistor. The sources of the fifth, sixth, seventh, and ninth PMOS transistors are all connected to a power supply. The sources of the nineteenth NMOS transistor, the twentieth NMOS transistor, the twentieth eleventh NMOS transistor, and the twenty-third NMOS transistor are all grounded.

9. A low-jitter injection-locked phase-locked loop based on multiphase injection according to claim 1, characterized in that, The locking unit includes a subsampling loop unit, a frequency-locking loop unit, a loop filter, and a buffer; The input terminal of the loop filter is connected to the output terminal of the subsampling loop unit and the output terminal of the frequency-locked loop unit, and the output terminal is connected to the input terminal of the injection-locked ring oscillator; The loop filter is used to receive current signals and generate control voltage signals based on the current signals. The current signals include a first current signal and a second current signal, which are the current signals output by the subsampling loop unit and the frequency-locked loop unit, respectively. The control voltage signals include a first control voltage signal and a second control voltage signal, whereby the first control voltage signal is generated based on the first current signal and the second control voltage signal is generated based on the second current signal. The input terminal of the buffer is connected to the output terminal of the injection-locked ring oscillator, and is used to receive the first oscillation signal and perform drive enhancement processing on the first oscillation signal to obtain the second oscillation signal; The frequency-locked loop unit includes a frequency divider, a frequency-phase detector, and a charge pump; the input terminal of the frequency divider is connected to the output terminal of the buffer; the first input terminal of the frequency-phase detector is connected to the output terminal of the frequency divider, and the second input terminal is connected to the reference signal; the input terminal of the charge pump is connected to the output terminal of the frequency-phase detector, and the output terminal is connected to the input terminal of the loop filter; the frequency-locked loop is used to receive the reference signal and the second oscillation signal, and generate the first current signal based on the reference signal and the second oscillation signal; The subsampling loop unit includes a subsampling phase detector and a transconductance module; the first input terminal of the subsampling phase detector is connected to a reference signal, and the second input terminal is connected to the output terminal of the buffer; the input terminal of the transconductance module is connected to the output terminal of the subsampling phase detector, and the output terminal is connected to the loop filter. The subsampling loop unit is used to receive the reference signal and the second oscillation signal, and generate the second current signal based on the reference signal and the second oscillation signal.

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