Circuit capable of automatically adjusting magnification times and realizing synchronous sampling

Abstract

The invention provides a circuit for automatically adjusting magnification times and realizing synchronous sampling, and belongs to the technical field of power electronics. The circuit comprises an amplifying circuit, a resistance switching circuit, a phase locking circuit and an acquisition circuit, the amplifying circuit is used for receiving and processing an original signal, obtaining a voltage signal and analyzing an amplification factor required by the voltage signal, and an amplifier is correspondingly connected to a resistor in the resistance switching circuit according to the required amplification factor and is used for acquiring the voltage signal. And amplifying the voltage signal according to the amplification factor, receiving the amplified voltage signal by the phase-locked loop, analyzing the amplified voltage signal to obtain an average voltage, and adjusting the output frequency of the phase-locked loop according to the average voltage to lock the phase. And the acquisition circuit is used for synchronously sampling the amplified voltage signal according to the locked phase. In an electric power system data acquisition application, the amplification factor can be automatically adjusted, phase synchronization can be realized, and signal acquisition and data analysis of different capacitive devices of a power grid can be satisfied.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology and relates to a circuit that automatically adjusts the amplification factor and achieves synchronous sampling. Background Technology

[0002] In power system data acquisition applications, signal acquisition circuits using the FFT algorithm for data processing are involved. First, small signals are amplified, then acquired by an ADC. Since the input signal is variable, an appropriate amplification factor is crucial. If the amplification factor is too small, the signal acquired by the ADC will be too weak, resulting in large errors in the FFT calculation; if the amplification factor is too large, it will cause signal distortion, exceeding the threshold and rendering the acquired data invalid. Furthermore, to calculate the dielectric losses of capacitive devices in the power grid, it is necessary to synchronously sample three voltage or current signals. Synchronous sampling requires phase synchronization to ensure the same number of sampling points per cycle, dynamically change the sampling period, and eliminate the influence of power grid frequency variations on subsequent calculations. Therefore, a circuit capable of automatically adjusting the amplification factor and synchronously acquiring data is an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to address the aforementioned problems in existing technologies by proposing a circuit that automatically adjusts the amplification factor and achieves synchronous sampling.

[0004] The objective of this invention can be achieved through the following technical solution: a circuit that automatically adjusts the amplification factor and achieves synchronous sampling, comprising:

[0005] Amplification circuit, resistor switching circuit, phase-locked circuit, and acquisition circuit;

[0006] The amplification circuit is used to receive and process the original signal to obtain a voltage signal, analyze the required amplification factor of the voltage signal, and connect the resistor in the resistor switching circuit according to the required amplification factor. Then, the voltage signal is amplified according to the amplification factor. The output terminal of the amplification circuit is connected to the input terminal of the acquisition circuit. The resistor switching circuit includes at least two or more resistors with different resistance values.

[0007] The phase-locked circuit includes a phase-locked loop. The input terminal of the phase-locked circuit is connected to the output terminal of the amplifier circuit. The phase-locked loop receives the amplified voltage signal, analyzes it to obtain an average voltage, and adjusts the output frequency of the phase-locked loop according to the average voltage to lock the phase.

[0008] The acquisition circuit is used to synchronously sample the amplified voltage signal according to the locked phase.

[0009] As an optional embodiment of the present invention, the amplification circuit is used to receive and process the original signal, including:

[0010] A conversion circuit, wherein the input terminal of the conversion circuit receives the original signal and the output terminal is connected to an amplifier;

[0011] The original signal is a current signal. The conversion circuit filters out the preset frequency interference signal of the current signal and converts the current signal into a voltage signal.

[0012] As an optional embodiment of the present invention, the amplification factor required for analyzing the voltage signal includes:

[0013] The voltage signal is acquired using an analog-to-digital converter, and the ratio of the voltage value of the voltage signal to the maximum input voltage value of the analog-to-digital converter is calculated.

[0014] The ratio is compared with a preset ratio range to determine the magnification factor required for the ratio to fall within the preset ratio range.

[0015] As an optional embodiment of the present invention, the phase-locking circuit further includes:

[0016] A signal conditioning circuit is provided, wherein the input terminal of the signal conditioning circuit receives the amplified voltage signal, and the output terminal is connected to the first input terminal of the phase-locked loop, for converting the voltage signal into a square wave signal and performing optocoupler isolation, wherein the frequency and phase of the square wave signal are the same as those of the voltage signal.

[0017] As an optional embodiment of the present invention, the phase-locked loop receives the amplified voltage signal and analyzes it to obtain an average voltage, including:

[0018] The phase-locked loop also includes a phase comparator and a low-pass filter;

[0019] The output terminal of the voltage-controlled oscillator is connected to the second input terminal of the phase comparator;

[0020] By comparing the voltage and phase at the first input terminal and the second input terminal of the phase comparator respectively, the error voltage and phase difference are obtained accordingly.

[0021] The error voltage is proportional to the phase difference and is input to the low-pass filter for filtering, outputting an average voltage.

[0022] As an optional embodiment of the present invention, adjusting the output frequency of the phase-locked loop according to the average voltage to lock the phase includes:

[0023] The frequency of the second input terminal is changed according to the average voltage feedback.

[0024] When the frequency of the second input terminal is the same as that of the first input terminal, and the phase difference between the second input terminal and the first input terminal remains constant, the phase is locked.

[0025] As an optional embodiment of the present invention, the acquisition circuit is used to synchronously sample the amplified voltage signal according to the locked phase, including:

[0026] After the phase is locked, the square wave signal at the first input terminal is used as the synchronization trigger reference.

[0027] The acquisition circuit samples the amplified voltage signal according to the synchronous trigger reference.

[0028] As an optional embodiment of the present invention, the amplification circuit further includes:

[0029] A voltage follower circuit, wherein the input terminal of the voltage follower circuit is connected to the output terminal of the amplifier, and the output terminal is connected to the input terminal of the phase-locked circuit, is used to perform voltage following on the amplified voltage signal.

[0030] As an optional embodiment of the present invention, the original signal received by the amplifier circuit is the signal output by any phase of the three-phase circuit.

[0031] As an optional embodiment of the present invention, the phase-locked loop is model CD4046.

[0032] Compared with existing technologies, this invention can automatically adjust the corresponding amplification resistor according to the magnitude of the input signal, thereby adjusting the amplification factor. It has strong applicability. Furthermore, it uses a portion of the amplified voltage signal flowing to the phase-locked circuit for phase synchronization. Thus, in a power system data acquisition application, it can both automatically adjust the amplification factor and achieve phase synchronization, which can meet the signal acquisition and data analysis needs of different capacitive devices in the power grid. Attached Figure Description

[0033] Figure 1 This is an amplifier circuit diagram according to an embodiment of the present invention;

[0034] Figure 2 This is a circuit diagram of the resistor switching circuit according to an embodiment of the present invention;

[0035] Figure 3 This is a phase-locked circuit diagram according to an embodiment of the present invention;

[0036] In the diagram: 10. Amplifier circuit; 11. Conversion circuit; 12. Voltage follower circuit; 20. Resistor switching circuit; 30. Phase-locked loop circuit; 31. Signal conditioning circuit; 32. Phase-locked loop. Detailed Implementation

[0037] The following are specific embodiments of the present invention, which are described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0038] Example 1

[0039] To address the problems raised in the background art, this embodiment employs a circuit that automatically adjusts the amplification factor and achieves synchronous sampling, comprising:

[0040] Amplifier circuit 10, resistor switching circuit 20, phase-locked circuit 30, and acquisition circuit;

[0041] The amplifier circuit 10 is used to receive and process the original signal to obtain a voltage signal, analyze the required amplification factor of the voltage signal, and connect the amplifier to the resistor in the resistor switching circuit 20 according to the required amplification factor. Then, the voltage signal is amplified according to the amplification factor. The output terminal of the amplifier circuit 10 is connected to the input terminal of the acquisition circuit. The resistor switching circuit 20 includes at least two or more resistors with different resistance values.

[0042] The phase-locked circuit 30 includes a phase-locked loop 32. The input terminal of the phase-locked circuit 30 is connected to the output terminal of the amplifier circuit 10. The phase-locked loop 32 receives the amplified voltage signal, analyzes it, obtains the average voltage, and adjusts the output frequency of the phase-locked loop 32 according to the average voltage to lock the phase.

[0043] The acquisition circuit is used to synchronously sample the amplified voltage signal according to the locked phase.

[0044] like Figure 1 As shown, amplifier circuit 10 receives the original signal from the AIN00 terminal, converts it into a voltage signal, and calculates the required amplification factor based on the voltage value of the voltage signal to ensure that the amplification factor is neither too small nor too large. After determining the amplification factor, it is connected to... Figure 2 The resistor switching circuit 20 shown adjusts the amplification resistance value by connecting different resistors, thereby adjusting the signal amplification factor. This allows the voltage signals corresponding to different original signals to be appropriately amplified by the active amplifier AD620. A portion of the amplified voltage signal flows to the acquisition circuit, and the remaining portion flows to... Figure 3The phase-locked circuit 30 shown analyzes the amplified voltage signal through the phase-locked loop 32 within the circuit, calculates the average voltage, and continuously adjusts the output frequency of the voltage-controlled oscillator (VCO) of the PLO 32 based on the average voltage to ensure that it matches the frequency of the amplified voltage signal while maintaining a constant phase difference, thus completing phase locking. After phase locking, the acquisition circuit acquires the amplified voltage signal according to the synchronous trigger reference. The acquired data can be used to calculate the dielectric loss of capacitive power grid equipment.

[0045] Preferably, the amplifier circuit 10 is used to receive and process the original signal, including:

[0046] The conversion circuit 11 receives the original signal at its input terminal and is connected to an amplifier at its output terminal.

[0047] The original signal is a current signal. The conversion circuit 11 filters out the preset frequency interference signal of the current signal and converts the current signal into a voltage signal.

[0048] like Figure 1 The conversion circuit 11 shown includes a low-pass filter composed of R4 and C6, a pre-stage protection device TVS1, and a high-precision low-temperature drift sampling resistor R9 connected in parallel. Its output is connected to pin 3 of the active amplifier AD620, and is connected to port 2 of the active amplifier AD620 and grounded. The input of the conversion circuit 11 is the AIN00 terminal, where a current signal is input. After the RC low-pass filter R4 and C6 filters out high-frequency interference signals above a preset frequency of 159Hz, the current signal is converted into a voltage signal by the high-precision low-temperature drift sampling resistor R9. The converted voltage signal is then output to the active amplifier AD620 for amplification. In the amplification section, pin 7 of the active amplifier AD620 is connected to a positive voltage of +15V, and pin 4 is connected to a negative voltage of -15V. When pin 4 is connected to a negative voltage of -15V, capacitor C8 and electrolytic capacitor C9 are connected in parallel, with one end connected to pin 4 and the other end grounded. When a positive voltage of +15V is applied to pin 7, capacitor C1 and electrolytic capacitor C2 are connected in parallel, with one end connected to pin 7 and the other end grounded.

[0049] Pin 1 of the AD620 / OS active amplifier is connected to RG1_2, and pin 8 is connected to RG1_1. A resistor is connected between RG1_1 and RG1_2. Specifically, as shown... Figure 2The resistor switching circuit 20 shown is model ADG1611. Pins 3 (S1) and 2 (D1) are used to connect the two ends of resistor R53, pins 14 (S2) and 15 (D2) are used to connect the two ends of resistor R54, pins 11 (S3) and 10 (D3) are used to connect the two ends of resistor R58, and pins 6 (S4) and 7 (D4) are used to connect the two ends of resistor R60. For example, when it is determined that resistor R60 needs to be connected, RG1_1 is connected to pin 6 (S4), and RG1_2 is connected to pin 7 (D4), meaning RG1_1 and RG1_2 are connected to the two ends of resistor R60, thereby adjusting the amplification factor of amplifier circuit 10. Pin 13 (VCC) is connected to a positive voltage of +5V, pin 4 (VSS) is connected to a negative voltage of -15V, pin 12 (NC) is left floating, and pin 5 (AGND) is grounded. Pins 1, 16, 9, and 8 (IN1 to IN4 terminals) are used for the inputs of the remaining circuitry.

[0050] Preferably, the amplification factor required for analyzing the voltage signal includes:

[0051] The voltage signal is acquired using an analog-to-digital converter, and the ratio of the voltage value of the voltage signal to the maximum input voltage value of the analog-to-digital converter is calculated.

[0052] The ratio is compared with a preset ratio range to determine the magnification factor required for the ratio to fall within the preset ratio range.

[0053] In this embodiment, the ratio of the VIN00 voltage value acquired by the high-precision ADC (analog-to-digital converter) to the full scale is used for judgment. It should be noted that the original current signal is converted into a voltage signal by the high-precision low-temperature drift sampling resistor R9. This voltage signal is represented by VIN00. The full scale is the maximum input voltage value that the ADC can measure.

[0054] The voltage value of the voltage signal VIN00 is acquired, and the ratio of this voltage value to the maximum input voltage value is calculated to determine the percentage of full-scale voltage reached. The preset ratio range is 60% to 90%. Based on the comparison between this preset ratio and the actual ratio, the amplification factor for the voltage signal VIN00 is determined, thereby determining the corresponding amplification resistor value. After determining the amplification resistor value, ADG1611 is connected to the two ends of resistors R53, R54, R58, or R60 in the resistor switching circuit 20, connecting them to RG1_1 and RG1_2. This adjusts the amplification factor according to the connected resistor, amplifying the voltage signal VIN00. The ratio of the amplified voltage signal to the full-scale voltage falls within the preset ratio range. Adjusting the amplification factor through these steps allows for appropriate amplification of the constantly changing input signal, preventing the acquired signal from being too small or distorted, thus avoiding invalid data during subsequent acquisition.

[0055] Preferably, the phase-locking circuit 30 further includes:

[0056] The signal conditioning circuit 31 receives the amplified voltage signal at its input terminal and is connected to the first input terminal of the phase-locked loop 32 at its output terminal. It is used to convert the voltage signal into a square wave signal and perform optocoupler isolation. The frequency and phase of the square wave signal are the same as those of the voltage signal.

[0057] like Figure 3 The signal conditioning circuit 31 shown in this embodiment conditions the amplified voltage signal VIN00 received by the phase-locked loop 30. This conditioning includes shaping, isolation, and interference suppression to output a cleaner voltage signal to the phase-locked loop 32. Specifically, the comparator LM311 in the signal conditioning circuit 31 shapes the voltage signal from a sine wave to a square wave, ensuring that the square wave has the same frequency and phase as the sine wave. Optical isolation is then achieved through the optocoupler TLP121. After optocoupler isolation, the output is connected to the first input terminal of the phase-locked loop 32, pin 14 (SINGIN terminal), via the NAND gate of the CD4093BCM chip.

[0058] Preferably, the phase-locked loop 32 receives the amplified voltage signal and analyzes it to obtain an average voltage, including:

[0059] The phase-locked loop 32 also includes a phase comparator and a low-pass filter;

[0060] The output terminal of the voltage-controlled oscillator is connected to the second input terminal of the phase comparator;

[0061] By comparing the voltage and phase at the first input terminal and the second input terminal of the phase comparator respectively, the error voltage and phase difference are obtained accordingly.

[0062] The error voltage is proportional to the phase difference and is input to the low-pass filter for filtering, outputting an average voltage.

[0063] The CD4046 phase-locked loop (PLL) chip integrates a phase comparator, a voltage-controlled oscillator (VCO), and a low-pass filter. The VCO's output, PC2OUT, is connected to the second input, VCOIN, of the phase comparator via pin 13. The voltage and phase of the phase comparator's first input, SINGIN, and second input, VCOIN, are compared to obtain the error voltage and phase difference. The error voltage is proportional to the phase difference, and after passing through the low-pass filter to remove high-frequency components, an average voltage is obtained.

[0064] Pin 11 (R1) of PLL 32 is connected to resistor R2 and grounded. Pin 12 (R2) is left floating. Pin 3 (COMPIN) is used to receive CPIN (clock pulse input). Pin 9 (VCOIN) is connected in series with resistor R1 and pin 13 (PC2OUT). Pin 9 (VCOIN) is also connected in series with resistor R3 and electrolytic capacitor C3 and grounded. Pin 5 (INH PHASE) is grounded. Pin 14 (SINGIN) is connected to the NAND gate of CD4093BCM to receive square waves. Pin 6 (CI(1)) is connected in series with capacitor C11 and pin 7 (CI(2)). Pin 8 (VSS) is grounded. Pins 2 (PC1OUT), 10 (DEMOUT), 1 (PILSES), and 15 (ZENER) are all left floating. Pin 4 (VCOOUT) is the frequency output terminal of the voltage-controlled oscillator.

[0065] Preferably, adjusting the output frequency of the phase-locked loop 32 according to the average voltage to lock the phase includes:

[0066] The frequency of the second input terminal is changed according to the average voltage feedback.

[0067] When the frequency of the second input terminal is the same as that of the first input terminal, and the phase difference between the second input terminal and the first input terminal remains constant, the phase is locked.

[0068] The average voltage, in turn, adjusts the output frequency of the voltage-controlled oscillator. That is, the average voltage changes in the direction of reducing the difference between the output frequency and the input frequency of the voltage-controlled oscillator, so that the output frequency of the voltage-controlled oscillator is the same as the frequency of the square wave signal. When the frequencies are the same, the phase difference between the two remains constant, that is, synchronization is achieved, and phase locking is completed.

[0069] Preferably, the acquisition circuit is used to synchronously sample the amplified voltage signal according to the locked phase, including:

[0070] After the phase is locked, the square wave signal at the first input terminal is used as the synchronization trigger reference; the acquisition circuit samples the amplified voltage signal according to the synchronization trigger reference.

[0071] After the phase is locked, a square wave signal is used as the synchronous trigger reference. For example, the acquisition circuit acquires the amplified voltage signal VIN00 by using the rising edge of the square wave signal, thereby realizing synchronous acquisition.

[0072] Preferably, the amplifier circuit 10 further includes:

[0073] A voltage follower circuit 12 is provided, the input of which is connected to the output of the amplifier and the output of which is connected to the input of the phase-locked circuit 30. The voltage follower circuit 12 is used to perform voltage following on the amplified voltage signal.

[0074] The OP27 / OS has strong anti-interference capabilities and is often used for high-precision signal transmission. It is generally used before signal acquisition. In this embodiment, a voltage follower circuit 12 based on the OP27 / OS is used to transmit the amplified voltage signal VIN00, thereby improving the stability of the overall circuit application system.

[0075] Pin 6 (output) of the amplifier is connected to pin 3 of the OP27 / OS, with a series resistor R10 and one end of capacitor C7 connected to resistor R10 and the other end grounded. Pin 2 is connected to the voltage signal VIN00 output from pin 6; pin 4 is connected to a negative voltage of -15V, with one end of capacitor C10 connected to pin 4 and the other end grounded. Pin 7 is connected to a positive voltage of +15V, with one end of capacitor C4 connected to pin 7 and the other end grounded. Pins 1, 5, and 8 are all left floating.

[0076] Preferably, the original signal received by the amplifier circuit 10 is the signal output by any phase of the three-phase circuit.

[0077] To achieve synchronous sampling of three-phase voltage or current signals, phase synchronization is required. Phase synchronization can be achieved by inputting the signal output from one phase into the phase-locked loop 32 for phase tracking. The signal output from one phase can be the signal output from any phase in the three-phase circuit.

[0078] Preferably, the phase-locked loop 32 is model CD4046.

[0079] The phase-locked loop 32 chip used in this embodiment is model CD4046. This phase-locked loop 32 has a built-in phase comparator, voltage-controlled oscillator and low-pass filter, eliminating the need to design a separate VCO or comparator, which not only reduces complexity but also enables phase synchronization.

[0080] The circuit described above, which automatically adjusts the amplification factor and achieves synchronous sampling, can automatically adjust the corresponding amplification resistor according to the magnitude of the input signal, thereby adjusting the amplification factor. It has strong applicability. Furthermore, by using a portion of the amplified voltage signal flowing into the phase-locked circuit 30 for phase synchronization, it can achieve both automatic amplification factor adjustment and phase synchronization in a power system data acquisition application, thus meeting the signal acquisition and data analysis needs of different capacitive devices in the power grid.

[0081] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0082] Furthermore, it should be noted that the use of terms such as "first," "second," and "a" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. The terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two elements or the interaction between two elements, unless otherwise explicitly specified. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0083] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0084] The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

Claims

1. A circuit that automatically adjusts the amplification factor and achieves synchronous sampling, characterized in that, include: Amplification circuit, resistor switching circuit, phase-locked circuit, and acquisition circuit; The amplification circuit is used to receive and process the original signal to obtain a voltage signal, analyze the required amplification factor of the voltage signal, and connect the resistor in the resistor switching circuit according to the required amplification factor. Then, the voltage signal is amplified according to the amplification factor. The output terminal of the amplification circuit is connected to the input terminal of the acquisition circuit. The resistor switching circuit includes at least two or more resistors with different resistance values. The phase-locked circuit includes a phase-locked loop. The input terminal of the phase-locked circuit is connected to the output terminal of the amplifier circuit. The phase-locked loop receives the amplified voltage signal, analyzes it to obtain an average voltage, and adjusts the output frequency of the phase-locked loop according to the average voltage to lock the phase. The acquisition circuit is used to synchronously sample the amplified voltage signal according to the locked phase.

2. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 1, characterized in that, The amplifier circuit is used to receive and process the original signal, including: A conversion circuit, wherein the input terminal of the conversion circuit receives the original signal and the output terminal is connected to an amplifier; The original signal is a current signal. The conversion circuit filters out the preset frequency interference signal of the current signal and converts the current signal into a voltage signal.

3. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 1, characterized in that, The amplification factor required for analyzing the voltage signal includes: The voltage signal is acquired using an analog-to-digital converter, and the ratio of the voltage value of the voltage signal to the maximum input voltage value of the analog-to-digital converter is calculated. The ratio is compared with a preset ratio range to determine the magnification factor required for the ratio to fall within the preset ratio range.

4. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 1, characterized in that, The phase-locking circuit further includes: A signal conditioning circuit is provided, wherein the input terminal of the signal conditioning circuit receives the amplified voltage signal, and the output terminal is connected to the first input terminal of the phase-locked loop, for converting the voltage signal into a square wave signal and performing optocoupler isolation, wherein the frequency and phase of the square wave signal are the same as those of the voltage signal.

5. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 4, characterized in that, The phase-locked loop receives and analyzes the amplified voltage signal to obtain an average voltage, including: The phase-locked loop also includes a phase comparator and a low-pass filter; The output terminal of the voltage-controlled oscillator is connected to the second input terminal of the phase comparator; By comparing the voltage and phase at the first input terminal and the second input terminal of the phase comparator respectively, the error voltage and phase difference are obtained accordingly. The error voltage is proportional to the phase difference and is input to the low-pass filter for filtering, outputting an average voltage.

6. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 5, characterized in that, Adjusting the output frequency of the phase-locked loop to lock the phase based on the average voltage includes: The frequency of the second input terminal is changed according to the average voltage feedback. When the frequency of the second input terminal is the same as that of the first input terminal, and the phase difference between the second input terminal and the first input terminal remains constant, the phase is locked.

7. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 6, characterized in that, The acquisition circuit is used to synchronously sample the amplified voltage signal according to the locked phase, including: After the phase is locked, the square wave signal at the first input terminal is used as the synchronization trigger reference. The acquisition circuit samples the amplified voltage signal according to the synchronous trigger reference.

8. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 1, characterized in that, The amplifier circuit also includes: A voltage follower circuit, wherein the input terminal of the voltage follower circuit is connected to the output terminal of the amplifier, and the output terminal is connected to the input terminal of the phase-locked circuit, is used to perform voltage following on the amplified voltage signal.

9. A circuit for automatically adjusting amplification factor and achieving synchronous sampling according to any one of claims 1-8, characterized in that, The original signal received by the amplifier circuit is the signal output by any phase of the three-phase circuit.

10. The circuit for automatically adjusting the amplification factor and achieving synchronous sampling according to claim 9, characterized in that, The phase-locked loop is model CD4046.

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