Dual-tail comparator circuit for pixel sensor column-parallel ADC and method of operation

Abstract

This application provides a dual-tailed comparator circuit and its operation method for a pixel sensor column-end ADC, solving the technical problems of high kickback noise and offset in existing comparators under high-frequency scenarios. It includes an input differential pair, a latch module, and a correction capacitor module. The latch module is connected to both the input differential pair and the correction capacitor module. The input differential pair provides input stage transconductance for rapid noise discharge. The latch module reduces the amplitude of the kickback noise and shortens its transient process. The correction capacitor module modulates the correction capacitor value to compensate for comparator offset. This application can be widely applied in the field of integrated circuit technology.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and more specifically, relates to a dual-tailed comparator circuit and its operation method for a pixel sensor column-end ADC. Background Technology

[0002] The comparator is a key module in an ADC (Analog-to-Digital Converter). Its function is to compare the voltage amplitudes of two input signals and output the corresponding binary comparison result. Essentially, a comparator is an open-loop high-gain amplifier, crucial to the performance of a SAR-ADC (Successive Approximation ADC). Since pixel sensors used for high-energy particle detection need to operate at extremely high frame rates, the comparators in their column-level SAR-ADCs must achieve low-noise design while maintaining high-speed operation and minimizing circuit area to maximize the effective sensitive area ratio of the sensor.

[0003] Traditional latch comparators introduce significant kickback noise into the input, which is transient noise introduced during comparator operation due to voltage changes at the output caused by the parasitic capacitance of the MOSFET. If this transient noise cannot be completely reset between two consecutive comparisons, it may affect the conversion accuracy of the ADC. A Chinese invention patent application (CN202311676115.8) proposes a comparator, analog-to-digital converter, and device for reducing kickback noise, utilizing the synergistic effect of an isolating switch module and a neutralizing capacitor module. However, this patent cannot discharge the accumulated charge on the parasitic capacitance of high-impedance nodes, and it suffers from incomplete comparator setup in high-frequency scenarios. This not only fails to solve the kickback noise problem in high-frequency scenarios but also causes offset due to accumulated charge.

[0004] Existing methods for comparator offset compensation include preamplifier compensation and input / output offset storage. All of these methods require the use of an active amplifier to amplify the input voltage, necessitating complete amplifier setup during the comparison process. However, comparators operate at extremely high speeds, thus placing high demands on amplifier bandwidth and slew rate. Therefore, existing offset compensation methods cannot compensate for comparator offset at extremely high frame rates. Summary of the Invention

[0005] The purpose of this application is to provide a dual-tailed comparator circuit for a pixel sensor column-end ADC to solve the technical problem that the existing technology cannot solve the high kickback noise and offset phenomenon of the comparator in high-frequency scenarios.

[0006] To achieve the above objectives, the first aspect of this application provides a dual-tailed comparator circuit for a pixel sensor column-end ADC, including: an input differential pair transistor, and further including a latch module and a correction capacitor module, wherein the latch module is connected to the input differential pair transistor and the correction capacitor module;

[0007] The input differential pair transistors are used to provide the input stage transconductance and quickly discharge noise voltage;

[0008] The latch module is used to reduce the amplitude of kickback noise and shorten the transient process of kickback noise;

[0009] The calibration capacitor module is used to modulate the size of the calibration capacitor to compensate for the comparator's offset.

[0010] Preferably, the latch module includes a positive feedback circuit, a time control switch, and a connection switch, with the connection switch connected to the positive feedback circuit;

[0011] The time-controlled switch is used to disconnect the input differential pair transistors and the positive feedback circuit to ensure a stable potential during the reset phase;

[0012] The connecting switch is used to turn on the circuit during the reset phase, ensuring that the charge on both sides of the branch is consistent during the reset phase.

[0013] Preferably, the correction capacitor module is a variable capacitor with a PMOS transistor. The source and drain of the PMOS transistor are shorted to the substrate and are symmetrically mounted on both sides of the positive feedback circuit as plates of the variable capacitor. The gate of the PMOS transistor is connected to the control voltage switch as the other plate of the variable capacitor. The control voltage switch is used to switch between two high and low control voltages VRP and VRN.

[0014] Preferably, the positive feedback circuit includes a zeroth PMOS transistor M0, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a sixth NMOS transistor M6, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13. The sources of the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11 are connected to the power supply. The gate of the zeroth PMOS transistor M0 is connected to the comparator clock. The drain of the zeroth PMOS transistor M0 is connected to the gate of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13. The gate of the second PMOS transistor M2 is connected to the gate of the sixth NMOS transistor M6. The drain of the second PMOS transistor M2 is connected to the time switch. The gate of the first PMOS transistor M1 is connected to the gate of the ninth NMOS transistor M9. The drain of the first PMOS transistor M1 is connected to the time switch. The gate of the third PMOS transistor M3 is connected to the comparator clock. The drain of the third PMOS transistor M3 is connected to the gate of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12. The drains of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 are connected to the input voltage VOP, and the source of the thirteenth NMOS transistor M13 is grounded to VSS. The drains of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 are connected to the input voltage VON, and the source of the twelfth NMOS transistor M12 is grounded to VSS.

[0015] Preferably, the sixth NMOS transistor M6 and the ninth NMOS transistor M9 are isolation switches. The isolation switches are used to isolate kickback noise introduced by the change of the comparison clock level during the startup phase, and to cancel out the positive kickback noise introduced by the comparison clock with the negative kickback noise caused by the common-mode voltage drop.

[0016] Preferably, the timing switch includes a fourth NMOS transistor M4 and an eighth NMOS transistor M8. The gate of the fourth NMOS transistor M4 is connected to a comparator clock, the source of the fourth NMOS transistor M4 is connected to an isolation switch, the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M2, the gate of the eighth NMOS transistor M8 is connected to a comparator clock, the source of the eighth NMOS transistor M8 is connected to an isolation switch, and the drain of the eighth NMOS transistor M8 is connected to the drain of the first PMOS transistor M1.

[0017] Preferably, the connection switch is turned on only during the reset phase. The connection switch is the fourteenth NMOS transistor M14. The source of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistor. The gate of the fourteenth NMOS transistor M14 is connected to the comparator clock. The drain of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistor.

[0018] The second aspect of this application provides a dual-tailed comparator operation method for a pixel sensor column-end ADC, including the following steps: inputting a low-level comparison clock to the latch module to reset the latch module, charging the mutually coupled positive feedback circuits on both sides to a high level, and simultaneously keeping the potentials on both sides of the connection switch consistent.

[0019] A high-level comparison clock is input to the latch module. The difference in discharge speed caused by the input voltage difference triggers the positive feedback circuit, which accelerates the current discharge and completes the voltage comparison.

[0020] The modulation correction capacitor module compensates for the offset generated during the comparison process.

[0021] Preferably, the compensation process includes: finding the lowest weight capacitor in the comparison process, the comparator continuing to compare, and based on the comparison result and the comparison result before the lowest weight capacitor was reset, determining whether the mismatch capacitor before the last comparison is greater than the lowest weight capacitor, reversing the lowest weight capacitor, connecting the redundant capacitor for comparison, and determining whether the mismatch capacitor has reached the maximum correction bit. If yes, the process ends; otherwise, the comparator continues to compare.

[0022] Preferably, by accelerating the current discharge, VDD and VSS are output on both sides of the comparator respectively, thus completing the voltage comparison.

[0023] The beneficial effects of this application are as follows: This application provides a dual-tailed comparator circuit and its operation method for a pixel sensor column-end ADC. Through the synergistic effect of the input differential pair transistors, latch module, and correction capacitor module, it overcomes the high kickback noise and offset phenomenon of existing comparators in high-frequency scenarios, reducing the comparison accuracy error caused by high kickback noise. By providing higher input stage transconductance through the input differential pair transistors, the ability of the amplifier input stage to convert the input differential voltage into output current is enhanced, thereby enabling the noise voltage to be discharged quickly and achieving fast response. During the reset phase, the latch module disconnects the input differential pair transistors from the positive feedback node in the comparator, ensuring the isolation of the positive feedback node, maintaining a stable potential, reducing the amplitude of kickback noise, shortening the transient process of kickback noise, reducing the interference time of noise on the signal, and ensuring the stability and reliability of the signal. Furthermore, during the initial comparison phase, kickback noise introduced by level changes is effectively isolated by the latch module, resulting in a smaller positive kickback to the gate of the input differential pair transistors in the comparator. This allows the positive and negative kickback noises to cancel each other out, effectively suppressing the kickback noise. The correction capacitor module adjusts the initial voltage of the lower plate of the load capacitor by modulating the size of the correction capacitor, thereby controlling the equivalent capacitance connected to the positive feedback node and achieving comparator offset compensation in high-speed scenarios. Using a correction capacitor module instead of the traditional series capacitor approach reduces the high power consumption or speed loss that may be introduced by traditional dynamic comparator offset correction methods, improving comparator accuracy with low area and low power consumption overhead.

[0024] In summary, this application can effectively solve the problems of kickback noise and misalignment generated by comparators in pixel sensors in high-frequency scenarios, and improve the accuracy of comparators with low area and low power consumption. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A circuit diagram of a dual-tailed comparator circuit for a column-end ADC of a pixel sensor provided in one embodiment of this application;

[0027] Figure 2 Simulation results of the correction capacitor changing with voltage as provided in an embodiment of this application and its variation at different voltage levels. P Schematic diagram of equivalent charge load under voltage;

[0028] Figure 3A flowchart illustrating the comparator offset correction process according to an embodiment of this application;

[0029] Figure 4 A simulation waveform diagram of the comparator correction capacitor module correcting offset according to an embodiment of this application;

[0030] Figure 5 The simulation results show the kickback noise comparison of different structures of dual-tailed comparators provided in one embodiment of this application. Detailed Implementation

[0031] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0032] Please see Figure 1 The first aspect of the first embodiment of this application provides a dual-tailed comparator circuit for a pixel sensor column-end ADC, comprising: an input differential pair transistor, a latch module, and a correction capacitor module, wherein the latch module is connected to the input differential pair transistor and the correction capacitor module.

[0033] The input differential pair transistors are used to provide the input stage transconductance and quickly discharge noise voltage;

[0034] The latch module is used to reduce the amplitude of kickback noise and shorten the transient process of kickback noise;

[0035] The calibration capacitor module is used to modulate the size of the calibration capacitor to compensate for the comparator's offset.

[0036] The first aspect of this application utilizes a latch module and an input differential pair to quickly discharge noise voltage, reduce the amplitude of kickback noise, shorten the transient process of kickback noise, and achieve effective suppression of kickback noise in high-frequency scenarios; the second aspect is to adjust the size of the unit correction capacitor according to the reference voltage and delay time to compensate for the offset of the comparator.

[0037] Specifically, the latch module includes a positive feedback circuit, a time control switch, and a connection switch. The time control switch is used to disconnect the input differential pair transistors and the positive feedback circuit to ensure a stable potential during the reset phase; the connection switch is used to turn on during the reset phase to ensure that the charge on both sides of the branch is consistent during the reset phase.

[0038] This application reduces the amplitude of kickback noise and shortens its transient process through the following two aspects. Firstly, it utilizes an isolating switch in the positive feedback circuit to cancel out both positive and negative kickback noise, and employs a time-controlled switch to isolate the input differential pair from the positive feedback circuit, thereby reducing the amplitude of the kickback noise. Secondly, it grounds the input differential pair to enhance the driving capability of the discharge path. These measures effectively shorten the transient process of the noise.

[0039] Specifically, the positive feedback circuit includes the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the sixth NMOS transistor M6, the ninth NMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, the twelfth NMOS transistor M12, and the thirteenth NMOS transistor M13. The sources of the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11 are connected to the power supply. The gate of the zeroth PMOS transistor M0 is connected to the comparator clock CLK. The drain of the zeroth PMOS transistor M0 is connected to the gates of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13. The gate of the second PMOS transistor M2 is connected to the gate of the sixth NMOS transistor M6. The drain of the second PMOS transistor M2 is connected to the time control switch. The gate of the first PMOS transistor M1 is connected to the gate of the ninth NMOS transistor M9. The drain of the first PMOS transistor M1 is connected to the time control switch. The gate of the third PMOS transistor M3 is connected to the comparator clock CLK. The drain of the third PMOS transistor M3 is connected to the gates of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12. The drains of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 are connected to the input voltage VOP, and the source of the thirteenth NMOS transistor M13 is grounded to VSS. The drains of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 are connected to the input voltage VON, and the source of the twelfth NMOS transistor M12 is grounded to VSS. The eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 form the inverter on the left, and the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 form the inverter on the right.

[0040] The sixth NMOS transistor M6 and the ninth NMOS transistor M9 are used as isolation switches to isolate kickback noise introduced by changes in the comparison clock CLK level during the comparator startup phase. The isolation switches effectively separate the noise introduced by the comparison clock from the gates of the input differential pair transistors, significantly reducing the positive kickback noise experienced by the gates of the input differential pair transistors. By adjusting the dimensions of the sixth NMOS transistor M6 and the ninth NMOS transistor M9, the positive kickback noise introduced by the comparison clock CLK can be mutually canceled out by the negative kickback noise caused by the common-mode voltage drop in the left and right branches of the dual-tailed comparator during the comparison process, effectively suppressing kickback noise. Specifically, the gate of the sixth NMOS transistor M6 is connected to the gate of the second PMOS transistor M2, the source of the sixth NMOS transistor M6 is connected to the input differential pair transistor, the drain of the sixth NMOS transistor M6 is connected to the time control switch, the gate of the ninth NMOS transistor M9 is connected to the gate of the first PMOS transistor M1, the source of the ninth NMOS transistor M9 is connected to the input differential pair transistor, and the drain of the ninth NMOS transistor M9 is connected to the time control switch.

[0041] Furthermore, this application disconnects the input differential pair transistors from the positive feedback circuit by setting a time-controlled switch, thereby isolating the positive feedback circuit and stabilizing the potential during the reset phase. Specifically, the time-controlled switch includes a fourth NMOS transistor M4 and an eighth NMOS transistor M8. The gate of the fourth NMOS transistor M4 is connected to the comparator clock CLK, the source of the fourth NMOS transistor M4 is connected to the isolation switch, and the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M2. The gate of the eighth NMOS transistor M8 is connected to the comparator clock CLK, the source of the eighth NMOS transistor M8 is connected to the isolation switch, and the drain of the eighth NMOS transistor M8 is connected to the drain of the first PMOS transistor M1.

[0042] To ensure consistent charge levels in both branches during the reset phase, this application adds a fourteenth NMOS transistor M14 at the drain node of the input differential pair, which is only turned on during the reset phase. The source of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair, the gate of the fourteenth NMOS transistor M14 is connected to the comparator clock CLKB, and the drain of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair.

[0043] This application retains the characteristic of grounding the input differential pair transistors in a traditional dual-tailed comparator, providing higher input stage transconductance, thereby enabling rapid discharge of noise voltage. Specifically, the input differential pair transistors include a fifth NMOS transistor M5 and a seventh NMOS transistor M7. The gate of the fifth NMOS transistor M5 is connected to the input voltage VIP, the source of the fifth NMOS transistor M5 is grounded to VSS, and the drain of the fifth NMOS transistor M5 is connected to the source of the isolating switch and the drain of the connecting switch. The gate of the seventh NMOS transistor M7 is connected to the input voltage VIP, the source of the seventh NMOS transistor M7 is grounded to VSS, and the drain of the seventh NMOS transistor M7 is connected to the source of the isolating switch and the drain of the connecting switch.

[0044] This application uses a correction capacitor module mounted on a positive feedback circuit to compensate for offset phenomena, thereby achieving offset calibration. This application directly calibrates the comparator's offset, combining metastable calibration and a varactor diode to finely adjust the size of the correction capacitor, achieving extremely high offset calibration accuracy. This eliminates the need for a preamplifier stage during multi-stage comparator calibration, and better compensates for comparator offset phenomena in high-speed scenarios.

[0045] Specifically, please refer to Figure 1 The two parts in the middle frame are: the correction capacitor module is a variable capacitor with a PMOS transistor, the source and drain of the PMOS transistor are shorted to the substrate, and it is symmetrically mounted on both sides of the comparator positive feedback circuit as one plate of the variable capacitor; the gate of the PMOS transistor is connected to the modulated control voltage switch as the other plate of the variable capacitor, and then switched between two high and low control voltages VRP and VRN.

[0046] Specifically, since the function of the correction capacitor module is mainly concentrated during the voltage drop process before the positive feedback begins, the comparator operation becomes dominated by the positive feedback regeneration circuit after the positive feedback begins. During the voltage drop process, the node has no active drive, resulting in extremely low charge discharge. Therefore, a very small correction capacitor is needed for load adjustment to achieve the required accuracy. However, existing metal capacitors are insufficient to meet such small capacitance requirements. While using capacitors in series can achieve the required capacitance, it significantly increases the chip area. This application uses a PMOS variable capacitor as the correction capacitor to compensate for the comparator's offset. Based on the characteristic that the capacitance of a PMOS variable capacitor varies with the voltage difference across its terminals, the equivalent capacitance connected to the positive feedback node is controlled by adjusting the initial voltage of the lower plate of the correction capacitor, thus solving the problem of achieving ultra-low capacitance. During the voltage drop process, the PMOS variable capacitor changes capacitance with different lower plate voltages... The equivalent capacitance value under the following conditions can be expressed as:

[0047] ;

[0048] In the formula, C var (V) is the capacitance across the PMOS variable as a function of the voltage difference across it. This represents the equivalent capacitance of the PMOS varactor. This is the power supply voltage. This is the voltage of the lower plate. This is the threshold voltage of the PMOS transistor.

[0049] This application utilizes the reference voltage of a PMOS varactor diode to modulate the correction capacitor. Specifically, when using a PMOS varactor diode of the minimum size specified in the design rules, C... var The function curve of (V) is as follows Figure 2 As shown, the horizontal axis represents the bias voltage (volts), and the vertical axis represents the capacitance value (picofarads). The solid blue line represents the capacitance change under different voltages. Different shaded areas represent different... In a single comparison process, the amount of charge discharged on the unit load correction capacitor can be modulated by the reference voltage of the PMOS varactor (varactor diode) to obtain a more precise offset correction capacitor, thereby reducing the single-step size of offset calibration and achieving more precise offset calibration.

[0050] This application sets the correction capacitor module to non-binary weights and reserves a certain amount of redundant bits. Even if a bit error occurs, the subsequent capacitor weights can cover the weight of that erroneous bit, and a certain amount of redundancy (N bits) is reserved, thereby greatly reducing the impact of noise-induced bit errors on correction accuracy. The capacitor with the above-mentioned redundant bits is inserted into the lowest weight capacitor ( After that, Encode the weights, where i is the current redundant capacitor position number, i is a positive integer from 1 to N, and set the difference term as... This is used in conjunction with the metastable state criterion, utilizing a capacitance value slightly higher than the minimum value. The load capacitor is used to construct a more refined calibration capacitor module. Furthermore, the comparator metastability discrimination circuit added to the calibration capacitor module can be matched with a delayed clock. The offset magnitude of the delayed clock is determined by the duration of the comparator's metastability, thereby allowing for more precise control over the comparator's offset calibration accuracy. The clock delay magnitude is determined through simulation and is set to a value that reflects the comparator's... The discrimination delay under mismatch conditions is adjusted, and a certain margin is left on this basis to reduce mismatch calibration compensation.

[0051] When the input voltages on both sides of the comparator's positive feedback circuit are the same, the lower the input offset voltage, the more consistent the discharge rates between the two branches. Therefore, a longer amplification time is required to activate the positive feedback regeneration node, directly increasing the comparator's propagation delay from the start of comparison to the completion of the comparison output. During this delay, the comparator is in a metastable state, and its outputs are both zero. Therefore, this application uses the comparator's propagation delay as a standard to measure the offset voltage in its input correction capacitor module, and adds a comparator delay criterion to the original calibration timing to dynamically determine the comparator's input offset voltage. This application uses propagation delay as an offset criterion to dynamically monitor and compensate for comparator offset phenomena.

[0052] A second aspect of this application provides a dual-tailed comparator operation method for a column-end ADC of a pixel sensor, including:

[0053] First, a low-level comparison clock CLK is input to the latch module, resetting it. The zeroth PMOS transistor M0 and the third PMOS transistor M3 are turned on, charging the mutually coupled positive feedback circuits on both sides to a high level. This high level is then output through the eleventh PMOS transistor M11 and the twelfth NMOS transistor M12 of the left inverter and the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 of the right inverter. The potential of the lower node is maintained at the same level through the conducting switch, the fourteenth NMOS transistor M14.

[0054] Secondly, a high-level comparison clock CLK is input to the latch module, turning off the zeroth PMOS transistor M0, the third PMOS transistor M3, and the fourteenth NMOS transistor M14. However, the gate voltages of the fifth NMOS transistor M5 and the seventh NMOS transistor M7 in the input differential pair are different, resulting in a difference in charge discharge speed between the two sides. If the input voltage VIP > VIN, the discharge speed of the left branch is greater than that of the right. Once the potential of this node in the positive feedback circuit on this side is discharged to the turn-on voltage (VDD-VTHP) of transistors M1 / M2, the positive feedback circuit operates and takes over the subsequent comparison process. At this time, the current discharge speed on the other side decreases due to the reduced gate voltage of the ninth NMOS transistor M9. Simultaneously, the first PMOS transistor M1 turns on, charging the right positive feedback node to VDD, causing the gate voltage on the left to rise. This gate voltage turns off the second PMOS transistor M2 and restores the sixth NMOS transistor M6 to full turn-on, further accelerating the current discharge on this side and pulling it down to ground VSS. Finally, one end of the comparator outputs power VDD, and the other end outputs ground VSS, completing the comparison process.

[0055] Next, the modulation correction capacitor module is used. V PA value of 900mV was used to obtain the absolute value of the equivalent differential load capacitance of 20aF, resulting in an offset calibration step size of 600μV. The modulated correction capacitor module was then used to compensate for the offset generated during the comparison process.

[0056] Specifically, please refer to Figure 3 First, connect the common-mode voltage level to the input differential pair of the dual-tailed comparator and connect the two ends to the maximum calibration capacitor. Input a comparison clock to start the comparator and perform a binary search for the mismatched capacitor until the lowest weighted capacitor has been compared. Then, the comparator performs one more comparison. Based on the result of this comparison and the result before the lowest weighted capacitor was reset, it determines whether the mismatched capacitor before the last comparison is greater than... (At this point, the mismatched capacitance must be less than) If the offset capacitance is greater than 100% in this state If the lowest weight capacitor is disconnected, the redundant bit is connected to continue the search and comparison. If the offset capacitor is less than 1 in this state... Then the lowest weight capacitor is reversed, so that its mismatched capacitor is in ( , Between these parameters, redundant capacitors are connected for comparison. During the comparison process, the comparator metastable time criterion is used to dynamically determine whether the mismatched capacitor has reached the expected level: if the comparator completes the comparison within the set delay time, it is considered that the comparator still has a large mismatch, and the subsequent search continues; if the comparator does not complete the comparison within the set delay time, and the outputs at both ends are low, the positive terminal correction load capacitor is reduced to determine whether it has reached the correction bit number. If so, the comparator is considered to have reached the required accuracy; otherwise, the comparator continues the comparison; if the outputs at both ends are high, the negative terminal correction load capacitor is reduced to determine whether it has reached the correction bit number. If so, the comparator is considered to have reached the required accuracy; otherwise, the comparator continues the comparison.

[0057] This application uses a 5-bit weighted matrix + 3-bit redundant matrix to design the calibration circuit, and the weights of each correction capacitor are shown in Table 1. Under these conditions, the simulation results of the comparator correction algorithm are as follows: Figure 4 As shown. At ①, the calibration begins. Then, at ②, the comparator performs continuous comparisons and searches for the equivalent mismatch capacitance of both branches. At ③, the delayed rising edge of the clock arrives before the comparator's established signal, indicating that the offset voltage meets the design criteria. Then, at ④, the comparator calibration algorithm dynamically ends, and the comparator calibration is complete.

[0058] Table 1. Weights of the Corrected Capacitor Array

[0059]

[0060] Specific Implementation Example 1: A Simulation Test

[0061] The dual-tailed comparator circuit of this application is compared with traditional single-tailed or dual-tailed comparators designed with the same width-to-length ratio devices. The comparison simulation results are as follows: Figure 5 As shown.

[0062] Depend on Figure 5 As can be seen, compared with ordinary latch comparators and traditional double-tail comparators, the novel double-tail comparator designed in this paper significantly improves both the amplitude of kickback noise and the noise recovery time. In high-frequency scenarios, the kickback noise amplitude is reduced by more than half, and the recovery time is less than 1 ns. Using voltage-modulated correction capacitors reduces the single-step error calibration from 2 mV to 600 μV, achieving more accurate error correction. Employing a dynamic comparator offset correction method based on comparator metastability further reduces the error calibration step size to N times the original (N being the number of redundant bits in the offset correction capacitor array). Simulation measurements of the comparator offset voltage before and after offset calibration show that the proposed calibration circuit can reduce the offset voltage from 5.40 mV to 0.23 mV.

[0063] In summary, this application can rapidly reduce the amplitude of kickback noise at high frequencies, reduce the calibration step size from 2mV to 600μV, significantly improve calibration time, and achieve more precise offset compensation.

[0064] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0065] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A dual-tailed comparator circuit for a pixel sensor column-end ADC, comprising an input differential pair transistor, characterized in that, It also includes a latch module and a correction capacitor module, wherein the latch module is connected to the input differential pair transistors and the correction capacitor module; The input differential pair transistors are used to provide input stage transconductance and quickly discharge noise voltage; The latch module is used to reduce the amplitude of the kickback noise and shorten the transient process of the kickback noise; The correction capacitor module is configured with non-binary weights and has N redundant bit capacitors for modulating the size of the correction capacitor to compensate for the comparator's offset. The compensation process includes: connecting the two ends of the input differential pair transistors of the dual-tailed comparator to a common-mode level, and connecting the two ends to the maximum calibration capacitor. Inputting comparison clocks CLKB and CLK to start the comparator comparison, performing a binary search for the mismatched capacitor, finding the lowest weight capacitor in the comparison process, the comparator continuing to compare to obtain the comparison result, and determining whether the mismatched capacitor before the last comparison is greater than the lowest weight capacitor based on the comparison result and the comparison result before the lowest weight capacitor is reset. If the mismatched capacitor is greater than the lowest weight capacitor, disconnecting the lowest weight capacitor and connecting the redundant bit capacitor to continue the search and comparison. If the mismatched capacitor is less than the lowest weighted capacitor, the lowest weighted capacitor is reversed and set so that the mismatched capacitor is between the lowest weighted capacitor and twice the lowest weighted capacitor. A redundant bit capacitor is then connected for comparison to determine whether the mismatched capacitor has reached the maximum number of correction bits. If so, the process ends; otherwise, the comparator continues to compare.

2. The dual-tailed comparator circuit for a pixel sensor column-end ADC as described in claim 1, characterized in that, The latch module includes a positive feedback circuit, a time control switch, and a connection switch, wherein the connection switch is connected to the positive feedback circuit. The time-controlled switch is used to disconnect the input differential pair transistors and the positive feedback circuit to ensure a stable potential during the reset phase; The connection switch is used to turn on during the reset phase to ensure that the charge on both sides of the branch is consistent during the reset phase.

3. The dual-tailed comparator circuit for a pixel sensor column-end ADC as described in claim 2, characterized in that, The correction capacitor module is a variable capacitor of a PMOS transistor. The source and drain of the PMOS transistor are shorted to the substrate and are symmetrically mounted on both sides of the positive feedback circuit as the plates of the variable capacitor. The gate of the PMOS transistor is connected to the control voltage switch as the other plate of the variable capacitor. The control voltage switch is used to switch between two high and low control voltages, VRP and VRN.

4. The dual-tailed comparator circuit for a pixel sensor column-end ADC as described in claim 2, characterized in that, The positive feedback circuit includes a zeroth PMOS transistor M0, a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a sixth NMOS transistor M6, a ninth NMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth NMOS transistor M12, and a thirteenth NMOS transistor M13. The sources of the zeroth PMOS transistor M0, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the tenth PMOS transistor M10, and the eleventh PMOS transistor M11 are connected to the power supply. The gate of the zeroth PMOS transistor M0 is connected to the comparator clock CLK. The drain of the zeroth PMOS transistor M0 is connected to the gates of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13. The gate of the second PMOS transistor M2 is connected to the gate of the sixth PMOS transistor M6. The gate of NMOS transistor M6 is connected to the gate of the second PMOS transistor M2, the drain of the first PMOS transistor M1 is connected to the gate of the ninth NMOS transistor M9, the drain of the first PMOS transistor M1 is connected to the time control switch, the gate of the third PMOS transistor M3 is connected to the comparator clock CLK, the drain of the third PMOS transistor M3 is connected to the gates of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12, the drains of the eleventh PMOS transistor M11 and the thirteenth NMOS transistor M13 are connected to the input voltage VOP, the source of the thirteenth NMOS transistor M13 is grounded to VSS, the drains of the tenth PMOS transistor M10 and the twelfth NMOS transistor M12 are connected to the input voltage VON, and the source of the twelfth NMOS transistor M12 is grounded to VSS.

5. The dual-tailed comparator circuit for a pixel sensor column-end ADC as described in claim 4, characterized in that, The sixth NMOS transistor M6 and the ninth NMOS transistor M9 are isolation switches. The isolation switches are used to isolate the kickback noise introduced by the change of the comparison clock CLK level during the startup phase, and to cancel out the positive kickback noise introduced by the comparison clock CLK with the negative kickback noise caused by the common-mode voltage drop.

6. The dual-tailed comparator circuit for a pixel sensor column-end ADC as described in claim 5, characterized in that, The timing switch includes a fourth NMOS transistor M4 and an eighth NMOS transistor M8. The gate of the fourth NMOS transistor M4 is connected to the comparator clock CLK, the source of the fourth NMOS transistor M4 is connected to the isolation switch, and the drain of the fourth NMOS transistor M4 is connected to the drain of the second PMOS transistor M2. The gate of the eighth NMOS transistor M8 is connected to the comparator clock CLK, the source of the eighth NMOS transistor M8 is connected to the isolation switch, and the drain of the eighth NMOS transistor M8 is connected to the drain of the first PMOS transistor M1.

7. The dual-tailed comparator circuit for a pixel sensor column-end ADC as described in claim 6, characterized in that, The connection switch is turned on only during the reset phase. The connection switch is the fourteenth NMOS transistor M14. The source of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistor. The gate of the fourteenth NMOS transistor M14 is connected to the comparator clock CLKB. The drain of the fourteenth NMOS transistor M14 is connected to the source of the isolation switch and the drain of the input differential pair transistor.

8. A method for operating a dual-tailed comparator for a pixel sensor column-end ADC, applied to the dual-tailed comparator circuit for a pixel sensor column-end ADC as described in any one of claims 1-7, characterized in that, Includes the following steps: Input a low-level comparison clock to the latch module to reset the latch module, charge the mutually coupled positive feedback circuits on both sides to a high level, and at the same time keep the potentials on both sides of the switch consistent. A high-level comparison clock is input to the latch module. The difference in discharge speed caused by the input voltage difference triggers the positive feedback circuit, which accelerates the current discharge and completes the voltage comparison. The modulation correction capacitor module compensates for the offset generated during the comparison process; The compensation process includes: connecting the two ends of the input differential pair transistors of the dual-tailed comparator to a common-mode level, and connecting the two ends to the maximum calibration capacitor. Inputting comparison clocks CLKB and CLK to start the comparator comparison, performing a binary search for the mismatched capacitor, finding the lowest weight capacitor in the comparison process, the comparator continuing to compare to obtain the comparison result, and determining whether the mismatched capacitor before the last comparison is greater than the lowest weight capacitor based on the comparison result and the comparison result before the lowest weight capacitor is reset. If the mismatched capacitor is greater than the lowest weight capacitor, disconnecting the lowest weight capacitor and connecting the redundant bit capacitor to continue the search and comparison. If the mismatched capacitor is less than the lowest weighted capacitor, the lowest weighted capacitor is reversed and set so that the mismatched capacitor is between the lowest weighted capacitor and twice the lowest weighted capacitor. A redundant bit capacitor is then connected for comparison to determine whether the mismatched capacitor has reached the maximum number of correction bits. If so, the process ends; otherwise, the comparator continues to compare.

9. The dual-tailed comparator operation method for a pixel sensor column-end ADC as described in claim 8, characterized in that, By accelerating the current discharge, VDD and VSS are output on both sides of the comparator respectively, thus completing the voltage comparison.

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