Reading circuit for improving dynamic range based on composite dielectric gate photosensitive detector

Abstract

The invention discloses a reading circuit for improving a dynamic range based on a composite dielectric gate photosensitive detector, and belongs to the field of integrated circuits. An overflow electron discharge circuit is designed for a composite dielectric gate photosensitive detector pixel in a readout circuit and is used for discharging electrons overflowing after a collection region of the composite dielectric gate photosensitive detector is saturated, so that the equivalent full well capacity is improved; a special time sequence is designed, and the same pixel is continuously read twice in an analog domain and a digital domain to improve the equivalent full well capacity or reduce the read noise so as to improve the dynamic range; therefore, the composite dielectric grating photosensitive detector can obtain a good detection effect in scenes such as astronomical observation, remote sensing monitoring and the like which need to capture high-brightness and low-light targets at the same time.

Description

Technical Field

[0001] The invention relates to a readout circuit for improving the dynamic range based on a composite dielectric grating photosensitive detector, and belongs to the field of integrated circuits. Background Art

[0002] Currently, CCD and CMOS-APS are the two mainstream imaging devices, but each has significant technical limitations. CCD devices require complex timing control and high-voltage drives, resulting in slow operation and difficulty in increasing integration. While CMOS-APS devices offer higher integration, their photodiode structure results in a low pixel fill factor and limited full-well charge capacity.

[0003] To address these issues, Chinese patent application CN102938409A proposes an innovative composite dielectric gate dual-transistor photodetector. This device integrates reset, photosensitivity, and readout functions into a single device, forming a complete pixel unit. This design not only significantly improves the pixel fill factor, but also combines advantages such as high operating speed, high fill factor, and large full-well charge capacity, while being fully compatible with CMOS processes. In particular, its use of a variable-threshold MOSFET signal readout region for signal reading gives it significant inherent performance advantages over traditional CCDs and CMOS-APSs.

[0004] Although composite dielectric gate dual-transistor photodetectors offer significant advantages over traditional CCDs and CMOS-APS in terms of integration, fill factor, and response speed, they still face several key technical bottlenecks that need to be overcome in practical applications. For example, under strong light imaging conditions (such as daytime outdoor scenes), the full well charge capacity of existing devices is still insufficient, making it difficult to effectively cope with high-intensity signals from direct sunlight or strong background light. This not only causes premature saturation of the photoelectric signal, but also significantly compresses the dynamic range of the device, affecting imaging quality. This defect is particularly evident in scenarios such as astronomical observations and remote sensing monitoring that require simultaneous capture of both bright and dim targets. In addition, the device's readout noise level is still relatively high. High readout noise not only reduces the signal-to-noise ratio of the image, but also limits the device's detection sensitivity in low-light environments, making it difficult to meet the stringent requirements of high-end scientific imaging, low-light-level night vision, and other fields. Summary of the Invention

[0005] To further improve the full-well charge capacity, the present invention considers both device-level and circuit-level approaches. However, increasing the full-well charge capacity of a single device at the device level presents significant challenges in terms of pixel area, dark current, thermal noise, and process compatibility. Furthermore, from a circuit-level perspective, the present invention studied existing CMOS-APS solutions and found that one approach to increasing the effective full-well capacity is delayed reset. This involves performing a partial charge transfer after the exposure phase, rather than immediately resetting the floating diffusion (FD) node. This prevents premature FD saturation and thus increases the effective full-well capacity. CMOS-APS can also transfer charge from the photodiode (PD) to the (FD) node in multiple stages via a transfer gate (TX), utilizing multi-stage charge transfer to avoid FD saturation caused by a single charge transfer. This technique requires multi-pulse transfer gate control and multi-phase clocking within the pixel, increasing circuit design complexity. However, since the device structure of a composite dielectric grating photodetector differs from that of a CMOS-APS, and its simplified pixel structure lacks an FD node, this approach cannot be applied to composite dielectric grating photodetectors.

[0006] The present invention addresses the unique structure of a composite dielectric grating photodetector and designs a readout circuit that improves dynamic range. This circuit incorporates an overflow electron discharge circuit for the composite dielectric grating photodetector pixel to discharge electrons that overflow after the collection region of the composite dielectric grating photodetector is saturated, thereby increasing the equivalent full well capacity. Furthermore, a special timing sequence is designed to read out the same pixel twice in succession in both the analog and digital domains to increase the equivalent full well capacity or reduce readout noise, thereby improving dynamic range. The specific scheme is as follows: A readout circuit for improving the dynamic range of a composite dielectric grating photosensitive detector, the circuit comprising a composite dielectric grating photosensitive detector pixel, an overflow electron discharge circuit, a clamping circuit, a switch S1, a precharge circuit, a comparator, a ramp generator, an AND gate, and a counter; The overflow electron discharge circuit includes an external capacitor C ext and reset transistor M Rst , the external capacitor C ext The positive electrode is connected to the drain end of the composite dielectric grating photosensitive detector pixel, and the negative electrode is connected to a negative voltage, the voltage value of the negative voltage is the same as the substrate voltage of the composite dielectric grating photosensitive detector pixel; the reset transistor M Rst Connect in parallel to the external capacitor C ext The two ends of the reset transistor M Rst The drain end is connected to the external capacitor C ext The positive pole of the source is connected to the external capacitor C ext The negative electrode of the gate terminal is provided with an external reset voltage V Reset as the gate voltage.

[0007] Optionally, the clamping circuit includes an amplifier and a first transistor M1, the gate end of the first transistor M1 is connected to the output end of the amplifier, the drain end of the composite dielectric grating photosensitive detector pixel is connected to the negative input end of the amplifier, and the positive input end of the amplifier is provided with a clamping voltage V externally. REF,CLAMP The source terminal of the first transistor M1 is connected to the drain terminal of the composite dielectric gate photosensitive detector pixel to form a feedback loop.

[0008] Optionally, the pre-charging circuit includes an integrating capacitor C INT The drain end of the first transistor M1 of the clamp circuit is connected to one end of the switch S1, and the other end of the switch S1 is connected to the integral capacitor C INT , the source terminal of the second transistor M2 and the positive input terminal of the comparator are connected; in the pre-charging circuit, the gate terminal of the second transistor M2 is connected to the pre-charging voltage V Precharge connected to the external power supply V DD connected, the source end and the integral capacitor C INT The positive electrode is connected to the integral capacitor C INT The negative pole of the

[0009] Optionally, the negative input of the comparator is provided by an external reference voltage V REF,COMP , its output voltage V COMPOUT Together with the read enable signal EN_READ, it serves as the input of the AND gate; the output of the AND gate is connected to the input of the counter; The comparator output voltage V COMPOUT The calculation result of the read enable signal EN_READ is used as the counting basis of the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer timing process, the value of the counter output port increases by 1 at the end of each clock cycle.

[0010] The present invention also provides a high-gain readout method for a composite dielectric grating photosensitive detector, which is implemented based on the above-mentioned readout circuit and includes: Reset stage before exposure: reset transistor M Rst Gate voltage V Reset Connect high level , reset transistor M Rst Close and connect the external capacitor C EXT Perform a reset; Exposure stage: switch S1 is disconnected, and the current signal path of the composite dielectric grating photosensitive detector pixel does not pass through the integration capacitor C INT The comparator and counter are connected, while the amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP ; Precharge voltage VPrecharge At high level VDD, it does not affect the integral capacitor C INT ; Turn off the readout signal EN_READ to stop the counter from working; the MOS-C signal collection area of ​​the composite dielectric grating photosensitive detector pixel generates a depletion region in the substrate under the action of the gate-substrate forward bias, thereby collecting photogenerated carriers and realizing exposure; Reset transistor M Rst In the open state, the reset transistor M Rst Gate voltage V Reset Connect low level V = 0, if the composite dielectric grating photosensitive detector is saturated under light, the external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation; if the light is strong enough, the external capacitor C EXT After charging is completed, the amount of stored charge is:

[0011] Among them, V REF,CLAMP is the clamping voltage, V SUB is the substrate voltage of the composite dielectric grating photosensitive detector, is the capacitance value of the external capacitor; Readout stage: switch S1 is closed, precharge voltage V Precharge Pull down the integral capacitor C INT Precharge to external voltage V DD , after which the precharge voltage V Precharge Pull high to turn on the readout enable signal EN_READ, and the ramp generator provides the gate of the composite dielectric gate photosensitive detector pixel with a voltage from V RampStart Start to gradually increase the voltage until it reaches V RampEnd At this time, turn off the readout signal EN_READ to enable reading; Reset phase: After the readout phase, the switch S1 is disconnected and the circuit is in the reset phase. The drain voltage of the composite dielectric grating photosensitive detector pixel remains constant and is at a stable voltage V REF,CLAMP .

[0012] The present invention also provides a low-noise readout method for a composite dielectric grating photosensitive detector, which is implemented by the above-mentioned readout circuit. The low-noise readout method averages two consecutive readout results in the digital domain. The low-noise readout method includes: Step S1.1: Expose the composite dielectric grating photosensitive detector pixel using an external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation. At this time, the integral capacitor C INTCharging; the ramp generator applies a ramp voltage to the gate of the composite dielectric grating photosensitive detector pixel and the counter starts counting. When the ramp voltage applied by the gate reaches the threshold of the composite dielectric grating photosensitive detector readout transistor, the readout transistor is turned on and the integral capacitor C int Discharge, the discharge rate is determined by the number of photoelectrons collected by the composite dielectric grating photosensitive detector and the external capacitor C EXT The amount of stored charge determines the integral capacitor C INT After the discharge is completed, the counter stops counting synchronously, and the value of the counter at this time is recorded as the pixel gray value DN1; Step S1.2, reduce the ramp generator voltage to the starting voltage V RAMP After that, the integral capacitor C INT Recharge and read out for the second time, the counter output value is recorded as the pixel gray value DN2; Step S1.3, the grayscale value DN output by the pixel of the composite dielectric grating photosensitive detector is: .

[0013] The present invention also provides a low-noise readout method for a composite dielectric grating photosensitive detector. The method is implemented based on the above-mentioned readout circuit. The low-noise readout method averages two readout results in the analog domain. The low-noise readout method includes: Step S2.1: Expose the composite dielectric grating photosensitive detector pixel using an external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation, and at the same time INT Charge; Step S2.2: The ramp generator applies a constant voltage greater than the threshold of the readout transistor of the composite dielectric grating photosensitive detector to the gate of the composite dielectric grating photosensitive detector pixel, and applies a voltage to the integral capacitor C INT Discharging, after completing the fixed time of discharge, stopping the discharge by stopping applying the constant voltage on the gate of the composite dielectric grating photosensitive detector pixel; Step S2.3, resetting the exposure signal in the pixel of the composite dielectric grating photosensitive detector and performing exposure again; Step S2.4: Repeat the readout operation of step S2.2, with the same discharge time as step S2.2; Step S2.5, read the integral capacitor C INT The residual charge in the grayscale is DN, and the average of the charge released by the two discharges is recorded as the grayscale value DN.

[0014] The present invention also provides a high full well charge readout method for a composite dielectric grating photosensitive detector. The method is implemented based on the above-mentioned readout circuit. The high full well charge readout method sums two consecutive readout results in the analog domain or the digital domain.

[0015] The beneficial effects of the present invention are: By designing an overflow electron discharge circuit for the composite dielectric grating photosensitive detector pixel in the readout circuit to discharge the electrons that overflow after the collection area of ​​the composite dielectric grating photosensitive detector is saturated, the equivalent full well capacity is improved. In addition, a special timing is designed to read the same pixel twice in succession in the analog domain and the digital domain to increase the equivalent full well capacity or reduce the readout noise to improve the dynamic range. This enables the composite dielectric grating photosensitive detector to achieve better detection effects in scenarios such as astronomical observation and remote sensing monitoring that require simultaneous capture of high-brightness and low-light targets. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 Schematic diagram of the readout circuit based on the composite dielectric grating photodetector.

[0018] Figure 2 This is a timing diagram of the working phase of the high-gain readout circuit based on the composite dielectric grating photodetector.

[0019] Figure 3 This is a timing diagram of the working stages of the digital domain double-reading readout circuit based on the composite dielectric grating photodetector.

[0020] Figure 4 This is the timing diagram of the working stages of the analog domain double-read readout circuit based on the composite dielectric grating photodetector. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0022] Example 1 This embodiment provides a readout circuit based on a composite dielectric grating photosensitive detector with improved dynamic range. Figure 1 The circuit includes a composite dielectric grating photodetector pixel, an overflow electron discharge circuit, a clamping circuit, a switch S1, a precharge circuit, a comparator, a ramp generator, an AND gate, and a counter. The specific structure of the composite dielectric grating photodetector can be found in the Chinese patent publication number CN102938409A. The gate terminal of the composite dielectric grating photodetector pixel is connected to the ramp generator, the source terminal is grounded, and the drain terminal is connected to the input terminal of the clamping circuit.

[0023] The overflow electronic discharge circuit includes an external capacitor C ext and reset transistor M Rst , external capacitor C ext The positive electrode is connected to the drain end of the composite dielectric grating photosensitive detector pixel, and the negative electrode is connected to a negative voltage, the voltage value of the negative voltage is the same as the substrate voltage of the composite dielectric grating photosensitive detector pixel; the reset transistor M Rst Connect in parallel to the external capacitor C ext The two ends of the reset transistor M Rst The drain end is connected to the external capacitor C ext The positive pole of the source is connected to the external capacitor C ext The negative electrode of the gate terminal is provided with an external reset voltage V Reset .

[0024] The clamping circuit is composed of an amplifier and a transistor (hereinafter referred to as the first transistor M1 ); the pre-charging circuit is composed of an integrating capacitor CINT and a transistor (hereinafter referred to as the second transistor M2 ).

[0025] In the clamping circuit, the gate terminal of the first transistor M1 is connected to the output terminal of the amplifier, the drain terminal of the composite dielectric grating photosensitive detector pixel is connected to the negative input terminal of the amplifier, and the positive input terminal of the amplifier is provided with a clamping voltage V externally. REF,CLAMP The source terminal of the first transistor M1 is connected to the drain terminal of the composite dielectric gate photosensitive detector pixel to form a feedback loop.

[0026] The drain end of the first transistor M1 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the integral capacitor C INT , the source terminal of the second transistor M2 and the positive input terminal of the comparator are connected; in the pre-charging circuit, the gate terminal of the second transistor M2 is connected to the pre-charging voltage V Precharge connected to the external power supply V DD connected, the source end and the integral capacitor C INT The positive electrode is connected to the integral capacitor C INT The negative pole of the

[0027] The other input of the comparator is provided by an external reference voltage V REF,COMP , its output voltage V COMPOUT The output of the AND gate is connected to the input of the counter, and the output voltage of the comparator V COMPOUT The calculation result of the read enable signal EN_READ is used as the counting basis of the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer timing process, the value of the counter output port increases by 1 at the end of each clock cycle.

[0028] Generally, the readout circuit has three working stages, including exposure stage, readout stage and reset stage. This embodiment designs a special timing for the additional overflow electron discharge circuit to achieve high-gain readout and thus improve the dynamic range. It includes four stages, namely, pre-exposure reset stage, exposure stage, readout stage and reset stage. That is, the pre-exposure reset stage is added before the exposure stage to EXT Reset to use external capacitor C during exposure EXT Discharge the electrons that overflow after the collection area of ​​the composite dielectric grating photosensitive detector is saturated, such as Figure 2 As shown: 1. Reset stage before exposure, reset transistor M Rst Gate voltage V Reset From low level to high level , reset transistor M Rst Close and connect the external capacitor C EXT Perform a reset.

[0029] 2. Exposure stage: When the switch S1 is disconnected, the circuit is in the exposure stage, and the current signal path of the composite dielectric grating photosensitive detector pixel does not pass through the integral capacitor C INT The comparator and counter circuits are connected, while the amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP , pre-charge voltage V Precharge At high level VDD, it does not affect the integral capacitor C INT Turning off the readout signal EN_READ disables the counter. Under the action of the gate-substrate forward bias, the MOS-C signal collection area of ​​the composite dielectric grating photodetector pixel generates a depletion region in the substrate, collecting photogenerated carriers and achieving exposure.

[0030] At this stage, the reset transistor M Rst If the composite dielectric grating photosensitive detector is saturated under light, the external capacitor C EXT It can collect the overflow electrons that cannot be collected after saturation. If the light is strong enough, the external capacitor C EXT After charging is completed, the amount of stored charge is: , where V REF,CLAMP is the clamping voltage, V SUB is the substrate voltage of the composite dielectric grating photosensitive detector, is the capacitance value of the external capacitor.

[0031] 3. Readout stage: When switch S1 is closed, the circuit is in the readout stage, and the precharge voltage V Precharge Pull down the integral capacitor C INT Precharge to external voltage VDD After that, the precharge voltage V Precharge Pull high to turn on the readout enable signal EN_READ, and the ramp generator provides the gate of the composite dielectric gate photosensitive detector pixel with a voltage from V RampStart Start to gradually increase the voltage until it reaches V RampEnd At this time, turn off the read signal EN_READ to enable reading.

[0032] The drain voltage of the composite dielectric grating photosensitive detector pixel is stabilized at V REF,CLAMP The ramp generator maintains the initial voltage V RampStart unchanged, the pre-charge voltage V Precharge Pull down, the second transistor M2 is turned on and the integral capacitor C INT Precharge to V DD , at this time the voltage on the integrating capacitor plate V X = V DD >V REF,COMP , so the comparator output V COMPOUT After the pre-charge is completed, the pre-charge voltage V Precharge Pull high to V DD , and at the same time turn on the read enable signal EN_READ, with the V COMPOUT EN_READ is used as the enable signal of the counter through the AND gate, and the counter starts counting. At the same time, the ramp voltage generated by the ramp generator is from V RampStart The composite dielectric grating photosensitive detector pixel pair integral capacitance C INT Discharge, the voltage on the plate of the integrating capacitor V X Gradually decreases, when V X drops below the comparator reference level V REF,COMP When the comparator outputs V COMPOUT Flip, from logic 1 to logic 0, it and EN_READ pass through the AND gate and output logic 0, and serve as the enable signal of the counter to stop counting, the count value is V OUT,CNT After that, when the ramp voltage provided by the ramp generator reaches V RampEnd When , turn off the readout signal EN_READ to enable reading.

[0033] 4. Reset phase: After the readout phase, switch S1 is disconnected and the circuit is in the reset phase. The drain voltage of the composite dielectric grating photosensitive detector pixel remains constant and is at a stable voltage V REF,CLAMP .

[0034] In this stage, a suitable negative bias voltage V is applied between the gate and substrate of the composite dielectric grating photosensitive detector pixel. Reset, the photoelectrons collected at the P-type substrate interface of MOS-C will leak out through the electrodes connected to the substrate under the action of the electric field. Turn off the readout enable signal EN_READ, and make the counter enable signal always logic 0 through the AND gate. The count value of the counter remains V OUT,CNT constant.

[0035] Example 2 This embodiment is based on the readout circuit for improving the dynamic range of the composite dielectric grating photosensitive detector provided in Example 1 to achieve low-noise or high full-well charge readout. Under the circuit structure described in Example 1, two consecutive readout results are averaged in the digital domain to reduce the readout noise, and the equivalent full-well charge is increased by repeatedly exposing the same pixel.

[0036] Step S1.1, the composite dielectric grating photosensitive detector pixel performs an exposure operation, and the composite dielectric grating photosensitive detector collects photoelectrons. The overflow electrons that cannot be collected after saturation are collected by the external capacitor C. EXT Collect, at this time the integration capacitor C INT Charging; the ramp generator applies a ramp voltage to the gate of the composite dielectric grating photosensitive detector pixel and the counter starts counting. When the ramp voltage applied by the gate reaches the threshold of the composite dielectric grating photosensitive detector readout transistor, the transistor is turned on and the integral capacitor C INT Discharge, the discharge rate is determined by the number of photoelectrons collected by the composite dielectric grating photosensitive detector and the external capacitor C EXT The amount of stored charge determines the integral capacitor C INT After the discharge is completed, the counter stops counting synchronously. The value of the counter at this time is the grayscale value DN1 of the pixel. Step S1.2, reduce the ramp generator voltage to the starting voltage V RAMP After that, the integral capacitor C INT Recharge and read out for the second time, the counter output value is the pixel gray value DN2; Step S1.3, output grayscale value DN; Step S1.3.1: average the two consecutive readout results to reduce the readout noise. The pixel output grayscale value DN of the composite dielectric grating photosensitive detector is: .

[0037] The working sequence of the readout circuit for two consecutive readouts in the digital domain is as follows Figure 3As shown. The circuit has four working stages: exposure stage, first readout stage, second readout stage, and reset stage. The exposure stage, first readout stage, and reset stage are the same as those described in Example 1. A second readout stage is added after the first readout stage for performing a second continuous readout without resetting or re-exposure. The readout signal is sampled twice independently, and random timing noise is reduced by digital domain averaging. The noise power reduction ratio is times.

[0038] Step S1.3.2, read the integral capacitor C INT The residual charge DN2 in the integral capacitor is recorded as the grayscale value accumulated by the two exposures. To achieve high full well charge readout.

[0039] In the second readout phase, the switch S1 is disconnected, the readout enable signal EN_READ is turned off, and the counter enable signal is always logic 0 through the AND gate, and the count value of the counter remains V OUT,CNT The ramp voltage generated by the ramp generator is from V RampEnd Reduce to V RampStart At this time, switch S1 is closed and the read enable signal EN_READ is turned on, and V COMPOUT EN_READ is used as the enable signal of the counter through the AND gate, the counter starts counting, and the circuit realizes the second continuous readout.

[0040] Averaging the two readout results in the analog domain can also reduce the readout noise. The solution is as follows: Step S2.1, the composite dielectric grating photosensitive detector pixel performs an exposure operation, and the composite dielectric grating photosensitive detector collects photoelectrons. The overflow electrons that cannot be collected after saturation are collected by the external capacitor C. EXT Collect and integrate capacitor C INT Charge; Step S2.2: The ramp generator applies a constant voltage greater than the threshold of the readout transistor of the composite dielectric grating photosensitive detector to the gate of the composite dielectric grating photosensitive detector pixel, and applies a voltage to the integral capacitor C INT Discharging, after completing the fixed time of discharge, stopping the discharge by stopping applying the constant voltage on the gate of the composite dielectric grating photosensitive detector pixel; Step S2.3, resetting the exposure signal in the pixel of the composite dielectric grating photosensitive detector and performing exposure again; Step S2.4: Repeat the readout operation of step S2.2, with the same discharge time as step S2.2; Step S2.5, outputting the grayscale value DN; Step S2.5.1, read the integral capacitance C INT The residual charge in the ,the average charge released by two discharges is recorded as the gray value DN to achieve low-noise readout; Step S2.5.2, read the integral capacitor C INT The residual charge in the well is recorded, and the charge released by the two discharges is recorded as the grayscale value DN accumulated by the two exposures to achieve high full-well charge readout.

[0041] The working sequence of the readout circuit for two consecutive readouts in the analog domain is as follows Figure 4 As shown. The circuit has six working stages: the first exposure stage, the first readout stage, the first reset stage, the second exposure stage, the second readout stage, and the second reset stage. Among them, the first exposure stage is the same as the exposure stage in Example 1; the second readout stage and the second readout stage are the same as the readout stage in Example 1; the first reset stage and the second reset stage are the same as the reset stage in Example 1. The ramp voltage of the ramp generator in the second exposure stage is V after the first reset stage. Reset Gradually increases to the ramp start voltage V RampStart .

[0042] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A readout circuit for improving the dynamic range of a composite dielectric grating photodetector, characterized in that: The circuit includes a composite dielectric grating photosensitive detector pixel, an overflow electron discharge circuit, a clamping circuit, a switch S1, a precharge circuit, a comparator, a ramp generator, an AND gate, and a counter; The overflow electron discharge circuit includes an external capacitor C ext and reset transistor M Rst , the external capacitor C ext The positive electrode is connected to the drain end of the composite dielectric grating photosensitive detector pixel, and the negative electrode is connected to a negative voltage, the voltage value of the negative voltage is the same as the substrate voltage of the composite dielectric grating photosensitive detector pixel; the reset transistor M Rst Connect in parallel to the external capacitor C ext The two ends of the reset transistor M Rst The drain end is connected to the external capacitor C ext The positive pole of the source is connected to the external capacitor C ext The negative electrode of the gate terminal is provided with an external reset voltage V Reset as the gate voltage.

2. The readout circuit according to claim 1, wherein: The clamping circuit includes an amplifier and a first transistor M1. The gate end of the first transistor M1 is connected to the output end of the amplifier. The drain end of the composite dielectric grating photosensitive detector pixel is connected to the negative input end of the amplifier. The positive input end of the amplifier is provided with a clamping voltage V by an external source. REF,CLAMP ; The source end of the first transistor M1 is connected to the drain end of the composite dielectric gate photosensitive detector pixel to form a feedback loop.

3. The readout circuit according to claim 2, wherein: The pre-charge circuit includes an integrating capacitor C INT The drain end of the first transistor M1 of the clamp circuit is connected to one end of the switch S1, and the other end of the switch S1 is connected to the integral capacitor C INT , the source terminal of the second transistor M2 and the positive input terminal of the comparator are connected; In the pre-charging circuit, the gate terminal of the second transistor M2 is connected to the external pre-charging voltage V Precharge connected to the external power supply V DD connected, the source end and the integral capacitor C INT The positive electrode is connected to the integral capacitor C INT The negative pole of the 4. The readout circuit according to claim 3, wherein: The negative input of the comparator is provided by an external reference voltage V REF,COMP , its output voltage V COMPOUT Together with the read enable signal EN_READ, it serves as the input of the AND gate; the output of the AND gate is connected to the input of the counter; The comparator output voltage V COMPOUT The calculation result of the read enable signal EN_READ is used as the counting basis of the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer timing process, the value of the counter output port increases by 1 at the end of each clock cycle.

5. A high-gain readout method for a composite dielectric grating photodetector, the method being implemented based on the readout circuit for improving dynamic range based on a composite dielectric grating photodetector according to any one of claims 1 to 4, the high-gain readout method comprising: Reset stage before exposure: reset transistor M Rst The gate voltage V Reset Connect high level , reset transistor M Rst Close and connect the external capacitor C EXT Perform a reset; Exposure stage: switch S1 is disconnected, and the current signal path of the composite dielectric grating photosensitive detector pixel does not pass through the integration capacitor C INT The comparator and counter are connected, while the amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP ; Precharge voltage V Precharge At high level VDD, it does not affect the integral capacitor C INT ; Turn off the readout signal EN_READ to stop the counter from working; the MOS-C signal collection area of ​​the composite dielectric grating photosensitive detector pixel generates a depletion region in the substrate under the action of the gate-substrate forward bias, thereby collecting photogenerated carriers and realizing exposure; Reset transistor M Rst In the open state, the reset transistor M Rst Gate voltage V Reset Connect low level V = 0, if the composite dielectric grating photosensitive detector is saturated under light, the external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation; if the light is strong enough, the external capacitor C EXT After charging is completed, the amount of stored charge is: Among them, V REF,CLAMP is the clamping voltage, V SUB is the substrate voltage of the composite dielectric grating photosensitive detector, is the capacitance value of the external capacitor; Readout stage: switch S1 is closed, precharge voltage V Precharge Pull down the integral capacitor C INT Precharge to external voltage V DD , after which the precharge voltage V Precharge Pull high to turn on the readout enable signal EN_READ, and the ramp generator provides the gate of the composite dielectric gate photosensitive detector pixel with a voltage from V RampStart Start to gradually increase the voltage until it reaches V RampEnd At this time, turn off the readout signal EN_READ to enable reading; Reset phase: After the readout phase, the switch S1 is disconnected and the circuit is in the reset phase. The drain voltage of the composite dielectric grating photosensitive detector pixel remains constant and is at a stable voltage V REF,CLAMP .

6. A low-noise readout method for a composite dielectric grating photodetector, characterized in that: The method is implemented based on the readout circuit for improving the dynamic range of the composite dielectric grating photosensitive detector according to any one of claims 1 to 4, wherein the low-noise readout method averages two consecutive readout results in the digital domain; The low-noise readout method comprises: Step S1.1: Expose the composite dielectric grating photosensitive detector pixel using an external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation. At this time, the integral capacitor C INT Charging; the ramp generator applies a ramp voltage to the gate of the composite dielectric grating photosensitive detector pixel and the counter starts counting. When the ramp voltage applied by the gate reaches the threshold of the composite dielectric grating photosensitive detector readout transistor, the readout transistor is turned on and the integral capacitor C int Discharge, the discharge rate is determined by the number of photoelectrons collected by the composite dielectric grating photosensitive detector and the external capacitor C EXT The amount of stored charge determines the integral capacitor C INT After the discharge is completed, the counter stops counting synchronously, and the value of the counter at this time is recorded as the pixel gray value DN1; Step S1.2, reduce the ramp generator voltage to the starting voltage V RAMP After that, the integral capacitor C INT Recharge and read out for the second time, the counter output value is recorded as the pixel gray value DN2; Step S1.3, the grayscale value DN output by the pixel of the composite dielectric grating photosensitive detector is: .

7. A low-noise readout method for a composite dielectric grating photosensitive detector, characterized in that: The method is implemented based on the readout circuit for improving the dynamic range of the composite dielectric grating photosensitive detector according to any one of claims 1 to 4, wherein the low-noise readout method averages the two readout results in the analog domain; The low-noise readout method comprises: Step S2.1: Expose the composite dielectric grating photosensitive detector pixel using an external capacitor C EXT Collect the overflow electrons that cannot be collected after saturation, and at the same time INT Charge; Step S2.2: The ramp generator applies a constant voltage greater than the threshold of the readout transistor of the composite dielectric grating photosensitive detector to the gate of the composite dielectric grating photosensitive detector pixel, and applies a voltage to the integral capacitor C INT Discharging, after completing the fixed time of discharge, stopping the discharge by stopping applying the constant voltage on the gate of the composite dielectric grating photosensitive detector pixel; Step S2.3, resetting the exposure signal in the pixel of the composite dielectric grating photosensitive detector and performing exposure again; Step S2.4: Repeat the readout operation of step S2.2, with the same discharge time as step S2.2; Step S2.5, read the integral capacitor C INT The residual charge in the grayscale is DN, and the average of the charge released by the two discharges is recorded as the grayscale value DN.

8. A method for reading out high full well charge of a composite dielectric grating photodetector, characterized in that: The method is implemented based on the readout circuit for improving the dynamic range of the composite dielectric grating photodetector according to any one of claims 1 to 4, and the high full well charge readout method sums two consecutive readout results in the analog domain or the digital domain.

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