Memory device and manufacturing method thereof
By adopting a dual work function word line structure in the memory device, using a fluorine-containing region and a low work function second word line layer design to capture electron-hole pairs, the problem of gate-induced drain leakage is solved and the memory performance is improved.
Patent Information
- Application Number
- CN202411616171.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-12
- Filing Date
- 2024-11-13
- Publication Date
- 2025-09-12
AI Technical Summary
Gate induced drain leakage (GIDL) in conventional memory devices needs to be further reduced to enhance device performance.
A dual work function word line structure is adopted. By forming a fluorine-containing area and a second low work function word line layer in the substrate, combined with the gate dielectric layer and barrier layer design, the number of electron-hole pairs is reduced and the electron-hole pairs are captured to reduce GIDL.
The gate induced drain leakage (GIDL) in the memory device is effectively reduced, thereby improving the performance of the memory device.
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Figure CN120640677A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a memory device and a method for manufacturing the same. Background Art
[0002] A dual-work-function wordline structure is a common wordline structure in memory devices. This structure comprises two conductive layers with different work functions, with source / drain regions formed flanking the conductive layer with the lower work function. This reduces gate-induced drain leakage (GIDL) in memory devices. However, GIDL needs to be further reduced to enhance memory device performance. Summary of the Invention
[0003] Some embodiments of the present invention provide a memory device comprising a substrate, a first wordline layer, a second wordline layer, a gate dielectric layer, and a plurality of source / drain regions. The first wordline layer is in the substrate. The second wordline layer is in the substrate and above the first wordline layer. The gate dielectric layer conformally extends along the sides and bottom of the first wordline layer and the sides of the second wordline layer. Source / drain regions are on the substrate and on opposing sides of the second wordline layer, wherein one of the source / drain regions includes a first fluorine-containing region adjacent to the second wordline layer.
[0004] In some embodiments, a bottom of the first fluorine-containing region is substantially flush with a top of the first word line layer.
[0005] In some embodiments, the memory device further includes a cap layer above the second word line layer, wherein the first fluorine-containing region is adjacent to the cap layer.
[0006] In some embodiments, the memory device further includes a barrier layer between the cap layer and the second word line layer.
[0007] In some embodiments, a portion of the gate dielectric layer above the top surface of the first word line layer includes fluorine.
[0008] In some embodiments, a fluorine concentration of a portion of the gate dielectric layer along the sidewalls and bottom of the first word line layer is lower than a fluorine concentration of a portion of the gate dielectric layer along the sidewalls of the second word line layer.
[0009] In some embodiments, a portion of one of the source / drain regions does not include fluorine.
[0010] In some embodiments, the memory device further includes a barrier layer between the first word line layer and the second word line layer.
[0011] In some embodiments, the memory device further includes an isolation structure in the substrate, wherein the isolation structure includes a second fluorine-containing region.
[0012] In some embodiments, the second word line layer is made of polysilicon.
[0013] Some embodiments of the present invention provide a method for manufacturing a memory device, the method comprising: forming a trench in a substrate; forming a gate dielectric layer along a surface of the trench in the substrate; forming a first word line layer above the gate dielectric layer and in the trench; after forming the first word line layer, performing an implantation process to form a first fluorine-containing region in the substrate; and after the implantation process is completed, forming a second word line layer in the trench and above the first word line.
[0014] In some embodiments, the implantation process is performed by implanting a plurality of ions into the substrate at an oblique angle relative to a top surface of the substrate.
[0015] In some embodiments, during the implantation process, fluorine is implanted into a portion of the gate dielectric layer exposed by the trench.
[0016] In some embodiments, the fabrication method further includes forming a capping layer in the trench and above the second word line, wherein the first fluorine-containing region is adjacent to the capping layer.
[0017] In some embodiments, the manufacturing method further includes forming a barrier layer over the second word line layer, wherein the barrier layer is formed before forming the cap layer.
[0018] In some embodiments, the manufacturing method further includes forming a barrier layer over the first word line layer, wherein the barrier layer is formed before forming the second word line layer.
[0019] In some embodiments, the first fluorine-containing region is adjacent to the second word line layer.
[0020] In some embodiments, a bottom of the first fluorine-containing region is substantially flush with a top of the first word line layer.
[0021] In some embodiments, the work function value of the second word line layer is lower than the work function value of the first word line layer.
[0022] In some embodiments, the manufacturing method further includes forming an isolation structure in the substrate, wherein a second fluorine-containing region is formed in the isolation structure during the implantation process.
[0023] It is to be understood that both the foregoing general description and the following detailed description are merely examples, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The present invention will be best understood by reading the following detailed description of the embodiments with reference to the accompanying drawings:
[0025] Figure 1FIG. 1 is a circuit diagram of a memory device according to some embodiments of the present invention.
[0026] Figures 2 to 14 A cross-section diagram illustrates a method for fabricating a memory device in accordance with some embodiments of the present invention. DETAILED DESCRIPTION
[0027] Some embodiments of the present invention relate to a memory device including a fluorine-containing region adjacent to a word line. The fluorine in the fluorine-containing region can be used to reduce gate-induced drain leakage (GIDL) in the memory device.
[0028] Figure 1 FIGURE 1 shows a circuit diagram of a memory device in some embodiments of the present invention. Figure 1 A memory device (e.g., a dynamic random access memory, DRAM) may include a plurality of memory cells MC. A typical DRAM memory cell MC includes a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on the charge state of the capacitor CA. A bit line BL is electrically connected to the source / drain region of the transistor TR, and a word line WL is electrically connected to the gate region of the transistor TR. The capacitor CA is electrically connected to the other source / drain region of each transistor TR. The word line WL in the present invention is a dual work function word line. The following discussion will emphasize the manufacturing process of the transistor TR and the word line WL, and the manufacturing method of the bit line BL and the capacitor CA will not be mentioned.
[0029] Figures 2 to 14 FIG2 is a cross-sectional view of a method for manufacturing a memory device according to some embodiments of the present invention. Figure 2 , a substrate 100 is provided, and an isolation structure 102 is formed in the substrate 100. The substrate 100 includes a doped region 104 at an upper portion of the substrate 100. The substrate 100 and the doped region 104 have different conductor types. For example, if the substrate 100 is an n-type substrate, the doped region 104 is a p-type region. If the substrate 100 is a p-type substrate, the doped region 104 is an n-type region. The p-type substrate and the p-type region include p-type dopants such as boron, gallium, or aluminum. The n-type substrate and the n-type region include n-type dopants such as phosphorus, arsenic, or antimony. The doped region 104 acts as Figure 1 The source / drain region in the transistor TR, and the substrate 100 acts as Figure 1 The channel region of the transistor TR in the substrate 100 is formed. In some embodiments, the substrate 100 may be made of a semiconductor material such as silicon. In some embodiments, the isolation structures 102 may be made of a dielectric material such as silicon oxide, silicon nitride, or a combination thereof. For example, each of the isolation structures 102 may include a first portion 102A of the isolation structure made of silicon oxide and a second portion 102B of the isolation structure made of silicon nitride.
[0030] Subsequently, a hard mask layer HM is formed over the substrate 100, and the substrate 100 is etched through the hard mask layer HM to form a trench T in the substrate 100. The bottom of the trench T is lower than the bottom of the doped region 104. In some embodiments, the trench T is further formed in the isolation structure 102, and the bottom of the trench T in the isolation structure 102 is lower than the bottom of the trench T in the substrate 100.
[0031] See Figure 3 A gate dielectric layer 110 is formed along the surfaces of the trench T in the substrate 100 and the trench T in the isolation structure 102. The gate dielectric layer 110 further extends along the top surface and sidewalls of the hard mask layer HM. In some embodiments, the gate dielectric layer 110 can be formed by atomic layer deposition (ALD), in-situ steam generation (ISSG), or a combination thereof. In some embodiments, the gate dielectric layer 110 is made of silicon oxide.
[0032] See Figure 4 , forming a first word line material layer 120' that overfills the trench T. That is, the first word line material layer 120' not only fills the trench T but also covers the hard mask layer HM and the gate dielectric layer 110. The first word line material layer 120' is formed of a conductive material. In some embodiments, the first word line material layer 120' is formed of titanium nitride (TiN).
[0033] See Figure 5 An etch-back process is performed on the first word line material layer 120′ to lower the top surface of the first word line material layer 120′, and the remaining portion of the first word line material layer 120′ is referred to as the first word line layer 120. In some embodiments, the top surface of the first word line layer 120 is no higher than the bottom of the doped region 104.
[0034] See Figure 6 A cleaning process is performed on the first wordline layer 120 to remove residues, such as native oxide, on the first wordline layer 120. In some embodiments, because the gate dielectric layer 110 also includes an oxide, portions of the gate dielectric layer 110 along the top surface and sidewalls of the hard mask layer HM are removed during the cleaning process, and portions of the gate dielectric layer 110 along the isolation structure 102 and the substrate 100 are thinned. This results in the thickness of the portion of the gate dielectric layer 110 protruding from the first wordline layer 120 being thinner than the thickness of the gate dielectric layer 110 covered by the first wordline layer 120.
[0035] See Figure 7After forming the first wordline layer 120, an implantation process is performed to form a fluorine-containing region 106 in the substrate 100. The implantation process can be performed by implanting fluorine into the substrate 100 at an oblique angle relative to the top surface of the substrate 100. The fluorine-containing region 106 is located in the doped region 104 of the substrate 100 and near the gate dielectric layer 110. A portion of the doped region 104 does not include fluorine (such as a portion of the doped region 104 away from the second wordline layer 140). Because the fluorine-containing region 106 is formed after forming the doped region 104, it also includes the same dopants as those in the doped region 104. Because the fluorine-containing region 106 is formed after forming the first wordline layer 120, the position of the fluorine-containing region 106 is precisely controlled. For example, the bottom of the fluorine-containing region 106 is substantially flush with the top of the first wordline layer 120. Because the fluorine atoms in the fluorine-containing region 106 do not diffuse into the channel region of the transistor (such as the portion of the substrate 100 covered by the first wordline layer 120), this reduces short channel effects. The fluorine concentration in the portion of the substrate 100 covered by the first wordline layer 120 is lower than the fluorine concentration in the portion of the substrate 100 adjacent to the second wordline layer 140. The bottom of the fluorine-containing region 106 is also higher than the bottom of the first wordline layer 120.
[0036] During the implantation process, a fluorine-containing region 106 is also formed in the isolation structure 102, and the bottom of the fluorine-containing region 106 of the isolation structure 102 is also flush with the top of the first wordline layer 120. In some embodiments, fluorine atoms are also implanted into the portion of the gate dielectric layer 110 exposed by the trench T, so that a portion of the gate dielectric layer 110 also includes fluorine after the implantation process is completed. For example, a thinner portion of the gate dielectric layer 110 that protrudes from the first wordline layer 120 (i.e., the portion of the gate dielectric layer 110 above the top surface of the first wordline layer 120) may be exposed to the implantation process and, therefore, may include fluorine as a result of the implantation process. On the other hand, a thicker portion of the gate dielectric layer 110 may be protected by the first wordline layer 120 and, therefore, may not contain fluorine (or may have a lower fluorine concentration than the thinner portion of the gate dielectric layer 110). That is, the fluorine concentration of the gate dielectric layer 110 along the sidewalls and bottom of the first word line layer 120 is lower than the fluorine concentration of the gate dielectric layer 110 along the sidewalls of the second word line layer 140 .
[0037] See Figure 8 , forming a barrier layer 130 along the surface of the trench T and above the first word line layer 120. The barrier layer 130 further extends along the top surface and sidewalls of the hard mask layer HM. The barrier layer 130 is formed of silicon oxide. Figure 9An etch-back process is performed on second word line material layer 140' to lower the top surface of second word line material layer 140', and the remaining portion of second word line material layer 140' is referred to as second word line layer 140. In some embodiments, the work function value of second word line material layer 140' is lower than the work function value of first word line layer 120. In some embodiments, second word line material layer 140' is made of polycrystalline silicon. In some embodiments, each first word line layer 120 and its corresponding second word line layer 140 can be referred to as a word line structure.
[0038] See Figure 10 After forming the second word line layer 140, a cleaning process is performed on the second word line layer 140 to remove residues on the second word line layer 140, such as native oxide. In some embodiments, because the barrier layer 130 also includes oxide, during the cleaning process, the barrier layer 130 along the top surface and sidewalls of the hard mask layer HM is removed, and the barrier layer 130 along the isolation structure 102 and the substrate 100 is thinned. In some embodiments, since the gate dielectric layer 110 protruding from the second word line layer 140 is Figure 7 After the implantation process in the second wordline layer 140, fluorine is included, and an observable interface may exist between the barrier layer 130 and the gate dielectric layer 110. Alternatively, the barrier layer 130 is formed after the implantation process, and therefore does not contain fluorine (or has a lower fluorine concentration than the gate dielectric layer 110). In some other embodiments, the barrier layer 130 along the isolation structure 102 and the substrate 100 is also removed. In some embodiments, the portion of the barrier layer 130 along the sidewalls of the second wordline layer 140 may also serve as the gate dielectric layer.
[0039] After forming the second wordline layer 140, the fluorine-containing region 106 is adjacent to the second wordline layer 140. The fluorine-containing region 106 is closer to the second wordline layer 140 than the doped region 104 and is used to reduce GIDL. Specifically, GIDL is likely to occur in the overlapping region between the doped region 104 and the second wordline layer 140. The fluorine-containing region 106 is formed between the doped region 104 and the second wordline layer 140, and the fluorine in the fluorine-containing region 106 is used to trap electron-hole pairs in the doped region 104. This reduces the number of electron-hole pairs near the gate dielectric layer 110, thereby reducing GIDL.
[0040] See Figure 11 A barrier layer 150 is formed along the surface of the trench T and above the second word line layer 140. The barrier layer 150 is further formed along the top surface and sidewalls of the hard mask layer HM. The barrier layer 150 is formed of silicon oxide.
[0041] See Figure 12, an etching process is performed to remove a portion of the barrier layer 150 covering the top surface of the hard mask layer HM, so that the top surface of the hard mask layer HM is exposed.
[0042] See Figure 13 A cap layer 160 is formed in the trench T and over the second word line layer 140 and the barrier layer 150. After the cap layer 160 is formed, the fluorine-containing region 106 is adjacent to the cap layer 160. In some embodiments, the cap layer 160 is made of a dielectric material. In some embodiments, the cap layer 160 is made of silicon nitride.
[0043] See Figure 14 A planarization process, such as CMP, is performed on the cap layer 160 until the doped regions 104 of the substrate 100 are exposed. During the planarization process, the hard mask layer HM may also be removed. Thereafter, the bit lines BL and capacitors CA electrically connected to the doped regions 104 may be formed.
[0044] The resulting memory device is shown in Figure 14 The memory device includes a substrate 100, a first wordline layer 120, a second wordline layer 140, a gate dielectric layer 110, and source / drain regions 104. The first wordline layer 120 is in the substrate 100. The second wordline layer 140 is in the substrate 100 and above the first wordline layer 120. The source / drain regions 104 are on the substrate 100 on the opposite side from the second wordline layer 140. One of the source / drain regions 104 includes a fluorine-containing region 106 adjacent to the second wordline layer 140. The work function of the second wordline layer 140 may be lower than that of the first wordline layer 120, and the first and second wordline layers 120 and 140 form a dual work function wordline structure. In this type of wordline structure, the doped region 104 serving as the source / drain region is formed adjacent to the second wordline layer 140 having a lower work function to reduce GIDL. In some embodiments, the first wordline layer 120 is made of titanium nitride, and the second wordline layer 140 is made of polysilicon. However, the present invention is not limited thereto. A fluorine-containing region 106 adjacent to the second wordline layer 140 can be used to further reduce GIDL. Specifically, the fluorine atoms in the fluorine-containing region 106 are used to capture electron-hole pairs in the doped region 104 of the substrate 100. This reduces the number of electron-hole pairs near the gate dielectric layer 110, and the GIDL is reduced. In some embodiments, the memory device further includes an isolation structure 102 in the substrate 100, and the isolation structure 102 also includes the fluorine-containing region 106.
[0045] The memory device further includes a cap layer 160, a barrier layer 130, and a barrier layer 150. The cap layer 160 is above the second word line layer 140, wherein the fluorine-containing region 106 is further adjacent to the cap layer 160. The barrier layer 150 is between the cap layer 160 and the second word line layer 140. The barrier layer 130 is between the first word line layer 120 and the second word line layer 140.
[0046] As mentioned above, the memory device of the present invention has the advantage of reducing the GIDL (gap-depletion-lowering) of a dual-work-function wordline structure. A fluorine-containing region is formed along the wordline layer with a lower work function and near the gate dielectric layer. The fluorine-containing region serves to trap electron-hole pairs near the gate dielectric layer, reducing the number of electron-hole pairs near the gate dielectric layer. Consequently, the GIDL (gap-depletion-lowering) is reduced in the memory device of the present invention.
[0047] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0048] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention encompass modifications and variations of the present invention, with the limitation that they are within the scope of the appended claims.
[0049]
Explanation of symbols
[0050] 100:Substrate
[0051] 102: Isolation Structure
[0052] 102A: Part 1
[0053] 102B: Part 2
[0054] 104: doped region / source / drain region
[0055] 106: Fluorine-containing area
[0056] 110: Gate dielectric layer
[0057] 120': first word line material layer
[0058] 120: First character line layer
[0059] 130: Barrier layer
[0060] 140': second word line material layer
[0061] 140: Second character line layer
[0062] 150: Barrier layer
[0063] 160: Top cover
[0064] BL: Bit Line
[0065] CA:Capacitor
[0066] HM: Hard Mask
[0067] MC:Memory Cell
[0068] TR: Transistor
[0069] T: Groove
[0070] WL: character line.
Claims
1. A memory device, characterized in that: Include: substrate; a first wordline layer in the substrate; a second word line layer in the substrate and above the first word line layer; a gate dielectric layer along the sidewalls and bottom of the first wordline layer and the sidewalls of the second wordline layer; and A plurality of source / drain regions are provided on the substrate on opposite sides of the second wordline layer, wherein one of the plurality of source / drain regions includes a first fluorine-containing region adjacent to the second wordline layer.
2. The memory device according to claim 1, wherein The bottom of the first fluorine-containing region is substantially flush with the top of the first word line layer.
3. The memory device according to claim 1, wherein Further including: A cap layer is above the second word line layer, wherein the first fluorine-containing region is adjacent to the cap layer.
4. The memory device according to claim 3, wherein: Further including: The barrier layer is between the cap layer and the second word line layer.
5. The memory device according to claim 1, wherein A portion of the gate dielectric layer above a top surface of the first word line layer includes fluorine. The memory device according to claim 1 , wherein: A fluorine concentration of a portion of the gate dielectric layer along the sidewall and the bottom of the first word line layer is lower than a fluorine concentration of a portion of the gate dielectric layer along the sidewall of the second word line layer.
7. The memory device according to claim 1, wherein: A portion of one of the plurality of source / drain regions does not contain fluorine.
8. The memory device according to claim 1, wherein Further including: The barrier layer is between the first word line layer and the second word line layer.
9. The memory device according to claim 1, wherein: Further including: An isolation structure is provided in the substrate, wherein the isolation structure comprises a second fluorine-containing region.
10. The memory device according to claim 1, wherein The second word line layer is made of polysilicon.
11. A method for manufacturing a memory device, characterized in that: Include: forming a trench in a substrate; forming a gate dielectric layer along a surface of the trench in the substrate; forming a first word line layer above the gate dielectric layer and in the trench; After forming the first word line layer, performing an implantation process to form a first fluorine-containing region in the substrate; and After the implantation process is completed, a second word line layer is formed in the trench and above the first word line layer.
12. The manufacturing method according to claim 11, characterized in that: The implantation process is performed by implanting a plurality of ions into the substrate at an oblique angle relative to a top surface of the substrate.
13. The manufacturing method according to claim 11, characterized in that: During the implantation process, fluorine is implanted into a portion of the gate dielectric layer exposed by the trench.
14. The manufacturing method according to claim 11, characterized in that Further including: A capping layer is formed in the trench and above the second word line layer, wherein the first fluorine-containing region is adjacent to the capping layer.
15. The manufacturing method according to claim 14, characterized in that: Further including: A barrier layer is formed over the second word line layer, wherein the barrier layer is formed before forming the cap layer.
16. The manufacturing method according to claim 11, characterized in that Further comprising the following steps: A barrier layer is formed over the first word line layer, wherein the barrier layer is formed before forming the second word line layer.
17. The manufacturing method according to claim 11, characterized in that: The first fluorine-containing region is adjacent to the second word line layer.
18. The manufacturing method according to claim 11, characterized in that The bottom of the first fluorine-containing region is substantially flush with the top of the first word line layer.
19. The manufacturing method according to claim 11, characterized in that The work function value of the second word line layer is lower than the work function value of the first word line layer.
20. The manufacturing method according to claim 11, characterized in that Further comprising the following steps: An isolation structure is formed in the substrate, wherein a second fluorine-containing region is formed in the isolation structure during the step of performing the implantation process.