Semiconductor device and preparation method thereof, three-dimensional memory and storage system

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a three-dimensional memory and a storage system. The semiconductor device includes: a stack structure; the first semiconductor structure is located on one side of the stacked structure and comprises a semiconductor layer, a first peripheral circuit at least partially located in the semiconductor layer, a source electrode layer and an isolation structure, the source electrode layer and the isolation structure are located on the side, facing the stacked structure, of the semiconductor layer, and the isolation structure surrounds the first peripheral circuit; the source electrode layer is located on one side, far away from the first peripheral circuit, of the isolation structure; the channel structure penetrates through the stacking structure and the source electrode layer in the first direction and extends into the semiconductor layer, the channel structure comprises a channel layer and a functional layer, the functional layer is arranged on the partial side wall, extending in the first direction, of the channel layer, and the channel layer is connected with the source electrode layer; and the first connecting contact penetrates through the semiconductor layer along the first direction and is connected with the source electrode layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to semiconductor devices and methods for manufacturing the same, three-dimensional memories, and storage systems. Background Art

[0002] Memory is a storage device used in modern information technology to store information. As the demand for integration and data storage density in various electronic devices continues to increase, semiconductor devices, such as three-dimensional memory, have emerged. As the number of stacked layers in three-dimensional memory increases, the difficulty of its fabrication process also increases.

[0003] Currently, how to reduce process difficulty and further improve the performance of semiconductor devices is one of the technical problems that technical personnel in this field urgently need to solve. Summary of the Invention

[0004] The semiconductor device and its manufacturing method, three-dimensional memory and storage system provided in the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] The semiconductor device provided according to the first aspect of the present application includes:

[0006] stacked structure;

[0007] a first semiconductor structure, located on one side of the stacked structure, comprising a semiconductor layer, a first peripheral circuit at least partially located within the semiconductor layer, and a source layer and an isolation structure located on a side of the semiconductor layer facing the stacked structure, the isolation structure surrounding the first peripheral circuit, and the source layer located on a side of the isolation structure away from the first peripheral circuit;

[0008] a channel structure, penetrating the stacked structure and the source layer along a first direction and extending into the semiconductor layer, the channel structure comprising a channel layer and a functional layer, the functional layer being disposed on a portion of a sidewall of the channel layer extending along the first direction, and the channel layer being connected to the source layer; and

[0009] A first connection contact penetrates the semiconductor layer along the first direction and is connected to the source layer.

[0010] According to the second aspect of the present application, a method for preparing a semiconductor device includes:

[0011] forming an initial semiconductor structure, the initial semiconductor structure comprising a semiconductor layer, a first peripheral circuit at least partially located within the semiconductor layer, and an interconnection sacrificial layer and an isolation structure located on one side of the semiconductor layer, the isolation structure surrounding the first peripheral circuit, and the interconnection sacrificial layer located on a side of the isolation structure away from the first peripheral circuit;

[0012] forming a stacked structure and a channel structure on one side of the initial semiconductor structure, which sequentially penetrates the stacked structure and the interconnection sacrificial layer along a first direction and extends into the semiconductor layer, wherein the channel structure includes a channel layer and a functional layer, and the functional layer is disposed on a sidewall of the channel layer extending along the first direction;

[0013] forming a first contact hole penetrating the semiconductor layer along the first direction from a side of the semiconductor layer away from the stack structure; and

[0014] The portion of the interconnection sacrificial layer and the functional layer is removed through the first contact hole, and the interconnection sacrificial layer is replaced with a source layer.

[0015] The three-dimensional memory provided according to the third aspect of the present application includes a second semiconductor structure and the semiconductor device described in the first aspect of the present application, the second semiconductor structure includes a second peripheral circuit, and the second semiconductor structure is bonded to the semiconductor device.

[0016] According to the storage system provided in the fourth aspect of the present application, the storage system includes a controller and the semiconductor device described in the first aspect of the present application, the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0017] The semiconductor device and its preparation method, three-dimensional memory and storage system provided by the embodiments of the present application, by forming an interconnected sacrificial layer and an isolation structure surrounding the first peripheral circuit on one side of the semiconductor layer of the initial semiconductor structure, and forming a stacked structure on one side of the initial semiconductor structure, can form a first contact hole from the side of the semiconductor layer away from the stacked structure, that is, from the back side, and without affecting the peripheral circuit, the first contact hole can be used to remove the portion of the functional layer of the channel structure located in the interconnected sacrificial layer and replace the interconnected sacrificial layer with the source layer, thereby achieving direct contact between the channel layer and the source layer, so that after the first connection contact is subsequently formed in the first contact hole, it can be electrically connected to the channel layer through the source layer. Since the first contact hole is formed from the back side of the present application, it is not affected by the number of stacked layers of the stacked structure, thereby significantly reducing the process difficulty of forming the first contact hole and the process difficulty of removing part of the functional layer, thereby reducing costs.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. The drawings are provided for a better understanding of the present invention and do not constitute a limitation of the present application. In the drawings:

[0020] Figure 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0021] Figures 2 to 11 is a process diagram of a method for preparing a semiconductor device according to another embodiment of the present application;

[0022] Figure 12 is a schematic perspective view of a semiconductor device according to another embodiment of the present application;

[0023] Figure 13 is a schematic flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0024] Figure 14 is a block diagram of a system having a semiconductor device according to one embodiment of the present application;

[0025] Figure 15 is a schematic diagram of a memory card having a semiconductor device according to one embodiment of the present application; and

[0026] Figure 16 is a schematic diagram of a solid-state drive having a semiconductor device according to one embodiment of the present application.

[0027] Reference numerals:

[0028] 100, stacking structure; 101, core area; 102, connection area; 103, peripheral area;

[0029] 104, bridging region; 105, first trench; 110, gate layer;

[0030] 120, first interlayer insulating layer; 130, first insulating layer; 140, second interlayer insulating layer;

[0031] 150, stacked structure; 200, first semiconductor structure; 201, initial semiconductor structure;

[0032] 210, semiconductor layer; 220, first peripheral circuit; 221, transistor;

[0033] 222, trench isolation structure; 223, interconnect layer; 224, source; 225, drain;

[0034] 226, gate insulating layer; 227, gate conductive layer; 227-1, first part;

[0035] 227-2, second part; 228, initial interconnection layer; 229, interconnection sacrificial layer;

[0036] 230, isolation structure; 240, source layer; 300, channel structure; 310, functional layer;

[0037] 320, channel layer; 330, filling core layer; 400, first connection contact;

[0038] 401, first contact hole; 410, contact insulating layer; 420, contact conductive layer;

[0039] 500, second connection contact; 600, third connection contact; 700, isolation layer;

[0040] 800, memory array structure; 810, first semiconductor layer; 820, insulating layer;

[0041] 830, peripheral circuit structure; 840, lead-out contact; 850, through-contact;

[0042] 900, system; 901, memory system; 902, semiconductor device;

[0043] 903, memory controller; 904, host; 910, memory card;

[0044] 911, memory card connector; 920, SSD; 921, SSD connector. DETAILED DESCRIPTION

[0045] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, and especially do not represent any order of precedence.

[0047] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0048] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0049] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0050] It should be noted that, unless otherwise specified or inconsistent with the context, the embodiments and features of the embodiments in this application may be combined with each other. Furthermore, unless expressly limited or inconsistent with the context, the specific steps included in the methods described in this application are not necessarily limited to the order in which they are described, but may be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0051] In addition, in the present application, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of the underlying or upper structure, or may have an extent that is smaller than the extent of the underlying or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A layer may include multiple sublayers. In addition, in the present application, when "connected" or "coupled" is used, it may indicate direct contact or indirect contact between the corresponding parts, unless otherwise clearly defined or inferred from the context.

[0052] like Figure 1As shown, an embodiment of the present application provides a semiconductor device, which includes a storage array structure 800 and a peripheral circuit structure 830 bonded to the storage array structure 800, the storage array structure 800 includes a first semiconductor layer 810, a stacking structure 100 located on one side of the first semiconductor layer 810 along a first direction (z direction), a channel structure 300 passing through the stacking structure 100 along the first direction (z direction) and extending into the first semiconductor layer 810, and an insulating layer 820 located on at least one side of the stacking structure 100 along a second direction (x direction), the peripheral circuit structure 830 is located on a side of the first semiconductor layer 810 away from the stacking structure 100, and the peripheral circuit structure 830 includes a second semiconductor layer 210 and a peripheral circuit at least partially located in the second semiconductor layer 210. The stacked structure 100 has a core area and a step area located on at least one side of the core area along the second direction (x direction). The channel structure 300 is located in the core area of ​​the stacked structure 100. The channel structure 300 includes a channel layer and a functional layer. The functional layer is located on the sidewall of the channel layer extending along the first direction (z direction). The storage array structure 800 also includes a lead-out contact 840 located on one side of the stacked structure 100 along the second direction (x direction). The lead-out contact 840 extends from the side of the insulating layer 820 away from the first semiconductor layer 810, penetrates the insulating layer 820 along the first direction (z direction) and is connected to the channel layer of the channel structure 300 through the source layer 240 located in the first semiconductor layer 810. The through contact 850 penetrates the insulating layer 820 along the first direction (z direction) and is connected to the peripheral circuit.

[0053] In order to connect the channel layer of the channel structure 300 to the lead contact 840 through the source layer 240, it is necessary to remove a portion of the functional layer of the channel structure 300 located in the first semiconductor layer 810 through a lead hole during the formation of the lead contact 840 to expose a portion of the channel layer 320, so that the exposed channel layer is in direct contact with the subsequently formed source layer 240. However, as the number of stacked layers in the stacked structure 100 increases, the difficulty of forming the lead hole from the side of the insulating layer 820 away from the first semiconductor layer 810, that is, from the front, increases. As a result, the difficulty of removing a portion of the functional layer 310 through the lead hole also increases, resulting in high process costs.

[0054] Based on this, in order to solve at least some of the above problems, an embodiment of the present application provides a method for preparing a semiconductor device. Figure 11 A schematic cross-sectional view of a semiconductor device according to one embodiment of the present application is shown. Figure 12 A schematic perspective view of a semiconductor device according to one embodiment of the present application is shown; Figure 13 A schematic flow chart of a method for manufacturing a semiconductor device according to one embodiment of the present application is shown. The manufacturing method 1000 includes:

[0055] S100, forming an initial semiconductor structure 201, the initial semiconductor structure 201 includes a semiconductor layer 210, a first peripheral circuit 220 at least partially located in the semiconductor layer 210, and an interconnection sacrificial layer 229 and an isolation structure 230 located on one side of the semiconductor layer 210, the isolation structure 230 surrounds the first peripheral circuit 220, and the interconnection sacrificial layer 229 is located on a side of the isolation structure 230 away from the first peripheral circuit 220 (see Figure 2 );

[0056] S200, forming a stacked structure 100 and a channel structure 300 that sequentially penetrates the stacked structure 100 and the interconnection sacrificial layer 229 along a first direction (z direction) and extends into the semiconductor layer 210 on one side of the initial semiconductor structure 201, wherein the channel structure 300 includes a channel layer 320 and a functional layer 310, wherein the functional layer 310 is located on a sidewall of the channel layer 320 extending along the first direction (see Figure 8 );

[0057] S300, forming a first contact hole 401 (see FIG. 4 ) penetrating the semiconductor layer 210 along a first direction (z direction) from a side of the semiconductor layer 210 away from the stack structure 100. Figure 9 );

[0058] S400 , removing the portion of the interconnection sacrificial layer 229 and the functional layer 310 through the first contact hole 401 , and replacing the interconnection sacrificial layer 229 with the source layer 240 .

[0059] In the embodiment of the present application, by forming an interconnect sacrificial layer 229 and an isolation structure 230 surrounding the first peripheral circuit 220 on one side of the semiconductor layer 210 of the initial semiconductor structure 201, and forming the stacked structure 100 on one side of the initial semiconductor structure 201, a first contact hole 401 can be formed from the side of the semiconductor layer 210 away from the stacked structure 100, that is, from the back side. Without affecting the peripheral circuit, the first contact hole 401 is used to remove the portion of the functional layer 310 of the channel structure 300 located within the interconnect sacrificial layer 229 and replace the interconnect sacrificial layer 229 with the source layer 240, thereby achieving direct contact between the channel layer 320 and the source layer 240. Subsequently, after forming the first connection contact 400 within the first contact hole 401, the source layer 240 can be electrically connected to the channel layer 320. Because the first contact hole 401 is formed from the back side of the present application, it is not affected by the number of stacked layers of the stacked structure 100, thereby significantly reducing the process difficulty of forming the first contact hole 401 and the process difficulty of removing part of the functional layer 310, thereby reducing costs.

[0060] The following is a detailed introduction to each step in the method for preparing a semiconductor device in an embodiment of the present application.

[0061] Step S100

[0062] Figure 2 A schematic cross-sectional view of an initial semiconductor structure according to one embodiment of the present application is shown. Figure 3 A schematic cross-sectional view of a transistor according to one embodiment of the present application is shown.

[0063] like Figure 2 and Figure 3 As shown, in step S100, an initial semiconductor structure 201 is formed. The initial semiconductor structure 201 includes a semiconductor layer 210, a first peripheral circuit 220 at least partially located within the semiconductor layer 210, and an interconnection sacrificial layer 229 and an isolation structure 230 located on one side of the semiconductor layer 210. The isolation structure 230 surrounds the first peripheral circuit 220, and the interconnection sacrificial layer 229 is located on a side of the isolation structure 230 away from the first peripheral circuit 220.

[0064] In some embodiments, the first peripheral circuit 220 includes peripheral devices and an interconnect layer 223. The peripheral devices may include, but are not limited to, at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device. The high-voltage device, the low-voltage device, or the ultra-low-voltage device may include at least one of an active or passive device such as a transistor 221, a diode, a resistor, and a capacitor. The high-voltage device may include, but is not limited to, at least one of a row decoder, a column decoder, a word line driver, and a bit line driver. The low-voltage device may include, but is not limited to, a page buffer or a logic device. The ultra-low-voltage device may include, but is not limited to, an I / O circuit. The operating voltage of a high-voltage device is generally greater than 3.3V, for example, 5V to 30V. As an example, the operating voltage of a high-voltage device can be 5V, 10V, 15V, 20V, 25V or 30V; the operating voltage of a low-voltage device is generally between 1.3V and 3.3V. As an example, the operating voltage of a low-voltage device can be 1.3V, 1.8V, 2.3V, 2.8V or 3.3V; the operating voltage of an ultra-low-voltage device is generally lower than 1.3V, for example, 0.9V to 1.2V; as an example, the operating voltage of an ultra-low-voltage device can be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V or 1.2V. It should be noted that the operating voltage of a high-voltage device, a low-voltage device or an ultra-low-voltage device can also be any value between any two of the above voltage values. Those skilled in the art should understand that the above description of the operating voltage ranges of high-voltage devices, low-voltage devices and ultra-low-voltage devices is for a better understanding of the present solution and does not constitute a limitation of the present application.

[0065] As an example, the initial semiconductor structure 201 can be formed by: forming a peripheral device based on the first surface of the semiconductor layer 210, the peripheral device including a transistor 221 at least partially located in the semiconductor layer 210; forming a trench isolation structure 222 around the active area of ​​the transistor 221 on the semiconductor layer 210 from the first surface, for example, forming an isolation trench around the active area of ​​the transistor 221 on the semiconductor layer 210; filling the isolation trench with a high-k dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc. to form the trench isolation structure 222 to reduce current leakage; forming an initial interconnection layer 228 covering the peripheral device and the trench isolation structure 222 on the first surface; forming a second trench (not shown) passing through the initial interconnection layer 228 and surrounding the peripheral device to divide the initial interconnection layer 228 into an interconnection sacrificial layer 229 and an interconnection layer 223, the second trench surrounding the interconnection layer 223; and forming an isolation structure 230 in the second trench. Furthermore, to prevent metal particles from the subsequently formed source layer 240 from diffusing into the stacked structure 100, an isolation layer 700 may be formed covering the initial interconnect layer 228. To simplify the process, the isolation layer 700 and the isolation structure 230 may be formed in the same process. For example, after forming the second trench, an isolation material may be deposited on the surface of the initial interconnect layer 228 away from the semiconductor layer 210 using a thin film deposition process, thereby forming the isolation structure 230 filling the second trench and the isolation layer 700 covering the initial interconnect layer 228. The isolation material may include, but is not limited to, silicon nitride or silicon carbide, such as nitride-doped silicon carbide (NDC). Thus, the isolation structure 230 not only protects the interconnect layer 223 from being removed when the interconnect sacrificial layer 229 is subsequently removed, but also prevents metal particles from the subsequently formed source layer 240 from diffusing into the interconnect layer 223 and the stacked structure 100. The thin film deposition process may be, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes.

[0066] It should be noted that the above-mentioned transistor 221 can be a recessed gate transistor or a flat gate transistor. For a flat gate transistor, its gate structure is located on one side of the semiconductor layer 210 along the first direction (z direction), and the effective channel length of the transistor 221 is the same as the width of its gate structure along the second direction (x direction). For a recessed gate transistor, its gate structure is located in the semiconductor layer 210, and the effective channel length of the transistor 221 is greater than the width of the bottom surface of its gate structure along the second direction (x direction). When the effective channel length is the same, the area of ​​the recessed gate transistor is smaller than the area of ​​the flat gate transistor. It can be seen that the recessed gate transistor can reduce the device area while maintaining better device leakage performance.

[0067] In order to reduce the size of the entire peripheral device, the peripheral device in the embodiment of the present application, especially the transistor 221 of the high voltage device, may be a recessed gate transistor. As an example, the peripheral device may be formed in the semiconductor layer 210 in the following manner: Figure 3 As shown, a gate structure is formed in the semiconductor layer 210, and the gate structure includes a gate insulating layer 226 and a gate conductive layer 227. For example, a gate trench (not shown) extending along a third direction (y direction) can be formed in the semiconductor layer 210 from the first surface; a gate insulating layer 226 is formed on the inner wall of the gate trench by a thin film deposition process or an oxidation process; and a gate conductive layer 227 is formed in the gap surrounded by the gate insulating layer 226. In addition, in order to improve the conductivity of the gate conductive layer 227, a portion of the gate conductive layer 227 can be doped by an ion implantation process or a diffusion process, so that the portion of the gate conductive layer 227 close to the initial interconnection layer 228 is doped with dopants. As shown in FIG. Figure 3 As shown, the gate conductive layer 227 may include a first portion 227-1 and a second portion 227-2, wherein the first portion 227-1 is doped with a dopant, and the second portion 227-2 is located on a side of the first portion 227-1 away from the stacked structure 100 along the first direction (z direction). The material of the gate insulating layer 226 may be, but is not limited to, a high-k dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide. The material of the gate conductive layer 227 may be, but is not limited to, polysilicon, a conductive metal, or a conductive alloy. For example, the material of the gate conductive layer 227 includes at least one of tungsten, titanium nitride, copper, and silver. Figure 2As shown, a source 224 and a drain 225 are formed on both sides of the gate structure along the second direction (x direction), respectively. The source 224 and the drain 225 serve as the active region of the transistor 221. The material of the semiconductor layer 210 may include, but is not limited to, silicon, silicon germanium, gallium arsenide, germanium, silicon-on-insulator, or any other suitable material. Furthermore, a well region may be formed in the semiconductor layer 210. For example, if the transistor 221 is an N-type transistor, a P-type doped well, also known as a P-well, may be formed in the semiconductor layer 210 using an ion implantation or diffusion process. The dopant may be a relatively low-concentration P-type dopant such as boron (B). If the transistor 221 is a P-type transistor, an N-type doped well, also known as an N-well, may be formed in the semiconductor layer 210 using an ion implantation or diffusion process. The dopant may be a relatively low-concentration N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb). It should be understood that the well region may be omitted or have different ranges and boundaries in the semiconductor layer 210, and this application is not limited thereto. The source 224 and the drain 225 can be formed in the well region. For example, if the transistor 221 is an N-type transistor, an N-type source 224 and an N-type drain 225 are formed in the P-type well region of the semiconductor layer 210 using N-type dopants such as phosphorus (P), arsenic (As) and antimony (Sb); if the transistor 221 is a P-type transistor, a P-type source 224 and a P-type drain 225 are formed in the N-type well region of the semiconductor layer 210 using P-type dopants such as boron (B). The portion of the well region between the source 224 and the drain 225 constitutes a channel.

[0068] Step S200

[0069] like Figure 8 As shown, a stacked structure 100 and a channel structure 300 are formed on one side of the initial semiconductor structure 201, sequentially penetrating the stacked structure 100 and the interconnect sacrificial layer 229 along a first direction (z-direction) and extending into the semiconductor layer 210. The channel structure 300 includes a channel layer 320 and a functional layer 310, with the functional layer 310 coating the sidewalls of the channel layer 320 extending along the first direction (z-direction). Furthermore, the channel structure 300 may further include a filling core layer 330, with the channel layer 320 coating the sidewalls of the filling core layer 330 extending along the first direction (z-direction).

[0070] In some embodiments, step S100 may include: Figure 4As shown, a stacked structure 150 is formed on one side of the initial semiconductor structure 201. The stacked structure 150 includes a first interlayer insulating layer 120 and a second interlayer insulating layer 140 alternately stacked along a first direction (z direction). The first interlayer insulating layer 120 and the second interlayer insulating layer 140 are made of different materials, and have different etching selectivities for the same etchant. The material of the first interlayer insulating layer 120 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or a high-K material such as hafnium oxide, zirconium oxide, aluminum oxide, or tantalum oxide. The material of the second interlayer insulating layer 140 may include, but is not limited to, silicon oxynitride, silicon nitride, polycrystalline silicon, or polycrystalline germanium. For example, the material of the first interlayer insulating layer 120 includes silicon oxide, and the material of the second interlayer insulating layer 140 includes silicon nitride. In addition, the stacked structure 150 can be formed on one side of the initial semiconductor structure 201 by a thin film deposition process. The thin film deposition process can be, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes. The stacked structure 150 can be, but is not limited to, including 64 pairs, 128 pairs, or more than 128 pairs of first interlayer insulating layers 120 and second interlayer insulating layers 140. The more layers of the first interlayer insulating layer 120 and the second interlayer insulating layer 140, the higher the integration, and the more storage units of the final semiconductor device. The number of layers of the first interlayer insulating layer 120 and the second interlayer insulating layer 140 can be designed according to actual needs, and this application does not limit this. A channel structure 300 is formed that sequentially penetrates the stacked structure 150 and the interconnection sacrificial layer 229 along the first direction (z direction) and extends into the semiconductor layer 210; Figure 7 As shown, at least a portion of the second interlayer insulating layer 140 is replaced with the gate layer 110 to form a stacked structure 100 .

[0071] In some embodiments, the channel structure 300 can be formed by forming a channel hole (not shown) along a first direction (z-direction) from a side of the stacked structure 150 away from the initial semiconductor structure 201, penetrating the stacked structure 150 and the interconnect sacrificial layer 229 and extending into the semiconductor layer 210. Given the lateral undercutting problem associated with wet etching, the channel hole can be formed using a dry etching process, a combination of dry and wet etching processes, or a patterning process, wherein the patterning process includes photolithography, cleaning, and chemical mechanical polishing. The cross-sectional shape of the channel hole, i.e., the cross-sectional shape of the channel hole perpendicular to its extension direction, can be, but is not limited to, circular, elliptical, or polygonal. A functional layer 310 is formed on the inner wall of the channel hole. The functional layer 310 includes a blocking layer, a charge trapping layer, and a tunneling layer. Specifically, the blocking layer can be formed on the inner wall of the channel hole to prevent the outflow of charge stored in the subsequently formed charge trapping layer. The material of the blocking layer can be, but is not limited to, silicon oxide, silicon nitride, a high-k dielectric material, or a combination of any of the foregoing. A charge trapping layer is formed on the side of the blocking layer away from the inner wall of the channel hole to store charge. The material of the charge trapping layer may include, but is not limited to, silicon nitride, silicon oxynitride, silicon, or a combination of any of the foregoing. A tunneling layer is formed on the side of the charge trapping layer away from the blocking layer. The material of the tunneling layer may include, but is not limited to, silicon oxide or silicon nitride. A channel layer 320 is formed on the side of the tunneling layer away from the charge trapping layer. Channel layer 320 is used to transport the required charges, i.e., electrons or holes. The material of channel layer 320 may include, but is not limited to, amorphous silicon, polycrystalline silicon, or single crystal silicon. A filling core layer 330 is formed within the gap formed by channel layer 320. The material of filling core layer 330 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, carbon-doped oxide, etc. In addition, a channel plug may be formed on the side of filling core layer 330 away from the initial semiconductor structure 201, contacting the channel layer 320. The material of the channel plug may be the same as that of the channel layer 320. The blocking layer, charge trapping layer, tunneling layer, and channel layer 320 can all be formed by thin film deposition processes. Furthermore, to reduce structural stress, at least one air gap can be formed in the filling core layer 330 during the formation of the filling core layer 330 by controlling corresponding parameters in the channel filling process.

[0072] In some embodiments, as Figure 5As shown, the stacked structure 150 may include a core region 101 and a connection region 102 located on at least one side of the core region 101 along the second direction (x direction). It should be noted that the portion of the stacked structure 150 located in the connection region 102 may be a step structure or a non-step structure. For example, under the SCT (Staircase Contact) architecture, the portion of the stacked structure 150 located in the connection region 102 does not need to be in a step shape. If the portion of the stacked structure 150 located in the connection region 102 is in a step shape, then after the first interlayer insulating layer 120 and the second interlayer insulating layer 140 are alternately stacked on one side of the initial semiconductor structure 201, a step structure can be formed by performing multiple trim-etch cycles on the portion of the first interlayer insulating layer 120 and the second interlayer insulating layer 140 located in the connection region 102.

[0073] like Figure 7 As shown, if the portion of the stacked structure 150 located in the connection region 102 is stepped, then the entire portion of the second interlayer insulating layer 140 located in the core region 101 and the entire portion of the second interlayer insulating layer 140 located in the connection region 102 can be replaced with the gate layer 110. Specifically, a plurality of gate line slits (GLS) are formed that penetrate the stacked structure 150 along a first direction (z direction). A plurality of gate line slits (not shown) are spaced apart along a third direction (y direction) and extend along a second direction (x direction) in the core region 101 and the connection region 102. The gate line slits are used to remove the entire portion of the second interlayer insulating layer 140 located in the core region 101 and the connection region 102 to form a gate gap (not shown). The gate line slits are used to fill the gate gaps with gate material to form the gate layer 110. The gate line gaps are filled with insulating material to form a gate line gap structure.

[0074] If the portion of the stacked structure 150 located in the connection region 102 is a non-step structure, then the entire portion of the second interlayer insulating layer 140140 located in the core region 101 and the portion thereof located in the connection region 102 can be replaced with the gate layer 110. In other words, a portion of the second interlayer insulating layer 140140 located in the connection region 102 is retained and not replaced with the gate layer 110. Specifically, a plurality of gate line slits (GLS) are formed, each extending through the stacked structure 150 along the first direction (z direction). As an example, the plurality of gate line slits include a plurality of first gate line slits spaced apart along a third direction (y direction) and at least one second gate line slit located between two adjacent first gate line slits. The first gate line slits extend along the second direction (x direction) in the core region 101 and the connection region 102 of the stacked structure 150, and the second gate line slit extends along the second direction (x direction) in the core region 101 of the stacked structure 150. A sacrificial material is filled into the first gate line gap and the second gate line gap to form a first sacrificial layer in the first gate line gap and a second sacrificial layer in the second gate line gap. The portion of the first sacrificial layer located in the core area 101 and the entire second sacrificial layer are removed to expose the portion of the first gate line gap located in the core area 101 and the second gate line gap. At this time, the portion of the first sacrificial layer located in the connection area 102 is not removed. The portion of the second interlayer insulating layer 140 located in the core area 101 is removed through the portion of the first gate line gap located in the core area 101 and the second gate line gap to form a first gap. It should be noted that in some other embodiments, only the first gate line gap may be provided without the second gate line gap. Of course, providing a second gate line gap between two adjacent first gate line gaps not only increases the removal rate when removing the portion of the second interlayer insulating layer 140 located in the core area 101, allowing for more complete removal of the second interlayer insulating layer 140, but also increases the subsequent filling rate of the gate material. Next, the portion of the first sacrificial layer located in the connection area 102 is removed to expose the portion of the first gate line gap located in the connection area 102; the portion of the second interlayer insulating layer 140 located in the connection area 102 is removed through the portion of the first gate line gap located in the connection area 102, forming a second gap, and the first gap and the second gap are connected. For example, when a wet etching process is used to remove the portion of the second interlayer insulating layer 140 located in the connection area 102, the etching solution passing through the first gate line gap contacts the portion of the second interlayer insulating layer 140 near the first gate line gap. By controlling etching conditions such as the etching time and the concentration of the etching solution, the portion of the second interlayer insulating layer 140 located in the connection area 102 near the first gate line gap can be removed, and the remaining portion away from the first gate line gap along the third direction (y direction) is retained. The gate material is filled in the first gap and the second gap through the first gate line gap and the second gate line gap to form the gate layer 110.An insulating material is filled in the first gate line gap and the second gate line gap to form a first gate line gap structure and a second gate line gap structure. Thus, the portion of the gate layer 110 located between the two first gate line gap structures includes a first sub-gate corresponding to the core area 101 and two second sub-gates corresponding to the connection area 102, the first sub-gate being located in the core area 101, the second sub-gate being located in the connection area 102, the two second sub-gates being opposite and spaced apart along a third direction (y direction), and the remaining second interlayer insulating layer 140 being located between the two second sub-gates, the second sub-gates extending along a second direction (x direction) and connected to the first sub-gate.

[0075] It should be noted that, after forming the first gap, the gate material can be directly filled into the first gap, and then the portion of the first sacrificial layer located in the connection region 102 can be removed. After forming the second gap, the gate material can be filled into the second gap. In addition, a dummy channel is formed in the stacked structure 100 located in the connection region 102. The dummy channel extends through the second sub-gate along the first direction (z direction). The dummy channel can provide mechanical support. The dummy channel and the channel structure 300 can be formed simultaneously, and the structures of the two can be the same.

[0076] In some embodiments, the stacked structure 150 has two core regions 101 distributed along the second direction (x direction), two connection regions 102 located between the two core regions 101, and a peripheral region 103 located between the two connection regions 102. The channel structure 300 is located in the core region 101. Figure 5 As shown, after forming the stacked structure 150 on one side of the initial semiconductor structure 201, at least the first interlayer insulating layer 120 and the second interlayer insulating layer 140 located in the peripheral area 103 may be removed to form a first trench 105; Figure 6 As shown, a first insulating layer 130 is formed in the first trench 105 .

[0077] It should be noted that when forming the first trench 105, a portion of the first interlayer insulating layer 120 and the second interlayer insulating layer 140 located in the connection area 102 and all of them located in the peripheral area 103 can be removed, so that the portion of the stacked structure 150 located in the connection area 102 is stepped. As a result, a portion of the first insulating layer 130 formed subsequently is located in the peripheral area 103, and another portion covers the step surface of the second interlayer insulating layer 140 located in the connection area 102. Of course, when forming the first trench 105 under the SCT architecture, only the first interlayer insulating layer 120 and the second interlayer insulating layer 140 located in the peripheral area 103 can be removed, so that the portion of the stacked structure 150 located in the connection area 102 is a non-step structure. In addition, in some embodiments, such as Figure 11As shown, in addition to the core region 101, the connection region 102, and the peripheral region 103, the stacked structure 150 may also include a bridge region 104. The bridge region 104 is located between the two core regions 101 along the second direction (x-direction) and to one side of the connection region 102 and the peripheral region 103 along the third direction (y-direction). After the first trench 105 is formed, the projection of the stacked structure 150 on a plane perpendicular to the first direction has an inverted "concave" shape. As a result, the gate layer 110 can extend from one core region 101 to the other core region 101 through the bridge region 104. The functional layer 310 and the channel layer 320 of the channel structure 300, the corresponding portion of the gate layer 110 of the stacked structure 100, and a portion of the gate layer 110 together constitute a memory cell. Multiple memory cells are connected in series along the stacking direction of the stacked structure 100, i.e., the first direction (z direction), to form a memory string. The memory cells located in the same row, i.e., distributed along the second direction (x direction), can be connected to the same word line. The remaining portion of the gate layer 110 can serve as the word line of multiple memory cells in the corresponding memory string. Each memory string, i.e., the memory cells in the same column, can be connected to the same bit line. Therefore, multiple memory cells located in the two core areas 101 can be connected to the same word line. Under the voltage control of the word line, the carriers in the channel layer 320 of these memory cells enter the charge capture layer of the functional layer 310, or the carriers in the charge capture layer of the functional layer 310 retreat to the channel layer 320, thereby realizing the programming or erasing of the memory cells. It can be seen that the existence of the bridge region 104 enables the same word line, ie, the gate layer 110 , to simultaneously control multiple memory cells in the two core regions 101 .

[0078] In some embodiments, the first peripheral circuit 220 is located below the peripheral region 103 along the first direction (z direction) and between the two core regions 101 along the second direction (x direction). Figure 8As shown, the fabrication method further includes forming a plurality of second connection contacts 500, each corresponding to the gate layer 110, on a side of the stacked structure 100 away from the initial semiconductor structure 201. The second connection contacts 500 extend along a first direction (z-direction) and connect to the corresponding gate layer 110. If the portion of the stacked structure 100 located in the connection region 102 is stepped, a portion of the first insulating layer 130 is located in the peripheral region 103, while another portion covers the stepped surface of the gate layer 110 located in the connection region 102. The second connection contacts 500 then penetrate the portion of the first insulating layer 130 located in the connection region 102 along the first direction (z-direction) and extend to the corresponding gate layer 110. If the portion of stacked structure 100 located in connection region 102 is a non-stepped structure, then first insulating layer 130 is located only in peripheral region 103. The portion of gate layer 110 located between the two first gate line gap structures includes a first sub-gate corresponding to core region 101 and two second sub-gates corresponding to connection region 102. The first sub-gate is located in core region 101, and the second sub-gate is located in connection region 102. The two second sub-gates are spaced apart and opposed to each other along a third direction (y-direction). The remaining second interlayer insulating layer 140 is located between the two second sub-gates. The second sub-gate extends along a second direction (x-direction) and is connected to the first sub-gate. Second connection contacts 500 extend along a first direction (z-direction) through multiple second interlayer insulating layers 140 and connect to the second sub-gate located in the same layer as the last second interlayer insulating layer 140 it penetrates. A plurality of third connection contacts 600 are formed on a side of stacked structure 100 away from initial semiconductor structure 201, penetrating first insulating layer 130 along the first direction and extending to first peripheral circuit 220.

[0079] In the embodiment of the present application, by arranging two connection areas 102 between the two core areas 101 and arranging a peripheral area 103 between the two connection areas 102, not only can a plurality of third connection contacts 600 be concentrated in the peripheral area 103, thereby making the layout of the first peripheral circuit 220 connected thereto more compact, thereby reducing the horizontal size of the semiconductor device and reducing the volume of the semiconductor device, but also reducing the process difficulty of manufacturing the semiconductor device.

[0080] Step S300

[0081] like Figure 9As shown, a first contact hole 401 is formed from the side of the semiconductor layer 210 away from the stacked structure 100 and passes through the semiconductor layer 210 along a first direction. In view of the problem of lateral undercutting in wet etching, the first contact hole 401 can be formed by a dry etching process, a combination of dry and wet etching processes, or a patterning process, wherein the patterning process includes photolithography, cleaning, and chemical mechanical polishing processes. The cross-sectional shape of the first contact hole 401, that is, the cross-sectional shape of the first contact hole 401 perpendicular to its extension direction, can be, but is not limited to, circular, elliptical, or polygonal. The first contact hole 401 passes through the semiconductor layer 210 along the first direction (z direction) and extends to the interconnection sacrificial layer 229. In other words, a portion of the interconnection sacrificial layer 229 can be exposed through the first contact hole 401.

[0082] Step S400

[0083] like Figure 6 As shown, the portion of functional layer 310 located within interconnect sacrificial layer 229 is removed through first contact hole 401, and interconnect sacrificial layer 229 is replaced with source layer 240. Because isolation structure 230 exists between interconnect sacrificial layer 229 and interconnect layer 223, isolation structure 230 protects interconnect layer 223 during the removal of interconnect sacrificial layer 229 through first contact hole 401, preventing interconnect layer 223 from being removed simultaneously. After the interconnect sacrificial layer 229 is removed, a sacrificial gap is formed. A conductive material is then filled into the sacrificial gap through first contact hole 401 to form source layer 240. The material of source layer 240 may include, but is not limited to, at least one of polysilicon, tungsten, cobalt, copper, aluminum, and silicide.

[0084] In some embodiments, as Figure 10 and Figure 11 As shown, the preparation method further includes: forming a first connection contact 400 in the first contact hole 401. As an example, the first connection contact 400 may include a contact insulating layer 410 and a contact conductive layer 420, wherein the contact conductive layer 420 penetrates the semiconductor layer 210 along the first direction (z direction) and extends to the source layer 240, and the contact insulating layer 410 covers the sidewalls of the contact conductive layer 420 extending along the first direction (z direction). The source layer 240, the contact insulating layer 410 and / or the contact conductive layer 420 can all be formed by a thin film deposition process, which can be, but is not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination of any of the above processes.

[0085] In addition, if Figure 11 and Figure 12 As shown, an embodiment of the present application further provides a semiconductor device, which includes a stacked structure 100, a first semiconductor structure 200, a channel structure 300, and a first connection contact 400. The first semiconductor structure 200 is located on one side of the stacked structure 100, and the channel structure 300 penetrates the stacked structure 100 along a first direction (z direction). The first semiconductor structure 200 includes a semiconductor layer 210, a first peripheral circuit 220 at least partially located within the semiconductor layer 210, and a source layer 240 and an isolation structure 230 located on a side of the semiconductor layer 210 facing the stacked structure 100. The isolation structure 230 surrounds the first peripheral circuit 220, and the source layer 240 is located on a side of the isolation structure 230 away from the first peripheral circuit 220. The channel structure 300 penetrates the stacked structure 100 and the source layer 240 along the first direction (z direction) and extends into the semiconductor layer 210. The channel structure 300 includes a channel layer 320 and a functional layer 310. The functional layer 310 is arranged on a portion of the side wall of the channel layer 320 extending along the first direction (z direction). The channel layer 320 is connected to the source layer 240. The first connection contact 400 penetrates the semiconductor layer 210 along the first direction (z direction) and is connected to the source layer 240.

[0086] In some embodiments, the stacked structure 100 includes two stacked portions and a first insulating layer 130 located between the two stacked portions along a second direction (x-direction). The stacked structure 100 has two core regions 101 distributed along the second direction (x-direction), two connection regions 102 located between the two core regions 101, and a peripheral region 103 located between the two connection regions 102. The stacked portions are located in the core regions 101 and the connection regions 102, the channel structure 300 is located in the core region 101, and the first insulating layer 130 is at least partially located in the peripheral region 103. The first direction and the second direction intersect.

[0087] In some embodiments, the portion of the stack located in the connection region 102 is stepped, and the stack includes gate layers 110 and first interlayer insulating layers 120 alternately stacked along a first direction (z direction). A portion of the first insulating layer 130 is located in the peripheral region 103, and another portion covers the stepped surface of the gate layer 110 located in the connection region 102. The first peripheral circuit 220 is located below the first insulating layer 130 along the first direction (z direction) and between the two core regions 101 along the second direction (x direction).

[0088] In some other embodiments, the portion of the stacking portion located in the connection area 102 is a non-step structure, and the stacking portion includes a gate layer 110 and a first interlayer insulating layer 120 alternately stacked along a first direction (z direction) and a second interlayer insulating layer 140 arranged in the same layer as the gate layer 110. For example, the semiconductor device may further include a plurality of first gate line gap structures extending through the stacked structure 100 along a first direction (z direction), the plurality of first gate line gap structures extending from one core region 101 to another core region 101 along a second direction (x direction), the plurality of first gate line gap structures being spaced apart along a third direction (y direction), the portion of the gate layer 110 located between the two first gate line gap structures including a first sub-gate corresponding to the core region 101 and two second sub-gates corresponding to the connection region 102, the first sub-gate being located in the core region 101, the two second sub-gates being located in the connection region 102 and being opposite and spaced apart along the third direction (y direction), a second interlayer insulating layer 140 being disposed between the two second sub-gates, the second sub-gate extending along the second direction (x direction) and connected to the first sub-gate. The first insulating layer 130 is located in the peripheral region 103, the first peripheral circuit 220 is located below the first insulating layer 130 along the first direction (z direction) and between the two core regions 101 along the second direction (x direction).

[0089] In some embodiments, stacked structure 100 further includes a bridging region 104. Bridging region 104 is located between the two core regions 101 along the second direction (x-direction) and to one side of connection region 102 and peripheral region 103 along the third direction (y-direction). Portions of the two stacked portions located in core regions 101 extend to bridging region 104 and connect to each other, with the first, second, and third directions intersecting in pairs. The presence of bridging region 104 enables simultaneous control of multiple memory cells within two core regions 101 using the same word line, i.e., gate layer 110.

[0090] In some embodiments, the semiconductor device further includes a plurality of second connection contacts 500 located in the connection region 102 and respectively corresponding to the plurality of gate layers 110. The second connection contacts 500 extend along a first direction (z-direction) and are connected to corresponding gate layers 110. If the portion of the stacked structure 100 located in the connection region 102 is stepped, a portion of the first insulating layer 130 is located in the peripheral region 103, while another portion covers the stepped surface of the gate layer 110 located in the connection region 102. The second connection contacts 500 then penetrate the portion of the first insulating layer 130 located in the connection region 102 along the first direction (z-direction) and extend to the corresponding gate layer 110. If the portion of the stacked structure 100 located in the connection area 102 is a non-step structure, then the first insulating layer 130 is only located in the peripheral area 103, and the portion of the gate layer 110 located between the two first gate line gap structures includes a first sub-gate corresponding to the core area 101 and two second sub-gates corresponding to the connection area 102, and the second connection contact 500 penetrates multiple second interlayer insulating layers 140 along the first direction (z direction) and is connected to the second sub-gate arranged in the same layer as the last second interlayer insulating layer 140 it penetrates.

[0091] In some embodiments, the semiconductor device further includes a plurality of third connection contacts 600 located in the peripheral region 103 . The third connection contacts 600 penetrate the first insulating layer 130 along the first direction (z direction) and are connected to the first peripheral circuit 220 .

[0092] In some embodiments, the semiconductor device further includes an isolation layer 700, which is located between the stacked structure 100 and the first semiconductor structure 200 along a first direction (z-direction). The isolation layer 700 is disposed corresponding to the core region 101 and the connection region 102. To simplify the process and reduce costs, the isolation layer 700 can be formed in the same process as the isolation structure 230. The presence of the isolation layer 700 can prevent metal particles in the source layer 240 from diffusing into the stacked structure 100. The material of the isolation layer 700 can include, but is not limited to, silicon nitride or silicon carbide. For example, the isolation material is nitride-doped silicon carbide (NDC).

[0093] In some embodiments, the first peripheral circuit 220 includes a peripheral device, a trench isolation structure 222, and an interconnect layer 223. The peripheral device includes a transistor 221 at least partially located in the semiconductor layer 210. The trench isolation structure 222 is located in the semiconductor layer 210 and surrounds the active area of ​​the transistor 221. The interconnect layer 223 is located on the side of the semiconductor layer 210 facing the stacked structure 100 and covers the peripheral device and the trench isolation structure 222. The interconnect layer 223 is connected to the peripheral device and the third connection contact 600, respectively. The peripheral device may include, but is not limited to, at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device. The high-voltage device, the low-voltage device, or the ultra-low-voltage device may include at least one of an active or passive device such as a transistor 221, a diode, a resistor, and a capacitor. The transistor 221 may be a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FINFET), or a bipolar junction transistor (BJT).

[0094] In some embodiments, transistor 221 is located in semiconductor layer 210 and contacts interconnect layer 223. Transistor 221 includes a source 224, a drain 225, and a gate structure. The drain 225 is located on one side of the source 224 along the second direction (x-direction). The gate structure is located between the source 224 and the drain 225. The gate structure includes a gate conductive layer 227 and a gate insulating layer 226. The gate insulating layer 226 covers the sidewalls of the gate conductive layer 227 extending along the first direction (z-direction) and the surface of the gate conductive layer 227 away from the interconnect layer 223 along the first direction (z-direction). To improve conductivity, the gate conductive layer 227 may include a first portion 227-1 doped with a dopant and a second portion 227-2 located on the side of the first portion 227-1 away from the stacked structure 100 along the first direction (z-direction).

[0095] In addition, embodiments of the present application further provide a three-dimensional memory device, comprising a second semiconductor structure and the aforementioned semiconductor device, wherein the second semiconductor structure comprises a second peripheral circuit, and the second semiconductor structure is bonded to the semiconductor device. For example, the second semiconductor structure is bonded to a side of the stacked structure 100 away from the first semiconductor structure 200. The second peripheral circuit may include, but is not limited to, at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device.

[0096] In addition, an embodiment of the present application further provides a storage system, which includes a controller and the above-mentioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0097] Figure 14FIG1 is a block diagram of a system having a semiconductor device according to an embodiment of the present application. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. Figure 14 As shown in FIG, system 900 may include a host 904 and a memory system 901, wherein the memory system 901 has one or more semiconductor devices 902 and a memory controller 903. The host 904 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). The host 904 may be configured to send data to or receive data from the semiconductor device 902.

[0098] The semiconductor device 902 may be any semiconductor device disclosed in this application, for example Figure 12 According to some embodiments, the memory controller 903 is coupled to the semiconductor device 902 and the host 904 and is configured to control the semiconductor device 902 . The memory controller 903 may manage data stored in the semiconductor device 902 and communicate with the host 904 .

[0099] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 903 can be configured to control the operations of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction code (ECC) associated with data read from or written to the semiconductor device 902. The memory controller 903 may also perform any other appropriate functions, such as formatting the semiconductor device 902. The memory controller 903 may communicate with an external device (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0100] The memory controller 903 and the one or more semiconductor devices 902 can be integrated into various types of memory devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 901 can be implemented and packaged into different types of final electronic products. Figure 15 In one example shown, the memory controller 903 and the single semiconductor device 902 may be integrated into a memory card 910. The memory card 910 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 910 may further include a memory card that connects the memory card 910 to a host (e.g., Figure 14 The memory card connector 911 is coupled to the host 904 in the embodiment. Figure 16 In another example shown, the memory controller 903 and the plurality of semiconductor devices 902 may be integrated into a solid-state drive (SSD) 920. The SSD 920 may further include a processor that connects the SSD 920 to a host (e.g., Figure 14 In some embodiments, the storage capacity and / or operating speed of the SSD 920 are higher than the storage capacity and / or operating speed of the memory card 910.

[0101] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved. This is not limited herein.

[0102] The above specific embodiments do not limit the scope of protection of this application. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application shall be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that: include: stacked structure; a first semiconductor structure, located on one side of the stacked structure, comprising a semiconductor layer, a first peripheral circuit at least partially located within the semiconductor layer, and a source layer and an isolation structure located on a side of the semiconductor layer facing the stacked structure, the isolation structure surrounding the first peripheral circuit, and the source layer located on a side of the isolation structure away from the first peripheral circuit; a channel structure, penetrating the stacked structure and the source layer along a first direction and extending into the semiconductor layer, the channel structure comprising a channel layer and a functional layer, the functional layer being disposed on a portion of a sidewall of the channel layer extending along the first direction, and the channel layer being connected to the source layer; as well as A first connection contact penetrates the semiconductor layer along the first direction and is connected to the source layer.

2. The semiconductor device according to claim 1, wherein The stacking structure includes two stacking parts and a first insulating layer located between the two stacking parts along a second direction, the stacking structure has two core areas distributed along the second direction, two connecting areas located between the two core areas, and a peripheral area located between the two connecting areas; The stacking portion is located in the core area and the connection area, and the stacking portion includes a gate layer and a first interlayer insulating layer alternately stacked along the first direction, the first insulating layer is at least partially located in the peripheral area, and the channel structure is located in the core area, and the first direction and the second direction intersect.

3. The semiconductor device according to claim 2, wherein The portion of the stacking portion located in the connection area is stepped, a portion of the first insulating layer is located in the peripheral area, and another portion covers the gate layer and is located on the step surface of the connection area, and the first peripheral circuit is located below the first insulating layer along the first direction and between the two core areas along the second direction.

4. The semiconductor device according to claim 2, wherein The portion of the stack located in the connection area also includes a second interlayer insulating layer arranged in the same layer as the gate layer, the first insulating layer is located in the peripheral area, and the first peripheral circuit is located below the first insulating layer along the first direction and between the two core areas along the second direction.

5. The semiconductor device according to claim 2, wherein The stacking structure also has a bridging area, which is located between the two core areas along the second direction and on one side of the connection area and the peripheral area along the third direction. The parts of the two stacking parts located in the core areas extend to the bridging area and are connected to each other, and the first direction, the second direction and the third direction intersect with each other.

6. The semiconductor device according to any one of claims 2 to 5, wherein The semiconductor device further includes: a plurality of second connection contacts, located in the connection region and respectively arranged corresponding to the plurality of gate layers, the second connection contacts extending along the first direction and connected to the corresponding gate layers; and A plurality of third connection contacts are located in the peripheral region, and the third connection contacts penetrate the first insulating layer along the first direction and are connected to the first peripheral circuit.

7. The semiconductor device according to any one of claims 2 to 5, wherein: The semiconductor device further includes: An isolation layer is located between the stacked structure and the first semiconductor structure along the first direction, and the isolation layer is arranged corresponding to the core area and the connection area.

8. The semiconductor device according to any one of claims 1 to 5, wherein The semiconductor device further includes a third connection contact penetrating the stack structure along the first direction; Wherein, the first peripheral circuit includes: a peripheral device comprising a transistor at least partially located in the semiconductor layer; a trench isolation structure located in the semiconductor layer and surrounding an active area of ​​the transistor; and An interconnection layer is located on a side of the semiconductor layer facing the stacked structure and covers the peripheral device and the trench isolation structure, and the interconnection layer is connected to the peripheral device and the third connection contact respectively.

9. The semiconductor device according to claim 8, wherein The peripheral device is a high-voltage device, and the transistor is located in the semiconductor layer and in contact with the interconnection layer; Wherein, the transistor includes: source; a drain electrode located on one side of the source electrode along a second direction intersecting the first direction; and A gate structure is located between the source and the drain, the gate structure includes a gate conductive layer and a gate insulating layer, and the sidewalls of the gate conductive layer extending along the first direction and the surface away from the interconnection layer along the first direction are covered with the gate insulating layer.

10. The semiconductor device according to claim 9, wherein The gate conductive layer includes: a first portion doped with a dopant; and The second portion is located along the first direction on a side of the first portion away from the stacking structure.

11. A method for preparing a semiconductor device, characterized in that: include: forming an initial semiconductor structure, the initial semiconductor structure comprising a semiconductor layer, a first peripheral circuit at least partially located within the semiconductor layer, and an interconnection sacrificial layer and an isolation structure located on one side of the semiconductor layer, the isolation structure surrounding the first peripheral circuit, and the interconnection sacrificial layer located on a side of the isolation structure away from the first peripheral circuit; forming a stacked structure and a channel structure on one side of the initial semiconductor structure, which sequentially penetrates the stacked structure and the interconnection sacrificial layer along a first direction and extends into the semiconductor layer, wherein the channel structure includes a channel layer and a functional layer, and the functional layer is disposed on a sidewall of the channel layer extending along the first direction; forming a first contact hole penetrating the semiconductor layer along the first direction from a side of the semiconductor layer away from the stack structure; as well as A portion of the functional layer located in the interconnection sacrificial layer is removed through the first contact hole, and the interconnection sacrificial layer is replaced with a source layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The steps of forming the stack structure and the channel structure include: forming a stacked structure on one side of the initial semiconductor structure, the stacked structure comprising first interlayer insulating layers and second interlayer insulating layers alternately stacked along the first direction; forming the channel structure that sequentially penetrates the stacked structure and the interconnection sacrificial layer and extends into the semiconductor layer; and At least a portion of the second interlayer insulating layer is replaced with a gate layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The stacked structure comprises two core regions distributed along a second direction, two connection regions located between the two core regions, and a peripheral region located between the two connection regions, the channel structure is located in the core region, and the first direction and the second direction intersect; Wherein, the preparation method further comprises: removing at least portions of the first interlayer insulating layer and the second interlayer insulating layer located in the peripheral region to form a first trench; and A first insulating layer is formed in the first trench.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: Removing at least portions of the first interlayer insulating layer and the second interlayer insulating layer located in the peripheral area includes: A portion of the second interlayer insulating layer and the first interlayer insulating layer located in the connection area and all of the second interlayer insulating layer and the first interlayer insulating layer located in the peripheral area are removed, so that the portion of the stacked structure located in the connection area is stepped.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, wherein: The preparation method further comprises: forming a plurality of second connection contacts respectively corresponding to the gate layers on a side of the stacked structure away from the initial semiconductor structure, wherein the second connection contacts extend along the first direction and are connected to the corresponding gate layers; and A plurality of third connection contacts are formed on a side of the stack structure away from the initial semiconductor structure, penetrating the first insulating layer along the first direction and extending to the first peripheral circuit.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: The first peripheral circuit includes peripheral devices and an interconnection layer; The forming of the initial semiconductor structure includes: forming a peripheral device based on the first surface of the semiconductor layer, the peripheral device including a transistor at least partially located in the semiconductor layer; forming a trench isolation structure surrounding an active region of the transistor on the semiconductor layer from the first surface; forming an initial interconnection layer covering the peripheral device and the trench isolation structure on the first surface; forming a second trench penetrating the initial interconnect layer and surrounding the peripheral device to divide the initial interconnect layer into an interconnect sacrificial layer and an interconnect layer, wherein the second trench surrounds the interconnect layer; and The isolation structure is formed in the second trench.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: Forming the isolation structure in the second trench includes: An isolation material is deposited on a surface of the initial interconnect layer away from the semiconductor layer to form an isolation structure filling the second trench and an isolation layer covering the initial interconnect layer.

18. A three-dimensional memory, characterized in that: The invention comprises a second semiconductor structure and the semiconductor device according to any one of claims 1 to 10, wherein the second semiconductor structure comprises a second peripheral circuit, and the second semiconductor structure is bonded to the semiconductor device.

19. A storage system, characterized in that: The storage system includes a controller and the semiconductor device according to any one of claims 1 to 10, wherein the controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.

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