Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; sequentially forming a first conductive layer and a first storage unit layer on the substrate in the first region; sequentially forming a second conductive layer, a second storage unit layer and a third conductive layer which are positioned in the first region and the second region on the first storage unit layer; the second area surrounds and is connected with the first area; and removing the second conductive layer, the second storage unit layer and the third conductive layer in the second region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid development. The feature sizes of semiconductor devices have continued to shrink, while the integration density of memory has increased, and its performance has become increasingly powerful. Currently, memory has gradually transitioned from simple planar structures to more complex three-dimensional structures. The number of stacked layers of memory cells in memory has increased, making the memory manufacturing process increasingly complex. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; sequentially forming a first conductive layer and a first storage unit layer on the substrate in a first region; sequentially forming a second conductive layer, a second storage unit layer, and a third conductive layer located in the first region and a second region on the first storage unit layer; the second region surrounds and connects the first region; and removing the second conductive layer, the second storage unit layer, and the third conductive layer located in the second region.

[0005] In some embodiments, the second conductive layer and the third conductive layer both include multiple initial conductive lines; the multiple initial conductive lines include a first initial conductive line running through the first area and a second initial conductive line located in the second area, the first initial conductive line includes a first part located in the first area, and a second part located in the second area; the removal of the second conductive layer, the second storage unit layer and the third conductive layer located in the second area includes: removing the storage unit located in the second area in the second storage unit layer, and the second initial conductive line and the second part in the second conductive layer and the third conductive layer, and the remaining first part forms a first conductive line.

[0006] In some embodiments, forming the multiple initial conductive lines includes: forming an initial conductive layer located in the first region and the second region; etching the initial conductive layer to form a plurality of first grooves parallel to each other, and the remaining initial conductive layer forms the multiple initial conductive lines; the initial conductive line has a first end and a second end located in the second region and opposite to each other; wherein the first ends of two adjacent initial conductive lines are connected to each other, and the second ends of two adjacent initial conductive lines are connected to each other.

[0007] In some embodiments, removing the second portion of the second conductive layer and the third conductive layer includes: removing portions of adjacent initial conductive lines that are connected to each other, so as to separate adjacent initial conductive lines from each other.

[0008] In some embodiments, forming the first storage cell layer and the second storage cell layer includes: forming an initial storage layer located in the first region and the second region; etching the initial storage layer to form a plurality of second grooves extending along a first direction, and the remaining initial storage layer forms a plurality of storage columns; the storage columns have a third end and a fourth end that are opposite in the first direction and located in the second region; wherein the third ends of two adjacent storage columns are connected to each other, and the fourth ends of two adjacent storage columns are connected to each other; the first direction is parallel to the surface of the substrate; etching the plurality of storage columns to form a plurality of third grooves extending along a second direction, and the plurality of third grooves divide the plurality of storage columns into a plurality of storage cells.

[0009] In some embodiments, forming the first memory cell layer further includes: removing the initial memory layer located in the second region.

[0010] In some embodiments, the forming of the initial storage layer located in the first region and the second region includes: sequentially forming a first electrode layer, a storage material layer, and a second electrode layer located in the first region and the second region and stacked; the first electrode layer, the storage material layer, and the second electrode layer are respectively used to form the first electrode, storage structure, and second electrode of the storage unit.

[0011] In some embodiments, the removing of the second conductive layer, the second storage cell layer, and the third conductive layer located in the second region includes: removing the second conductive layer, the second storage cell layer, and the third conductive layer located in the second region to form a fourth trench surrounding the remaining second conductive layer, the second storage cell layer, and the third conductive layer in the first region; the manufacturing method also includes: forming a dielectric layer in the fourth trench.

[0012] In some embodiments, forming the first conductive layer includes forming a plurality of second conductive lines located in the first region and parallel to each other.

[0013] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, which is formed by the manufacturing method described in any one of the above embodiments.

[0014] In the disclosed embodiment, a second conductive layer, a second storage cell layer, and a third conductive layer are sequentially formed on the first storage cell layer, located in the first region and the second region; then, the second conductive layer, the second storage cell layer, and the third conductive layer located in the second region are removed. In other words, the disclosed embodiment removes the second conductive layer, the second storage cell layer, and the third conductive layer located in the second region all at once, which helps simplify the semiconductor structure manufacturing process, reduce process costs, and minimize etching damage to each storage cell layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of two storage unit layers provided in one embodiment of the present disclosure.

[0016] Figures 2a to 2s A schematic diagram of a process for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0017] Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure.

[0018] Figures 4a to 4r A schematic diagram of a process for manufacturing a semiconductor structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0020] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0021] In the drawings, like reference numerals refer to like elements throughout.

[0022] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0025] Memory devices may include magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), ferroelectric RAM (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), flash memory, phase change memory (PCM), selector only memory (SOM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for extended periods of time in the absence of an external power source. Volatile memory cells lose their stored state over time when power is lost and typically require periodic refreshing with an external power source.

[0026] For ease of understanding, the memory devices in the disclosed embodiments are described using a selector-only memory (SOM) as an example. Compared to three-dimensional phase-change memory (3D XPoint), selector-only memory offers advantages such as simple structure, high scalability, fast data read and write speeds, long cycle life, vertical stacking capability, and low write crosstalk due to thermal effects. It is a promising non-volatile memory with significant advantages and promising application prospects in areas such as high-speed interconnect technologies (Compute Express Link, CXL) and high-bandwidth memory (HBM).

[0027] Exemplary, reference Figure 1The memory cell array includes a first memory cell layer located between a first conductive line 301 and a second conductive line 303, and a second memory cell layer located between the second conductive line 303 and a third conductive line 305. The first memory cell layer includes a plurality of first memory cells 302, and the second memory cell layer includes a plurality of second memory cells 304. The first memory cells 302 include a first electrode, a storage structure, and a second electrode, and the second memory cells 304 include a first electrode, a storage structure, and a second electrode. In some embodiments, the first conductive line is perpendicular to the second conductive line, and the first conductive line is parallel to the third conductive line. Exemplarily, the first conductive line and the third conductive line are word lines WL, and the second conductive line is a bit line BL. It should be understood that the word lines WL and the bit lines BL can be interchanged.

[0028] In some embodiments, the storage structure has both storage and switching functions, that is, the material of the storage structure is a dual-function material (DFM). Exemplarily, the material of the storage structure may include any appropriate bidirectional threshold switch (OTS) material, which may include chalcogenide alloys such as germanium (Ge), arsenic (As) and selenium (Se) and their compounds; the first electrode and the second electrode may be the same material or different materials, and the materials of the first electrode and the second electrode include but are not limited to copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and its compounds, conductive doped semiconductors, etc.

[0029] In some embodiments, during a write operation in a memory device, such as a SOM device, each memory cell can be programmed to store two storage states represented by logic "1" (low resistance state, SET state) and logic "0" (high resistance state, RESET state). A forward pulse is applied to a selected memory cell to cause the elements in the OTS material to migrate forward or be positively polarized. This process is called a SET process, or a SET operation. A reverse pulse (or negative pulse) is applied to a selected memory cell to cause the elements in the OTS material to migrate backward or be reversely polarized. This process is called a RESET process, or a RESET operation. In other devices, more than two states can be stored, which will not be described in detail here.

[0030] In some embodiments, during a read operation, the SOM device can obtain data by applying a pulse voltage between the SET and RESET threshold transition voltages, i.e., a read voltage VRead, to the memory cell to measure the resistance values ​​of the two states of the OTS material in the memory cell. It should be understood that a small number of reads of the read voltage generally does not change the memory state of the SOM device.

[0031] Here and below, the first direction and the second direction may be two directions parallel to the substrate surface, and the third direction may be a direction perpendicular to the substrate surface. In some embodiments, the first direction intersects with the second direction, and the angle between the two is in the range of 0-90 degrees. In some embodiments, the first direction may be perpendicular to the second direction. In order to clearly describe the present disclosure, the following embodiments are described by taking the first direction as the Y direction in the accompanying drawings, the second direction as the X direction in the accompanying drawings, and the third direction as the Z direction in the accompanying drawings as an example. However, it should be noted that the description of the directions in the following embodiments is only used to illustrate the present disclosure and is not intended to limit the scope of the present disclosure.

[0032] Figures 2a to 2s The present invention exemplarily shows a manufacturing process of a semiconductor structure 400 , which may be at least a part of a selector-only memory.

[0033] refer to Figure 2a , providing a substrate 410, and forming a peripheral circuit 420 above the substrate 410. The space on the substrate 410 can be divided into a first area A1 and a second area A2 surrounding the first area A1. It should be noted that, except for the top view (XY plane), in this disclosure, only the second area A2 on one side of the first area A1 in the X direction is shown, and the second area on the other side is omitted.

[0034] refer to Figure 2b An initial storage layer 431 is formed above the peripheral circuit 420. The initial storage layer 431 includes a first electrode layer 432, a storage material layer 433, and a second electrode layer 434 stacked in sequence along the Z direction. The initial storage layer 431 is located in the first area A1 and the second area A2.

[0035] In some embodiments, before forming the initial storage layer 431 above the peripheral circuit 420 , a bottom-most word line or bit line may be formed first.

[0036] refer to Figure 2c and Figure 2d , the initial storage layer 431 is etched to form a plurality of second trenches T2 extending along the first direction (Y direction), and the plurality of second trenches T2 divide the initial storage layer 431 into a plurality of storage columns 402 . Figure 2dThis is a top view of the initial memory layer 431 after forming the second trenches T2. It should be noted that because the memory columns 402 and the second trenches T2 are alternately arranged along the X-direction using self-aligned double patterning (SADP) technology, the hard mask layers in the second area A2 may connect to each other during the SADP process, resulting in the portions of two adjacent memory columns 402 located in the second area A2 being connected to each other. For example, the third ends 402a of two adjacent memory columns 402 in the Y-direction are connected to each other, and the fourth ends 402b of two adjacent memory columns 402 in the Y-direction are connected to each other. Therefore, a subsequent etching process needs to remove the portions of the memory columns 402 located in the second area A2, thereby separating the two adjacent memory columns 402 from each other.

[0037] refer to Figure 2e , etching a plurality of memory columns 402 to form a plurality of third trenches ( Figure 2e (not shown), multiple second trenches T2 and multiple third trenches divide the initial storage layer 431 into multiple storage cells 401, wherein the first electrode layer, the storage material layer and the second electrode layer respectively form the first electrode 403, the storage structure 404 and the second electrode 405 of the storage cell 401.

[0038] refer to Figure 2f and Figure 2g , the memory columns 402 located in the second area A2 are etched away, and the portion of the memory columns 402 that pass through the first area A1 and are located in the second area A2 are etched away, forming a fifth trench T5 located in the second area A2, thereby separating two adjacent memory columns 402 from each other, and the remaining memory columns 402 are all located in the first area A1. It should be noted that Figure 2e and Figure 2f ( Figure 2g ) The order of the corresponding steps can be interchanged, or Figure 2e and Figure 2f ( Figure 2g ) The corresponding steps can be completed through the same etching process.

[0039] In some embodiments, reference Figure 2h A dielectric material may be filled into the second trench T2, the third trench, and the fifth trench T5 to form a storage layer 440 including a plurality of storage units 401 and the dielectric material.

[0040] refer to Figure 2hAn initial conductive layer 451 is formed in the first area A1 and the second area A2 above the storage layer 440. The material of the initial conductive layer 451 includes but is not limited to tungsten, copper, aluminum, gold, carbon and its compounds, conductive doped semiconductors, etc. The initial conductive layer 451 is used to form conductive lines such as word lines and bit lines.

[0041] refer to Figure 2i and Figure 2j , the initial conductive layer 451 is etched to form a plurality of first trenches T1 parallel to each other, and the remaining initial conductive layer 451 forms a plurality of initial conductive lines 452 parallel to each other. Figure 2j This is a top view of the initial conductive layer 451 after forming the first trench T1. It should be noted that since the alternating arrangement of the initial conductive lines 452 and the third trench T1 is formed using the self-aligned double patterning (SADP) technique, the hard mask located in the second area A2 may be connected to each other during the SADP process, resulting in the portions of two adjacent initial conductive lines 452 located in the second area A2 being connected to each other. For example, the initial conductive lines 452 have first ends 452a and second ends 452b located in the second area A2 and opposing each other, the first ends 452a of the two adjacent initial conductive lines 452 being connected to each other, and the second ends 452b of the two adjacent initial conductive lines 452 being connected to each other. In this way, the subsequent etching process needs to remove the portions of the initial conductive lines 452 located in the second area A2, thereby separating the two adjacent initial conductive lines 452 from each other. Each initial conductive line 452 connects to multiple memory cells below, thereby serving as a word line or bit line.

[0042] In some embodiments, the initial conductive lines 452 formed by etching may extend along the X direction. In other embodiments, the initial conductive lines 452 formed by etching may also extend along the Y direction. It should be noted that the directions of the initial conductive lines 452 above two adjacent storage layers 440 are perpendicular to each other, that is, the two conductive lines connected to the same storage cell are ultimately perpendicular to each other.

[0043] refer to Figure 2k and Figure 2l , the initial conductive line 452 located in the second area A2 is etched away, and the portion of the initial conductive line 452 that passes through the first area A1 and is located in the second area A2 is etched away to form a sixth trench T6 located in the second area A2, thereby separating two adjacent initial conductive lines 452 from each other, and the remaining initial conductive line 452 located in the first area A1 forms a conductive line 453.

[0044] In some embodiments, dielectric material may be further filled into the sixth trench T6 to form a conductive structure layer 450 including a plurality of conductive lines 453 and dielectric material. The memory layer 440 and the conductive structure layer 450 above the memory layer 440 together constitute a first device layer 471 .

[0045] In some embodiments, the Figures 2b to 2l , thereby forming a plurality of first device layers 471 stacked on the substrate 410. In two adjacent first device layers 471, the extending directions of the conductive lines 453 are perpendicular to each other.

[0046] refer to Figure 2m An initial storage layer 431 is formed on the first device layer 471. The initial storage layer 431 includes a first electrode layer 432, a storage material layer 433, and a second electrode layer 434 stacked in sequence along the Z direction. The initial storage layer 431 is located in the first area A1 and the second area A2.

[0047] refer to Figure 2n , the initial storage layer 431 is etched to form a plurality of second trenches T2 extending along the first direction (Y direction), and a plurality of third trenches extending along the second direction (X direction). The plurality of second trenches T2 and the plurality of third trenches divide the initial storage layer 431 into a plurality of storage cells 401, wherein the first electrode layer, the storage material layer, and the second electrode layer respectively form a first electrode 403, a storage structure 404, and a second electrode 405 of the storage cell 401.

[0048] In some embodiments, dielectric material may be further filled into the second trench T2 and the third trench, thereby forming a storage layer 440 including a plurality of storage units 401 and dielectric material.

[0049] refer to Figure 2o An initial conductive layer 451 is formed in the first area A1 and the second area A2 above the storage layer 440. The material of the initial conductive layer 451 includes but is not limited to tungsten, copper, aluminum, gold, carbon and its compounds, conductive doped semiconductors, etc. The initial conductive layer 451 is used to form conductive lines such as word lines and bit lines.

[0050] refer to Figure 2p and Figure 2q , the initial conductive layer 451 is etched to form a plurality of first trenches T1 parallel to each other, and the remaining initial conductive layer 451 forms a plurality of initial conductive lines 452 parallel to each other. Figure 2qThis is a top view of the initial conductive layer 451 after forming the first trench T1. It should be noted that since the alternating arrangement of the initial conductive lines 452 and the first trench T1 is formed using the self-aligned double patterning (SADP) technique, the hard mask located in the second area A2 may be connected to each other during the SADP process, resulting in the portions of two adjacent initial conductive lines 452 located in the second area A2 being connected to each other. For example, the initial conductive lines 452 have first ends 452a and second ends 452b located in the second area A2 and opposing each other, the first ends 452a of the two adjacent initial conductive lines 452 being connected to each other, and the second ends 452b of the two adjacent initial conductive lines 452 being connected to each other. In this way, the subsequent etching process needs to remove the portions of the initial conductive lines 452 located in the second area A2, thereby separating the two adjacent initial conductive lines 452 from each other. Each initial conductive line 452 connects to multiple memory cells below, thereby serving as a word line or bit line.

[0051] refer to Figure 2r , the initial conductive layer 451 and the storage layer 440 located in the second area A2 are etched away to form a seventh trench T7, so that two adjacent initial conductive lines 452 are separated from each other, and the remaining initial conductive lines 452 located in the first area A1 form conductive lines 453.

[0052] refer to Figure 2s , a dielectric material is filled into the seventh trench T7, thereby forming a conductive structure layer 450 including a plurality of conductive lines 453 and the dielectric material. The storage layer 440 and the conductive structure layer 450 above the storage layer 440 together constitute the second device layer 472. It should be noted that the second device layer 472 refers to the topmost storage layer 440 and the conductive structure layer 450, and the first device layer 471 refers to the device layer below the second device layer 472.

[0053] It can be understood that, during the process of forming the second device layer 472, the initial conductive layer 451 and the portion of the storage layer 440 located in the second area A2 are removed by one etching step ( Figure 2r As shown in the step), without forming the first device layer 471 as described above, the initial conductive layer 451 and the initial storage layer 431 are respectively removed by two etchings in the second area A2 ( Figure 2c 、 Figure 2i steps shown).

[0054] For forming the first device layer 471, the initial storage layer 431 needs to be etched once to remove the portion in the second area A2, and after filling the dielectric material in the fifth trench T5, a chemical mechanical polishing (CMP) process is performed. The initial conductive layer 451 also needs to be etched once to remove the portion in the second area A2, and after filling the dielectric material in the sixth trench T6, a chemical mechanical polishing process is performed. In this way, multiple etchings will greatly increase the process cost (including etching, photolithography, chemical mechanical planarization and other processes), and will also cause more etching damage to structures such as storage units and conductive lines, affecting product yield. In particular, for device layers with more than three layers (including more than two first device layers 471), the process complexity and cost will be higher.

[0055] The present disclosure provides a method for manufacturing a semiconductor structure. Figure 3 As shown, the manufacturing method includes the following steps:

[0056] Step S10: providing a substrate;

[0057] Step S20: forming a first conductive layer and a first memory cell layer in sequence on the substrate in the first region;

[0058] Step S30: forming a second conductive layer, a second memory cell layer, and a third conductive layer in the first region and the second region on the first memory cell layer in sequence; the second region surrounds and connects to the first region;

[0059] Step S40: removing the second conductive layer, the second memory cell layer, and the third conductive layer located in the second region.

[0060] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 3 The steps shown in the following can be adjusted in order according to actual needs. Figures 4a to 4r The semiconductor structure 500 may be at least a portion of a selector-only memory.

[0061] like Figure 4aAs shown, a substrate 510 is provided, and a peripheral circuit 520 is formed above the substrate 510. The substrate 510 can be divided into a first area A1 and a second area A2 surrounding the first area A1. The substrate 510 can be made of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 510 can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator. The present disclosure does not specifically limit the constituent materials of the substrate 201. The peripheral circuits 520 may include any suitable digital, analog, and / or mixed-signal circuits for facilitating the operation of the memory device. For example, the peripheral circuits may include control logic, data buffers, decoders, drivers, and read / write circuits. The peripheral circuits 520 are used to control operations such as reading, writing, and erasing the memory cells.

[0062] In some embodiments, forming the first conductive layer includes forming a plurality of second conductive lines located in the first region and parallel to each other.

[0063] In the embodiment of the present disclosure, Figure 4b As shown, after the peripheral circuit 520 is formed on the substrate 510, a first conductive layer 580 can be formed on the peripheral circuit 520. Specifically, an initial conductive layer can be formed in the first area A1 and the second area A2 on the peripheral circuit 520, and then the initial conductive layer can be etched to form a plurality of mutually parallel second conductive lines 581. Finally, the second conductive lines 581 located in the second area A2 are removed. For example, the second conductive lines 581 can be used as word lines or bit lines, and the second conductive lines 581 can extend in a direction parallel to the surface of the substrate 510, for example, in the X direction or the Y direction.

[0064] In some embodiments, the forming of the initial storage layer located in the first region and the second region includes: sequentially forming a first electrode layer, a storage material layer, and a second electrode layer located in the first region and the second region and stacked; the first electrode layer, the storage material layer, and the second electrode layer are respectively used to form the first electrode, storage structure, and second electrode of the storage unit.

[0065] like Figure 4bAs shown, an initial storage layer 531 can be formed above the peripheral circuit 520 through processes such as deposition and epitaxial growth. The initial storage layer 531 includes a first electrode layer 532, a storage material layer 533, and a second electrode layer 534 stacked in sequence along the Z direction. The initial storage layer 531 is located in the first area A1 and the second area A2. The first electrode layer 532 and the second electrode layer 534 can be made of a metal or alloy material, such as a material containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, or the like. They can also be made of metal oxides, metal nitrides, metal silicides, metal carbides, and the like, such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (AZO), iridium oxide (IrOx), ruthenium oxide (RuOx), and other metal oxide conductive materials. Furthermore, they can be made of metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN). The first electrode layer 532 and the second electrode layer 534 can be a single layer or multiple layers. For example, the first electrode layer 532 and the second electrode layer 534 can each include a metal layer and an adhesion layer, wherein the metal layer can be tungsten and the adhesion layer can be titanium nitride.

[0066] In the present disclosure, deposition processes include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof. In the present disclosure, epitaxial growth processes include, but are not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0067] In some embodiments, forming the first storage cell layer and the second storage cell layer includes: forming an initial storage layer located in the first region and the second region; etching the initial storage layer to form a plurality of second grooves extending along a first direction, and the remaining initial storage layer forms a plurality of storage columns; the storage columns have a third end and a fourth end that are opposite in the first direction and located in the second region; wherein the third ends of two adjacent storage columns are connected to each other, and the fourth ends of two adjacent storage columns are connected to each other; the first direction is parallel to the surface of the substrate; etching the plurality of storage columns to form a plurality of third grooves extending along a second direction, and the plurality of third grooves divide the plurality of storage columns into a plurality of storage cells.

[0068] like Figure 4c and Figure 4d As shown, a plurality of second trenches T2 extending along the first direction (Y direction) are formed in the initial storage layer 531 through processes such as photolithography and etching. The plurality of second trenches T2 divide the initial storage layer 531 into a plurality of storage columns 502 . Figure 4d This is a top view of the initial memory layer 531 after forming the second trenches T2. It should be noted that because the memory columns 502 and the second trenches T2 are alternately arranged along the X-direction using self-aligned double patterning (SADP) technology, the hard mask located in the second area A2 may be interconnected during the SADP process, resulting in the portions of two adjacent memory columns 502 located in the second area A2 being interconnected. For example, the third ends 502a of two adjacent memory columns 502 in the Y-direction are interconnected, and the fourth ends 502b of two adjacent memory columns 502 in the Y-direction are interconnected. Therefore, a subsequent etching process needs to remove the portions of the memory columns 502 located in the second area A2, thereby separating the two adjacent memory columns 502 from each other.

[0069] In this disclosure, etching processes can be divided into dry etching and wet etching. Dry etching can include ion milling etching, plasma etching, reactive ion etching, or laser ablation, while wet etching uses solvents or solutions, such as acid or alkali solutions.

[0070] refer to Figure 4e , etching a plurality of memory columns 502 to form a plurality of third trenches ( Figure 4e(not shown), multiple second trenches T2 and multiple third trenches divide the initial storage layer 531 into multiple storage cells 501, wherein the first electrode layer, the storage material layer and the second electrode layer respectively form the first electrode 503, the storage structure 504 and the second electrode 505 of the storage cell 501.

[0071] In some embodiments, forming the first memory cell layer further includes: removing the initial memory layer located in the second region.

[0072] refer to Figure 4f and Figure 4g , the memory columns 502 located in the second area A2 are etched away, and the portion of the memory columns 502 that penetrate the first area A1 and are located in the second area A2 are etched away (i.e., the memory cells 501 in the second area A2 are removed), forming a fifth trench T5 located in the second area A2, thereby separating two adjacent memory columns 502 from each other, and the remaining memory columns 502 (memory cells 501) are all located in the first area A1. It should be noted that Figure 4e and Figure 4f ( Figure 4g ) The order of the corresponding steps can be interchanged, or Figure 4e and Figure 4f ( Figure 4g ) The corresponding steps can be completed through the same etching process.

[0073] In some embodiments, dielectric material can also be filled into the second trench T2, the third trench and the fifth trench T5 to form a first storage cell layer 541 located in the first area A1 and including multiple storage cells 501 and dielectric material. It can be understood that the first storage cell layer 541 does not include the dielectric material located in the fifth trench T5.

[0074] The dielectric materials disclosed herein include but are not limited to silicon oxide (such as silicon dioxide), silicon nitride (such as silicon oxynitride), nitride (such as silicon nitride), metal oxide (such as Al2O3), metal oxynitride (such as AlON), high-K dielectric material (dielectric constant greater than 3.9), low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-K dielectric material (dielectric constant less than 2.5), carbide (such as silicon carbide) or a combination thereof.

[0075] In some embodiments, forming the multiple initial conductive lines includes: forming an initial conductive layer located in the first region and the second region; etching the initial conductive layer to form a plurality of first grooves parallel to each other, and the remaining initial conductive layer forms the multiple initial conductive lines; the initial conductive line has a first end and a second end located in the second region and opposite to each other; wherein the first ends of two adjacent initial conductive lines are connected to each other, and the second ends of two adjacent initial conductive lines are connected to each other.

[0076] refer to Figure 4h An initial conductive layer 551 is formed in the first region A1 and the second region A2 above the first memory cell layer 541 through processes such as deposition and epitaxial growth. The material of the initial conductive layer 551 includes but is not limited to tungsten, copper, aluminum, gold, carbon and its compounds, conductive doped semiconductors, etc. The initial conductive layer 551 is used to form conductive lines such as word lines and bit lines.

[0077] refer to Figure 4i and Figure 4j , the initial conductive layer 551 is etched to form a plurality of first trenches T1 parallel to each other, and the remaining initial conductive layer 551 forms a plurality of initial conductive lines 552 parallel to each other. Figure 4j This is a top view of the initial conductive layer 551 after forming the first trench T1. It should be noted that since the alternating arrangement of the initial conductive lines 552 and the first trench T1 is formed using the self-aligned double patterning (SADP) technique, the hard mask located in the second area A2 may be connected to each other during the SADP process, resulting in the portions of two adjacent initial conductive lines 552 located in the second area A2 being connected to each other. For example, the initial conductive lines 552 have first ends 552a and second ends 552b located in the second area A2 and opposing each other, the first ends 552a of the two adjacent initial conductive lines 552 being connected to each other, and the second ends 552b of the two adjacent initial conductive lines 552 being connected to each other. In this way, the subsequent etching process needs to remove the portions of the initial conductive lines 552 located in the second area A2, thereby separating the two adjacent initial conductive lines 552 from each other. Each initial conductive line 552 connects to multiple memory cells below, thereby serving as a word line or bit line.

[0078] In some embodiments, the initial conductive lines 552 formed by etching may extend along the X direction. In other embodiments, the initial conductive lines 552 formed by etching may also extend along the Y direction. It should be noted that the directions of the initial conductive lines 552 above two adjacent layers of memory cells are perpendicular, that is, the two conductive lines connected to the same memory cell are ultimately perpendicular to each other.

[0079] In some embodiments, dielectric material may be further filled into the first trench T1 to form a second conductive layer 582 including a plurality of initial conductive lines 552 and dielectric material. The first memory cell layer 541 and the second conductive layer 582 above the first memory cell layer 541 together constitute a first device layer 571 .

[0080] In some embodiments, the Figures 4b to 4j , thereby forming a plurality of first device layers 571 stacked on the substrate 510. In two adjacent first device layers 571, the extending directions of the conductive lines 553 are perpendicular to each other.

[0081] That is to say, for the first device layer 571, after etching to form the initial conductive line 552 and the first trench T1, the initial conductive line 552 located in the second area A2 and the portion of the initial conductive line 552 that passes through the first area A1 and is located in the second area A2 may not be temporarily removed, that is, the portion of the initial conductive layer 551 located in the second area A2 is temporarily retained. Subsequently, after forming multiple device layers, the portions of the multiple initial conductive layers 551 located in the second area A2 are etched away at one time, thereby simplifying the manufacturing process of the semiconductor structure, reducing process costs, and reducing etching damage to each device layer. In the present disclosure, "one-time etching" may refer to etching performed using the same mask layer, and "one-time etching" may also include multiple-step etching, with each step etching to a different depth.

[0082] It should be noted that for each first device layer 571, it is still necessary to remove the storage column 502 located in the second area A2, and remove the part of the storage column 502 that passes through the first area A1 and is located in the second area A2, so as to form a fifth trench T5 located in the second area A2. In this way, space can be freed up to form a contact structure connected to each first storage unit layer 541.

[0083] After forming one or more first device layers 471, a second device layer can be formed on top. It will be appreciated that the memory cells in the first device layer are located only in the first region A1. Furthermore, after forming the top second device layer, the portions of multiple device layers located in the second region A2 can be etched away at once. Therefore, the memory cells in the second device layer can be located in both the first region A1 and the second region A2.

[0084] refer to Figure 4k An initial storage layer 531 is formed on the first device layer 571. The initial storage layer 531 includes a first electrode layer 532, a storage material layer 533, and a second electrode layer 534 stacked in sequence along the Z direction. The initial storage layer 531 is located in the first area A1 and the second area A2.

[0085] refer to Figure 4l, the initial storage layer 531 is etched to form a plurality of second trenches T2 extending along the first direction (Y direction), and a plurality of third trenches (not shown) extending along the second direction (X direction). The plurality of second trenches T2 and the plurality of third trenches divide the initial storage layer 531 into a plurality of storage cells 501, wherein the first electrode layer, the storage material layer, and the second electrode layer respectively form the first electrode 503, the storage structure 504, and the second electrode 505 of the storage cell 501.

[0086] In some embodiments, dielectric material may be further filled into the second trench T2 and the third trench to form a second memory cell layer 542 including multiple memory cells 501 and dielectric material. It is understood that the multiple memory cells 501 in the second memory cell layer 542 are located in the first area A1 and the second area A2.

[0087] refer to Figure 4m An initial conductive layer 551 is formed in the first area A1 and the second area A2 above the second storage cell layer 542. The material of the initial conductive layer 551 includes but is not limited to tungsten, copper, aluminum, gold, carbon and its compounds, conductive doped semiconductors, etc. The initial conductive layer 551 is used to form conductive lines such as word lines and bit lines.

[0088] refer to Figure 4n and Figure 4o , the initial conductive layer 551 is etched to form a plurality of first trenches T1 parallel to each other, and the remaining initial conductive layer 551 forms a plurality of initial conductive lines 552 parallel to each other. Figure 4o This is a top view of the initial conductive layer 551 after forming the first trench T1. It should be noted that since the alternating arrangement of the initial conductive lines 552 and the first trench T1 is formed using the self-aligned double patterning (SADP) technique, the hard mask located in the second area A2 may be connected to each other during the SADP process, resulting in the portions of two adjacent initial conductive lines 552 located in the second area A2 being connected to each other. For example, the initial conductive lines 552 have first ends 552a and second ends 552b located in the second area A2 and opposing each other, the first ends 552a of the two adjacent initial conductive lines 552 being connected to each other, and the second ends 552b of the two adjacent initial conductive lines 552 being connected to each other. In this way, the subsequent etching process needs to remove the portions of the initial conductive lines 552 located in the second area A2, thereby separating the two adjacent initial conductive lines 552 from each other. Each initial conductive line 552 connects to multiple memory cells below, thereby serving as a word line or bit line.

[0089] After forming the initial conductive lines 552 and the first trenches T1, dielectric material can be filled into the first trenches T1 using a deposition process or other similar process, thereby forming a third conductive layer 583 including the plurality of initial conductive lines 552 and the dielectric material. The second memory cell layer 542 and the third conductive layer 583 above the second memory cell layer 542 together constitute the second device layer 572. It will be understood that the memory cells 501 of the second memory cell layer 542 in the second device layer 572 are located within the first and second regions A1 and A2, and the initial conductive lines 552 of the third conductive layer 583 in the second device layer 572 are located within the first and second regions A1 and A2.

[0090] In some embodiments, the second conductive layer and the third conductive layer both include multiple initial conductive lines; the multiple initial conductive lines include a first initial conductive line running through the first area and a second initial conductive line located in the second area, the first initial conductive line includes a first part located in the first area, and a second part located in the second area; the removal of the second conductive layer, the second storage unit layer and the third conductive layer located in the second area includes: removing the storage unit located in the second area in the second storage unit layer, and the second initial conductive line and the second part in the second conductive layer and the third conductive layer, and the remaining first part forms a first conductive line.

[0091] In some embodiments, removing the second portion of the second conductive layer and the third conductive layer includes: removing portions of adjacent initial conductive lines that are connected to each other, so as to separate adjacent initial conductive lines from each other.

[0092] In the embodiment of the present disclosure, the initial conductive line 552 formed in the second device layer may include a first initial conductive line 554 running through the first area A1 and a second initial conductive line 555 located in the second area A2. The first initial conductive line 554 includes a first portion 5541 located in the first area A1 and a second portion 5542 located in the second area A2.

[0093] refer to Figure 4p and Figure 4q , the second conductive layer 582, the second storage unit layer 542 and the portion of the third conductive layer 583 located in the second area A2 can be removed by one-time etching, so that two adjacent initial conductive lines 552 in the third conductive layer 583 and the second conductive layer 582 are separated from each other, and only the first portion 5541 located in the first area A1 is retained in the third conductive layer 583 and the second conductive layer 582. The remaining first portion 5541 is the first conductive line, which can be used as a word line or a bit line.

[0094] In some embodiments, the removing of the second conductive layer, the second storage cell layer, and the third conductive layer located in the second region includes: removing the second conductive layer, the second storage cell layer, and the third conductive layer located in the second region to form a fourth trench surrounding the remaining second conductive layer, the second storage cell layer, and the third conductive layer in the first region; the manufacturing method also includes: forming a dielectric layer in the fourth trench.

[0095] Continue to refer Figure 4p The portions of the second conductive layer 582, the second storage cell layer 542 and the third conductive layer 583 located in the second area A2 are removed to form a fourth trench T4 surrounding the remaining second conductive layer 582, the second storage cell layer 542 and the third conductive layer 583 in the first area A1.

[0096] refer to Figure 4r , a dielectric material is filled into the fourth trench T4 by using a deposition process to form a dielectric layer 590 .

[0097] It can be understood that the present disclosure first sequentially forms the second conductive layer, the second memory cell layer, and the third conductive layer located in the first and second regions on the first memory cell layer; then removes the second conductive layer, the second memory cell layer, and the third conductive layer located in the second region. In other words, the present disclosure removes the second conductive layer, the second memory cell layer, and the third conductive layer located in the second region all at once, which helps simplify the semiconductor structure manufacturing process, reduces process costs, and minimizes etching damage to the individual memory cell layers.

[0098] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, which is formed by the manufacturing method described in any one of the above embodiments.

[0099] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0100] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0101] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: providing a substrate; forming a first conductive layer and a first memory cell layer in sequence on the substrate in the first region; forming a second conductive layer, a second memory cell layer, and a third conductive layer located in the first region and the second region on the first memory cell layer in sequence; wherein the second region surrounds and connects to the first region; The second conductive layer, the second memory cell layer, and the third conductive layer located in the second region are removed.

2. The manufacturing method according to claim 1, characterized in that The second conductive layer and the third conductive layer each include a plurality of initial conductive lines; the plurality of initial conductive lines include a first initial conductive line running through the first region and a second initial conductive line located in the second region; the first initial conductive line includes a first portion located in the first region and a second portion located in the second region; The removing of the second conductive layer, the second storage unit layer, and the third conductive layer located in the second region includes: The memory cells in the second region of the second memory cell layer, and the second initial conductive line and the second portion in the second conductive layer and the third conductive layer are removed, and the remaining first portion forms a first conductive line.

3. The manufacturing method according to claim 2, characterized in that Forming the plurality of initial conductive lines comprises: forming an initial conductive layer located in the first region and the second region; The initial conductive layer is etched to form a plurality of first grooves parallel to each other, and the remaining initial conductive layer forms the plurality of initial conductive lines; the initial conductive lines have a first end and a second end opposite to each other and located in the second region; wherein the first ends of two adjacent initial conductive lines are connected to each other, and the second ends of two adjacent initial conductive lines are connected to each other.

4. The manufacturing method according to claim 3, characterized in that Removing the second portion of the second conductive layer and the third conductive layer includes: The portions where adjacent initial conductive lines are connected to each other are removed to separate the adjacent initial conductive lines from each other.

5. The manufacturing method according to claim 1, characterized in that Forming the first memory cell layer and the second memory cell layer both includes: forming an initial storage layer located in the first region and the second region; The initial storage layer is etched to form a plurality of second trenches extending along a first direction, and the remaining initial storage layer forms a plurality of storage columns; the storage columns have third and fourth ends that are opposite to each other in the first direction and located within the second region; wherein the third ends of two adjacent storage columns are connected to each other, and the fourth ends of two adjacent storage columns are connected to each other; and the first direction is parallel to the surface of the substrate; The plurality of memory columns are etched to form a plurality of third trenches extending along the second direction, wherein the plurality of third trenches divide the plurality of memory columns into a plurality of memory cells.

6. The manufacturing method according to claim 5, characterized in that Forming the first memory cell layer further includes: The initial storage layer located in the second area is removed.

7. The manufacturing method according to claim 5, characterized in that The forming of the initial storage layer located in the first region and the second region includes: A first electrode layer, a storage material layer, and a second electrode layer are sequentially formed and stacked in the first region and the second region; the first electrode layer, the storage material layer, and the second electrode layer are respectively used to form the first electrode, the storage structure, and the second electrode of the storage unit.

8. The manufacturing method according to claim 1, characterized in that The removing of the second conductive layer, the second storage unit layer, and the third conductive layer located in the second region includes: removing the second conductive layer, the second memory cell layer, and the third conductive layer located in the second region, and forming a fourth trench surrounding the second conductive layer, the second memory cell layer, and the third conductive layer remaining in the first region; The manufacturing method further comprises: A dielectric layer is formed in the fourth trench.

9. The manufacturing method according to claim 1, characterized in that Forming the first conductive layer includes: A plurality of second conductive lines are formed in the first region and are parallel to each other.

10. A semiconductor structure, characterized in that The semiconductor structure is formed by the manufacturing method according to any one of claims 1 to 9.

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