Semiconductor packaging structure of integrated vertical interconnection glass bridge unit and manufacturing method thereof

Abstract

The invention discloses a semiconductor packaging structure integrated with a vertical interconnection glass bridge unit and a manufacturing method thereof, the packaging structure comprises a first plastic packaging material, a glass bridge unit and a glass interconnection unit are arranged in the first plastic packaging material, the glass bridge unit is provided with a plurality of first metalized through holes, and one side of the glass bridge unit is provided with a first rewiring structure; the glass interconnection unit is provided with a plurality of second metalized through holes; one side of the first molding compound is provided with a second rewiring structure, and the other side is provided with a third rewiring structure; and the first rewiring structure, the second rewiring structure and the third rewiring structure are communicated through the first metallization through hole and the second metallization through hole. Due to the combination of the glass bridge unit and the glass interconnection unit, conduction with an external circuit is realized, the bandwidth is effectively improved, the delay is reduced, and the application requirements of high-performance calculation, artificial intelligence and the like on the data transmission speed are met.

Description

Technical Field

[0001] The present invention relates to the field of advanced packaging technology, and in particular to a semiconductor packaging structure integrating vertical interconnected glass bridge units and a manufacturing method thereof. Background Art

[0002] With the increasing demand for electronic products, the development of semiconductor packaging technology has evolved from 2D structure to 2.5D and even 3D structure, which has put higher requirements on system-level packaging, including high-density integration and heterogeneous structure packaging.

[0003] In a 2.5D packaging structure, a silicon-based adapter board is made of an integral silicon-based material, and different dies are welded onto it to achieve interconnection between different dies. One method is to form through-silicon vias on the silicon-based adapter board, and then metallize the through-silicon vias to achieve conduction. However, the silicon-based adapter board itself also needs to be manufactured using chip process technology, so the cost is difficult to reduce. In addition, the area of ​​the silicon interposer is limited by the semiconductor process technology, which ultimately leads to further restrictions on the number of dies that can be accommodated on it. Moreover, as a semiconductor, silicon material has a strong electromagnetic coupling effect with the substrate material when transmitting signals in the line, generating eddy currents in the substrate, resulting in poor signal integrity (insertion loss, crosstalk, etc.).

[0004] Therefore, a process method has emerged that uses silicon bridges as interconnections between dies. That is, silicon bridges made into small-sized units are embedded inside the substrate to achieve connections between the dies, and the remaining areas that do not require connection are filled with traditional processes. This method greatly reduces the area compared to a whole silicon-based adapter board, while reducing manufacturing costs. At the same time, because there are far fewer structures on a single silicon bridge unit, the yield is greatly improved.

[0005] However, the silicon-based material used in the silicon bridge does not change the electrical properties of silicon as a semiconductor itself, and still requires high-purity silicon as raw material.

[0006] Application publication number CN117612954A discloses a method for realizing multi-chip interconnection, including the following steps: S1: a glass layer is installed on a glass substrate and a cavity is set; S2: a plurality of conductor posts are set in the cavity; S3: a chip is set in the cavity, a plurality of conductor posts are set on the top surface of the chip, and an organic dielectric layer is used to fill the chip and bury the cavity; S4: an upper redistribution layer and an upper connection point layer are generated on the glass layer, and the connection points of the connection point layer are connected to the top of the conductor posts; S5: the chip is flipped on the upper connection point layer; S6: the glass substrate is debonded, and a plurality of glass through holes are made under the glass layer; S7: a lower redistribution layer and a lower connection point layer are generated under the glass through holes of the glass layer, and the connection points on the lower connection point layer are connected to the bottom end of the conductor posts or the metal bumps of the buried chip through the pins of the lower redistribution layer; S8: balls are planted on the connection points of the lower connection point layer to complete the multi-chip interconnection.

[0007] The above method proposes a multi-chip interconnection method using glass as a substrate. However, the above method first generates conductor columns and redistribution layers, and then makes glass through-holes. The subsequent glass through-hole forming process may lead to the possibility of attacking the conductor columns that have been produced in the previous process, so there is a risk of reducing the yield.

[0008] As an insulator, glass overcomes many of the disadvantages of signal transmission in terms of electrical performance compared to semiconductor materials such as silicon: its dielectric constant is only about 1 / 3 of that of silicon, and its loss factor is 2 to 3 orders of magnitude lower than that of silicon; these characteristics greatly reduce substrate loss and parasitic effects, effectively improving the integrity of transmitted signals. For high-performance computing chips, this characteristic is particularly important, helping to improve overall efficiency and reliability; and the cost of glass is much lower than that of high-purity silicon.

[0009] Therefore, how to utilize the many advantages of glass materials and combine them with the structural advantages of the silicon bridge structure itself in chip three-dimensional packaging so that the final packaging structure not only has the electrical properties of glass-based materials but also avoids the yield reduction problem caused by large-area wiring on glass substrates; is an urgent problem to be solved. Summary of the Invention

[0010] The present invention aims to solve at least one of the technical problems in the above-mentioned technologies to a certain extent. To this end, one object of the present invention is to provide a semiconductor package structure with an integrated vertical interconnect glass bridge unit, comprising:

[0011] The first plastic encapsulation material has a glass bridge unit and a glass interconnection unit therein, wherein the glass bridge unit has a plurality of first metallized through holes, and one side of the glass bridge unit has a first redistribution structure; the glass interconnection unit has a plurality of second metallized through holes;

[0012] A first molding compound has a second redistribution structure on one side and a third redistribution structure on the other side; the first redistribution structure, the second redistribution structure, and the third redistribution structure are connected via a first metallized through-hole and a second metallized through-hole; a semiconductor device assembly including a plurality of chips connected to the second redistribution structure;

[0013] The second molding compound is used to fill the spaces between the chips and between the semiconductor device group and the second redistribution structure.

[0014] According to the semiconductor packaging structure with integrated vertical interconnect glass bridge units according to the embodiments of the present invention, the semiconductor device group uses a combination of glass bridge units and glass interconnect units to achieve connectivity with external circuits. Compared to existing silicon-based substrates, the glass substrate has a dielectric constant of only about one-third that of silicon and a loss factor that is 2 to 3 orders of magnitude lower than that of silicon. These characteristics significantly reduce substrate loss and parasitic effects, effectively improving the integrity of transmitted signals and thereby increasing the overall efficiency of the chip.

[0015] Compared with the existing whole glass substrate, the glass bridge unit and the glass interconnection unit of the present invention can be manufactured separately, thereby improving manufacturing efficiency and yield.

[0016] Compared with traditional substrates, it effectively increases bandwidth and reduces latency, meeting the application requirements of high-performance computing, artificial intelligence, and other applications that have extremely high requirements for data transmission speeds.

[0017] Optionally, the first metallized through hole and the second metallized through hole are manufactured using a TGV process.

[0018] Optionally, the first redistribution structure is a high-density interconnect line.

[0019] Optionally, the first redistribution structure and the second redistribution structure are connected through the first metallized through-hole.

[0020] Optionally, the second redistribution structure and the third redistribution structure are connected through the second metallized via.

[0021] Another object of the present invention is to provide a manufacturing method comprising the following steps:

[0022] S1: forming a first metallized through hole and a second metal through hole on a glass substrate;

[0023] S2: arranging a first redistribution structure to connect the first metallized through-hole;

[0024] S3: Cutting the glass substrate, wherein the glass substrate having the first redistribution structure and the first metallized through hole is used as a glass bridge unit, and the glass substrate having the second metallized through hole is used as a glass interconnect unit;

[0025] S4: placing the glass bridge unit and the glass interconnection unit on a carrier plate, and fixing the glass bridge unit and the glass interconnection unit in a first molding compound;

[0026] S5: removing the first plastic encapsulation material from the carrier board, and providing a second redistribution structure on one side to connect the first metallized through hole and the second metallized through hole;

[0027] S6: The chip is connected to the second rewiring structure;

[0028] S7: Filling the second plastic compound between the chips;

[0029] S8: thinning the first molding compound until the first metallized through hole and the second metallized through hole are exposed;

[0030] S9: Disposing a third redistribution structure and forming a bump on the surface where the first metallized through-hole and the second metallized through-hole are exposed.

[0031] The packaging structure manufactured by the manufacturing method of the present invention uses a combination of glass bridge units and glass interconnect units to connect the semiconductor device group to the external circuit. Compared with existing silicon-based substrates, the glass substrate has a dielectric constant of only about 1 / 3 of that of silicon materials, and the loss factor is 2 to 3 orders of magnitude lower than that of silicon materials. This reduces overall packaging loss and parasitic effects, ensures the integrity of the transmitted signal, and thus improves the overall efficiency of the chip.

[0032] Compared with the existing whole glass substrate, the glass bridge unit and glass interconnect unit of the present invention can be manufactured separately, and avoids the possibility of the wiring structure being damaged by subsequent processes caused by first manufacturing the wiring structure and then forming the metallized through-hole in the existing technology, thereby improving manufacturing efficiency and yield; in addition, wiring on a large-area glass substrate is different from the existing silicon substrate process, and the wiring yield of a large-area glass substrate is low. However, the present invention manufactures the glass bridge unit and the glass interconnect unit separately, and wiring is performed on the two types of units, and then wiring is performed between the units, thereby avoiding the risk of reduced yield due to completing large-area wiring at one time.

[0033] Compared with traditional substrates, it effectively increases bandwidth and reduces latency, meeting the application requirements of high-performance computing, artificial intelligence, and other applications that have extremely high requirements for data transmission speeds.

[0034] Optionally, in step S1 , the formed hole is a TGV hole.

[0035] Optionally, the bump is a solder joint or a copper pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 and Figure 2 The manufacturing process of glass bridge unit and glass interconnection unit;

[0037] Figures 3 to 5 a process for forming a reconstructed wafer for a glass bridge unit and a glass interconnect unit;

[0038] Figure 6 Schematic diagram of the connection between the chip, glass bridge unit and glass interconnection unit;

[0039] Figure 7 This is a schematic diagram of the chip after being encapsulated and fixed with the second plastic encapsulation compound;

[0040] Figure 8 exposing a first metallized through hole and a second metallized through hole after grinding the package structure;

[0041] Figure 9 A schematic diagram of connecting a first metallized through hole and a second metallized through hole of a package structure and forming a bump;

[0042] Figure 10 A complete structural cross-sectional view of an embodiment of a packaging structure.

[0043] Description of labels:

[0044] Semiconductor device group 1 chip 11

[0045] Glass bridge unit 2 First metallized through hole 21 First redistribution structure 22

[0046] Glass interconnect unit 3 Second metallized through hole 31

[0047] First molding compound 4 Second redistribution structure 41 Third redistribution structure 42

[0048] Second plastic compound 5

[0049] Bump 6

[0050] Carrier board 7. DETAILED DESCRIPTION

[0051] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0052] The present invention uses a combination of glass bridge units and glass interconnect units to achieve conduction with external circuits, which effectively increases bandwidth and reduces latency compared to traditional substrates, meeting the application requirements of high-performance computing, artificial intelligence, and other applications with extremely high requirements for data transmission speed.

[0053] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0054] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0055] Figures 1 to 10 A semiconductor package structure integrating vertical interconnection glass bridge units according to an embodiment of the present invention includes:

[0056] The first molding compound 4 has a glass bridge unit 2 and a glass interconnection unit 3 inside.

[0057] The glass bridge unit 2 has a plurality of first metallized through holes 21, and one side of the glass bridge unit 2 has a first redistribution structure 22; the glass interconnect unit 3 has a plurality of second metallized through holes 31;

[0058] The glass bridge unit 2, by providing the first redistribution structure 22, not only realizes the function of connecting different chips 11, but also enables itself to form an integrated passive device, that is, to be transformed into a glass bridge chip. Compared with the existing glass substrate packaging structure, this solution is different in that the glass bridge unit 2 and the glass interconnection unit 3 can be manufactured independently. Therefore, it has a wider range of characteristics than the packaging using a whole glass substrate. It is a packaging structure that uses the first plastic encapsulation material 4 as the overall base material and has the beneficial characteristics of the glass substrate.

[0059] Specifically, the first metallized through hole and the second metallized through hole are manufactured using a TGV process.

[0060] The first molding compound 4 has a second redistribution structure 41 on one side and a third redistribution structure 42 on the other side; the first redistribution structure 22, the second redistribution structure 41 and the third redistribution structure 42 are connected through the first metallized through hole 21 and the second metallized through hole 31;

[0061] The semiconductor device group 1 includes a plurality of chips 11 connected to a second redistribution structure 41;

[0062] The second molding compound 5 fills the space between the chips 11 and the space between the semiconductor device group 1 and the second redistribution structure 41 .

[0063] A specific solution is to package the GPU and HBM chip into an integrated structure. Compared with existing solutions, the final structure of this solution is as follows: the GPU and HBM are embedded in the second molding compound 5, and the glass bridge unit 2 and the glass interconnect unit 3 are embedded in the first molding compound 4. The first molding compound 4 and the second molding compound 5 can be resins.

[0064] Since the chips 11 are interconnected using the glass bridge unit 2 structure, and the chip 11 is connected to the glass interconnect unit 3, there is no direct structural connection between the glass bridge unit 2 and the glass interconnect unit 3. Except for the materials necessary for conduction, the gaps between the units are filled with the first plastic packaging material 4. This also means that each glass bridge unit 2 and glass interconnect unit 3 can be manufactured using different dimensions and specifications. This achieves one of the technical objectives of the present solution, namely, utilizing the adjustable thermal expansion coefficient of glass to reduce thermal mismatch with different materials, reduce wafer warpage, and reduce processing difficulty and yield loss.

[0065] Since glass materials have no freely moving charges and do not require the deposition of an insulating layer, they have excellent dielectric properties. Their dielectric constant is only about 1 / 3 of that of silicon materials, and their loss factor is 2-3 orders of magnitude lower than that of silicon materials. By embedding the glass bridge unit 2 and the glass interconnect unit 3, the overall packaging loss and parasitic effects can be greatly reduced, ensuring the integrity of the transmission signal, thereby improving the overall efficiency of the chip 1.

[0066] Optionally, the first rewiring structure 22 and the second rewiring structure 41 are connected through the first metallized through-hole 21 .

[0067] Optionally, the second redistribution structure 41 and the third redistribution structure 42 are connected through the second metallized via 31 .

[0068] Preferably, the glass bridge through-holes 21 and the glass interconnect through-holes 31 are formed using the TGV process. In this solution, since the glass bridge unit 2 and the glass interconnect unit 3 are manufactured separately, the two units can be produced on a single piece of glass material using the TGV process, then cut into small units for screening. After removing unqualified units, they can be placed in the chip package as several independent small components. However, if a large area of ​​glass material is formed into an overall structure using the TGV process, even if a small number of holes fail, they will have to be scrapped. Alternatively, if defects are not discovered during the inspection process, the defective structure will be packaged into the chip and only discovered during subsequent overall chip testing, which will require the chip to be scrapped or downgraded.

[0069] Therefore, the chips made using this process reduce the overall process requirements for the glass-based material by manufacturing the glass units separately and breaking them down into small units. Instead, they are cut into several small-scale units after manufacturing, so that the glass material after the TGV process can be utilized to the greatest extent, and the glass substrate with local process defects is avoided to the greatest extent possible from being encapsulated into the chip, thereby improving the overall chip yield.

[0070] The method to achieve the above package structure is:

[0071] Performing step S1: forming a first metallized through hole and a second metallized through hole on the glass substrate;

[0072] Specifically, the first metallized through hole and the second metallized through hole may be formed by using a TGV process.

[0073] To adapt the die's working state in the chip, it is necessary to select the appropriate glass type to ensure the final yield of the glass bridge unit and glass interconnect unit;

[0074] On this basis, the glass substrate is pretreated and cleaned: First, the glass substrate is pretreated, including cleaning and heat treatment, to ensure that the surface is clean and stress-free, laying a good foundation for subsequent processes;

[0075] Next, vertical micro-holes are made on the glass substrate; the hole-forming processes that can be used include laser drilling, ultrasonic drilling and wet etching, which can be used alone or in combination;

[0076] Ultrasonic cleaning, chemical cleaning and other methods are then used to remove the residues generated during the hole making process to ensure that the inner wall of the micropore is clean, providing a good foundation for subsequent metallization treatment;

[0077] Finally, the micropores are metallized. First, a seeding layer is deposited. A thin film is formed on the inner wall of the micropores through methods such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). Then, a thick metal layer is plated on the seeding layer through chemical or electrochemical methods. Common metals include copper and nickel.

[0078] After the processing, the substrate is formed with metal connection pads on both sides of the glass substrate through photolithography and etching processes, which form electrical connections with the metal layer in the micropores. At this point, the glass bridge unit and glass interconnect unit on the glass substrate have their own preliminary structures.

[0079] Execute step S2: Figure 2 As shown, a first redistribution structure is provided to connect the first metallized through-holes;

[0080] Execute step S3: Figure 1 and Figure 2As shown, the glass substrate is cut, and the glass substrate with the first redistribution structure and the first metallized through hole is used as a glass bridge unit, and the glass substrate with the second metallized through hole is used as a glass interconnect unit;

[0081] Execute step S4: Figure 3 、 Figure 4 As shown, the glass bridge unit and the glass interconnection unit are placed on the carrier plate 7, and the glass bridge unit and the glass interconnection unit are fixed in the first molding compound 4;

[0082] Execute step S5: Figure 5 As shown, the first plastic encapsulation material 4 is removed from the carrier board 7, and a second redistribution structure is provided on one side to connect the first metallized through hole and the second metallized through hole;

[0083] Execute step S6: Figure 6 As shown, the chip is connected to the second rewiring structure;

[0084] Execute step S7: Figure 7 As shown, the second plastic packaging material 5 is filled between the chips;

[0085] Execute step S8: Figure 8 As shown, the first molding compound 4 is thinned until the first metallized through hole and the second metallized through hole are exposed;

[0086] Execute step S9: Figure 9 、 Figure 10 As shown, a third redistribution structure is provided on the surface where the first metallized through-hole and the second metallized through-hole are exposed, and a bump is formed.

[0087] Specifically, the bumps in step S9 can be solder joints or copper pillars.

[0088] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0089] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0090] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0091] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A semiconductor package structure integrating vertical interconnected glass bridge units, characterized in that: include The first molding compound has a glass bridge unit and a glass interconnection unit inside, wherein The glass bridge unit has a plurality of first metallized through holes, and one side of the glass bridge unit has a first redistribution structure; A glass interconnect unit having a plurality of second metallized through holes; The first molding compound has a second redistribution structure on one side and a third redistribution structure on the other side; the first redistribution structure, the second redistribution structure and the third redistribution structure are connected through a first metallized through hole and a second metallized through hole; a semiconductor device group, including a plurality of chips, connected to the second redistribution structure; The second molding compound is used to fill the spaces between the chips and between the semiconductor device group and the second redistribution structure.

2. The semiconductor package structure with integrated vertical interconnect glass bridge units according to claim 1, wherein: The first metallized through hole and the second metallized through hole are manufactured by adopting the TGV process.

3. The semiconductor package structure with integrated vertical interconnect glass bridge units according to claim 1, wherein: The first redistribution structure is a high-density interconnection line.

4. The semiconductor package structure with integrated vertical interconnect glass bridge units according to claim 1, wherein: The first redistribution structure and the second redistribution structure are connected through the first metallized through-hole.

5. The semiconductor package structure with integrated vertical interconnect glass bridge units according to claim 1, wherein: The second redistribution structure and the third redistribution structure are connected through the second metallized via.

6. A method for manufacturing a semiconductor package structure integrating vertical interconnected glass bridge units, characterized in that: Includes the following steps S1: forming a first metallized through hole and a second metal through hole on a glass substrate; S2: arranging a first redistribution structure to connect the first metallized through-hole; S3: Cutting the glass substrate, wherein the glass substrate having the first redistribution structure and the first metallized through hole is used as a glass bridge unit, and the glass substrate having the second metallized through hole is used as a glass interconnect unit; S4: placing the glass bridge unit and the glass interconnection unit on a carrier plate, and fixing the glass bridge unit and the glass interconnection unit in a first molding compound; S5: removing the first plastic encapsulation material from the carrier board, and providing a second redistribution structure on one side to connect the first metallized through hole and the second metallized through hole; S6: The chip is connected to the second rewiring structure; S7: Filling the second plastic compound between the chips; S8: thinning the first molding compound until the first metallized through hole and the second metallized through hole are exposed; S9: Disposing a third redistribution structure and forming a bump on the surface where the first metallized through-hole and the second metallized through-hole are exposed.

7. The manufacturing method according to claim 6, wherein: In step S1 , the hole formed is a TGV hole.

8. The manufacturing method according to claim 6, wherein: The bumps are solder joints or copper pillars.

Images