Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; ion implantation for forming a channel region in the BCD device and ion implantation for forming a body region in the SGT device are adopted to synchronously form an anode doping region of the Zener diode in the substrate; a cathode doped region of the Zener diode is synchronously formed in the anode doped region by ion implantation forming a first source-drain doped region in the BCD device and the SGT device, the electrical types of doped ions in the cathode doped region and the anode doped region are opposite, and the anode doped region and the cathode doped region form a PN junction of the Zener diode. The requirement of an anode doping region in the Zener diode for ion doping concentration is met through an ion dose superposition injection mode, the anode doping region in the Zener diode is formed through synchronous parasitism of processes for forming a BCD device and an SGT device, and the phenomenon that a photomask process is additionally added to form the anode doping region with the heavy doping requirement is avoided. Therefore, the processing steps of the Zener diode are simplified, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] A Zener diode is a surface-contact crystal diode that utilizes its avalanche breakdown effect, also known as a voltage-stabilizing diode. A Zener diode exploits the principle that when a PN junction operates in reverse breakdown, the current changes significantly near the breakdown voltage, while the voltage changes very little. It is a semiconductor device that exhibits high resistance up to its critical reverse breakdown voltage. During reverse breakdown, the terminal voltage remains virtually constant within a certain current range (or power loss range), exhibiting voltage-stabilizing characteristics. When the reverse voltage of a Zener diode increases to a certain value, a slight change in bias voltage results in a significant increase in current. At this critical breakdown point, the reverse resistance decreases to a very low value. In this low-resistance region, the current increases while the voltage remains constant. The voltage that causes this effect is called the "breakdown" voltage or "Zener voltage" and is widely used in voltage-stabilized power supplies and limiter circuits.

[0003] Zener diodes are widely used in voltage-stabilized power supplies as reference voltage sources or as protection diodes in overcurrent protection circuits. They are often used as voltage regulators in low-voltage circuits. They are also used for surge protection, overvoltage protection, arc suppression, and series voltage regulation, and can be used to suppress transient interference and extremely high-speed pulse interference. Zener diodes are also widely used in LEDs. For example, when manufacturing high-power LEDs, a Zener diode can be connected in parallel for ESD protection or in series to help stabilize the voltage and prevent damage to the LED components due to current flow.

[0004] Hipower is a fusion process platform of BCD (Bipolar CMOS DMOS) and SGT (Split Gate Trench), dedicated to the production of intelligent power switch chips. Its low cost means high market competitiveness. Currently, the Hipower process platform can also form isolated Zener diodes.

[0005] However, the prior art has the problem of requiring a dedicated mask in the process of forming a Zener diode based on the Hipower process platform, resulting in high cost and low competitiveness. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to simplify the process steps and reduce the production cost.

[0007] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; using ion implantation to form a channel region in a BCD device and a body region in an SGT device to simultaneously form an anode doping region of a Zener diode in the substrate, wherein the substrate exposes the top surface of the anode doping region, and the electrical type of the doped ions in the anode doping region, the channel region, and the body region is the same; using ion implantation to form a first source / drain doping region in a BCD device and an SGT device to simultaneously form a cathode doping region of a Zener diode in the anode doping region, wherein the substrate exposes the top surface of the cathode doping region, the electrical type of the doped ions in the cathode doping region and the first source / drain doping region is the same, and the electrical types of the doped ions in the cathode doping region and the anode doping region are opposite, and the anode doping region and the cathode doping region form a PN junction of the Zener diode.

[0008] Optionally, after forming the anode doping region, the method further includes: using ion implantation to form the second source / drain doping region in the BCD device to simultaneously form an anode lead-out region of the Zener diode in the anode doping region, the substrate exposes the top surface of the anode lead-out region, and the electrical types of the doped ions in the anode lead-out region, the second source / drain doping region, and the anode doping region are the same.

[0009] Optionally, the anode lead-out region surrounds the cathode doped region.

[0010] Optionally, before forming the anode doping region, the method further includes: using a process for forming a shallow trench isolation structure in a BCD device to simultaneously form an isolation ring of a Zener diode in the substrate, wherein the substrate exposes a top surface of the isolation ring.

[0011] Optionally, the anode lead-out region is located between adjacent isolation rings, and the isolation rings surround the cathode doping region.

[0012] Optionally, before forming the anode doping region, it also includes: using ion implantation to form a buried layer and a deep well layer in a BCD device to synchronously form a doping region of a Zener diode in the substrate, the substrate exposes the top surface of the doping region, and the electrical type of the doped ions in the doping region, the buried layer and the deep well layer is the same.

[0013] Optionally, before forming the anode doping region, it also includes: using ion implantation to form the first high-voltage well region in the BCD device to synchronously form the first well region of the Zener diode in the doping region, the substrate exposes the top surface of the first well region, the anode doping region is located in the first well region, the electrical type of the doped ions in the first well region and the first high-voltage well region is the same, and the electrical type of the doped ions in the first well region is opposite to that in the doping region and the anode doping region, respectively.

[0014] Optionally, before forming the anode doping region, it also includes: using ion implantation to form a second high-voltage well region in the BCD device to synchronously form a guard ring of the Zener diode in the doping region, the substrate exposes the top surface of the guard ring, the electrical type of the doped ions in the guard ring and the second high-voltage well region is the same, and the electrical type of the doped ions in the guard ring and the first well region is opposite.

[0015] Optionally, the doping ions in the anode doping region are P-type ions; and the doping ions in the cathode doping region are N-type ions.

[0016] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by adopting any one of the above technical solutions, including: a substrate; an anode doping region of a Zener diode located in the substrate, the substrate exposing the top surface of the anode doping region; a cathode doping region of a Zener diode located in the anode doping region, the substrate exposing the top surface of the cathode doping region, the electrical types of the doped ions in the cathode doping region and the anode doping region are opposite, and the anode doping region and the cathode doping region constitute the PN junction of the Zener diode.

[0017] Optionally, it further includes: an anode lead-out region of a Zener diode located in the anode doping region, the substrate exposes the top surface of the anode lead-out region, and the electrical type of doped ions in the anode lead-out region and the anode doping region is the same.

[0018] Optionally, the anode lead-out region surrounds the cathode doped region.

[0019] Optionally, the method further includes: an isolation ring of the Zener diode located in the substrate, wherein the substrate exposes a top surface of the isolation ring.

[0020] Optionally, the anode lead-out region is located between adjacent isolation rings, and the isolation rings surround the cathode doping region.

[0021] Optionally, the method further includes: a doping region of a Zener diode located in the substrate, wherein the substrate exposes a top surface of the doping region.

[0022] Optionally, it also includes: a first well region of the Zener diode located in the doped region, the substrate exposing the top surface of the first well region, the anode doped region located in the first well region, and the electrical type of the doped ions in the first well region being opposite to that in the doped region and the anode doped region, respectively.

[0023] Optionally, the method further includes: a guard ring of a Zener diode located in the doped region, the substrate exposing a top surface of the guard ring, and the electrical types of the doped ions in the guard ring and the first well region are opposite.

[0024] Optionally, the doping ions in the anode doping region are P-type ions; and the doping ions in the cathode doping region are N-type ions.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the method for forming a semiconductor structure according to the technical solution of the present invention, ion implantation, which forms the channel region of a BCD device and the body region of an SGT device, is used to simultaneously form the anode doping region of the Zener diode within the substrate. By employing a stacked ion implantation method to meet the ion doping concentration requirements of the anode doping region of the Zener diode, the anode doping region of the Zener diode is parasitically formed simultaneously using the processes for forming the BCD and SGT devices. This avoids the need for an additional photomask process to form the heavily doped anode doping region, thereby simplifying the Zener diode manufacturing process and reducing production costs.

[0027] Furthermore, before forming the anode doped region, the method further includes: simultaneously forming an isolation ring for the Zener diode within the substrate using a process for forming shallow trench isolation structures in BCD devices, with the substrate exposing the top surface of the isolation ring. The isolation ring serves to electrically isolate the active area of ​​the Zener diode from other devices. By forming a high-impedance isolation region around the Zener diode, current leakage from the Zener diode to the substrate or other adjacent devices is prevented, thereby improving the performance and stability of the Zener diode.

[0028] Furthermore, before forming the anode doped region, the method further includes: using ion implantation to form the second high-voltage well region in the BCD device to simultaneously form a guard ring for the Zener diode within the doped region, wherein the substrate exposes the top surface of the guard ring, and the ions doped in the guard ring and the second high-voltage well region have the same electrical type, while the ions doped in the guard ring and the first well region have opposite electrical types. During operation, a Zener diode may be affected by external noise or transient current, which may induce latch-up. The guard ring, by providing a low-impedance path, can effectively discharge the trigger current of the parasitic structure, preventing the occurrence of latch-up.

[0029] In the semiconductor structure of the present invention, ion implantation, which forms the channel region of the BCD device and the body region of the SGT device, is used to simultaneously form the anode doping region of the Zener diode within the substrate. Ion implantation with overlapping ion doses satisfies the ion doping concentration requirements of the anode doping region of the Zener diode. The anode doping region of the Zener diode is parasitically formed simultaneously using the processes for forming the BCD and SGT devices, thereby avoiding the need for additional photomask steps to form the heavily doped anode doping region. This simplifies the Zener diode manufacturing process and reduces production costs.

[0030] Furthermore, the device includes an isolation ring for the Zener diode located within the substrate, with the substrate exposing the top surface of the isolation ring. The isolation ring electrically isolates the active area of ​​the Zener diode from other devices. By forming a high-impedance isolation region around the Zener diode, current leakage from the Zener diode to the substrate or other adjacent devices is prevented, thereby improving the performance and stability of the Zener diode.

[0031] Furthermore, the device further includes a guard ring for a Zener diode located within the doped region, wherein the top surface of the guard ring is exposed by the substrate, and the electrical type of the ions doped in the guard ring and the first well region is opposite. During operation, the Zener diode may be affected by external noise or transient current, thereby inducing latch-up. The guard ring effectively discharges the trigger current of the parasitic structure by providing a low-impedance path, thereby preventing the occurrence of latch-up. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a Zener diode;

[0033] Figures 2 to 8 1. It is a schematic structural diagram of each step of a semiconductor structure and a method for forming the same according to an embodiment of the present invention;

[0034] Figure 9 Schematic diagram of the structure of an SGT device in an embodiment of the present invention;

[0035] Figure 10 1 is a schematic structural diagram of an NLDMOS device in a BCD device according to an embodiment of the present invention;

[0036] Figure 11 Schematic diagram of the structure of an NMOS device in a BCD device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the prior art of forming Zener diodes based on the HiPower process platform has the problem of requiring a dedicated mask, high cost, and low competitiveness.

[0038] Figure 1 It is a structural diagram of a Zener diode.

[0039] Please refer to Figure 1 Zener diodes, as voltage clamping devices, have widespread market demand. The HiPower process platform can manufacture isolated Zener diodes. The current fabrication method includes: first, within the N-type substrate and epitaxial layer forming the SGT device, ion implantation is used to form the P-type buried layer (PBL) and P-type deep well layer (DPW) in the BCD device to form a P-type region 100; ion implantation and shallow trench isolation (STI) are used to form the N-type high-voltage well region in the BCD device to form an N-type well region 101 and an isolation ring 102; ion implantation is used to form the P-type high-voltage well region in the BCD device to form a guard ring 103; a separate photomask process is used to form a deep, heavily doped N-type doped region 104; and ion implantation is used to form the heavily doped P-type region in the BCD device to form a surface P-type doped region 105. A PN junction is formed between the N-type doped region 104 and the P-type doped region 105, thereby obtaining a vertical Zener diode. The P-type doped region 105 serves as the anode of the Zener diode, and the cathode of the Zener diode is led out through the N-type second source-drain doped region formed between the shallow trench isolation structures.

[0040] However, the N-type doping region 104 in the Zener diode requires a heavy doping concentration, but the concentration of the N-type ion implantation performed during the manufacturing process of the SGT device and the BCD device fails to meet the requirement. Therefore, an additional mask process is required to form the N-type doping region 104 with a heavy doping concentration, and it cannot be formed simultaneously parasitically during the process of forming the SGT device and the BCD device, which will increase the manufacturing cost.

[0041] Based on this, the present invention provides a semiconductor structure and a method for forming it. Ion implantation, which forms the channel region of a BCD device and the body region of an SGT device, simultaneously forms the anode doping region of a Zener diode within the substrate. This approach uses a stacked ion implantation method to meet the ion doping concentration requirements of the anode doping region of the Zener diode. The anode doping region of the Zener diode is parasitically formed simultaneously using the processes for forming the BCD and SGT devices, thereby avoiding the need for additional photomask steps to form the heavily doped anode doping region. This simplifies the Zener diode manufacturing process and reduces production costs.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 2 to 81. It is a schematic structural diagram of each step of a semiconductor structure and a method for forming the same according to an embodiment of the present invention; Figure 9 Schematic diagram of the structure of an SGT device in an embodiment of the present invention; Figure 10 1 is a schematic structural diagram of an NLDMOS device in a BCD device according to an embodiment of the present invention; Figure 11 Schematic diagram of the structure of an NMOS device in a BCD device according to an embodiment of the present invention.

[0044] Please refer to Figure 2 , providing a substrate 200.

[0045] In this embodiment, the substrate 200 includes a base and an epitaxial layer (not shown) located on the base, wherein the epitaxial layer is doped with N-type ions.

[0046] In this embodiment, the substrate 200 is made of silicon.

[0047] In other embodiments, the substrate may be made of germanium, silicon carbide, or silicon germanium.

[0048] Please refer to Figure 3 、 Figure 10 and Figure 11 The ion implantation for forming the buried layer 300 and the deep well layer 301 in the BCD device is used to simultaneously form the doped region 201 of the Zener diode in the substrate 200. The substrate 200 exposes the top surface of the doped region 201. The electrical type of the doped ions in the doped region 201, the buried layer 300 and the deep well layer 301 is the same.

[0049] It should be noted that, in this embodiment, the buried layer 300 can effectively isolate different devices and prevent electrical interference between them. In the BCD process, the buried layer 300 can isolate DMOS structures, CMOS structures, and bipolar devices, preventing mutual interference between them. Furthermore, the isolation effect of the buried layer 300 can reduce parasitic capacitance and parasitic resistance, thereby improving device performance and reliability. The deep well layer 301 can increase the device's voltage resistance, enabling the device to operate at higher voltages. This is particularly important for high-voltage applications in BCD devices. Furthermore, the isolation provided by the deep well layer 301 can reduce the propagation of noise from the substrate 200, improving the device's electrical stability. In summary, the buried layer 300 and the deep well layer 301, through their isolation and shielding effects, respectively, in BCD devices improve device performance, voltage resistance, and reliability, while reducing parasitic effects and substrate 200 noise.

[0050] In this embodiment, the doped ions in the buried layer 300 and the deep well layer 301 are P-type ions.

[0051] Please refer to Figure 4 , and continue to combine reference Figure 10 The first well region 202 of the Zener diode is simultaneously formed in the doping region 201 by ion implantation for forming the first high-voltage well region 302 in the BCD device. The substrate 200 exposes the top surface of the first well region 202. The anode doping region 201 is located in the first well region 202. The electrical type of the doped ions in the first well region 202 and the first high-voltage well region 302 is the same. The electrical type of the doped ions in the first well region 202 is opposite to that in the doping region 201 and the anode doping region 201, respectively.

[0052] It should be noted that, in this embodiment, the doped ions in the first well region 202 and the first high-voltage well region 302 are N-type ions. The first high-voltage well region 302 is used to form the drift region of the high-voltage device in the BCD device. By optimizing its doping concentration and depth, the device's breakdown voltage can be effectively improved. For example, in a high-voltage LDMOS (lateral double-diffused MOS) device, the first high-voltage well region 302 can control the impurity distribution in the drift region to meet field-limited depletion conditions, thereby achieving higher voltage withstand capability. The first high-voltage well region 302 can also be combined with other isolation technologies (such as the P-type buried layer 300 or shallow trench isolation structure) to achieve isolation between different high-voltage devices. This isolation prevents electrical interference between high-voltage devices, ensuring that each device can operate independently.

[0053] Please refer to Figure 5 , and continue to combine reference Figure 10 and Figure 11 The isolation ring 203 of the Zener diode is simultaneously formed in the substrate 200 using the process of forming the shallow trench isolation structure 303 in the BCD device, and the top surface of the isolation ring 203 is exposed on the substrate 200.

[0054] In this embodiment, the method for forming the shallow trench isolation structure 303 includes: forming a shallow trench (not shown) in the substrate 200 ; and forming an insulating material in the shallow trench to form the shallow trench isolation structure 303 .

[0055] In this embodiment, the shallow trench isolation structure 303 is made of silicon oxide.

[0056] It should be noted that in this embodiment, the shallow trench isolation structure 303 achieves electrical isolation between different devices by etching deep, narrow trenches between them and filling them with a high-density insulating material. This effectively prevents leakage current and electrical interference between devices, ensuring that each device can operate independently. In BCD devices, bipolar devices (such as BJTs) and CMOS devices (such as MOSFETs) typically require strict isolation. The shallow trench isolation structure 303 prevents base current or collector current from the bipolar device from leaking into the CMOS device, and vice versa. The shallow trench isolation structure 303 can also be used to isolate high-voltage devices (such as DMOS) from low-voltage devices (such as low-voltage CMOS logic circuits), preventing the high voltage of the high-voltage device from damaging the low-voltage device. The insulating material in the shallow trench isolation structure 303 fills the gaps between the devices, reducing electric field coupling between them and thereby lowering parasitic capacitance. This is particularly important for high-frequency and high-speed circuits, as it can reduce signal delay and power consumption. In high-voltage BCD devices, the shallow trench isolation structure 303 can also be combined with other voltage-resistant structures (such as the N-type first high-voltage well region 302 and the P-type buried layer 300) to form more effective voltage-resistant isolation. For example, in a high-voltage LDMOS device, the shallow trench isolation structure 303 can be combined with the N-type first high-voltage well region 302 to optimize the electric field distribution in the drift region and increase the device's breakdown voltage. For a Zener diode, the isolation ring 203 serves to electrically isolate the active area of ​​the Zener diode from other devices. By forming a high-impedance isolation region around the Zener diode, current can be prevented from leaking from the Zener diode to the substrate 200 or other adjacent devices, thereby improving the performance and stability of the Zener diode.

[0057] Please refer to Figure 6 , and continue to combine reference Figure 10 The ion implantation for forming the second high-voltage well region 304 in the BCD device is used to simultaneously form a guard ring 204 of the Zener diode in the doping region 201. The substrate 200 exposes the top surface of the guard ring 204. The electrical type of the doped ions in the guard ring 204 and the second high-voltage well region 304 is the same, while the electrical type of the doped ions in the guard ring 204 and the first well region 202 is opposite.

[0058] It should be noted that in this embodiment, the doped ions in the guard ring 204 and the second high-voltage well region 304 are P-type ions. The second high-voltage well region 304 is a critical component of the medium-voltage device in the BCD device, forming the substrate 200 region of a high-voltage MOS device (such as an HVPMOS). By optimizing the doping concentration and depth of the second high-voltage well region 304, the device's voltage withstand capability can be effectively improved. For example, in a high-voltage PMOS device, the second high-voltage well region 304 can withstand high reverse bias voltages. The second high-voltage well region 304 also isolates high-voltage and low-voltage devices, preventing high-voltage signals from interfering with low-voltage logic circuits. This isolation ensures compatibility between high-voltage and low-voltage devices on the same chip. Furthermore, the second high-voltage well region 304 can be combined with other isolation technologies (such as the shallow trench isolation structure 303) to further enhance device isolation. Zener diodes can be affected by external noise or transient currents during operation, potentially inducing latch-up. The guard ring 204 can effectively discharge the trigger current of the parasitic structure and prevent the latch-up effect by providing a low-impedance path.

[0059] Please refer to Figure 7 and Figure 9 , and continue to combine reference Figure 11 The anode doping region 205 of the Zener diode is simultaneously formed in the substrate 200 by ion implantation for forming the channel region 305 in the BCD device and the body region 400 in the SGT device. The substrate 200 exposes the top surface of the anode doping region 205. The electrical type of the doped ions in the anode doping region 205, the channel region 305 and the body region 400 is the same.

[0060] The ion dose superposition injection method is used to meet the ion doping concentration requirement of the anode doping region 205 in the Zener diode. The anode doping region 205 in the Zener diode is parasitically formed synchronously by utilizing the process of forming the BCD device and the SGT device, thereby avoiding the additional mask process to form the anode doping region 205 with heavy doping requirements, thereby simplifying the process steps of the Zener diode and reducing production costs.

[0061] It should be noted that in this embodiment, the doping ions in the anode doping region 205, the channel region 305, and the body region 400 are P-type ions. The channel region 305 serves as the channel of the NMOS device in the BCD device, and the body region 400 forms the channel portion of the device due to the lateral diffusion difference with the source in the SGT device.

[0062] Please refer to Figure 8 , and continue to combine reference Figures 9 to 11Ion implantation, which forms the first source / drain doping regions in the BCD device and the SGT device, is used to simultaneously form a cathode doping region 206 of the Zener diode in the anode doping region 205. The substrate 200 exposes the top surface of the cathode doping region 206. The electrical type of the doped ions in the cathode doping region 206 and the first source / drain doping regions is the same, and the electrical type of the doped ions in the cathode doping region 206 and the anode doping region 205 is opposite. The anode doping region 205 and the cathode doping region 206 form a PN junction of the Zener diode.

[0063] It should be noted that, in this embodiment, the first source / drain doping region formed in the BCD device is the BCD source / drain doping region 306 , and the first source / drain doping region formed in the SGT device is the SGT source / drain doping region 401 .

[0064] In this embodiment, the doping ions in the cathode doping region 206 and the first source / drain doping region are N-type ions, and the BCD source / drain doping region 306 serves as the source / drain of the NMOS transistor in the BCD device.

[0065] In this embodiment, ion implantation for forming the first source / drain doping regions in the BCD device and the SGT device also simultaneously forms a well lead-out region 207 of the Zener diode in the first well region 202. The well lead-out region 207 serves as a lead contact of the first well region 202, thereby reducing contact resistance.

[0066] Please continue to refer to Figure 8 、 Figure 10 and Figure 11 In this embodiment, after forming the anode doping region 205, the method further includes: using ion implantation for forming the second source / drain doping region (not shown) in the BCD device to simultaneously form an anode lead-out region 208 of the Zener diode in the anode doping region 205, wherein the substrate 200 exposes the top surface of the anode lead-out region 208, and the electrical type of the doped ions in the anode lead-out region 208, the second source / drain doping region, and the anode doping region 205 is the same.

[0067] It should be noted that, in this embodiment, the anode lead-out region 208, the second source / drain doping region, and the anode doping region 205 are doped with P-type ions. The second source / drain doping region serves as the source / drain of a PMOS transistor (not shown) in a BCD device.

[0068] In this embodiment, ion implantation for forming the second source / drain doping region in the BCD device also forms a guard ring lead-out region 209 of a Zener diode in the guard ring 204 . The guard ring lead-out region 209 serves as a lead contact for the guard ring 204 , thereby reducing contact resistance.

[0069] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by using any one of the above embodiments, please continue to refer to Figure 8 , including: a substrate 200; an anode doping region 205 of a Zener diode located in the substrate 200, the substrate 200 exposing the top surface of the anode doping region 205; a cathode doping region 206 of the Zener diode located in the anode doping region 205, the substrate 200 exposing the top surface of the cathode doping region 206, the electrical type of doped ions in the cathode doping region 206 and the anode doping region 205 is opposite, and the anode doping region 205 and the cathode doping region 206 constitute a PN junction of the Zener diode.

[0070] The ion dose superposition injection method is used to meet the ion doping concentration requirement of the anode doping region 205 in the Zener diode. The anode doping region 205 in the Zener diode is parasitically formed synchronously by utilizing the process of forming the BCD device and the SGT device, thereby avoiding the additional mask process to form the anode doping region 205 with heavy doping requirements, thereby simplifying the process steps of the Zener diode and reducing production costs.

[0071] In this embodiment, the doping ions in the anode doping region 205 are P-type ions.

[0072] In this embodiment, the doping ions in the cathode doping region 206 are N-type ions.

[0073] In this embodiment, the substrate 200 includes a base and an epitaxial layer (not shown) located on the base, wherein the epitaxial layer is doped with N-type ions.

[0074] In this embodiment, the substrate 200 is made of silicon.

[0075] In other embodiments, the substrate may be made of germanium, silicon carbide, or silicon germanium.

[0076] In this embodiment, it also includes: an anode lead-out region 208 of the Zener diode located in the anode doping region 205, the substrate 200 exposes the top surface of the anode lead-out region 208, and the electrical type of the doped ions in the anode lead-out region 208 and the anode doping region 205 is the same.

[0077] In this embodiment, the doping ions in the anode lead-out region 208 are P-type ions.

[0078] In this embodiment, the anode lead-out region 208 surrounds the cathode doped region 206 .

[0079] This embodiment further includes an isolation ring 203 for the Zener diode located within the substrate 200, with the top surface of the isolation ring 203 exposed from the substrate 200. The isolation ring 203 electrically isolates the active area of ​​the Zener diode from other devices. By forming a high-impedance isolation region around the Zener diode, current leakage from the Zener diode to the substrate 200 or other adjacent devices is prevented, thereby improving the performance and stability of the Zener diode.

[0080] In this embodiment, the isolation ring 203 is made of silicon oxide.

[0081] In this embodiment, the anode lead-out region 208 is located between adjacent isolation rings 203 , and the isolation rings 203 surround the cathode doping region 206 .

[0082] In this embodiment, the device further includes a doping region 201 of the Zener diode located in the substrate 200 , and the substrate 200 exposes a top surface of the doping region 201 .

[0083] In this embodiment, the doping ions in the doping region 201 are P-type ions.

[0084] In this embodiment, it also includes: a first well region 202 of the Zener diode located in the doping region 201, the substrate 200 exposes the top surface of the first well region 202, the anode doping region 205 is located in the first well region 202, and the electrical type of the doped ions in the first well region 202 is opposite to that in the doping region 201 and the anode doping region 205.

[0085] In this embodiment, the doping ions in the first well region 202 are N-type ions.

[0086] This embodiment further includes a guard ring 204 for the Zener diode located within the doped region 201. The top surface of the guard ring 204 is exposed by the substrate 200. The guard ring 204 and the first well region 202 have doped ions of opposite electrical type. During operation, the Zener diode may be affected by external noise or transient current, which may induce latch-up. The guard ring 204 provides a low-impedance path to effectively dissipate the trigger current of the parasitic structure, preventing latch-up.

[0087] In this embodiment, the doping ions in the guard ring 204 are P-type ions.

[0088] In this embodiment, the anode lead-out region 208 surrounds the cathode doped region 206 ; the anode lead-out region 208 is located between adjacent isolation rings 203 , and the isolation rings 203 surround the cathode doped region 206 .

[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; An anode doping region of a Zener diode is simultaneously formed in the substrate by ion implantation for forming a channel region in a BCD device and a body region in an SGT device, wherein the substrate exposes a top surface of the anode doping region, and the electrical type of doping ions in the anode doping region, the channel region, and the body region is the same; Ion implantation, which forms the first source / drain doping region in the BCD device and the SGT device, is used to simultaneously form a cathode doping region of the Zener diode in the anode doping region. The substrate exposes the top surface of the cathode doping region. The electrical types of the doped ions in the cathode doping region and the first source / drain doping region are the same, while the electrical types of the doped ions in the cathode doping region and the anode doping region are opposite. The anode doping region and the cathode doping region form a PN junction of the Zener diode.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming the anode doping region, the method further includes: using ion implantation to form the second source and drain doping region in the BCD device to simultaneously form an anode lead-out region of the Zener diode in the anode doping region, the substrate exposes the top surface of the anode lead-out region, and the electrical type of the doped ions in the anode lead-out region, the second source and drain doping region, and the anode doping region is the same.

3. The method for forming a semiconductor structure according to claim 2, wherein: The anode lead-out region surrounds the cathode doped region.

4. The method for forming a semiconductor structure according to claim 2, wherein: Before forming the anode doping region, the method further includes: using a process for forming a shallow trench isolation structure in a BCD device to simultaneously form an isolation ring of a Zener diode in the substrate, wherein the substrate exposes a top surface of the isolation ring.

5. The method for forming a semiconductor structure according to claim 4, wherein: The anode lead-out region is located between adjacent isolation rings, and the isolation rings surround the cathode doping region.

6. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the anode doping region, the method further includes: using ion implantation to form a buried layer and a deep well layer in a BCD device to synchronously form a doping region of a Zener diode in the substrate, wherein the substrate exposes the top surface of the doping region, and the electrical type of the doped ions in the doping region, the buried layer and the deep well layer is the same.

7. The method for forming a semiconductor structure according to claim 6, wherein: Before forming the anode doping region, the method further includes: using ion implantation to form the first high-voltage well region in the BCD device to synchronously form the first well region of the Zener diode in the doping region, the substrate exposes the top surface of the first well region, the anode doping region is located in the first well region, the electrical type of the doped ions in the first well region and the first high-voltage well region is the same, and the electrical type of the doped ions in the first well region is opposite to that in the doping region and the anode doping region, respectively.

8. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the anode doping region, it also includes: using ion implantation to form a second high-voltage well region in the BCD device to synchronously form a guard ring of the Zener diode in the doping region, the substrate exposes the top surface of the guard ring, the electrical type of the doped ions in the guard ring and the second high-voltage well region is the same, and the electrical type of the doped ions in the guard ring and the first well region is opposite.

9. The method for forming a semiconductor structure according to claim 1, wherein: The doping ions in the anode doping region are P-type ions; the doping ions in the cathode doping region are N-type ions.

10. A semiconductor structure formed by the forming method according to any one of claims 1 to 9, characterized in that: include: substrate; an anode doped region of a Zener diode located within a substrate, the substrate exposing a top surface of the anode doped region; The cathode doping region of the Zener diode is located in the anode doping region, the substrate exposes the top surface of the cathode doping region, the electrical types of the doped ions in the cathode doping region and the anode doping region are opposite, and the anode doping region and the cathode doping region constitute a PN junction of the Zener diode.

11. The semiconductor structure according to claim 10, wherein: Also includes: The anode lead-out region of the Zener diode is located in the anode doping region, the substrate exposes the top surface of the anode lead-out region, and the electrical type of doped ions in the anode lead-out region and the anode doping region is the same.

12. The semiconductor structure according to claim 11, wherein: The anode lead-out region surrounds the cathode doped region.

13. The semiconductor structure according to claim 11, wherein: Also includes: An isolation ring of the Zener diode is located within the substrate, the substrate exposing a top surface of the isolation ring.

14. The semiconductor structure according to claim 13, wherein: The anode lead-out region is located between adjacent isolation rings, and the isolation rings surround the cathode doping region.

15. The semiconductor structure according to claim 10, wherein: Also includes: A doped region of the Zener diode is located in the substrate, and the substrate exposes a top surface of the doped region.

16. The semiconductor structure according to claim 15, wherein: Also includes: The first well region of the Zener diode is located in the doped region, the substrate exposes the top surface of the first well region, the anode doped region is located in the first well region, and the electrical type of the doped ions in the first well region is opposite to that in the doped region and the anode doped region.

17. The semiconductor structure according to claim 16, wherein: Also includes: A guard ring of the Zener diode is located in the doped region, the substrate exposes a top surface of the guard ring, and the electrical types of doped ions in the guard ring and the first well region are opposite.

18. The semiconductor structure according to claim 10, wherein: The doping ions in the anode doping region are P-type ions; the doping ions in the cathode doping region are N-type ions.

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